VirtualBox

source: vbox/trunk/src/VBox/VMM/EM.cpp@ 22480

Last change on this file since 22480 was 22480, checked in by vboxsync, 15 years ago

SSM,VMM,Devices,Main,VBoxBFE: Live snapshot/migration SSM API adjustments.
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1/* $Id: EM.cpp 22480 2009-08-26 17:14:13Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_em EM - The Execution Monitor / Manager
23 *
24 * The Execution Monitor/Manager is responsible for running the VM, scheduling
25 * the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
26 * Interpreted), and keeping the CPU states in sync. The function
27 * EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
28 * modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
29 * emR3RemExecute).
30 *
31 * The interpreted execution is only used to avoid switching between
32 * raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
33 * The interpretation is thus implemented as part of EM.
34 *
35 * @see grp_em
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_EM
42#include <VBox/em.h>
43#include <VBox/vmm.h>
44#ifdef VBOX_WITH_VMI
45# include <VBox/parav.h>
46#endif
47#include <VBox/patm.h>
48#include <VBox/csam.h>
49#include <VBox/selm.h>
50#include <VBox/trpm.h>
51#include <VBox/iom.h>
52#include <VBox/dbgf.h>
53#include <VBox/pgm.h>
54#include <VBox/rem.h>
55#include <VBox/tm.h>
56#include <VBox/mm.h>
57#include <VBox/ssm.h>
58#include <VBox/pdmapi.h>
59#include <VBox/pdmcritsect.h>
60#include <VBox/pdmqueue.h>
61#include <VBox/hwaccm.h>
62#include <VBox/patm.h>
63#include "EMInternal.h"
64#include <VBox/vm.h>
65#include <VBox/cpumdis.h>
66#include <VBox/dis.h>
67#include <VBox/disopcode.h>
68#include <VBox/dbgf.h>
69
70#include <iprt/string.h>
71#include <iprt/stream.h>
72
73
74/*******************************************************************************
75* Defined Constants And Macros *
76*******************************************************************************/
77#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
78#define EM_NOTIFY_HWACCM
79#endif
80
81
82/*******************************************************************************
83* Internal Functions *
84*******************************************************************************/
85static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
86static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPhase);
87static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc);
88static int emR3RemStep(PVM pVM, PVMCPU pVCpu);
89static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
90DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
91int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
92
93
94/**
95 * Initializes the EM.
96 *
97 * @returns VBox status code.
98 * @param pVM The VM to operate on.
99 */
100VMMR3DECL(int) EMR3Init(PVM pVM)
101{
102 LogFlow(("EMR3Init\n"));
103 /*
104 * Assert alignment and sizes.
105 */
106 AssertCompileMemberAlignment(VM, em.s, 32);
107 AssertCompile(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
108 AssertCompile(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump));
109 AssertCompileMemberAlignment(EM, CritSectREM, sizeof(uintptr_t));
110
111 /*
112 * Init the structure.
113 */
114 pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
115 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
116 if (RT_FAILURE(rc))
117 pVM->fRawR3Enabled = true;
118 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
119 if (RT_FAILURE(rc))
120 pVM->fRawR0Enabled = true;
121 Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
122
123 /*
124 * Initialize the REM critical section.
125 */
126 rc = PDMR3CritSectInit(pVM, &pVM->em.s.CritSectREM, "EM-REM");
127 AssertRCReturn(rc, rc);
128
129 /*
130 * Saved state.
131 */
132 rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
133 NULL, NULL, NULL,
134 NULL, emR3Save, NULL,
135 NULL, emR3Load, NULL);
136 if (RT_FAILURE(rc))
137 return rc;
138
139 for (unsigned i=0;i<pVM->cCPUs;i++)
140 {
141 PVMCPU pVCpu = &pVM->aCpus[i];
142
143 pVCpu->em.s.offVMCPU = RT_OFFSETOF(VMCPU, em.s);
144
145 pVCpu->em.s.enmState = (i == 0) ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
146 pVCpu->em.s.enmPrevState = EMSTATE_NONE;
147 pVCpu->em.s.fForceRAW = false;
148
149 pVCpu->em.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
150 pVCpu->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
151 AssertMsg(pVCpu->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
152
153# define EM_REG_COUNTER(a, b, c) \
154 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
155 AssertRC(rc);
156
157# define EM_REG_COUNTER_USED(a, b, c) \
158 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, c, b, i); \
159 AssertRC(rc);
160
161# define EM_REG_PROFILE(a, b, c) \
162 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
163 AssertRC(rc);
164
165# define EM_REG_PROFILE_ADV(a, b, c) \
166 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
167 AssertRC(rc);
168
169 /*
170 * Statistics.
171 */
172#ifdef VBOX_WITH_STATISTICS
173 PEMSTATS pStats;
174 rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
175 if (RT_FAILURE(rc))
176 return rc;
177
178 pVCpu->em.s.pStatsR3 = pStats;
179 pVCpu->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
180 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
181
182 EM_REG_PROFILE(&pStats->StatRZEmulate, "/EM/CPU%d/RZ/Interpret", "Profiling of EMInterpretInstruction.");
183 EM_REG_PROFILE(&pStats->StatR3Emulate, "/EM/CPU%d/R3/Interpret", "Profiling of EMInterpretInstruction.");
184
185 EM_REG_PROFILE(&pStats->StatRZInterpretSucceeded, "/EM/CPU%d/RZ/Interpret/Success", "The number of times an instruction was successfully interpreted.");
186 EM_REG_PROFILE(&pStats->StatR3InterpretSucceeded, "/EM/CPU%d/R3/Interpret/Success", "The number of times an instruction was successfully interpreted.");
187
188 EM_REG_COUNTER_USED(&pStats->StatRZAnd, "/EM/CPU%d/RZ/Interpret/Success/And", "The number of times AND was successfully interpreted.");
189 EM_REG_COUNTER_USED(&pStats->StatR3And, "/EM/CPU%d/R3/Interpret/Success/And", "The number of times AND was successfully interpreted.");
190 EM_REG_COUNTER_USED(&pStats->StatRZAdd, "/EM/CPU%d/RZ/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
191 EM_REG_COUNTER_USED(&pStats->StatR3Add, "/EM/CPU%d/R3/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
192 EM_REG_COUNTER_USED(&pStats->StatRZAdc, "/EM/CPU%d/RZ/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
193 EM_REG_COUNTER_USED(&pStats->StatR3Adc, "/EM/CPU%d/R3/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
194 EM_REG_COUNTER_USED(&pStats->StatRZSub, "/EM/CPU%d/RZ/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
195 EM_REG_COUNTER_USED(&pStats->StatR3Sub, "/EM/CPU%d/R3/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
196 EM_REG_COUNTER_USED(&pStats->StatRZCpuId, "/EM/CPU%d/RZ/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
197 EM_REG_COUNTER_USED(&pStats->StatR3CpuId, "/EM/CPU%d/R3/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
198 EM_REG_COUNTER_USED(&pStats->StatRZDec, "/EM/CPU%d/RZ/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
199 EM_REG_COUNTER_USED(&pStats->StatR3Dec, "/EM/CPU%d/R3/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
200 EM_REG_COUNTER_USED(&pStats->StatRZHlt, "/EM/CPU%d/RZ/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
201 EM_REG_COUNTER_USED(&pStats->StatR3Hlt, "/EM/CPU%d/R3/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
202 EM_REG_COUNTER_USED(&pStats->StatRZInc, "/EM/CPU%d/RZ/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
203 EM_REG_COUNTER_USED(&pStats->StatR3Inc, "/EM/CPU%d/R3/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
204 EM_REG_COUNTER_USED(&pStats->StatRZInvlPg, "/EM/CPU%d/RZ/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
205 EM_REG_COUNTER_USED(&pStats->StatR3InvlPg, "/EM/CPU%d/R3/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
206 EM_REG_COUNTER_USED(&pStats->StatRZIret, "/EM/CPU%d/RZ/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
207 EM_REG_COUNTER_USED(&pStats->StatR3Iret, "/EM/CPU%d/R3/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
208 EM_REG_COUNTER_USED(&pStats->StatRZLLdt, "/EM/CPU%d/RZ/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
209 EM_REG_COUNTER_USED(&pStats->StatR3LLdt, "/EM/CPU%d/R3/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
210 EM_REG_COUNTER_USED(&pStats->StatRZLIdt, "/EM/CPU%d/RZ/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
211 EM_REG_COUNTER_USED(&pStats->StatR3LIdt, "/EM/CPU%d/R3/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
212 EM_REG_COUNTER_USED(&pStats->StatRZLGdt, "/EM/CPU%d/RZ/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
213 EM_REG_COUNTER_USED(&pStats->StatR3LGdt, "/EM/CPU%d/R3/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
214 EM_REG_COUNTER_USED(&pStats->StatRZMov, "/EM/CPU%d/RZ/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
215 EM_REG_COUNTER_USED(&pStats->StatR3Mov, "/EM/CPU%d/R3/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
216 EM_REG_COUNTER_USED(&pStats->StatRZMovCRx, "/EM/CPU%d/RZ/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
217 EM_REG_COUNTER_USED(&pStats->StatR3MovCRx, "/EM/CPU%d/R3/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
218 EM_REG_COUNTER_USED(&pStats->StatRZMovDRx, "/EM/CPU%d/RZ/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
219 EM_REG_COUNTER_USED(&pStats->StatR3MovDRx, "/EM/CPU%d/R3/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
220 EM_REG_COUNTER_USED(&pStats->StatRZOr, "/EM/CPU%d/RZ/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
221 EM_REG_COUNTER_USED(&pStats->StatR3Or, "/EM/CPU%d/R3/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
222 EM_REG_COUNTER_USED(&pStats->StatRZPop, "/EM/CPU%d/RZ/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
223 EM_REG_COUNTER_USED(&pStats->StatR3Pop, "/EM/CPU%d/R3/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
224 EM_REG_COUNTER_USED(&pStats->StatRZRdtsc, "/EM/CPU%d/RZ/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
225 EM_REG_COUNTER_USED(&pStats->StatR3Rdtsc, "/EM/CPU%d/R3/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
226 EM_REG_COUNTER_USED(&pStats->StatRZRdpmc, "/EM/CPU%d/RZ/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
227 EM_REG_COUNTER_USED(&pStats->StatR3Rdpmc, "/EM/CPU%d/R3/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
228 EM_REG_COUNTER_USED(&pStats->StatRZSti, "/EM/CPU%d/RZ/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
229 EM_REG_COUNTER_USED(&pStats->StatR3Sti, "/EM/CPU%d/R3/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
230 EM_REG_COUNTER_USED(&pStats->StatRZXchg, "/EM/CPU%d/RZ/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
231 EM_REG_COUNTER_USED(&pStats->StatR3Xchg, "/EM/CPU%d/R3/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
232 EM_REG_COUNTER_USED(&pStats->StatRZXor, "/EM/CPU%d/RZ/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
233 EM_REG_COUNTER_USED(&pStats->StatR3Xor, "/EM/CPU%d/R3/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
234 EM_REG_COUNTER_USED(&pStats->StatRZMonitor, "/EM/CPU%d/RZ/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
235 EM_REG_COUNTER_USED(&pStats->StatR3Monitor, "/EM/CPU%d/R3/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
236 EM_REG_COUNTER_USED(&pStats->StatRZMWait, "/EM/CPU%d/RZ/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
237 EM_REG_COUNTER_USED(&pStats->StatR3MWait, "/EM/CPU%d/R3/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
238 EM_REG_COUNTER_USED(&pStats->StatRZBtr, "/EM/CPU%d/RZ/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
239 EM_REG_COUNTER_USED(&pStats->StatR3Btr, "/EM/CPU%d/R3/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
240 EM_REG_COUNTER_USED(&pStats->StatRZBts, "/EM/CPU%d/RZ/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
241 EM_REG_COUNTER_USED(&pStats->StatR3Bts, "/EM/CPU%d/R3/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
242 EM_REG_COUNTER_USED(&pStats->StatRZBtc, "/EM/CPU%d/RZ/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
243 EM_REG_COUNTER_USED(&pStats->StatR3Btc, "/EM/CPU%d/R3/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
244 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
245 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg, "/EM/CPU%d/R3/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
246 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
247 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg8b, "/EM/CPU%d/R3/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
248 EM_REG_COUNTER_USED(&pStats->StatRZXAdd, "/EM/CPU%d/RZ/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
249 EM_REG_COUNTER_USED(&pStats->StatR3XAdd, "/EM/CPU%d/R3/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
250 EM_REG_COUNTER_USED(&pStats->StatR3Rdmsr, "/EM/CPU%d/R3/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
251 EM_REG_COUNTER_USED(&pStats->StatRZRdmsr, "/EM/CPU%d/RZ/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
252 EM_REG_COUNTER_USED(&pStats->StatR3Wrmsr, "/EM/CPU%d/R3/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
253 EM_REG_COUNTER_USED(&pStats->StatRZWrmsr, "/EM/CPU%d/RZ/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
254 EM_REG_COUNTER_USED(&pStats->StatR3StosWD, "/EM/CPU%d/R3/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
255 EM_REG_COUNTER_USED(&pStats->StatRZStosWD, "/EM/CPU%d/RZ/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
256 EM_REG_COUNTER_USED(&pStats->StatRZWbInvd, "/EM/CPU%d/RZ/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
257 EM_REG_COUNTER_USED(&pStats->StatR3WbInvd, "/EM/CPU%d/R3/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
258 EM_REG_COUNTER_USED(&pStats->StatRZLmsw, "/EM/CPU%d/RZ/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
259 EM_REG_COUNTER_USED(&pStats->StatR3Lmsw, "/EM/CPU%d/R3/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
260
261 EM_REG_COUNTER(&pStats->StatRZInterpretFailed, "/EM/CPU%d/RZ/Interpret/Failed", "The number of times an instruction was not interpreted.");
262 EM_REG_COUNTER(&pStats->StatR3InterpretFailed, "/EM/CPU%d/R3/Interpret/Failed", "The number of times an instruction was not interpreted.");
263
264 EM_REG_COUNTER_USED(&pStats->StatRZFailedAnd, "/EM/CPU%d/RZ/Interpret/Failed/And", "The number of times AND was not interpreted.");
265 EM_REG_COUNTER_USED(&pStats->StatR3FailedAnd, "/EM/CPU%d/R3/Interpret/Failed/And", "The number of times AND was not interpreted.");
266 EM_REG_COUNTER_USED(&pStats->StatRZFailedCpuId, "/EM/CPU%d/RZ/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
267 EM_REG_COUNTER_USED(&pStats->StatR3FailedCpuId, "/EM/CPU%d/R3/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
268 EM_REG_COUNTER_USED(&pStats->StatRZFailedDec, "/EM/CPU%d/RZ/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
269 EM_REG_COUNTER_USED(&pStats->StatR3FailedDec, "/EM/CPU%d/R3/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
270 EM_REG_COUNTER_USED(&pStats->StatRZFailedHlt, "/EM/CPU%d/RZ/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
271 EM_REG_COUNTER_USED(&pStats->StatR3FailedHlt, "/EM/CPU%d/R3/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
272 EM_REG_COUNTER_USED(&pStats->StatRZFailedInc, "/EM/CPU%d/RZ/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
273 EM_REG_COUNTER_USED(&pStats->StatR3FailedInc, "/EM/CPU%d/R3/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
274 EM_REG_COUNTER_USED(&pStats->StatRZFailedInvlPg, "/EM/CPU%d/RZ/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
275 EM_REG_COUNTER_USED(&pStats->StatR3FailedInvlPg, "/EM/CPU%d/R3/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
276 EM_REG_COUNTER_USED(&pStats->StatRZFailedIret, "/EM/CPU%d/RZ/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
277 EM_REG_COUNTER_USED(&pStats->StatR3FailedIret, "/EM/CPU%d/R3/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
278 EM_REG_COUNTER_USED(&pStats->StatRZFailedLLdt, "/EM/CPU%d/RZ/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
279 EM_REG_COUNTER_USED(&pStats->StatR3FailedLLdt, "/EM/CPU%d/R3/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
280 EM_REG_COUNTER_USED(&pStats->StatRZFailedLIdt, "/EM/CPU%d/RZ/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
281 EM_REG_COUNTER_USED(&pStats->StatR3FailedLIdt, "/EM/CPU%d/R3/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
282 EM_REG_COUNTER_USED(&pStats->StatRZFailedLGdt, "/EM/CPU%d/RZ/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
283 EM_REG_COUNTER_USED(&pStats->StatR3FailedLGdt, "/EM/CPU%d/R3/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
284 EM_REG_COUNTER_USED(&pStats->StatRZFailedMov, "/EM/CPU%d/RZ/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
285 EM_REG_COUNTER_USED(&pStats->StatR3FailedMov, "/EM/CPU%d/R3/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
286 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovCRx, "/EM/CPU%d/RZ/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
287 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovCRx, "/EM/CPU%d/R3/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
288 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovDRx, "/EM/CPU%d/RZ/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
289 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovDRx, "/EM/CPU%d/R3/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
290 EM_REG_COUNTER_USED(&pStats->StatRZFailedOr, "/EM/CPU%d/RZ/Interpret/Failed/Or", "The number of times OR was not interpreted.");
291 EM_REG_COUNTER_USED(&pStats->StatR3FailedOr, "/EM/CPU%d/R3/Interpret/Failed/Or", "The number of times OR was not interpreted.");
292 EM_REG_COUNTER_USED(&pStats->StatRZFailedPop, "/EM/CPU%d/RZ/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
293 EM_REG_COUNTER_USED(&pStats->StatR3FailedPop, "/EM/CPU%d/R3/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
294 EM_REG_COUNTER_USED(&pStats->StatRZFailedSti, "/EM/CPU%d/RZ/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
295 EM_REG_COUNTER_USED(&pStats->StatR3FailedSti, "/EM/CPU%d/R3/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
296 EM_REG_COUNTER_USED(&pStats->StatRZFailedXchg, "/EM/CPU%d/RZ/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
297 EM_REG_COUNTER_USED(&pStats->StatR3FailedXchg, "/EM/CPU%d/R3/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
298 EM_REG_COUNTER_USED(&pStats->StatRZFailedXor, "/EM/CPU%d/RZ/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
299 EM_REG_COUNTER_USED(&pStats->StatR3FailedXor, "/EM/CPU%d/R3/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
300 EM_REG_COUNTER_USED(&pStats->StatRZFailedMonitor, "/EM/CPU%d/RZ/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
301 EM_REG_COUNTER_USED(&pStats->StatR3FailedMonitor, "/EM/CPU%d/R3/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
302 EM_REG_COUNTER_USED(&pStats->StatRZFailedMWait, "/EM/CPU%d/RZ/Interpret/Failed/MWait", "The number of times MONITOR was not interpreted.");
303 EM_REG_COUNTER_USED(&pStats->StatR3FailedMWait, "/EM/CPU%d/R3/Interpret/Failed/MWait", "The number of times MONITOR was not interpreted.");
304 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdtsc, "/EM/CPU%d/RZ/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
305 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdtsc, "/EM/CPU%d/R3/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
306 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdpmc, "/EM/CPU%d/RZ/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
307 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdpmc, "/EM/CPU%d/R3/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
308 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdmsr, "/EM/CPU%d/RZ/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
309 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdmsr, "/EM/CPU%d/R3/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
310 EM_REG_COUNTER_USED(&pStats->StatRZFailedWrmsr, "/EM/CPU%d/RZ/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
311 EM_REG_COUNTER_USED(&pStats->StatR3FailedWrmsr, "/EM/CPU%d/R3/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
312 EM_REG_COUNTER_USED(&pStats->StatRZFailedLmsw, "/EM/CPU%d/RZ/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
313 EM_REG_COUNTER_USED(&pStats->StatR3FailedLmsw, "/EM/CPU%d/R3/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
314
315 EM_REG_COUNTER_USED(&pStats->StatRZFailedMisc, "/EM/CPU%d/RZ/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
316 EM_REG_COUNTER_USED(&pStats->StatR3FailedMisc, "/EM/CPU%d/R3/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
317 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdd, "/EM/CPU%d/RZ/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
318 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdd, "/EM/CPU%d/R3/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
319 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdc, "/EM/CPU%d/RZ/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
320 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdc, "/EM/CPU%d/R3/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
321 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtr, "/EM/CPU%d/RZ/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
322 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtr, "/EM/CPU%d/R3/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
323 EM_REG_COUNTER_USED(&pStats->StatRZFailedBts, "/EM/CPU%d/RZ/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
324 EM_REG_COUNTER_USED(&pStats->StatR3FailedBts, "/EM/CPU%d/R3/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
325 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtc, "/EM/CPU%d/RZ/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
326 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtc, "/EM/CPU%d/R3/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
327 EM_REG_COUNTER_USED(&pStats->StatRZFailedCli, "/EM/CPU%d/RZ/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
328 EM_REG_COUNTER_USED(&pStats->StatR3FailedCli, "/EM/CPU%d/R3/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
329 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
330 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
331 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
332 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg8b, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
333 EM_REG_COUNTER_USED(&pStats->StatRZFailedXAdd, "/EM/CPU%d/RZ/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
334 EM_REG_COUNTER_USED(&pStats->StatR3FailedXAdd, "/EM/CPU%d/R3/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
335 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovNTPS, "/EM/CPU%d/RZ/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
336 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovNTPS, "/EM/CPU%d/R3/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
337 EM_REG_COUNTER_USED(&pStats->StatRZFailedStosWD, "/EM/CPU%d/RZ/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
338 EM_REG_COUNTER_USED(&pStats->StatR3FailedStosWD, "/EM/CPU%d/R3/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
339 EM_REG_COUNTER_USED(&pStats->StatRZFailedSub, "/EM/CPU%d/RZ/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
340 EM_REG_COUNTER_USED(&pStats->StatR3FailedSub, "/EM/CPU%d/R3/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
341 EM_REG_COUNTER_USED(&pStats->StatRZFailedWbInvd, "/EM/CPU%d/RZ/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
342 EM_REG_COUNTER_USED(&pStats->StatR3FailedWbInvd, "/EM/CPU%d/R3/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
343
344 EM_REG_COUNTER_USED(&pStats->StatRZFailedUserMode, "/EM/CPU%d/RZ/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
345 EM_REG_COUNTER_USED(&pStats->StatR3FailedUserMode, "/EM/CPU%d/R3/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
346 EM_REG_COUNTER_USED(&pStats->StatRZFailedPrefix, "/EM/CPU%d/RZ/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
347 EM_REG_COUNTER_USED(&pStats->StatR3FailedPrefix, "/EM/CPU%d/R3/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
348
349 EM_REG_COUNTER_USED(&pStats->StatCli, "/EM/CPU%d/R3/PrivInst/Cli", "Number of cli instructions.");
350 EM_REG_COUNTER_USED(&pStats->StatSti, "/EM/CPU%d/R3/PrivInst/Sti", "Number of sli instructions.");
351 EM_REG_COUNTER_USED(&pStats->StatIn, "/EM/CPU%d/R3/PrivInst/In", "Number of in instructions.");
352 EM_REG_COUNTER_USED(&pStats->StatOut, "/EM/CPU%d/R3/PrivInst/Out", "Number of out instructions.");
353 EM_REG_COUNTER_USED(&pStats->StatIoRestarted, "/EM/CPU%d/R3/PrivInst/IoRestarted", "Number of restarted i/o instructions.");
354 EM_REG_COUNTER_USED(&pStats->StatHlt, "/EM/CPU%d/R3/PrivInst/Hlt", "Number of hlt instructions not handled in GC because of PATM.");
355 EM_REG_COUNTER_USED(&pStats->StatInvlpg, "/EM/CPU%d/R3/PrivInst/Invlpg", "Number of invlpg instructions.");
356 EM_REG_COUNTER_USED(&pStats->StatMisc, "/EM/CPU%d/R3/PrivInst/Misc", "Number of misc. instructions.");
357 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[0], "/EM/CPU%d/R3/PrivInst/Mov CR0, X", "Number of mov CR0 read instructions.");
358 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[1], "/EM/CPU%d/R3/PrivInst/Mov CR1, X", "Number of mov CR1 read instructions.");
359 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[2], "/EM/CPU%d/R3/PrivInst/Mov CR2, X", "Number of mov CR2 read instructions.");
360 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[3], "/EM/CPU%d/R3/PrivInst/Mov CR3, X", "Number of mov CR3 read instructions.");
361 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[4], "/EM/CPU%d/R3/PrivInst/Mov CR4, X", "Number of mov CR4 read instructions.");
362 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[0], "/EM/CPU%d/R3/PrivInst/Mov X, CR0", "Number of mov CR0 write instructions.");
363 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[1], "/EM/CPU%d/R3/PrivInst/Mov X, CR1", "Number of mov CR1 write instructions.");
364 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[2], "/EM/CPU%d/R3/PrivInst/Mov X, CR2", "Number of mov CR2 write instructions.");
365 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[3], "/EM/CPU%d/R3/PrivInst/Mov X, CR3", "Number of mov CR3 write instructions.");
366 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[4], "/EM/CPU%d/R3/PrivInst/Mov X, CR4", "Number of mov CR4 write instructions.");
367 EM_REG_COUNTER_USED(&pStats->StatMovDRx, "/EM/CPU%d/R3/PrivInst/MovDRx", "Number of mov DRx instructions.");
368 EM_REG_COUNTER_USED(&pStats->StatIret, "/EM/CPU%d/R3/PrivInst/Iret", "Number of iret instructions.");
369 EM_REG_COUNTER_USED(&pStats->StatMovLgdt, "/EM/CPU%d/R3/PrivInst/Lgdt", "Number of lgdt instructions.");
370 EM_REG_COUNTER_USED(&pStats->StatMovLidt, "/EM/CPU%d/R3/PrivInst/Lidt", "Number of lidt instructions.");
371 EM_REG_COUNTER_USED(&pStats->StatMovLldt, "/EM/CPU%d/R3/PrivInst/Lldt", "Number of lldt instructions.");
372 EM_REG_COUNTER_USED(&pStats->StatSysEnter, "/EM/CPU%d/R3/PrivInst/Sysenter", "Number of sysenter instructions.");
373 EM_REG_COUNTER_USED(&pStats->StatSysExit, "/EM/CPU%d/R3/PrivInst/Sysexit", "Number of sysexit instructions.");
374 EM_REG_COUNTER_USED(&pStats->StatSysCall, "/EM/CPU%d/R3/PrivInst/Syscall", "Number of syscall instructions.");
375 EM_REG_COUNTER_USED(&pStats->StatSysRet, "/EM/CPU%d/R3/PrivInst/Sysret", "Number of sysret instructions.");
376
377 EM_REG_COUNTER(&pVCpu->em.s.StatTotalClis, "/EM/CPU%d/Cli/Total", "Total number of cli instructions executed.");
378 pVCpu->em.s.pCliStatTree = 0;
379
380 /* these should be considered for release statistics. */
381 EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction.");
382 EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged.");
383 EM_REG_COUNTER(&pVCpu->em.s.StatMiscEmu, "/PROF/CPU%d/EM/Emulation/Misc", "Profiling of emR3RawExecuteInstruction.");
384 EM_REG_PROFILE(&pVCpu->em.s.StatHwAccEntry, "/PROF/CPU%d/EM/HwAccEnter", "Profiling Hardware Accelerated Mode entry overhead.");
385 EM_REG_PROFILE(&pVCpu->em.s.StatHwAccExec, "/PROF/CPU%d/EM/HwAccExec", "Profiling Hardware Accelerated Mode execution.");
386 EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution.");
387 EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%d/EM/REMExec", "Profiling REM execution.");
388 EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing.");
389 EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead.");
390 EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution.");
391 EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead.");
392
393#endif /* VBOX_WITH_STATISTICS */
394
395 EM_REG_COUNTER(&pVCpu->em.s.StatForcedActions, "/PROF/CPU%d/EM/ForcedActions", "Profiling forced action execution.");
396 EM_REG_COUNTER(&pVCpu->em.s.StatHalted, "/PROF/CPU%d/EM/Halted", "Profiling halted state (VMR3WaitHalted).");
397 EM_REG_COUNTER(&pVCpu->em.s.StatREMTotal, "/PROF/CPU%d/EM/REMTotal", "Profiling emR3RemExecute (excluding FFs).");
398 EM_REG_COUNTER(&pVCpu->em.s.StatRAWTotal, "/PROF/CPU%d/EM/RAWTotal", "Profiling emR3RawExecute (excluding FFs).");
399
400 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatTotal, "/PROF/CPU%d/EM/Total", "Profiling EMR3ExecuteVM.");
401 }
402
403 return VINF_SUCCESS;
404}
405
406
407/**
408 * Initializes the per-VCPU EM.
409 *
410 * @returns VBox status code.
411 * @param pVM The VM to operate on.
412 */
413VMMR3DECL(int) EMR3InitCPU(PVM pVM)
414{
415 LogFlow(("EMR3InitCPU\n"));
416 return VINF_SUCCESS;
417}
418
419
420/**
421 * Applies relocations to data and code managed by this
422 * component. This function will be called at init and
423 * whenever the VMM need to relocate it self inside the GC.
424 *
425 * @param pVM The VM.
426 */
427VMMR3DECL(void) EMR3Relocate(PVM pVM)
428{
429 LogFlow(("EMR3Relocate\n"));
430 for (unsigned i=0;i<pVM->cCPUs;i++)
431 {
432 PVMCPU pVCpu = &pVM->aCpus[i];
433
434 if (pVCpu->em.s.pStatsR3)
435 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVCpu->em.s.pStatsR3);
436 }
437}
438
439
440/**
441 * Reset notification.
442 *
443 * @param pVM
444 */
445VMMR3DECL(void) EMR3Reset(PVM pVM)
446{
447 LogFlow(("EMR3Reset: \n"));
448 for (unsigned i=0;i<pVM->cCPUs;i++)
449 {
450 PVMCPU pVCpu = &pVM->aCpus[i];
451
452 pVCpu->em.s.fForceRAW = false;
453 }
454}
455
456
457/**
458 * Terminates the EM.
459 *
460 * Termination means cleaning up and freeing all resources,
461 * the VM it self is at this point powered off or suspended.
462 *
463 * @returns VBox status code.
464 * @param pVM The VM to operate on.
465 */
466VMMR3DECL(int) EMR3Term(PVM pVM)
467{
468 AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
469
470 PDMR3CritSectDelete(&pVM->em.s.CritSectREM);
471 return VINF_SUCCESS;
472}
473
474/**
475 * Terminates the per-VCPU EM.
476 *
477 * Termination means cleaning up and freeing all resources,
478 * the VM it self is at this point powered off or suspended.
479 *
480 * @returns VBox status code.
481 * @param pVM The VM to operate on.
482 */
483VMMR3DECL(int) EMR3TermCPU(PVM pVM)
484{
485 return 0;
486}
487
488/**
489 * Execute state save operation.
490 *
491 * @returns VBox status code.
492 * @param pVM VM Handle.
493 * @param pSSM SSM operation handle.
494 */
495static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
496{
497 for (VMCPUID i = 0; i < pVM->cCPUs; i++)
498 {
499 PVMCPU pVCpu = &pVM->aCpus[i];
500
501 int rc = SSMR3PutBool(pSSM, pVCpu->em.s.fForceRAW);
502 AssertRCReturn(rc, rc);
503
504 Assert(pVCpu->em.s.enmState == EMSTATE_SUSPENDED);
505 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
506 rc = SSMR3PutU32(pSSM, pVCpu->em.s.enmPrevState);
507 AssertRCReturn(rc, rc);
508 }
509 return VINF_SUCCESS;
510}
511
512
513/**
514 * Execute state load operation.
515 *
516 * @returns VBox status code.
517 * @param pVM VM Handle.
518 * @param pSSM SSM operation handle.
519 * @param uVersion Data layout version.
520 * @param uPhase The data phase.
521 */
522static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPhase)
523{
524 /*
525 * Validate version.
526 */
527 if ( uVersion != EM_SAVED_STATE_VERSION
528 && uVersion != EM_SAVED_STATE_VERSION_PRE_SMP)
529 {
530 AssertMsgFailed(("emR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, EM_SAVED_STATE_VERSION));
531 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
532 }
533
534 /*
535 * Load the saved state.
536 */
537 for (VMCPUID i = 0; i < pVM->cCPUs; i++)
538 {
539 PVMCPU pVCpu = &pVM->aCpus[i];
540
541 int rc = SSMR3GetBool(pSSM, &pVCpu->em.s.fForceRAW);
542 if (RT_FAILURE(rc))
543 pVCpu->em.s.fForceRAW = false;
544 AssertRCReturn(rc, rc);
545
546 if (uVersion > EM_SAVED_STATE_VERSION_PRE_SMP)
547 {
548 AssertCompile(sizeof(pVCpu->em.s.enmPrevState) == sizeof(uint32_t));
549 rc = SSMR3GetU32(pSSM, (uint32_t *)&pVCpu->em.s.enmPrevState);
550 AssertRCReturn(rc, rc);
551 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
552
553 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
554 }
555 Assert(!pVCpu->em.s.pCliStatTree);
556 }
557 return VINF_SUCCESS;
558}
559
560
561/**
562 * Raise a fatal error.
563 *
564 * Safely terminate the VM with full state report and stuff. This function
565 * will naturally never return.
566 *
567 * @param pVCpu VMCPU handle.
568 * @param rc VBox status code.
569 */
570VMMR3DECL(void) EMR3FatalError(PVMCPU pVCpu, int rc)
571{
572 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
573 longjmp(pVCpu->em.s.u.FatalLongJump, rc);
574 AssertReleaseMsgFailed(("longjmp returned!\n"));
575}
576
577
578/**
579 * Gets the EM state name.
580 *
581 * @returns pointer to read only state name,
582 * @param enmState The state.
583 */
584VMMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
585{
586 switch (enmState)
587 {
588 case EMSTATE_NONE: return "EMSTATE_NONE";
589 case EMSTATE_RAW: return "EMSTATE_RAW";
590 case EMSTATE_HWACC: return "EMSTATE_HWACC";
591 case EMSTATE_REM: return "EMSTATE_REM";
592 case EMSTATE_PARAV: return "EMSTATE_PARAV";
593 case EMSTATE_HALTED: return "EMSTATE_HALTED";
594 case EMSTATE_WAIT_SIPI: return "EMSTATE_WAIT_SIPI";
595 case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
596 case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
597 case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
598 case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
599 case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
600 case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
601 default: return "Unknown!";
602 }
603}
604
605
606#ifdef VBOX_WITH_STATISTICS
607/**
608 * Just a braindead function to keep track of cli addresses.
609 * @param pVM VM handle.
610 * @param pVMCPU VMCPU handle.
611 * @param GCPtrInstr The EIP of the cli instruction.
612 */
613static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
614{
615 PCLISTAT pRec;
616
617 pRec = (PCLISTAT)RTAvlPVGet(&pVCpu->em.s.pCliStatTree, (AVLPVKEY)GCPtrInstr);
618 if (!pRec)
619 {
620 /* New cli instruction; insert into the tree. */
621 pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
622 Assert(pRec);
623 if (!pRec)
624 return;
625 pRec->Core.Key = (AVLPVKEY)GCPtrInstr;
626
627 char szCliStatName[32];
628 RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
629 STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
630
631 bool fRc = RTAvlPVInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
632 Assert(fRc); NOREF(fRc);
633 }
634 STAM_COUNTER_INC(&pRec->Counter);
635 STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
636}
637#endif /* VBOX_WITH_STATISTICS */
638
639
640/**
641 * Debug loop.
642 *
643 * @returns VBox status code for EM.
644 * @param pVM VM handle.
645 * @param pVCpu VMCPU handle.
646 * @param rc Current EM VBox status code..
647 */
648static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc)
649{
650 for (;;)
651 {
652 Log(("emR3Debug: rc=%Rrc\n", rc));
653 const int rcLast = rc;
654
655 /*
656 * Debug related RC.
657 */
658 switch (rc)
659 {
660 /*
661 * Single step an instruction.
662 */
663 case VINF_EM_DBG_STEP:
664 if ( pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
665 || pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
666 || pVCpu->em.s.fForceRAW /* paranoia */)
667 rc = emR3RawStep(pVM, pVCpu);
668 else
669 {
670 Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
671 rc = emR3RemStep(pVM, pVCpu);
672 }
673 break;
674
675 /*
676 * Simple events: stepped, breakpoint, stop/assertion.
677 */
678 case VINF_EM_DBG_STEPPED:
679 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
680 break;
681
682 case VINF_EM_DBG_BREAKPOINT:
683 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
684 break;
685
686 case VINF_EM_DBG_STOP:
687 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
688 break;
689
690 case VINF_EM_DBG_HYPER_STEPPED:
691 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
692 break;
693
694 case VINF_EM_DBG_HYPER_BREAKPOINT:
695 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
696 break;
697
698 case VINF_EM_DBG_HYPER_ASSERTION:
699 RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
700 rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
701 break;
702
703 /*
704 * Guru meditation.
705 */
706 case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
707 rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
708 break;
709 case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
710 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
711 break;
712
713 default: /** @todo don't use default for guru, but make special errors code! */
714 rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
715 break;
716 }
717
718 /*
719 * Process the result.
720 */
721 do
722 {
723 switch (rc)
724 {
725 /*
726 * Continue the debugging loop.
727 */
728 case VINF_EM_DBG_STEP:
729 case VINF_EM_DBG_STOP:
730 case VINF_EM_DBG_STEPPED:
731 case VINF_EM_DBG_BREAKPOINT:
732 case VINF_EM_DBG_HYPER_STEPPED:
733 case VINF_EM_DBG_HYPER_BREAKPOINT:
734 case VINF_EM_DBG_HYPER_ASSERTION:
735 break;
736
737 /*
738 * Resuming execution (in some form) has to be done here if we got
739 * a hypervisor debug event.
740 */
741 case VINF_SUCCESS:
742 case VINF_EM_RESUME:
743 case VINF_EM_SUSPEND:
744 case VINF_EM_RESCHEDULE:
745 case VINF_EM_RESCHEDULE_RAW:
746 case VINF_EM_RESCHEDULE_REM:
747 case VINF_EM_HALT:
748 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
749 {
750 rc = emR3RawResumeHyper(pVM, pVCpu);
751 if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
752 continue;
753 }
754 if (rc == VINF_SUCCESS)
755 rc = VINF_EM_RESCHEDULE;
756 return rc;
757
758 /*
759 * The debugger isn't attached.
760 * We'll simply turn the thing off since that's the easiest thing to do.
761 */
762 case VERR_DBGF_NOT_ATTACHED:
763 switch (rcLast)
764 {
765 case VINF_EM_DBG_HYPER_STEPPED:
766 case VINF_EM_DBG_HYPER_BREAKPOINT:
767 case VINF_EM_DBG_HYPER_ASSERTION:
768 case VERR_TRPM_PANIC:
769 case VERR_TRPM_DONT_PANIC:
770 case VERR_VMM_RING0_ASSERTION:
771 case VERR_VMM_HYPER_CR3_MISMATCH:
772 case VERR_VMM_RING3_CALL_DISABLED:
773 return rcLast;
774 }
775 return VINF_EM_OFF;
776
777 /*
778 * Status codes terminating the VM in one or another sense.
779 */
780 case VINF_EM_TERMINATE:
781 case VINF_EM_OFF:
782 case VINF_EM_RESET:
783 case VINF_EM_NO_MEMORY:
784 case VINF_EM_RAW_STALE_SELECTOR:
785 case VINF_EM_RAW_IRET_TRAP:
786 case VERR_TRPM_PANIC:
787 case VERR_TRPM_DONT_PANIC:
788 case VERR_VMM_RING0_ASSERTION:
789 case VERR_VMM_HYPER_CR3_MISMATCH:
790 case VERR_VMM_RING3_CALL_DISABLED:
791 case VERR_INTERNAL_ERROR:
792 case VERR_INTERNAL_ERROR_2:
793 case VERR_INTERNAL_ERROR_3:
794 case VERR_INTERNAL_ERROR_4:
795 case VERR_INTERNAL_ERROR_5:
796 case VERR_IPE_UNEXPECTED_STATUS:
797 case VERR_IPE_UNEXPECTED_INFO_STATUS:
798 case VERR_IPE_UNEXPECTED_ERROR_STATUS:
799 return rc;
800
801 /*
802 * The rest is unexpected, and will keep us here.
803 */
804 default:
805 AssertMsgFailed(("Unxpected rc %Rrc!\n", rc));
806 break;
807 }
808 } while (false);
809 } /* debug for ever */
810}
811
812/**
813 * Steps recompiled code.
814 *
815 * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
816 * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
817 *
818 * @param pVM VM handle.
819 * @param pVCpu VMCPU handle.
820 */
821static int emR3RemStep(PVM pVM, PVMCPU pVCpu)
822{
823 LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
824
825 EMRemLock(pVM);
826
827 /*
828 * Switch to REM, step instruction, switch back.
829 */
830 int rc = REMR3State(pVM, pVCpu);
831 if (RT_SUCCESS(rc))
832 {
833 rc = REMR3Step(pVM, pVCpu);
834 REMR3StateBack(pVM, pVCpu);
835 }
836 EMRemUnlock(pVM);
837
838 LogFlow(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
839 return rc;
840}
841
842
843/**
844 * Executes recompiled code.
845 *
846 * This function contains the recompiler version of the inner
847 * execution loop (the outer loop being in EMR3ExecuteVM()).
848 *
849 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
850 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
851 *
852 * @param pVM VM handle.
853 * @param pVCpu VMCPU handle.
854 * @param pfFFDone Where to store an indicator telling wheter or not
855 * FFs were done before returning.
856 *
857 */
858static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
859{
860#ifdef LOG_ENABLED
861 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
862 uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
863
864 if (pCtx->eflags.Bits.u1VM)
865 Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
866 else
867 Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0));
868#endif
869 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatREMTotal, a);
870
871#if defined(VBOX_STRICT) && defined(DEBUG_bird)
872 AssertMsg( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
873 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVCpu)), /** @todo #1419 - get flat address. */
874 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
875#endif
876
877 /* Big lock, but you are not supposed to own any lock when coming in here. */
878 EMRemLock(pVM);
879
880 /*
881 * Spin till we get a forced action which returns anything but VINF_SUCCESS
882 * or the REM suggests raw-mode execution.
883 */
884 *pfFFDone = false;
885 bool fInREMState = false;
886 int rc = VINF_SUCCESS;
887
888 /* Flush the recompiler TLB if the VCPU has changed. */
889 if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
890 {
891 REMFlushTBs(pVM);
892 /* Also sync the entire state. */
893 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
894 }
895 pVM->em.s.idLastRemCpu = pVCpu->idCpu;
896
897 for (;;)
898 {
899 /*
900 * Update REM state if not already in sync.
901 */
902 if (!fInREMState)
903 {
904 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, b);
905 rc = REMR3State(pVM, pVCpu);
906 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, b);
907 if (RT_FAILURE(rc))
908 break;
909 fInREMState = true;
910
911 /*
912 * We might have missed the raising of VMREQ, TIMER and some other
913 * imporant FFs while we were busy switching the state. So, check again.
914 */
915 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_TERMINATE | VM_FF_RESET)
916 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER | VMCPU_FF_REQUEST))
917 {
918 LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fGlobalForcedActions));
919 goto l_REMDoForcedActions;
920 }
921 }
922
923
924 /*
925 * Execute REM.
926 */
927 STAM_PROFILE_START(&pVCpu->em.s.StatREMExec, c);
928 rc = REMR3Run(pVM, pVCpu);
929 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMExec, c);
930
931
932 /*
933 * Deal with high priority post execution FFs before doing anything else.
934 */
935 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
936 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
937 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
938
939 /*
940 * Process the returned status code.
941 * (Try keep this short! Call functions!)
942 */
943 if (rc != VINF_SUCCESS)
944 {
945 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
946 break;
947 if (rc != VINF_REM_INTERRUPED_FF)
948 {
949 /*
950 * Anything which is not known to us means an internal error
951 * and the termination of the VM!
952 */
953 AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
954 break;
955 }
956 }
957
958
959 /*
960 * Check and execute forced actions.
961 * Sync back the VM state before calling any of these.
962 */
963#ifdef VBOX_HIGH_RES_TIMERS_HACK
964 TMTimerPollVoid(pVM, pVCpu);
965#endif
966 AssertCompile((VMCPU_FF_ALL_BUT_RAW_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE)) & VMCPU_FF_TIMER);
967 if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK)
968 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_BUT_RAW_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE)))
969 {
970l_REMDoForcedActions:
971 if (fInREMState)
972 {
973 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, d);
974 REMR3StateBack(pVM, pVCpu);
975 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, d);
976 fInREMState = false;
977 }
978 STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatREMTotal, a);
979 rc = emR3ForcedActions(pVM, pVCpu, rc);
980 STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatREMTotal, a);
981 if ( rc != VINF_SUCCESS
982 && rc != VINF_EM_RESCHEDULE_REM)
983 {
984 *pfFFDone = true;
985 break;
986 }
987 }
988
989 } /* The Inner Loop, recompiled execution mode version. */
990
991
992 /*
993 * Returning. Sync back the VM state if required.
994 */
995 if (fInREMState)
996 {
997 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, e);
998 REMR3StateBack(pVM, pVCpu);
999 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, e);
1000 }
1001 EMRemUnlock(pVM);
1002
1003 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatREMTotal, a);
1004 return rc;
1005}
1006
1007
1008#ifdef DEBUG
1009
1010int emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1011{
1012 EMSTATE enmOldState = pVCpu->em.s.enmState;
1013
1014 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1015
1016 Log(("Single step BEGIN:\n"));
1017 for (uint32_t i = 0; i < cIterations; i++)
1018 {
1019 DBGFR3PrgStep(pVCpu);
1020 DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
1021 emR3RemStep(pVM, pVCpu);
1022 if (emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx) != EMSTATE_REM)
1023 break;
1024 }
1025 Log(("Single step END:\n"));
1026 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1027 pVCpu->em.s.enmState = enmOldState;
1028 return VINF_EM_RESCHEDULE;
1029}
1030
1031#endif /* DEBUG */
1032
1033
1034/**
1035 * Decides whether to execute RAW, HWACC or REM.
1036 *
1037 * @returns new EM state
1038 * @param pVM The VM.
1039 * @param pVCpu The VMCPU handle.
1040 * @param pCtx The CPU context.
1041 */
1042EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1043{
1044 /*
1045 * When forcing raw-mode execution, things are simple.
1046 */
1047 if (pVCpu->em.s.fForceRAW)
1048 return EMSTATE_RAW;
1049
1050 /*
1051 * We stay in the wait for SIPI state unless explicitly told otherwise.
1052 */
1053 if (pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI)
1054 return EMSTATE_WAIT_SIPI;
1055
1056 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1057 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1058 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1059
1060 X86EFLAGS EFlags = pCtx->eflags;
1061 if (HWACCMIsEnabled(pVM))
1062 {
1063 /* Hardware accelerated raw-mode:
1064 *
1065 * Typically only 32-bits protected mode, with paging enabled, code is allowed here.
1066 */
1067 if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
1068 return EMSTATE_HWACC;
1069
1070 /* Note: Raw mode and hw accelerated mode are incompatible. The latter turns
1071 * off monitoring features essential for raw mode! */
1072 return EMSTATE_REM;
1073 }
1074
1075 /*
1076 * Standard raw-mode:
1077 *
1078 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1079 * or 32 bits protected mode ring 0 code
1080 *
1081 * The tests are ordered by the likelyhood of being true during normal execution.
1082 */
1083 if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
1084 {
1085 Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
1086 return EMSTATE_REM;
1087 }
1088
1089#ifndef VBOX_RAW_V86
1090 if (EFlags.u32 & X86_EFL_VM) {
1091 Log2(("raw mode refused: VM_MASK\n"));
1092 return EMSTATE_REM;
1093 }
1094#endif
1095
1096 /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
1097 uint32_t u32CR0 = pCtx->cr0;
1098 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
1099 {
1100 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1101 return EMSTATE_REM;
1102 }
1103
1104 if (pCtx->cr4 & X86_CR4_PAE)
1105 {
1106 uint32_t u32Dummy, u32Features;
1107
1108 CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1109 if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
1110 return EMSTATE_REM;
1111 }
1112
1113 unsigned uSS = pCtx->ss;
1114 if ( pCtx->eflags.Bits.u1VM
1115 || (uSS & X86_SEL_RPL) == 3)
1116 {
1117 if (!EMIsRawRing3Enabled(pVM))
1118 return EMSTATE_REM;
1119
1120 if (!(EFlags.u32 & X86_EFL_IF))
1121 {
1122 Log2(("raw mode refused: IF (RawR3)\n"));
1123 return EMSTATE_REM;
1124 }
1125
1126 if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
1127 {
1128 Log2(("raw mode refused: CR0.WP + RawR0\n"));
1129 return EMSTATE_REM;
1130 }
1131 }
1132 else
1133 {
1134 if (!EMIsRawRing0Enabled(pVM))
1135 return EMSTATE_REM;
1136
1137 /* Only ring 0 supervisor code. */
1138 if ((uSS & X86_SEL_RPL) != 0)
1139 {
1140 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
1141 return EMSTATE_REM;
1142 }
1143
1144 // Let's start with pure 32 bits ring 0 code first
1145 /** @todo What's pure 32-bit mode? flat? */
1146 if ( !(pCtx->ssHid.Attr.n.u1DefBig)
1147 || !(pCtx->csHid.Attr.n.u1DefBig))
1148 {
1149 Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
1150 return EMSTATE_REM;
1151 }
1152
1153 /* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
1154 if (!(u32CR0 & X86_CR0_WP))
1155 {
1156 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1157 return EMSTATE_REM;
1158 }
1159
1160 if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
1161 {
1162 Log2(("raw r0 mode forced: patch code\n"));
1163 return EMSTATE_RAW;
1164 }
1165
1166#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1167 if (!(EFlags.u32 & X86_EFL_IF))
1168 {
1169 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
1170 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1171 return EMSTATE_REM;
1172 }
1173#endif
1174
1175 /** @todo still necessary??? */
1176 if (EFlags.Bits.u2IOPL != 0)
1177 {
1178 Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
1179 return EMSTATE_REM;
1180 }
1181 }
1182
1183 Assert(PGMPhysIsA20Enabled(pVCpu));
1184 return EMSTATE_RAW;
1185}
1186
1187
1188/**
1189 * Executes all high priority post execution force actions.
1190 *
1191 * @returns rc or a fatal status code.
1192 *
1193 * @param pVM VM handle.
1194 * @param pVCpu VMCPU handle.
1195 * @param rc The current rc.
1196 */
1197int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1198{
1199 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PDM_CRITSECT))
1200 PDMCritSectFF(pVCpu);
1201
1202 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION))
1203 CSAMR3DoPendingAction(pVM, pVCpu);
1204
1205 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1206 {
1207 if ( rc > VINF_EM_NO_MEMORY
1208 && rc <= VINF_EM_LAST)
1209 rc = VINF_EM_NO_MEMORY;
1210 }
1211
1212 return rc;
1213}
1214
1215
1216/**
1217 * Executes all pending forced actions.
1218 *
1219 * Forced actions can cause execution delays and execution
1220 * rescheduling. The first we deal with using action priority, so
1221 * that for instance pending timers aren't scheduled and ran until
1222 * right before execution. The rescheduling we deal with using
1223 * return codes. The same goes for VM termination, only in that case
1224 * we exit everything.
1225 *
1226 * @returns VBox status code of equal or greater importance/severity than rc.
1227 * The most important ones are: VINF_EM_RESCHEDULE,
1228 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1229 *
1230 * @param pVM VM handle.
1231 * @param pVCpu VMCPU handle.
1232 * @param rc The current rc.
1233 *
1234 */
1235int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1236{
1237 STAM_REL_PROFILE_START(&pVCpu->em.s.StatForcedActions, a);
1238#ifdef VBOX_STRICT
1239 int rcIrq = VINF_SUCCESS;
1240#endif
1241 int rc2;
1242#define UPDATE_RC() \
1243 do { \
1244 AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
1245 if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
1246 break; \
1247 if (!rc || rc2 < rc) \
1248 rc = rc2; \
1249 } while (0)
1250
1251 /*
1252 * Post execution chunk first.
1253 */
1254 if ( VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK)
1255 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK))
1256 {
1257 /*
1258 * EMT Rendezvous (must be serviced before termination).
1259 */
1260 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1261 VMMR3EmtRendezvousFF(pVM, pVCpu);
1262
1263 /*
1264 * Termination request.
1265 */
1266 if (VM_FF_ISPENDING(pVM, VM_FF_TERMINATE))
1267 {
1268 Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
1269 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1270 return VINF_EM_TERMINATE;
1271 }
1272
1273 /*
1274 * Debugger Facility polling.
1275 */
1276 if (VM_FF_ISPENDING(pVM, VM_FF_DBGF))
1277 {
1278 rc2 = DBGFR3VMMForcedAction(pVM);
1279 UPDATE_RC();
1280 }
1281
1282 /*
1283 * Postponed reset request.
1284 */
1285 if (VM_FF_TESTANDCLEAR(pVM, VM_FF_RESET))
1286 {
1287 rc2 = VMR3Reset(pVM);
1288 UPDATE_RC();
1289 }
1290
1291 /*
1292 * CSAM page scanning.
1293 */
1294 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1295 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE))
1296 {
1297 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1298
1299 /** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
1300 Log(("Forced action VMCPU_FF_CSAM_SCAN_PAGE\n"));
1301
1302 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1303 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE);
1304 }
1305
1306 /*
1307 * Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
1308 */
1309 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1310 {
1311 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1312 UPDATE_RC();
1313 if (rc == VINF_EM_NO_MEMORY)
1314 return rc;
1315 }
1316
1317 /* check that we got them all */
1318 AssertCompile(VM_FF_NORMAL_PRIORITY_POST_MASK == (VM_FF_TERMINATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1319 AssertCompile(VMCPU_FF_NORMAL_PRIORITY_POST_MASK == VMCPU_FF_CSAM_SCAN_PAGE);
1320 }
1321
1322 /*
1323 * Normal priority then.
1324 * (Executed in no particular order.)
1325 */
1326 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
1327 {
1328 /*
1329 * PDM Queues are pending.
1330 */
1331 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
1332 PDMR3QueueFlushAll(pVM);
1333
1334 /*
1335 * PDM DMA transfers are pending.
1336 */
1337 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
1338 PDMR3DmaRun(pVM);
1339
1340 /*
1341 * EMT Rendezvous (make sure they are handled before the requests).
1342 */
1343 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1344 VMMR3EmtRendezvousFF(pVM, pVCpu);
1345
1346 /*
1347 * Requests from other threads.
1348 */
1349 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
1350 {
1351 rc2 = VMR3ReqProcessU(pVM->pUVM, VMCPUID_ANY);
1352 Assert(rc2 != VINF_EM_RESET); /* should be per-VCPU */
1353 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE)
1354 {
1355 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1356 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1357 return rc2;
1358 }
1359 UPDATE_RC();
1360 }
1361
1362 /* Replay the handler notification changes. */
1363 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REM_HANDLER_NOTIFY, VM_FF_PGM_NO_MEMORY))
1364 {
1365 /* Try not to cause deadlocks. */
1366 if ( pVM->cCPUs == 1
1367 || ( !PGMIsLockOwner(pVM)
1368 && !IOMIsLockOwner(pVM))
1369 )
1370 {
1371 EMRemLock(pVM);
1372 REMR3ReplayHandlerNotifications(pVM);
1373 EMRemUnlock(pVM);
1374 }
1375 }
1376
1377 /* check that we got them all */
1378 AssertCompile(VM_FF_NORMAL_PRIORITY_MASK == (VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_REM_HANDLER_NOTIFY | VM_FF_EMT_RENDEZVOUS));
1379 }
1380
1381 /*
1382 * Normal priority then. (per-VCPU)
1383 * (Executed in no particular order.)
1384 */
1385 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1386 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK))
1387 {
1388 /*
1389 * Requests from other threads.
1390 */
1391 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1392 {
1393 rc2 = VMR3ReqProcessU(pVM->pUVM, pVCpu->idCpu);
1394 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE || rc2 == VINF_EM_RESET)
1395 {
1396 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1397 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1398 return rc2;
1399 }
1400 UPDATE_RC();
1401 }
1402
1403 /* check that we got them all */
1404 Assert(!(VMCPU_FF_NORMAL_PRIORITY_MASK & ~(VMCPU_FF_REQUEST)));
1405 }
1406
1407 /*
1408 * High priority pre execution chunk last.
1409 * (Executed in ascending priority order.)
1410 */
1411 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK)
1412 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK))
1413 {
1414 /*
1415 * Timers before interrupts.
1416 */
1417 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER)
1418 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1419 TMR3TimerQueuesDo(pVM);
1420
1421 /*
1422 * The instruction following an emulated STI should *always* be executed!
1423 */
1424 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1425 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1426 {
1427 Log(("VM_FF_EMULATED_STI at %RGv successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu), EMGetInhibitInterruptsPC(pVCpu)));
1428 if (CPUMGetGuestEIP(pVCpu) != EMGetInhibitInterruptsPC(pVCpu))
1429 {
1430 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
1431 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1432 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1433 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1434 */
1435 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1436 }
1437 if (HWACCMR3IsActive(pVCpu))
1438 rc2 = VINF_EM_RESCHEDULE_HWACC;
1439 else
1440 rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
1441
1442 UPDATE_RC();
1443 }
1444
1445 /*
1446 * Interrupts.
1447 */
1448 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1449 && !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1450 && (!rc || rc >= VINF_EM_RESCHEDULE_HWACC)
1451 && !TRPMHasTrap(pVCpu) /* an interrupt could already be scheduled for dispatching in the recompiler. */
1452 && PATMAreInterruptsEnabled(pVM)
1453 && !HWACCMR3IsEventPending(pVCpu))
1454 {
1455 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1456 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
1457 {
1458 /* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
1459 /** @todo this really isn't nice, should properly handle this */
1460 rc2 = TRPMR3InjectEvent(pVM, pVCpu, TRPM_HARDWARE_INT);
1461#ifdef VBOX_STRICT
1462 rcIrq = rc2;
1463#endif
1464 UPDATE_RC();
1465 }
1466 /** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
1467 else if (REMR3QueryPendingInterrupt(pVM, pVCpu) != REM_NO_PENDING_IRQ)
1468 {
1469 rc2 = VINF_EM_RESCHEDULE_REM;
1470 UPDATE_RC();
1471 }
1472 }
1473
1474 /*
1475 * Allocate handy pages.
1476 */
1477 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1478 {
1479 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1480 UPDATE_RC();
1481 }
1482
1483 /*
1484 * Debugger Facility request.
1485 */
1486 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_DBGF, VM_FF_PGM_NO_MEMORY))
1487 {
1488 rc2 = DBGFR3VMMForcedAction(pVM);
1489 UPDATE_RC();
1490 }
1491
1492 /*
1493 * EMT Rendezvous (must be serviced before termination).
1494 */
1495 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1496 VMMR3EmtRendezvousFF(pVM, pVCpu);
1497
1498 /*
1499 * Termination request.
1500 */
1501 if (VM_FF_ISPENDING(pVM, VM_FF_TERMINATE))
1502 {
1503 Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
1504 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1505 return VINF_EM_TERMINATE;
1506 }
1507
1508 /*
1509 * Out of memory? Since most of our fellow high priority actions may cause us
1510 * to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
1511 * at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
1512 * than us since we can terminate without allocating more memory.
1513 */
1514 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1515 {
1516 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1517 UPDATE_RC();
1518 if (rc == VINF_EM_NO_MEMORY)
1519 return rc;
1520 }
1521
1522 /*
1523 * If the virtual sync clock is still stopped, make TM restart it.
1524 */
1525 if (VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
1526 TMR3VirtualSyncFF(pVM, pVCpu);
1527
1528#ifdef DEBUG
1529 /*
1530 * Debug, pause the VM.
1531 */
1532 if (VM_FF_ISPENDING(pVM, VM_FF_DEBUG_SUSPEND))
1533 {
1534 VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
1535 Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
1536 return VINF_EM_SUSPEND;
1537 }
1538#endif
1539
1540 /* check that we got them all */
1541 AssertCompile(VM_FF_HIGH_PRIORITY_PRE_MASK == (VM_FF_TM_VIRTUAL_SYNC | VM_FF_DBGF | VM_FF_TERMINATE | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1542 AssertCompile(VMCPU_FF_HIGH_PRIORITY_PRE_MASK == (VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_INHIBIT_INTERRUPTS));
1543 }
1544
1545#undef UPDATE_RC
1546 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1547 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1548 Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
1549 return rc;
1550}
1551
1552/**
1553 * Release the IOM lock if owned by the current VCPU
1554 *
1555 * @param pVM The VM to operate on.
1556 */
1557VMMR3DECL(void) EMR3ReleaseOwnedLocks(PVM pVM)
1558{
1559 while (PDMCritSectIsOwner(&pVM->em.s.CritSectREM))
1560 PDMCritSectLeave(&pVM->em.s.CritSectREM);
1561}
1562
1563
1564/**
1565 * Execute VM.
1566 *
1567 * This function is the main loop of the VM. The emulation thread
1568 * calls this function when the VM has been successfully constructed
1569 * and we're ready for executing the VM.
1570 *
1571 * Returning from this function means that the VM is turned off or
1572 * suspended (state already saved) and deconstruction in next in line.
1573 *
1574 * All interaction from other thread are done using forced actions
1575 * and signaling of the wait object.
1576 *
1577 * @returns VBox status code, informational status codes may indicate failure.
1578 * @param pVM The VM to operate on.
1579 * @param pVCpu The VMCPU to operate on.
1580 */
1581VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
1582{
1583 LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
1584 pVCpu->em.s.enmState, EMR3GetStateName(pVCpu->em.s.enmState), pVCpu->em.s.fForceRAW));
1585 VM_ASSERT_EMT(pVM);
1586 AssertMsg( pVCpu->em.s.enmState == EMSTATE_NONE
1587 || pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI
1588 || pVCpu->em.s.enmState == EMSTATE_SUSPENDED,
1589 ("%s\n", EMR3GetStateName(pVCpu->em.s.enmState)));
1590
1591 int rc = setjmp(pVCpu->em.s.u.FatalLongJump);
1592 if (rc == 0)
1593 {
1594 /*
1595 * Start the virtual time.
1596 */
1597 TMR3NotifyResume(pVM, pVCpu);
1598
1599 /*
1600 * The Outer Main Loop.
1601 */
1602 bool fFFDone = false;
1603
1604 /* Reschedule right away to start in the right state. */
1605 rc = VINF_SUCCESS;
1606
1607 /* If resuming after a pause or a state load, restore the previous
1608 state or else we'll start executing code. Else, just reschedule. */
1609 if ( pVCpu->em.s.enmState == EMSTATE_SUSPENDED
1610 && ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
1611 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED))
1612 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
1613 else
1614 pVCpu->em.s.enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1615
1616 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
1617 for (;;)
1618 {
1619 /*
1620 * Before we can schedule anything (we're here because
1621 * scheduling is required) we must service any pending
1622 * forced actions to avoid any pending action causing
1623 * immediate rescheduling upon entering an inner loop
1624 *
1625 * Do forced actions.
1626 */
1627 if ( !fFFDone
1628 && rc != VINF_EM_TERMINATE
1629 && rc != VINF_EM_OFF
1630 && ( VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK)
1631 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_BUT_RAW_MASK)))
1632 {
1633 rc = emR3ForcedActions(pVM, pVCpu, rc);
1634 if ( ( rc == VINF_EM_RESCHEDULE_REM
1635 || rc == VINF_EM_RESCHEDULE_HWACC)
1636 && pVCpu->em.s.fForceRAW)
1637 rc = VINF_EM_RESCHEDULE_RAW;
1638 }
1639 else if (fFFDone)
1640 fFFDone = false;
1641
1642 /*
1643 * Now what to do?
1644 */
1645 Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
1646 switch (rc)
1647 {
1648 /*
1649 * Keep doing what we're currently doing.
1650 */
1651 case VINF_SUCCESS:
1652 break;
1653
1654 /*
1655 * Reschedule - to raw-mode execution.
1656 */
1657 case VINF_EM_RESCHEDULE_RAW:
1658 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVCpu->em.s.enmState, EMSTATE_RAW));
1659 pVCpu->em.s.enmState = EMSTATE_RAW;
1660 break;
1661
1662 /*
1663 * Reschedule - to hardware accelerated raw-mode execution.
1664 */
1665 case VINF_EM_RESCHEDULE_HWACC:
1666 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVCpu->em.s.enmState, EMSTATE_HWACC));
1667 Assert(!pVCpu->em.s.fForceRAW);
1668 pVCpu->em.s.enmState = EMSTATE_HWACC;
1669 break;
1670
1671 /*
1672 * Reschedule - to recompiled execution.
1673 */
1674 case VINF_EM_RESCHEDULE_REM:
1675 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVCpu->em.s.enmState, EMSTATE_REM));
1676 pVCpu->em.s.enmState = EMSTATE_REM;
1677 break;
1678
1679#ifdef VBOX_WITH_VMI
1680 /*
1681 * Reschedule - parav call.
1682 */
1683 case VINF_EM_RESCHEDULE_PARAV:
1684 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_PARAV: %d -> %d (EMSTATE_PARAV)\n", pVCpu->em.s.enmState, EMSTATE_PARAV));
1685 pVCpu->em.s.enmState = EMSTATE_PARAV;
1686 break;
1687#endif
1688
1689 /*
1690 * Resume.
1691 */
1692 case VINF_EM_RESUME:
1693 Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVCpu->em.s.enmState));
1694 /* Don't reschedule in the halted or wait for SIPI case. */
1695 if ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
1696 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED)
1697 break;
1698 /* fall through and get scheduled. */
1699
1700 /*
1701 * Reschedule.
1702 */
1703 case VINF_EM_RESCHEDULE:
1704 {
1705 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1706 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, EMR3GetStateName(enmState)));
1707 pVCpu->em.s.enmState = enmState;
1708 break;
1709 }
1710
1711 /*
1712 * Halted.
1713 */
1714 case VINF_EM_HALT:
1715 Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_HALTED));
1716 pVCpu->em.s.enmState = EMSTATE_HALTED;
1717 break;
1718
1719 /*
1720 * Switch to the wait for SIPI state (application processor only)
1721 */
1722 case VINF_EM_WAIT_SIPI:
1723 Assert(pVCpu->idCpu != 0);
1724 Log2(("EMR3ExecuteVM: VINF_EM_WAIT_SIPI: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_WAIT_SIPI));
1725 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
1726 break;
1727
1728
1729 /*
1730 * Suspend.
1731 */
1732 case VINF_EM_SUSPEND:
1733 Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
1734 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
1735 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
1736 break;
1737
1738 /*
1739 * Reset.
1740 * We might end up doing a double reset for now, we'll have to clean up the mess later.
1741 */
1742 case VINF_EM_RESET:
1743 {
1744 if (pVCpu->idCpu == 0)
1745 {
1746 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1747 Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, EMR3GetStateName(enmState)));
1748 pVCpu->em.s.enmState = enmState;
1749 }
1750 else
1751 {
1752 /* All other VCPUs go into the wait for SIPI state. */
1753 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
1754 }
1755 break;
1756 }
1757
1758 /*
1759 * Power Off.
1760 */
1761 case VINF_EM_OFF:
1762 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
1763 Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
1764 TMR3NotifySuspend(pVM, pVCpu);
1765 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1766 return rc;
1767
1768 /*
1769 * Terminate the VM.
1770 */
1771 case VINF_EM_TERMINATE:
1772 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
1773 Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
1774 if (pVM->enmVMState < VMSTATE_DESTROYING) /* ugly */
1775 TMR3NotifySuspend(pVM, pVCpu);
1776 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1777 return rc;
1778
1779
1780 /*
1781 * Out of memory, suspend the VM and stuff.
1782 */
1783 case VINF_EM_NO_MEMORY:
1784 Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
1785 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
1786 TMR3NotifySuspend(pVM, pVCpu);
1787 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1788
1789 rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
1790 N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
1791 if (rc != VINF_EM_SUSPEND)
1792 {
1793 if (RT_SUCCESS_NP(rc))
1794 {
1795 AssertLogRelMsgFailed(("%Rrc\n", rc));
1796 rc = VERR_EM_INTERNAL_ERROR;
1797 }
1798 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
1799 }
1800 return rc;
1801
1802 /*
1803 * Guest debug events.
1804 */
1805 case VINF_EM_DBG_STEPPED:
1806 AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
1807 case VINF_EM_DBG_STOP:
1808 case VINF_EM_DBG_BREAKPOINT:
1809 case VINF_EM_DBG_STEP:
1810 if (pVCpu->em.s.enmState == EMSTATE_RAW)
1811 {
1812 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
1813 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1814 }
1815 else
1816 {
1817 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
1818 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1819 }
1820 break;
1821
1822 /*
1823 * Hypervisor debug events.
1824 */
1825 case VINF_EM_DBG_HYPER_STEPPED:
1826 case VINF_EM_DBG_HYPER_BREAKPOINT:
1827 case VINF_EM_DBG_HYPER_ASSERTION:
1828 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_HYPER));
1829 pVCpu->em.s.enmState = EMSTATE_DEBUG_HYPER;
1830 break;
1831
1832 /*
1833 * Guru mediations.
1834 */
1835 case VERR_VMM_RING0_ASSERTION:
1836 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVCpu->em.s.enmState, EMSTATE_GURU_MEDITATION));
1837 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
1838 break;
1839
1840 /*
1841 * Any error code showing up here other than the ones we
1842 * know and process above are considered to be FATAL.
1843 *
1844 * Unknown warnings and informational status codes are also
1845 * included in this.
1846 */
1847 default:
1848 if (RT_SUCCESS_NP(rc))
1849 {
1850 AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
1851 rc = VERR_EM_INTERNAL_ERROR;
1852 }
1853 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
1854 Log(("EMR3ExecuteVM returns %d\n", rc));
1855 break;
1856 }
1857
1858 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x); /* (skip this in release) */
1859 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
1860
1861 /*
1862 * Act on the state.
1863 */
1864 switch (pVCpu->em.s.enmState)
1865 {
1866 /*
1867 * Execute raw.
1868 */
1869 case EMSTATE_RAW:
1870 rc = emR3RawExecute(pVM, pVCpu, &fFFDone);
1871 break;
1872
1873 /*
1874 * Execute hardware accelerated raw.
1875 */
1876 case EMSTATE_HWACC:
1877 rc = emR3HwAccExecute(pVM, pVCpu, &fFFDone);
1878 break;
1879
1880 /*
1881 * Execute recompiled.
1882 */
1883 case EMSTATE_REM:
1884 rc = emR3RemExecute(pVM, pVCpu, &fFFDone);
1885 Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
1886 break;
1887
1888#ifdef VBOX_WITH_VMI
1889 /*
1890 * Execute PARAV function.
1891 */
1892 case EMSTATE_PARAV:
1893 rc = PARAVCallFunction(pVM);
1894 pVCpu->em.s.enmState = EMSTATE_REM;
1895 break;
1896#endif
1897
1898 /*
1899 * Application processor execution halted until SIPI.
1900 */
1901 case EMSTATE_WAIT_SIPI:
1902 /* no break */
1903 /*
1904 * hlt - execution halted until interrupt.
1905 */
1906 case EMSTATE_HALTED:
1907 {
1908 STAM_REL_PROFILE_START(&pVCpu->em.s.StatHalted, y);
1909 rc = VMR3WaitHalted(pVM, pVCpu, !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
1910 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHalted, y);
1911 break;
1912 }
1913
1914 /*
1915 * Suspended - return to VM.cpp.
1916 */
1917 case EMSTATE_SUSPENDED:
1918 TMR3NotifySuspend(pVM, pVCpu);
1919 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1920 return VINF_EM_SUSPEND;
1921
1922 /*
1923 * Debugging in the guest.
1924 */
1925 case EMSTATE_DEBUG_GUEST_REM:
1926 case EMSTATE_DEBUG_GUEST_RAW:
1927 TMR3NotifySuspend(pVM, pVCpu);
1928 rc = emR3Debug(pVM, pVCpu, rc);
1929 TMR3NotifyResume(pVM, pVCpu);
1930 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
1931 break;
1932
1933 /*
1934 * Debugging in the hypervisor.
1935 */
1936 case EMSTATE_DEBUG_HYPER:
1937 {
1938 TMR3NotifySuspend(pVM, pVCpu);
1939 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1940
1941 rc = emR3Debug(pVM, pVCpu, rc);
1942 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
1943 if (rc != VINF_SUCCESS)
1944 {
1945 /* switch to guru meditation mode */
1946 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
1947 VMMR3FatalDump(pVM, pVCpu, rc);
1948 return rc;
1949 }
1950
1951 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
1952 TMR3NotifyResume(pVM, pVCpu);
1953 break;
1954 }
1955
1956 /*
1957 * Guru meditation takes place in the debugger.
1958 */
1959 case EMSTATE_GURU_MEDITATION:
1960 {
1961 TMR3NotifySuspend(pVM, pVCpu);
1962 VMMR3FatalDump(pVM, pVCpu, rc);
1963 emR3Debug(pVM, pVCpu, rc);
1964 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1965 return rc;
1966 }
1967
1968 /*
1969 * The states we don't expect here.
1970 */
1971 case EMSTATE_NONE:
1972 case EMSTATE_TERMINATING:
1973 default:
1974 AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVCpu->em.s.enmState));
1975 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
1976 TMR3NotifySuspend(pVM, pVCpu);
1977 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1978 return VERR_EM_INTERNAL_ERROR;
1979 }
1980 } /* The Outer Main Loop */
1981 }
1982 else
1983 {
1984 /*
1985 * Fatal error.
1986 */
1987 LogFlow(("EMR3ExecuteVM: returns %Rrc (longjmp / fatal error)\n", rc));
1988 TMR3NotifySuspend(pVM, pVCpu);
1989 VMMR3FatalDump(pVM, pVCpu, rc);
1990 emR3Debug(pVM, pVCpu, rc);
1991 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1992 /** @todo change the VM state! */
1993 return rc;
1994 }
1995
1996 /* (won't ever get here). */
1997 AssertFailed();
1998}
1999
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