EM.cpp@ 2397

Last change on this file since 2397 was 2232, checked in by vboxsync, 18 years ago
Put back 20576. Not sure what went wrong before.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 140.7 KB

Line
1	/* $Id: EM.cpp 2232 2007-04-19 14:19:16Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor/Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/** @page pg_em EM - The Execution Monitor/Manager
24	*
25	* The Execution Monitor/Manager is responsible for running the VM, scheduling
26	* the right kind of execution (Raw, Recompiled, Interpreted,..), and keeping
27	* the CPU states in sync. The function RMR3ExecuteVM() is the 'main-loop' of
28	* the VM.
29	*
30	*/
31
32	/*******************************************************************************
33	* Header Files *
34	*******************************************************************************/
35	#define LOG_GROUP LOG_GROUP_EM
36	#include <VBox/em.h>
37	#include <VBox/vmm.h>
38	#include <VBox/patm.h>
39	#include <VBox/csam.h>
40	#include <VBox/selm.h>
41	#include <VBox/trpm.h>
42	#include <VBox/iom.h>
43	#include <VBox/dbgf.h>
44	#include <VBox/pgm.h>
45	#include <VBox/rem.h>
46	#include <VBox/tm.h>
47	#include <VBox/mm.h>
48	#include <VBox/pdm.h>
49	#include <VBox/hwaccm.h>
50	#include <VBox/patm.h>
51	#include "EMInternal.h"
52	#include <VBox/vm.h>
53	#include <VBox/cpumdis.h>
54	#include <VBox/dis.h>
55	#include <VBox/disopcode.h>
56	#include <VBox/dbgf.h>
57
58	#include <VBox/log.h>
59	#include <iprt/thread.h>
60	#include <iprt/assert.h>
61	#include <iprt/asm.h>
62	#include <iprt/semaphore.h>
63	#include <iprt/string.h>
64	#include <iprt/avl.h>
65	#include <iprt/stream.h>
66	#include <VBox/param.h>
67	#include <VBox/err.h>
68
69
70	/*******************************************************************************
71	* Internal Functions *
72	*******************************************************************************/
73	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
74	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
75	static int emR3Debug(PVM pVM, int rc);
76	static int emR3RemStep(PVM pVM);
77	static int emR3RemExecute(PVM pVM, bool *pfFFDone);
78	static int emR3RawResumeHyper(PVM pVM);
79	static int emR3RawStep(PVM pVM);
80	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
81	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
82	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
83	static int emR3RawExecute(PVM pVM, bool *pfFFDone);
84	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
85	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
86	static int emR3ForcedActions(PVM pVM, int rc);
87	static int emR3RawGuestTrap(PVM pVM);
88
89
90	/**
91	* Initializes the EM.
92	*
93	* @returns VBox status code.
94	* @param pVM The VM to operate on.
95	*/
96	EMR3DECL(int) EMR3Init(PVM pVM)
97	{
98	LogFlow(("EMR3Init\n"));
99	/*
100	* Assert alignment and sizes.
101	*/
102	AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
103	AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
104	AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
105	("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
106
107	/*
108	* Init the structure.
109	*/
110	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
111	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
112	if (VBOX_FAILURE(rc))
113	pVM->fRawR3Enabled = true;
114	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
115	if (VBOX_FAILURE(rc))
116	pVM->fRawR0Enabled = true;
117	Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
118	pVM->em.s.enmState = EMSTATE_NONE;
119	pVM->em.s.fForceRAW = false;
120
121	rc = CPUMQueryGuestCtxPtr(pVM, &pVM->em.s.pCtx);
122	AssertMsgRC(rc, ("CPUMQueryGuestCtxPtr -> %Vrc\n", rc));
123	pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
124	AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
125
126	/*
127	* Saved state.
128	*/
129	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
130	NULL, emR3Save, NULL,
131	NULL, emR3Load, NULL);
132	if (VBOX_FAILURE(rc))
133	return rc;
134
135	/*
136	* Statistics.
137	*/
138	#ifdef VBOX_WITH_STATISTICS
139	PEMSTATS pStats;
140	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
141	if (VBOX_FAILURE(rc))
142	return rc;
143	pVM->em.s.pStatsHC = pStats;
144	pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pStats);
145
146	STAM_REG(pVM, &pStats->StatGCEmulate, STAMTYPE_PROFILE, "/EM/GC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
147	STAM_REG(pVM, &pStats->StatHCEmulate, STAMTYPE_PROFILE, "/EM/HC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
148
149	STAM_REG(pVM, &pStats->StatGCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
150	STAM_REG(pVM, &pStats->StatHCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
151
152	STAM_REG_USED(pVM, &pStats->StatGCAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
153	STAM_REG_USED(pVM, &pStats->StatHCAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
154	STAM_REG_USED(pVM, &pStats->StatGCAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
155	STAM_REG_USED(pVM, &pStats->StatHCAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
156	STAM_REG_USED(pVM, &pStats->StatGCAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
157	STAM_REG_USED(pVM, &pStats->StatHCAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
158	STAM_REG_USED(pVM, &pStats->StatGCSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
159	STAM_REG_USED(pVM, &pStats->StatHCSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
160	STAM_REG_USED(pVM, &pStats->StatGCCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
161	STAM_REG_USED(pVM, &pStats->StatHCCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
162	STAM_REG_USED(pVM, &pStats->StatGCDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
163	STAM_REG_USED(pVM, &pStats->StatHCDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
164	STAM_REG_USED(pVM, &pStats->StatGCHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
165	STAM_REG_USED(pVM, &pStats->StatHCHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
166	STAM_REG_USED(pVM, &pStats->StatGCInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
167	STAM_REG_USED(pVM, &pStats->StatHCInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
168	STAM_REG_USED(pVM, &pStats->StatGCInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
169	STAM_REG_USED(pVM, &pStats->StatHCInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
170	STAM_REG_USED(pVM, &pStats->StatGCIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
171	STAM_REG_USED(pVM, &pStats->StatHCIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
172	STAM_REG_USED(pVM, &pStats->StatGCLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
173	STAM_REG_USED(pVM, &pStats->StatHCLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
174	STAM_REG_USED(pVM, &pStats->StatGCMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
175	STAM_REG_USED(pVM, &pStats->StatHCMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
176	STAM_REG_USED(pVM, &pStats->StatGCMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
177	STAM_REG_USED(pVM, &pStats->StatHCMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
178	STAM_REG_USED(pVM, &pStats->StatGCMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
179	STAM_REG_USED(pVM, &pStats->StatHCMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
180	STAM_REG_USED(pVM, &pStats->StatGCOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
181	STAM_REG_USED(pVM, &pStats->StatHCOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
182	STAM_REG_USED(pVM, &pStats->StatGCPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
183	STAM_REG_USED(pVM, &pStats->StatHCPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
184	STAM_REG_USED(pVM, &pStats->StatGCRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
185	STAM_REG_USED(pVM, &pStats->StatHCRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
186	STAM_REG_USED(pVM, &pStats->StatGCSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
187	STAM_REG_USED(pVM, &pStats->StatHCSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
188	STAM_REG_USED(pVM, &pStats->StatGCXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
189	STAM_REG_USED(pVM, &pStats->StatHCXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
190	STAM_REG_USED(pVM, &pStats->StatGCXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
191	STAM_REG_USED(pVM, &pStats->StatHCXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
192	STAM_REG_USED(pVM, &pStats->StatGCMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
193	STAM_REG_USED(pVM, &pStats->StatHCMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
194	STAM_REG_USED(pVM, &pStats->StatGCMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
195	STAM_REG_USED(pVM, &pStats->StatHCMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
196	STAM_REG_USED(pVM, &pStats->StatGCBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
197	STAM_REG_USED(pVM, &pStats->StatHCBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
198	STAM_REG_USED(pVM, &pStats->StatGCBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
199	STAM_REG_USED(pVM, &pStats->StatHCBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
200	STAM_REG_USED(pVM, &pStats->StatGCBtc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
201	STAM_REG_USED(pVM, &pStats->StatHCBtc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
202	STAM_REG_USED(pVM, &pStats->StatGCCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
203	STAM_REG_USED(pVM, &pStats->StatHCCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
204
205	STAM_REG(pVM, &pStats->StatGCInterpretFailed, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
206	STAM_REG(pVM, &pStats->StatHCInterpretFailed, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
207
208	STAM_REG_USED(pVM, &pStats->StatGCFailedAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
209	STAM_REG_USED(pVM, &pStats->StatHCFailedAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
210	STAM_REG_USED(pVM, &pStats->StatGCFailedCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
211	STAM_REG_USED(pVM, &pStats->StatHCFailedCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
212	STAM_REG_USED(pVM, &pStats->StatGCFailedDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
213	STAM_REG_USED(pVM, &pStats->StatHCFailedDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
214	STAM_REG_USED(pVM, &pStats->StatGCFailedHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
215	STAM_REG_USED(pVM, &pStats->StatHCFailedHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
216	STAM_REG_USED(pVM, &pStats->StatGCFailedInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
217	STAM_REG_USED(pVM, &pStats->StatHCFailedInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
218	STAM_REG_USED(pVM, &pStats->StatGCFailedInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
219	STAM_REG_USED(pVM, &pStats->StatHCFailedInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
220	STAM_REG_USED(pVM, &pStats->StatGCFailedIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
221	STAM_REG_USED(pVM, &pStats->StatHCFailedIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
222	STAM_REG_USED(pVM, &pStats->StatGCFailedLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
223	STAM_REG_USED(pVM, &pStats->StatHCFailedLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
224	STAM_REG_USED(pVM, &pStats->StatGCFailedMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
225	STAM_REG_USED(pVM, &pStats->StatHCFailedMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
226	STAM_REG_USED(pVM, &pStats->StatGCFailedMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
227	STAM_REG_USED(pVM, &pStats->StatHCFailedMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
228	STAM_REG_USED(pVM, &pStats->StatGCFailedMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
229	STAM_REG_USED(pVM, &pStats->StatHCFailedMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
230	STAM_REG_USED(pVM, &pStats->StatGCFailedOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
231	STAM_REG_USED(pVM, &pStats->StatHCFailedOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
232	STAM_REG_USED(pVM, &pStats->StatGCFailedPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
233	STAM_REG_USED(pVM, &pStats->StatHCFailedPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
234	STAM_REG_USED(pVM, &pStats->StatGCFailedSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
235	STAM_REG_USED(pVM, &pStats->StatHCFailedSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
236	STAM_REG_USED(pVM, &pStats->StatGCFailedXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
237	STAM_REG_USED(pVM, &pStats->StatHCFailedXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
238	STAM_REG_USED(pVM, &pStats->StatGCFailedXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
239	STAM_REG_USED(pVM, &pStats->StatHCFailedXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
240	STAM_REG_USED(pVM, &pStats->StatGCFailedMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
241	STAM_REG_USED(pVM, &pStats->StatHCFailedMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
242	STAM_REG_USED(pVM, &pStats->StatGCFailedMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
243	STAM_REG_USED(pVM, &pStats->StatHCFailedMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
244	STAM_REG_USED(pVM, &pStats->StatGCFailedRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
245	STAM_REG_USED(pVM, &pStats->StatHCFailedRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
246
247	STAM_REG_USED(pVM, &pStats->StatGCFailedMisc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
248	STAM_REG_USED(pVM, &pStats->StatHCFailedMisc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
249	STAM_REG_USED(pVM, &pStats->StatGCFailedAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
250	STAM_REG_USED(pVM, &pStats->StatHCFailedAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
251	STAM_REG_USED(pVM, &pStats->StatGCFailedAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
252	STAM_REG_USED(pVM, &pStats->StatHCFailedAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
253	STAM_REG_USED(pVM, &pStats->StatGCFailedBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
254	STAM_REG_USED(pVM, &pStats->StatHCFailedBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
255	STAM_REG_USED(pVM, &pStats->StatGCFailedBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
256	STAM_REG_USED(pVM, &pStats->StatHCFailedBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
257	STAM_REG_USED(pVM, &pStats->StatGCFailedBtc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
258	STAM_REG_USED(pVM, &pStats->StatHCFailedBtc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
259	STAM_REG_USED(pVM, &pStats->StatGCFailedCli, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
260	STAM_REG_USED(pVM, &pStats->StatHCFailedCli, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
261	STAM_REG_USED(pVM, &pStats->StatGCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
262	STAM_REG_USED(pVM, &pStats->StatHCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
263	STAM_REG_USED(pVM, &pStats->StatGCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
264	STAM_REG_USED(pVM, &pStats->StatHCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
265	STAM_REG_USED(pVM, &pStats->StatGCFailedStosWD, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
266	STAM_REG_USED(pVM, &pStats->StatHCFailedStosWD, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
267	STAM_REG_USED(pVM, &pStats->StatGCFailedSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
268	STAM_REG_USED(pVM, &pStats->StatHCFailedSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
269	STAM_REG_USED(pVM, &pStats->StatGCFailedWbInvd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
270	STAM_REG_USED(pVM, &pStats->StatHCFailedWbInvd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
271
272	STAM_REG_USED(pVM, &pStats->StatGCFailedUserMode, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
273	STAM_REG_USED(pVM, &pStats->StatHCFailedUserMode, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
274	STAM_REG_USED(pVM, &pStats->StatGCFailedPrefix, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
275	STAM_REG_USED(pVM, &pStats->StatHCFailedPrefix, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
276
277	STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
278	STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
279	STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/HC/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
280	STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
281	STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
282	STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
283	STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
284	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
285	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
286	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
287	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
288	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
289	STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
290	STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
291	STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
292	STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
293	STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
294	STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/HC/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
295	STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
296	STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
297	STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
298	STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
299	STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
300	STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
301	STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
302	STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
303
304	STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
305	pVM->em.s.pCliStatTree = 0;
306	#endif /* VBOX_WITH_STATISTICS */
307
308	/* these should be considered for release statistics. */
309	STAM_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
310	STAM_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
311	STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
312	STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
313	STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
314	STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
315	STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
316	STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
317	STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
318	STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
319	STAM_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
320	STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
321	STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
322	STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
323	STAM_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
324	STAM_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
325
326
327	return VINF_SUCCESS;
328	}
329
330
331
332	/**
333	* Applies relocations to data and code managed by this
334	* component. This function will be called at init and
335	* whenever the VMM need to relocate it self inside the GC.
336	*
337	* @param pVM The VM.
338	*/
339	EMR3DECL(void) EMR3Relocate(PVM pVM)
340	{
341	LogFlow(("EMR3Relocate\n"));
342	if (pVM->em.s.pStatsHC)
343	pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pVM->em.s.pStatsHC);
344	}
345
346
347	/**
348	* Reset notification.
349	*
350	* @param pVM
351	*/
352	EMR3DECL(void) EMR3Reset(PVM pVM)
353	{
354	LogFlow(("EMR3Reset: \n"));
355	pVM->em.s.fForceRAW = false;
356	}
357
358
359	/**
360	* Terminates the EM.
361	*
362	* Termination means cleaning up and freeing all resources,
363	* the VM it self is at this point powered off or suspended.
364	*
365	* @returns VBox status code.
366	* @param pVM The VM to operate on.
367	*/
368	EMR3DECL(int) EMR3Term(PVM pVM)
369	{
370	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
371
372	return VINF_SUCCESS;
373	}
374
375
376	/**
377	* Execute state save operation.
378	*
379	* @returns VBox status code.
380	* @param pVM VM Handle.
381	* @param pSSM SSM operation handle.
382	*/
383	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
384	{
385	return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
386	}
387
388
389	/**
390	* Execute state load operation.
391	*
392	* @returns VBox status code.
393	* @param pVM VM Handle.
394	* @param pSSM SSM operation handle.
395	* @param u32Version Data layout version.
396	*/
397	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
398	{
399	/*
400	* Validate version.
401	*/
402	if (u32Version != EM_SAVED_STATE_VERSION)
403	{
404	Log(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
405	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
406	}
407
408	/*
409	* Load the saved state.
410	*/
411	int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
412	if (VBOX_FAILURE(rc))
413	pVM->em.s.fForceRAW = false;
414
415	Assert(pVM->em.s.pCliStatTree == 0);
416	return rc;
417	}
418
419
420	/**
421	* Enables or disables a set of raw-mode execution modes.
422	*
423	* @returns VINF_SUCCESS on success.
424	* @returns VINF_RESCHEDULE if a rescheduling might be required.
425	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
426	*
427	* @param pVM The VM to operate on.
428	* @param enmMode The execution mode change.
429	* @thread The emulation thread.
430	*/
431	EMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
432	{
433	switch (enmMode)
434	{
435	case EMRAW_NONE:
436	pVM->fRawR3Enabled = false;
437	pVM->fRawR0Enabled = false;
438	break;
439	case EMRAW_RING3_ENABLE:
440	pVM->fRawR3Enabled = true;
441	break;
442	case EMRAW_RING3_DISABLE:
443	pVM->fRawR3Enabled = false;
444	break;
445	case EMRAW_RING0_ENABLE:
446	pVM->fRawR0Enabled = true;
447	break;
448	case EMRAW_RING0_DISABLE:
449	pVM->fRawR0Enabled = false;
450	break;
451	default:
452	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
453	return VERR_INVALID_PARAMETER;
454	}
455	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool pVM->fRawR3Enabled=%RTbool\n",
456	pVM->fRawR3Enabled, pVM->fRawR0Enabled, pVM->fRawR3Enabled));
457	return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
458	}
459
460
461	/**
462	* Raise a fatal error.
463	*
464	* Safely terminate the VM with full state report and stuff. This function
465	* will naturally never return.
466	*
467	* @param pVM VM handle.
468	* @param rc VBox status code.
469	*/
470	EMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
471	{
472	longjmp(pVM->em.s.u.FatalLongJump, rc);
473	AssertReleaseMsgFailed(("longjmp returned!\n"));
474	}
475
476
477	/**
478	* Gets the EM state name.
479	*
480	* @returns pointer to read only state name,
481	* @param enmState The state.
482	*/
483	EMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
484	{
485	switch (enmState)
486	{
487	case EMSTATE_RAW: return "EMSTATE_RAW";
488	case EMSTATE_HWACC: return "EMSTATE_HWACC";
489	case EMSTATE_REM: return "EMSTATE_REM";
490	case EMSTATE_HALTED: return "EMSTATE_HALTED";
491	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
492	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
493	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
494	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
495	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
496	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
497	default: return "Unknown!";
498	}
499	}
500
501
502	#ifdef VBOX_WITH_STATISTICS
503	/**
504	* Just a braindead function to keep track of cli addresses.
505	* @param pVM VM handle.
506	* @param pInstrGC The EIP of the cli instruction.
507	*/
508	static void emR3RecordCli(PVM pVM, RTGCPTR pInstrGC)
509	{
510	PCLISTAT pRec;
511
512	pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)pInstrGC);
513	if (!pRec)
514	{
515	/* New cli instruction; insert into the tree. */
516	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
517	Assert(pRec);
518	if (!pRec)
519	return;
520	pRec->Core.Key = (AVLPVKEY)pInstrGC;
521
522	char szCliStatName[32];
523	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%VGv", pInstrGC);
524	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
525
526	bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
527	Assert(fRc); NOREF(fRc);
528	}
529	STAM_COUNTER_INC(&pRec->Counter);
530	STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
531	}
532	#endif /* VBOX_WITH_STATISTICS */
533
534
535	/**
536	* Debug loop.
537	*
538	* @returns VBox status code for EM.
539	* @param pVM VM handle.
540	* @param rc Current EM VBox status code..
541	*/
542	static int emR3Debug(PVM pVM, int rc)
543	{
544	for (;;)
545	{
546	Log(("emR3Debug: rc=%Vrc\n", rc));
547	const int rcLast = rc;
548
549	/*
550	* Debug related RC.
551	*/
552	switch (rc)
553	{
554	/*
555	* Single step an instruction.
556	*/
557	case VINF_EM_DBG_STEP:
558	if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
559	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
560	\|\| pVM->em.s.fForceRAW /* paranoia */)
561	rc = emR3RawStep(pVM);
562	else
563	{
564	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
565	rc = emR3RemStep(pVM);
566	}
567	break;
568
569	/*
570	* Simple events: stepped, breakpoint, stop/assertion.
571	*/
572	case VINF_EM_DBG_STEPPED:
573	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
574	break;
575
576	case VINF_EM_DBG_BREAKPOINT:
577	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
578	break;
579
580	case VINF_EM_DBG_STOP:
581	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
582	break;
583
584	case VINF_EM_DBG_HYPER_STEPPED:
585	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
586	break;
587
588	case VINF_EM_DBG_HYPER_BREAKPOINT:
589	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
590	break;
591
592	case VINF_EM_DBG_HYPER_ASSERTION:
593	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
594	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
595	break;
596
597	/*
598	* Guru meditation.
599	*/
600	default: /** @todo don't use default for guru, but make special errors code! */
601	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
602	break;
603	}
604
605	/*
606	* Process the result.
607	*/
608	do
609	{
610	switch (rc)
611	{
612	/*
613	* Continue the debugging loop.
614	*/
615	case VINF_EM_DBG_STEP:
616	case VINF_EM_DBG_STOP:
617	case VINF_EM_DBG_STEPPED:
618	case VINF_EM_DBG_BREAKPOINT:
619	case VINF_EM_DBG_HYPER_STEPPED:
620	case VINF_EM_DBG_HYPER_BREAKPOINT:
621	case VINF_EM_DBG_HYPER_ASSERTION:
622	break;
623
624	/*
625	* Resuming execution (in some form) has to be done here if we got
626	* a hypervisor debug event.
627	*/
628	case VINF_SUCCESS:
629	case VINF_EM_RESUME:
630	case VINF_EM_SUSPEND:
631	case VINF_EM_RESCHEDULE:
632	case VINF_EM_RESCHEDULE_RAW:
633	case VINF_EM_RESCHEDULE_REM:
634	case VINF_EM_HALT:
635	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
636	{
637	rc = emR3RawResumeHyper(pVM);
638	if (rc != VINF_SUCCESS && VBOX_SUCCESS(rc))
639	continue;
640	}
641	if (rc == VINF_SUCCESS)
642	rc = VINF_EM_RESCHEDULE;
643	return rc;
644
645	/*
646	* The debugger isn't attached.
647	* We'll simply turn the thing off since that's the easiest thing to do.
648	*/
649	case VERR_DBGF_NOT_ATTACHED:
650	switch (rcLast)
651	{
652	case VINF_EM_DBG_HYPER_ASSERTION:
653	case VINF_EM_DBG_HYPER_STEPPED:
654	case VINF_EM_DBG_HYPER_BREAKPOINT:
655	return rcLast;
656	}
657	return VINF_EM_OFF;
658
659	/*
660	* Status codes terminating the VM in one or another sense.
661	*/
662	case VINF_EM_TERMINATE:
663	case VINF_EM_OFF:
664	case VINF_EM_RESET:
665	case VINF_EM_RAW_STALE_SELECTOR:
666	case VINF_EM_RAW_IRET_TRAP:
667	case VERR_TRPM_PANIC:
668	case VERR_TRPM_DONT_PANIC:
669	case VERR_INTERNAL_ERROR:
670	return rc;
671
672	/*
673	* The rest is unexpected, and will keep us here.
674	*/
675	default:
676	AssertMsgFailed(("Unxpected rc %Vrc!\n", rc));
677	break;
678	}
679	} while (false);
680	} /* debug for ever */
681	}
682
683
684	/**
685	* Steps recompiled code.
686	*
687	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
688	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
689	*
690	* @param pVM VM handle.
691	*/
692	static int emR3RemStep(PVM pVM)
693	{
694	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
695
696	/*
697	* Switch to REM, step instruction, switch back.
698	*/
699	int rc = REMR3State(pVM);
700	if (VBOX_SUCCESS(rc))
701	{
702	rc = REMR3Step(pVM);
703	REMR3StateBack(pVM);
704	}
705	LogFlow(("emR3RemStep: returns %Vrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
706	return rc;
707	}
708
709	/**
710	* Executes recompiled code.
711	*
712	* This function contains the recompiler version of the inner
713	* execution loop (the outer loop being in EMR3ExecuteVM()).
714	*
715	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
716	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
717	*
718	* @param pVM VM handle.
719	* @param pfFFDone Where to store an indicator telling wheter or not
720	* FFs were done before returning.
721	*
722	*/
723	static int emR3RemExecute(PVM pVM, bool *pfFFDone)
724	{
725	#ifdef LOG_ENABLED
726	PCPUMCTX pCtx = pVM->em.s.pCtx;
727	if (pCtx->eflags.Bits.u1VM)
728	Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
729	else if ((pCtx->ss & X86_SEL_RPL) == 0)
730	Log(("EMR0: %08X ESP=%08X IF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (pCtx->ss & X86_SEL_RPL)));
731	else if ((pCtx->ss & X86_SEL_RPL) == 3)
732	Log(("EMR3: %08X ESP=%08X IF=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF));
733	#endif
734	STAM_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
735
736	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
737	AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3\|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
738	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
739	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
740	#endif
741
742	/*
743	* Spin till we get a forced action which returns anything but VINF_SUCCESS
744	* or the REM suggests raw-mode execution.
745	*/
746	*pfFFDone = false;
747	bool fInREMState = false;
748	int rc = VINF_SUCCESS;
749	for (;;)
750	{
751	/*
752	* Update REM state if not already in sync.
753	*/
754	if (!fInREMState)
755	{
756	STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
757	rc = REMR3State(pVM);
758	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
759	if (VBOX_FAILURE(rc))
760	break;
761	fInREMState = true;
762
763	/*
764	* We might have missed the raising of VMREQ, TIMER and some other
765	* imporant FFs while we were busy switching the state. So, check again.
766	*/
767	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_TIMER \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_RESET))
768	{
769	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
770	goto l_REMDoForcedActions;
771	}
772	}
773
774
775	/*
776	* Execute REM.
777	*/
778	STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
779	rc = REMR3Run(pVM);
780	STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
781
782
783	/*
784	* Deal with high priority post execution FFs before doing anything else.
785	*/
786	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
787	rc = emR3HighPriorityPostForcedActions(pVM, rc);
788
789	/*
790	* Process the returned status code.
791	* (Try keep this short! Call functions!)
792	*/
793	if (rc != VINF_SUCCESS)
794	{
795	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
796	break;
797	if (rc != VINF_REM_INTERRUPED_FF)
798	{
799	/*
800	* Anything which is not known to us means an internal error
801	* and the termination of the VM!
802	*/
803	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
804	break;
805	}
806	}
807
808
809	/*
810	* Check and execute forced actions.
811	* Sync back the VM state before calling any of these.
812	*/
813	#ifdef VBOX_HIGH_RES_TIMERS_HACK
814	TMTimerPoll(pVM);
815	#endif
816	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_PENDING_ACTION \| VM_FF_CSAM_SCAN_PAGE)))
817	{
818	l_REMDoForcedActions:
819	if (fInREMState)
820	{
821	STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
822	REMR3StateBack(pVM);
823	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
824	fInREMState = false;
825	}
826	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
827	rc = emR3ForcedActions(pVM, rc);
828	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
829	if ( rc != VINF_SUCCESS
830	&& rc != VINF_EM_RESCHEDULE_REM)
831	{
832	*pfFFDone = true;
833	break;
834	}
835	}
836
837	} /* The Inner Loop, recompiled execution mode version. */
838
839
840	/*
841	* Returning. Sync back the VM state if required.
842	*/
843	if (fInREMState)
844	{
845	STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
846	REMR3StateBack(pVM);
847	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
848	}
849
850	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
851	return rc;
852	}
853
854
855	/**
856	* Resumes executing hypervisor after a debug event.
857	*
858	* This is kind of special since our current guest state is
859	* potentially out of sync.
860	*
861	* @returns VBox status code.
862	* @param pVM The VM handle.
863	*/
864	static int emR3RawResumeHyper(PVM pVM)
865	{
866	int rc;
867	PCPUMCTX pCtx = pVM->em.s.pCtx;
868	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
869	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
870
871	/*
872	* Resume execution.
873	*/
874	CPUMRawEnter(pVM, NULL);
875	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_RF);
876	rc = VMMR3ResumeHyper(pVM);
877	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Vrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
878	rc = CPUMRawLeave(pVM, NULL, rc);
879	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
880
881	/*
882	* Deal with the return code.
883	*/
884	rc = emR3HighPriorityPostForcedActions(pVM, rc);
885	rc = emR3RawHandleRC(pVM, pCtx, rc);
886	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
887	return rc;
888	}
889
890
891	/**
892	* Steps rawmode.
893	*
894	* @returns VBox status code.
895	* @param pVM The VM handle.
896	*/
897	static int emR3RawStep(PVM pVM)
898	{
899	Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
900	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
901	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
902	int rc;
903	PCPUMCTX pCtx = pVM->em.s.pCtx;
904	bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
905	#ifndef DEBUG_sandervl
906	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
907	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
908	#endif
909	if (fGuest)
910	{
911	/*
912	* Check vital forced actions, but ignore pending interrupts and timers.
913	*/
914	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
915	{
916	rc = emR3RawForcedActions(pVM, pCtx);
917	if (VBOX_FAILURE(rc))
918	return rc;
919	}
920
921	/*
922	* Set flags for single stepping.
923	*/
924	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
925	}
926	else
927	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
928
929	/*
930	* Single step.
931	* We do not start time or anything, if anything we should just do a few nanoseconds.
932	*/
933	CPUMRawEnter(pVM, NULL);
934	do
935	{
936	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
937	rc = VMMR3ResumeHyper(pVM);
938	else
939	rc = VMMR3RawRunGC(pVM);
940	#ifndef DEBUG_sandervl
941	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Vrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
942	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
943	#endif
944	} while ( rc == VINF_SUCCESS
945	\|\| rc == VINF_EM_RAW_INTERRUPT);
946	rc = CPUMRawLeave(pVM, NULL, rc);
947	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
948
949	/*
950	* Make sure the trap flag is cleared.
951	* (Too bad if the guest is trying to single step too.)
952	*/
953	if (fGuest)
954	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
955	else
956	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
957
958	/*
959	* Deal with the return codes.
960	*/
961	rc = emR3HighPriorityPostForcedActions(pVM, rc);
962	rc = emR3RawHandleRC(pVM, pCtx, rc);
963	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
964	return rc;
965	}
966
967	/**
968	* Steps hardware accelerated mode.
969	*
970	* @returns VBox status code.
971	* @param pVM The VM handle.
972	*/
973	static int emR3HwAccStep(PVM pVM)
974	{
975	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
976
977	int rc;
978	PCPUMCTX pCtx = pVM->em.s.pCtx;
979	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
980
981	/*
982	* Check vital forced actions, but ignore pending interrupts and timers.
983	*/
984	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
985	{
986	rc = emR3RawForcedActions(pVM, pCtx);
987	if (VBOX_FAILURE(rc))
988	return rc;
989	}
990	/*
991	* Set flags for single stepping.
992	*/
993	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
994
995	/*
996	* Single step.
997	* We do not start time or anything, if anything we should just do a few nanoseconds.
998	*/
999	do
1000	{
1001	rc = VMMR3HwAccRunGC(pVM);
1002	} while ( rc == VINF_SUCCESS
1003	\|\| rc == VINF_EM_RAW_INTERRUPT);
1004	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1005
1006	/*
1007	* Make sure the trap flag is cleared.
1008	* (Too bad if the guest is trying to single step too.)
1009	*/
1010	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1011
1012	/*
1013	* Deal with the return codes.
1014	*/
1015	rc = emR3HighPriorityPostForcedActions(pVM, rc);
1016	rc = emR3RawHandleRC(pVM, pCtx, rc);
1017	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1018	return rc;
1019	}
1020
1021	#ifdef DEBUG
1022	void emR3SingleStepExecRaw(PVM pVM, uint32_t cIterations)
1023	{
1024	EMSTATE enmOldState = pVM->em.s.enmState;
1025	PCPUMCTX pCtx = pVM->em.s.pCtx;
1026
1027	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1028
1029	Log(("Single step BEGIN:\n"));
1030	for(uint32_t i=0;i<cIterations;i++)
1031	{
1032	DBGFR3PrgStep(pVM);
1033	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1034	emR3RawStep(pVM);
1035	}
1036	Log(("Single step END:\n"));
1037	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1038	pVM->em.s.enmState = enmOldState;
1039	}
1040
1041	void emR3SingleStepExecHwAcc(PVM pVM, uint32_t cIterations)
1042	{
1043	EMSTATE enmOldState = pVM->em.s.enmState;
1044	PCPUMCTX pCtx = pVM->em.s.pCtx;
1045
1046	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
1047
1048	Log(("Single step BEGIN:\n"));
1049	for(uint32_t i=0;i<cIterations;i++)
1050	{
1051	DBGFR3PrgStep(pVM);
1052	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1053	emR3HwAccStep(pVM);
1054	}
1055	Log(("Single step END:\n"));
1056	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1057	pVM->em.s.enmState = enmOldState;
1058	}
1059
1060	void emR3SingleStepExecRem(PVM pVM, uint32_t cIterations)
1061	{
1062	EMSTATE enmOldState = pVM->em.s.enmState;
1063	PCPUMCTX pCtx = pVM->em.s.pCtx;
1064
1065	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1066
1067	Log(("Single step BEGIN:\n"));
1068	for(uint32_t i=0;i<cIterations;i++)
1069	{
1070	DBGFR3PrgStep(pVM);
1071	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1072	emR3RemStep(pVM);
1073	}
1074	Log(("Single step END:\n"));
1075	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1076	pVM->em.s.enmState = enmOldState;
1077	}
1078	#endif
1079
1080	/**
1081	* Executes one (or perhaps a few more) instruction(s).
1082	*
1083	* @returns VBox status code suitable for EM.
1084	*
1085	* @param pVM VM handle.
1086	* @param rcGC GC return code
1087	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1088	* instruction and prefix the log output with this text.
1089	*/
1090	#ifdef LOG_ENABLED
1091	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
1092	#else
1093	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
1094	#endif
1095	{
1096	PCPUMCTX pCtx = pVM->em.s.pCtx;
1097	int rc;
1098
1099	/*
1100	*
1101	* The simple solution is to use the recompiler.
1102	* The better solution is to disassemble the current instruction and
1103	* try handle as many as possible without using REM.
1104	*
1105	*/
1106
1107	#ifdef LOG_ENABLED
1108	/*
1109	* Disassemble the instruction if requested.
1110	*/
1111	if (pszPrefix)
1112	{
1113	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1114	DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1115	}
1116	#endif /* LOG_ENABLED */
1117
1118	/*
1119	* PATM is making life more interesting.
1120	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1121	* tell PATM there is a trap in this code and have it take the appropriate actions
1122	* to allow us execute the code in REM.
1123	*/
1124	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1125	{
1126	Log(("emR3RawExecuteInstruction: In patch block. eip=%VGv\n", pCtx->eip));
1127
1128	RTGCPTR pNewEip;
1129	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1130	switch (rc)
1131	{
1132	/*
1133	* It's not very useful to emulate a single instruction and then go back to raw
1134	* mode; just execute the whole block until IF is set again.
1135	*/
1136	case VINF_SUCCESS:
1137	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %VGv IF=%d VMIF=%x\n",
1138	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1139	pCtx->eip = pNewEip;
1140	Assert(pCtx->eip);
1141
1142	if (pCtx->eflags.Bits.u1IF)
1143	{
1144	/*
1145	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1146	*/
1147	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1148	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1149	}
1150	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1151	{
1152	/* special case: iret, that sets IF, detected a pending irq/event */
1153	return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1154	}
1155	return VINF_EM_RESCHEDULE_REM;
1156
1157	/*
1158	* One instruction.
1159	*/
1160	case VINF_PATCH_EMULATE_INSTR:
1161	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1162	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1163	pCtx->eip = pNewEip;
1164	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1165
1166	/*
1167	* The patch was disabled, hand it to the REM.
1168	*/
1169	case VERR_PATCH_DISABLED:
1170	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %VGv IF=%d VMIF=%x\n",
1171	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1172	pCtx->eip = pNewEip;
1173	if (pCtx->eflags.Bits.u1IF)
1174	{
1175	/*
1176	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1177	*/
1178	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1179	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1180	}
1181	return VINF_EM_RESCHEDULE_REM;
1182
1183	/* Force continued patch exection; usually due to write monitored stack. */
1184	case VINF_PATCH_CONTINUE:
1185	return VINF_SUCCESS;
1186
1187	default:
1188	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap\n", rc));
1189	return VERR_INTERNAL_ERROR;
1190	}
1191	}
1192
1193	#if 0 /// @todo Sander, this breaks the linux image (panics). So, I'm disabling it for now. (OP_MOV triggers it btw.)
1194	DISCPUSTATE Cpu;
1195	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "GEN EMU");
1196	if (VBOX_SUCCESS(rc))
1197	{
1198	uint32_t size;
1199
1200	switch (Cpu.pCurInstr->opcode)
1201	{
1202	case OP_MOV:
1203	case OP_AND:
1204	case OP_OR:
1205	case OP_XOR:
1206	case OP_POP:
1207	case OP_INC:
1208	case OP_DEC:
1209	case OP_XCHG:
1210	STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1211	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1212	if (VBOX_SUCCESS(rc))
1213	{
1214	pCtx->eip += Cpu.opsize;
1215	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1216	return rc;
1217	}
1218	if (rc != VERR_EM_INTERPRETER)
1219	AssertMsgFailedReturn(("rc=%Vrc\n", rc), rc);
1220	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1221	break;
1222	}
1223	}
1224	#endif
1225	STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1226	rc = REMR3EmulateInstruction(pVM);
1227	STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1228
1229	return rc;
1230	}
1231
1232
1233	/**
1234	* Executes one (or perhaps a few more) instruction(s).
1235	* This is just a wrapper for discarding pszPrefix in non-logging builds.
1236	*
1237	* @returns VBox status code suitable for EM.
1238	* @param pVM VM handle.
1239	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1240	* instruction and prefix the log output with this text.
1241	* @param rcGC GC return code
1242	*/
1243	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1244	{
1245	#ifdef LOG_ENABLED
1246	return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1247	#else
1248	return emR3RawExecuteInstructionWorker(pVM, rcGC);
1249	#endif
1250	}
1251
1252	/**
1253	* Executes one (or perhaps a few more) IO instruction(s).
1254	*
1255	* @returns VBox status code suitable for EM.
1256	* @param pVM VM handle.
1257	*/
1258	int emR3RawExecuteIOInstruction(PVM pVM)
1259	{
1260	int rc;
1261	PCPUMCTX pCtx = pVM->em.s.pCtx;
1262
1263	STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1264
1265	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1266	* as io instructions tend to come in packages of more than one
1267	*/
1268	DISCPUSTATE Cpu;
1269	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "IO EMU");
1270	if (VBOX_SUCCESS(rc))
1271	{
1272	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1273	{
1274	switch (Cpu.pCurInstr->opcode)
1275	{
1276	case OP_IN:
1277	{
1278	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1279
1280	rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1281	if (rc == VINF_SUCCESS)
1282	{
1283	pCtx->eip += Cpu.opsize;
1284	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1285	return VINF_SUCCESS;
1286	}
1287	else
1288	if (rc == VINF_EM_RAW_GUEST_TRAP)
1289	{
1290	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1291	rc = emR3RawGuestTrap(pVM);
1292	return rc;
1293	}
1294	/* emulate in the recompiler */
1295	break;
1296	}
1297
1298	case OP_OUT:
1299	{
1300	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1301
1302	rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1303	if (rc == VINF_SUCCESS)
1304	{
1305	pCtx->eip += Cpu.opsize;
1306	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1307	return VINF_SUCCESS;
1308	}
1309	else
1310	if (rc == VINF_EM_RAW_GUEST_TRAP)
1311	{
1312	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1313	rc = emR3RawGuestTrap(pVM);
1314	return rc;
1315	}
1316	/* emulate in the recompiler */
1317	break;
1318	}
1319
1320	default:
1321	break;
1322	}
1323	}//if(!(Cpu.prefix & (PREFIX_REP\|PREFIX_REPNE))
1324	else if (Cpu.prefix & PREFIX_REP)
1325	{
1326	switch (Cpu.pCurInstr->opcode)
1327	{
1328	case OP_INSB:
1329	case OP_INSWD:
1330	{
1331	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1332	rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1333	if (rc == VINF_SUCCESS)
1334	{
1335	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1336	pCtx->eip += Cpu.opsize;
1337	return rc;
1338	}
1339	else
1340	if (rc == VINF_EM_RAW_GUEST_TRAP)
1341	{
1342	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1343	rc = emR3RawGuestTrap(pVM);
1344	return rc;
1345	}
1346	/* emulate in the recompiler */
1347	break;
1348	}
1349	case OP_OUTSB:
1350	case OP_OUTSWD:
1351	{
1352	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1353	rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1354	if (rc == VINF_SUCCESS)
1355	{
1356	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1357	pCtx->eip += Cpu.opsize;
1358	return rc;
1359	}
1360	else
1361	if (rc == VINF_EM_RAW_GUEST_TRAP)
1362	{
1363	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1364	rc = emR3RawGuestTrap(pVM);
1365	return rc;
1366	}
1367	/* emulate in the recompiler */
1368	break;
1369	}
1370	}
1371	}//if(Cpu.prefix & PREFIX_REP)
1372	}
1373
1374	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1375	return emR3RawExecuteInstruction(pVM, "IO: ");
1376	}
1377
1378
1379	/**
1380	* Handle a guest context trap.
1381	*
1382	* @returns VBox status code suitable for EM.
1383	* @param pVM VM handle.
1384	*/
1385	static int emR3RawGuestTrap(PVM pVM)
1386	{
1387	PCPUMCTX pCtx = pVM->em.s.pCtx;
1388
1389	/*
1390	* Get the trap info.
1391	*/
1392	uint8_t u8TrapNo;
1393	TRPMEVENT enmType;;
1394	RTGCUINT uErrorCode;
1395	RTGCUINTPTR uCR2;
1396	int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1397	if (VBOX_FAILURE(rc))
1398	{
1399	AssertReleaseMsgFailed(("No trap! (rc=%Vrc)\n", rc));
1400	return rc;
1401	}
1402
1403	/* Traps can be directly forwarded in hardware accelerated mode. */
1404	if (HWACCMR3IsActive(pVM))
1405	{
1406	#ifdef LOGGING_ENABLED
1407	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1408	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1409	#endif
1410	return VINF_EM_RESCHEDULE_HWACC;
1411	}
1412
1413	/** Scan kernel code that traps; we might not get another chance. */
1414	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1415	&& !pCtx->eflags.Bits.u1VM)
1416	{
1417	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1418	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
1419	}
1420
1421	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1422	{
1423	DISCPUSTATE cpu;
1424
1425	/* If MONITOR & MWAIT are supported, then interpret them here. */
1426	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap (#UD): ");
1427	if ( VBOX_SUCCESS(rc)
1428	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
1429	{
1430	uint32_t u32Dummy, u32Features, u32ExtFeatures, size;
1431
1432	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1433
1434	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1435	{
1436	rc = TRPMResetTrap(pVM);
1437	AssertRC(rc);
1438
1439	rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &size);
1440	if (VBOX_SUCCESS(rc))
1441	{
1442	pCtx->eip += cpu.opsize;
1443	return rc;
1444	}
1445	return emR3RawExecuteInstruction(pVM, "Monitor: ");
1446	}
1447	}
1448	}
1449	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1450	{
1451	DISCPUSTATE cpu;
1452
1453	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap: ");
1454	if (VBOX_SUCCESS(rc) && (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1455	{
1456	/*
1457	* We should really check the TSS for the IO bitmap, but it's not like this
1458	* lazy approach really makes things worse.
1459	*/
1460	rc = TRPMResetTrap(pVM);
1461	AssertRC(rc);
1462	return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1463	}
1464	}
1465
1466	#ifdef LOG_ENABLED
1467	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1468	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1469
1470	/* Get guest page information. */
1471	uint64_t fFlags = 0;
1472	RTGCPHYS GCPhys = 0;
1473	int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1474	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%VGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1475	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1476	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1477	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1478	#endif
1479
1480	/*
1481	* #PG has CR2.
1482	* (Because of stuff like above we must set CR2 in a delayed fashion.)
1483	*/
1484	if (u8TrapNo == 14 /* #PG */)
1485	pCtx->cr2 = uCR2;
1486
1487	return VINF_EM_RESCHEDULE_REM;
1488	}
1489
1490
1491	/**
1492	* Handle a ring switch trap.
1493	* Need to do statistics and to install patches. The result is going to REM.
1494	*
1495	* @returns VBox status code suitable for EM.
1496	* @param pVM VM handle.
1497	*/
1498	int emR3RawRingSwitch(PVM pVM)
1499	{
1500	int rc;
1501	DISCPUSTATE Cpu;
1502	PCPUMCTX pCtx = pVM->em.s.pCtx;
1503
1504	/*
1505	* sysenter, syscall & callgate
1506	*/
1507	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "RSWITCH: ");
1508	if (VBOX_SUCCESS(rc))
1509	{
1510	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1511	{
1512	if (pCtx->SysEnter.cs != 0)
1513	{
1514	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
1515	SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1516	if (VBOX_SUCCESS(rc))
1517	{
1518	DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1519	return VINF_EM_RESCHEDULE_RAW;
1520	}
1521	}
1522	}
1523
1524	#ifdef VBOX_WITH_STATISTICS
1525	switch (Cpu.pCurInstr->opcode)
1526	{
1527	case OP_SYSENTER:
1528	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysEnter);
1529	break;
1530	case OP_SYSEXIT:
1531	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysExit);
1532	break;
1533	case OP_SYSCALL:
1534	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysCall);
1535	break;
1536	case OP_SYSRET:
1537	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysRet);
1538	break;
1539	}
1540	#endif
1541	}
1542	else
1543	AssertRC(rc);
1544
1545	/* go to the REM to emulate a single instruction */
1546	return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1547	}
1548
1549	/**
1550	* Handle a trap (#PF or #GP) in patch code
1551	*
1552	* @returns VBox status code suitable for EM.
1553	* @param pVM VM handle.
1554	* @param pCtx CPU context
1555	* @param gcret GC return code
1556	*/
1557	int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1558	{
1559	uint8_t u8TrapNo;
1560	int rc;
1561	TRPMEVENT enmType;
1562	RTGCUINT uErrorCode;
1563	RTGCUINTPTR uCR2;
1564
1565	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1566
1567	if (gcret == VINF_PATM_PATCH_INT3)
1568	{
1569	u8TrapNo = 3;
1570	uCR2 = 0;
1571	uErrorCode = 0;
1572	}
1573	else
1574	if (gcret == VINF_PATM_PATCH_TRAP_GP)
1575	{
1576	/* No active trap in this case. Kind of ugly. */
1577	u8TrapNo = X86_XCPT_GP;
1578	uCR2 = 0;
1579	uErrorCode = 0;
1580	}
1581	else
1582	{
1583	rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1584	if (VBOX_FAILURE(rc))
1585	{
1586	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Vrc) gcret=%Vrc\n", rc, gcret));
1587	return rc;
1588	}
1589	/* Reset the trap as we'll execute the original instruction again. */
1590	TRPMResetTrap(pVM);
1591	}
1592
1593	/*
1594	* Deal with traps inside patch code.
1595	* (This code won't run outside GC.)
1596	*/
1597	if (u8TrapNo != 1)
1598	{
1599	#ifdef LOG_ENABLED
1600	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1601	DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1602
1603	DISCPUSTATE Cpu;
1604	int rc;
1605
1606	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1607	if ( VBOX_SUCCESS(rc)
1608	&& Cpu.pCurInstr->opcode == OP_IRET)
1609	{
1610	uint32_t eip, selCS, uEFlags;
1611
1612	/* Iret crashes are bad as we have already changed the flags on the stack */
1613	rc = PGMPhysReadGCPtr(pVM, &eip, pCtx->esp, 4);
1614	rc \|= PGMPhysReadGCPtr(pVM, &selCS, pCtx->esp+4, 4);
1615	rc \|= PGMPhysReadGCPtr(pVM, &uEFlags, pCtx->esp+8, 4);
1616	if (rc == VINF_SUCCESS)
1617	{
1618	if ( (uEFlags & X86_EFL_VM)
1619	\|\| (selCS & X86_SEL_RPL) == 3)
1620	{
1621	uint32_t selSS, esp;
1622
1623	rc \|= PGMPhysReadGCPtr(pVM, &esp, pCtx->esp + 12, 4);
1624	rc \|= PGMPhysReadGCPtr(pVM, &selSS, pCtx->esp + 16, 4);
1625
1626	if (uEFlags & X86_EFL_VM)
1627	{
1628	uint32_t selDS, selES, selFS, selGS;
1629	rc = PGMPhysReadGCPtr(pVM, &selES, pCtx->esp + 20, 4);
1630	rc \|= PGMPhysReadGCPtr(pVM, &selDS, pCtx->esp + 24, 4);
1631	rc \|= PGMPhysReadGCPtr(pVM, &selFS, pCtx->esp + 28, 4);
1632	rc \|= PGMPhysReadGCPtr(pVM, &selGS, pCtx->esp + 32, 4);
1633	if (rc == VINF_SUCCESS)
1634	{
1635	Log(("Patch code: IRET->VM stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1636	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1637	}
1638	}
1639	else
1640	Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1641	}
1642	else
1643	Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x\n", selCS, eip, uEFlags));
1644	}
1645	}
1646	#endif
1647	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1648	pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0));
1649
1650	RTGCPTR pNewEip;
1651	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1652	switch (rc)
1653	{
1654	/*
1655	* Execute the faulting instruction.
1656	*/
1657	case VINF_SUCCESS:
1658	{
1659	/** @todo execute a whole block */
1660	Log(("emR3PatchTrap: Executing faulting instruction at new address %VGv\n", pNewEip));
1661	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1662	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1663
1664	pCtx->eip = pNewEip;
1665	AssertRelease(pCtx->eip);
1666
1667	if (pCtx->eflags.Bits.u1IF)
1668	{
1669	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1670	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1671	*/
1672	if ( u8TrapNo == X86_XCPT_GP
1673	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1674	{
1675	/** @todo move to PATMR3HandleTrap */
1676	Log(("Possible Windows XP iret fault at %VGv\n", pCtx->eip));
1677	PATMR3RemovePatch(pVM, pCtx->eip);
1678	}
1679
1680	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1681	/** @note possibly because a reschedule is required (e.g. iret to V86 code) */
1682
1683	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1684	/* Interrupts are enabled; just go back to the original instruction.
1685	return VINF_SUCCESS; */
1686	}
1687	return VINF_EM_RESCHEDULE_REM;
1688	}
1689
1690	/*
1691	* One instruction.
1692	*/
1693	case VINF_PATCH_EMULATE_INSTR:
1694	Log(("emR3PatchTrap: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1695	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1696	pCtx->eip = pNewEip;
1697	AssertRelease(pCtx->eip);
1698	return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1699
1700	/*
1701	* The patch was disabled, hand it to the REM.
1702	*/
1703	case VERR_PATCH_DISABLED:
1704	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1705	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1706	pCtx->eip = pNewEip;
1707	AssertRelease(pCtx->eip);
1708
1709	if (pCtx->eflags.Bits.u1IF)
1710	{
1711	/*
1712	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1713	*/
1714	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1715	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1716	}
1717	return VINF_EM_RESCHEDULE_REM;
1718
1719	/* Force continued patch exection; usually due to write monitored stack. */
1720	case VINF_PATCH_CONTINUE:
1721	return VINF_SUCCESS;
1722
1723	/*
1724	* Anything else is fatal.
1725	*/
1726	default:
1727	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap!\n", rc));
1728	return VERR_INTERNAL_ERROR;
1729	}
1730	}
1731	return VINF_SUCCESS;
1732	}
1733
1734
1735	/**
1736	* Handle a privileged instruction.
1737	*
1738	* @returns VBox status code suitable for EM.
1739	* @param pVM VM handle.
1740	*/
1741	int emR3RawPrivileged(PVM pVM)
1742	{
1743	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1744	PCPUMCTX pCtx = pVM->em.s.pCtx;
1745
1746	Assert(!pCtx->eflags.Bits.u1VM);
1747
1748	if (PATMIsEnabled(pVM))
1749	{
1750	/*
1751	* Check if in patch code.
1752	*/
1753	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1754	{
1755	#ifdef LOG_ENABLED
1756	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1757	#endif
1758	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1759	return VERR_EM_RAW_PATCH_CONFLICT;
1760	}
1761	if ( (pCtx->ss & X86_SEL_RPL) == 0
1762	&& !pCtx->eflags.Bits.u1VM
1763	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1764	{
1765	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
1766	SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1767	if (VBOX_SUCCESS(rc))
1768	{
1769	#ifdef LOG_ENABLED
1770	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1771	#endif
1772	DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1773	return VINF_SUCCESS;
1774	}
1775	}
1776	}
1777
1778	#ifdef LOG_ENABLED
1779	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1780	{
1781	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1782	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1783	}
1784	#endif
1785
1786	/*
1787	* Instruction statistics and logging.
1788	*/
1789	DISCPUSTATE Cpu;
1790	int rc;
1791
1792	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "PRIV: ");
1793	if (VBOX_SUCCESS(rc))
1794	{
1795	#ifdef VBOX_WITH_STATISTICS
1796	PEMSTATS pStats = pVM->em.s.CTXSUFF(pStats);
1797	switch (Cpu.pCurInstr->opcode)
1798	{
1799	case OP_INVLPG:
1800	STAM_COUNTER_INC(&pStats->StatInvlpg);
1801	break;
1802	case OP_IRET:
1803	STAM_COUNTER_INC(&pStats->StatIret);
1804	break;
1805	case OP_CLI:
1806	STAM_COUNTER_INC(&pStats->StatCli);
1807	emR3RecordCli(pVM, pCtx->eip);
1808	break;
1809	case OP_STI:
1810	STAM_COUNTER_INC(&pStats->StatSti);
1811	break;
1812	case OP_INSB:
1813	case OP_INSWD:
1814	case OP_IN:
1815	case OP_OUTSB:
1816	case OP_OUTSWD:
1817	case OP_OUT:
1818	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1819	break;
1820
1821	case OP_MOV_CR:
1822	if (Cpu.param1.flags & USE_REG_GEN32)
1823	{
1824	//read
1825	Assert(Cpu.param2.flags & USE_REG_CR);
1826	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1827	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1828	}
1829	else
1830	{
1831	//write
1832	Assert(Cpu.param1.flags & USE_REG_CR);
1833	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1834	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1835	}
1836	break;
1837
1838	case OP_MOV_DR:
1839	STAM_COUNTER_INC(&pStats->StatMovDRx);
1840	break;
1841	case OP_LLDT:
1842	STAM_COUNTER_INC(&pStats->StatMovLldt);
1843	break;
1844	case OP_LIDT:
1845	STAM_COUNTER_INC(&pStats->StatMovLidt);
1846	break;
1847	case OP_LGDT:
1848	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1849	break;
1850	case OP_SYSENTER:
1851	STAM_COUNTER_INC(&pStats->StatSysEnter);
1852	break;
1853	case OP_SYSEXIT:
1854	STAM_COUNTER_INC(&pStats->StatSysExit);
1855	break;
1856	case OP_SYSCALL:
1857	STAM_COUNTER_INC(&pStats->StatSysCall);
1858	break;
1859	case OP_SYSRET:
1860	STAM_COUNTER_INC(&pStats->StatSysRet);
1861	break;
1862	case OP_HLT:
1863	STAM_COUNTER_INC(&pStats->StatHlt);
1864	break;
1865	default:
1866	STAM_COUNTER_INC(&pStats->StatMisc);
1867	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1868	break;
1869	}
1870	#endif
1871	if ( (pCtx->ss & X86_SEL_RPL) == 0
1872	&& !pCtx->eflags.Bits.u1VM
1873	&& SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid))
1874	{
1875	uint32_t size;
1876
1877	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1878	switch (Cpu.pCurInstr->opcode)
1879	{
1880	case OP_CLI:
1881	pCtx->eflags.u32 &= ~X86_EFL_IF;
1882	Assert(Cpu.opsize == 1);
1883	pCtx->eip += Cpu.opsize;
1884	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1885	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1886
1887	case OP_STI:
1888	pCtx->eflags.u32 \|= X86_EFL_IF;
1889	EMSetInhibitInterruptsPC(pVM, pCtx->eip + Cpu.opsize);
1890	Assert(Cpu.opsize == 1);
1891	pCtx->eip += Cpu.opsize;
1892	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1893	return VINF_SUCCESS;
1894
1895	case OP_HLT:
1896	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1897	{
1898	PATMTRANSSTATE enmState;
1899	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1900
1901	if (enmState == PATMTRANS_OVERWRITTEN)
1902	{
1903	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1904	Assert(rc == VERR_PATCH_DISABLED);
1905	/* Conflict detected, patch disabled */
1906	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->eip));
1907
1908	enmState = PATMTRANS_SAFE;
1909	}
1910
1911	/* The translation had better be successful. Otherwise we can't recover. */
1912	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->eip));
1913	if (enmState != PATMTRANS_OVERWRITTEN)
1914	pCtx->eip = pOrgInstrGC;
1915	}
1916	/* no break; we could just return VINF_EM_HALT here */
1917
1918	case OP_MOV_CR:
1919	case OP_MOV_DR:
1920	#ifdef LOG_ENABLED
1921	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1922	{
1923	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1924	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1925	}
1926	#endif
1927
1928	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1929	if (VBOX_SUCCESS(rc))
1930	{
1931	pCtx->eip += Cpu.opsize;
1932	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1933
1934	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
1935	&& Cpu.param1.flags == USE_REG_CR /* write */
1936	)
1937	{
1938	/* Reschedule is necessary as the execution/paging mode might have changed. */
1939	return VINF_EM_RESCHEDULE;
1940	}
1941	return rc; /* can return VINF_EM_HALT as well. */
1942	}
1943	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Vrc\n", rc), rc);
1944	break; /* fall back to the recompiler */
1945	}
1946	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1947	}
1948	}
1949
1950	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1951	return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
1952
1953	return emR3RawExecuteInstruction(pVM, "PRIV");
1954	}
1955
1956
1957	/**
1958	* Update the forced rawmode execution modifier.
1959	*
1960	* This function is called when we're returning from the raw-mode loop(s). If we're
1961	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1962	* if not in patch code, the flag will be cleared.
1963	*
1964	* We should never interrupt patch code while it's being executed. Cli patches can
1965	* contain big code blocks, but they are always executed with IF=0. Other patches
1966	* replace single instructions and should be atomic.
1967	*
1968	* @returns Updated rc.
1969	*
1970	* @param pVM The VM handle.
1971	* @param pCtx The guest CPU context.
1972	* @param rc The result code.
1973	*/
1974	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
1975	{
1976	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1977	{
1978	/* ignore reschedule attempts. */
1979	switch (rc)
1980	{
1981	case VINF_EM_RESCHEDULE:
1982	case VINF_EM_RESCHEDULE_REM:
1983	rc = VINF_SUCCESS;
1984	break;
1985	}
1986	pVM->em.s.fForceRAW = true;
1987	}
1988	else
1989	pVM->em.s.fForceRAW = false;
1990	return rc;
1991	}
1992
1993
1994	/**
1995	* Process a subset of the raw-mode return code.
1996	*
1997	* Since we have to share this with raw-mode single stepping, this inline
1998	* function has been created to avoid code duplication.
1999	*
2000	* @returns VINF_SUCCESS if it's ok to continue raw mode.
2001	* @returns VBox status code to return to the EM main loop.
2002	*
2003	* @param pVM The VM handle
2004	* @param rc The return code.
2005	* @param pCtx The guest cpu context.
2006	*/
2007	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
2008	{
2009	switch (rc)
2010	{
2011	/*
2012	* Common & simple ones.
2013	*/
2014	case VINF_SUCCESS:
2015	break;
2016	case VINF_EM_RESCHEDULE_RAW:
2017	case VINF_EM_RESCHEDULE_HWACC:
2018	case VINF_EM_RAW_INTERRUPT:
2019	case VINF_EM_RAW_TO_R3:
2020	case VINF_EM_RAW_TIMER_PENDING:
2021	case VINF_EM_PENDING_REQUEST:
2022	rc = VINF_SUCCESS;
2023	break;
2024
2025	/*
2026	* Privileged instruction.
2027	*/
2028	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2029	case VINF_PATM_PATCH_TRAP_GP:
2030	rc = emR3RawPrivileged(pVM);
2031	break;
2032
2033	/*
2034	* Got a trap which needs dispatching.
2035	*/
2036	case VINF_EM_RAW_GUEST_TRAP:
2037	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2038	{
2039	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2040	rc = VERR_EM_RAW_PATCH_CONFLICT;
2041	break;
2042	}
2043
2044	Assert(TRPMHasTrap(pVM));
2045	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2046
2047	if (TRPMHasTrap(pVM))
2048	{
2049	uint8_t u8Interrupt;
2050	uint32_t uErrorCode;
2051	TRPMERRORCODE enmError = TRPM_TRAP_NO_ERRORCODE;
2052
2053	rc = TRPMQueryTrapAll(pVM, &u8Interrupt, NULL, &uErrorCode, NULL);
2054	AssertRC(rc);
2055
2056	if (uErrorCode != ~0U)
2057	enmError = TRPM_TRAP_HAS_ERRORCODE;
2058
2059	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2060	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2061	{
2062	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2063	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2064
2065	/** If it was successful, then we could go back to raw mode. */
2066	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER)
2067	{
2068	rc = TRPMForwardTrap(pVM, CPUMCTX2CORE(pCtx), u8Interrupt, uErrorCode, enmError, TRPM_TRAP);
2069	if (rc == VINF_SUCCESS /* Don't use VBOX_SUCCESS */)
2070	{
2071	TRPMResetTrap(pVM);
2072	return VINF_EM_RESCHEDULE_RAW;
2073	}
2074	}
2075	}
2076	}
2077	rc = emR3RawGuestTrap(pVM);
2078	break;
2079
2080	/*
2081	* Trap in patch code.
2082	*/
2083	case VINF_PATM_PATCH_TRAP_PF:
2084	case VINF_PATM_PATCH_INT3:
2085	rc = emR3PatchTrap(pVM, pCtx, rc);
2086	break;
2087
2088	case VINF_PATM_DUPLICATE_FUNCTION:
2089	Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2090	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2091	AssertRC(rc);
2092	rc = VINF_SUCCESS;
2093	break;
2094
2095	case VINF_PATM_CHECK_PATCH_PAGE:
2096	rc = PATMR3HandleMonitoredPage(pVM);
2097	AssertRC(rc);
2098	rc = VINF_SUCCESS;
2099	break;
2100
2101	/*
2102	* Patch manager.
2103	*/
2104	case VERR_EM_RAW_PATCH_CONFLICT:
2105	AssertReleaseMsgFailed(("%Vrc handling is not yet implemented\n", rc));
2106	break;
2107
2108	/*
2109	* Memory mapped I/O access - attempt to patch the instruction
2110	*/
2111	case VINF_PATM_HC_MMIO_PATCH_READ:
2112	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
2113	PATMFL_MMIO_ACCESS \| (SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0));
2114	if (VBOX_FAILURE(rc))
2115	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2116	break;
2117
2118	case VINF_PATM_HC_MMIO_PATCH_WRITE:
2119	AssertFailed(); /* not yet implemented. */
2120	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2121	break;
2122
2123	/*
2124	* Conflict or out of page tables.
2125	*
2126	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2127	* do here is to execute the pending forced actions.
2128	*/
2129	case VINF_PGM_SYNC_CR3:
2130	AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2131	("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2132	rc = VINF_SUCCESS;
2133	break;
2134
2135	/*
2136	* Paging mode change.
2137	*/
2138	case VINF_PGM_CHANGE_MODE:
2139	rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, 0);
2140	if (VBOX_SUCCESS(rc))
2141	rc = VINF_EM_RESCHEDULE;
2142	break;
2143
2144	/*
2145	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
2146	*/
2147	case VINF_CSAM_PENDING_ACTION:
2148	rc = VINF_SUCCESS;
2149	break;
2150
2151	/*
2152	* Invoked Interrupt gate - must directly (!) go to the recompiler.
2153	*/
2154	case VINF_EM_RAW_INTERRUPT_PENDING:
2155	case VINF_EM_RAW_RING_SWITCH_INT:
2156	{
2157	uint8_t u8Interrupt;
2158
2159	Assert(TRPMHasTrap(pVM));
2160	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2161
2162	if (TRPMHasTrap(pVM))
2163	{
2164	u8Interrupt = TRPMGetTrapNo(pVM);
2165
2166	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2167	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2168	{
2169	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2170	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2171	/** @note If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2172	}
2173	}
2174	rc = VINF_EM_RESCHEDULE_REM;
2175	break;
2176	}
2177
2178	/*
2179	* Other ring switch types.
2180	*/
2181	case VINF_EM_RAW_RING_SWITCH:
2182	rc = emR3RawRingSwitch(pVM);
2183	break;
2184
2185	/*
2186	* REMGCNotifyInvalidatePage() failed because of overflow.
2187	*/
2188	case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2189	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2190	REMR3ReplayInvalidatedPages(pVM);
2191	break;
2192
2193	/*
2194	* I/O Port access - emulate the instruction.
2195	*/
2196	case VINF_IOM_HC_IOPORT_READ:
2197	case VINF_IOM_HC_IOPORT_WRITE:
2198	case VINF_IOM_HC_IOPORT_READWRITE:
2199	rc = emR3RawExecuteIOInstruction(pVM);
2200	break;
2201
2202	/*
2203	* Memory mapped I/O access - emulate the instruction.
2204	*/
2205	case VINF_IOM_HC_MMIO_READ:
2206	case VINF_IOM_HC_MMIO_WRITE:
2207	case VINF_IOM_HC_MMIO_READ_WRITE:
2208	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2209	break;
2210
2211	/*
2212	* Execute instruction.
2213	*/
2214	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2215	rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2216	break;
2217	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2218	rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2219	break;
2220	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2221	rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2222	break;
2223	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2224	rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2225	break;
2226	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2227	rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2228	break;
2229
2230	case VINF_EM_RAW_EMULATE_INSTR_HLT:
2231	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2232	rc = emR3RawPrivileged(pVM);
2233	break;
2234
2235	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2236	rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2237	break;
2238
2239	case VINF_EM_RAW_EMULATE_INSTR:
2240	case VINF_PATCH_EMULATE_INSTR:
2241	rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2242	break;
2243
2244	/*
2245	* Stale selector and iret traps => REM.
2246	*/
2247	case VINF_EM_RAW_STALE_SELECTOR:
2248	case VINF_EM_RAW_IRET_TRAP:
2249	/* We will not go to the recompiler if EIP points to patch code. */
2250	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2251	{
2252	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2253	}
2254	LogFlow(("emR3RawHandleRC: %Vrc -> %Vrc\n", rc, VINF_EM_RESCHEDULE_REM));
2255	rc = VINF_EM_RESCHEDULE_REM;
2256	break;
2257
2258	/*
2259	* Up a level.
2260	*/
2261	case VINF_EM_TERMINATE:
2262	case VINF_EM_OFF:
2263	case VINF_EM_RESET:
2264	case VINF_EM_SUSPEND:
2265	case VINF_EM_HALT:
2266	case VINF_EM_RESUME:
2267	case VINF_EM_RESCHEDULE:
2268	case VINF_EM_RESCHEDULE_REM:
2269	break;
2270
2271	/*
2272	* Up a level and invoke the debugger.
2273	*/
2274	case VINF_EM_DBG_STEPPED:
2275	case VINF_EM_DBG_BREAKPOINT:
2276	case VINF_EM_DBG_STEP:
2277	case VINF_EM_DBG_HYPER_ASSERTION:
2278	case VINF_EM_DBG_HYPER_BREAKPOINT:
2279	case VINF_EM_DBG_HYPER_STEPPED:
2280	case VINF_EM_DBG_STOP:
2281	break;
2282
2283	/*
2284	* Up a level, dump and debug.
2285	*/
2286	case VERR_TRPM_DONT_PANIC:
2287	case VERR_TRPM_PANIC:
2288	break;
2289
2290	/*
2291	* Anything which is not known to us means an internal error
2292	* and the termination of the VM!
2293	*/
2294	default:
2295	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
2296	break;
2297	}
2298	return rc;
2299	}
2300
2301	/**
2302	* Check for pending raw actions
2303	*
2304	* @returns VBox status code.
2305	* @param pVM The VM to operate on.
2306	*/
2307	EMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM)
2308	{
2309	return emR3RawForcedActions(pVM, pVM->em.s.pCtx);
2310	}
2311
2312
2313	/**
2314	* Process raw-mode specific forced actions.
2315	*
2316	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2317	*
2318	* @returns VBox status code.
2319	* Only the normal success/failure stuff, no VINF_EM_*.
2320	* @param pVM The VM handle.
2321	* @param pCtx The guest CPUM register context.
2322	*/
2323	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2324	{
2325	/*
2326	* Note that the order is vitally important!
2327	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2328	*/
2329
2330
2331	/*
2332	* Sync selector tables.
2333	*/
2334	if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT))
2335	{
2336	int rc = SELMR3UpdateFromCPUM(pVM);
2337	if (VBOX_FAILURE(rc))
2338	return rc;
2339	}
2340
2341	/*
2342	* Sync IDT.
2343	*/
2344	if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2345	{
2346	int rc = TRPMR3SyncIDT(pVM);
2347	if (VBOX_FAILURE(rc))
2348	return rc;
2349	}
2350
2351	/*
2352	* Sync TSS.
2353	*/
2354	if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2355	{
2356	int rc = SELMR3SyncTSS(pVM);
2357	if (VBOX_FAILURE(rc))
2358	return rc;
2359	}
2360
2361	/*
2362	* Sync page directory.
2363	*/
2364	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2365	{
2366	int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2367	if (VBOX_FAILURE(rc))
2368	return rc;
2369
2370	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2371
2372	/* Prefetch pages for EIP and ESP */
2373	/** @todo This is rather expensive. Should investigate if it really helps at all. */
2374	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip));
2375	if (rc == VINF_SUCCESS)
2376	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->ss, &pCtx->ssHid, pCtx->esp));
2377	if (rc != VINF_SUCCESS)
2378	{
2379	if (rc != VINF_PGM_SYNC_CR3)
2380	return rc;
2381	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2382	if (VBOX_FAILURE(rc))
2383	return rc;
2384	}
2385	/** @todo maybe prefetch the supervisor stack page as well */
2386	}
2387
2388	return VINF_SUCCESS;
2389	}
2390
2391
2392	/**
2393	* Executes raw code.
2394	*
2395	* This function contains the raw-mode version of the inner
2396	* execution loop (the outer loop being in EMR3ExecuteVM()).
2397	*
2398	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2399	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2400	*
2401	* @param pVM VM handle.
2402	* @param pfFFDone Where to store an indicator telling whether or not
2403	* FFs were done before returning.
2404	*/
2405	static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2406	{
2407	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2408
2409	int rc = VERR_INTERNAL_ERROR;
2410	PCPUMCTX pCtx = pVM->em.s.pCtx;
2411	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2412	pVM->em.s.fForceRAW = false;
2413	*pfFFDone = false;
2414
2415
2416	/*
2417	*
2418	* Spin till we get a forced action or raw mode status code resulting in
2419	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2420	*
2421	*/
2422	for (;;)
2423	{
2424	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2425
2426	/*
2427	* Check various preconditions.
2428	*/
2429	#ifdef VBOX_STRICT
2430	Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2431	Assert(!(pCtx->cr4 & X86_CR4_PAE));
2432	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
2433	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2434	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2435	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2436	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2437	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2438	{
2439	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2440	return VERR_INTERNAL_ERROR;
2441	}
2442	#endif /* VBOX_STRICT */
2443
2444	/*
2445	* Process high priority pre-execution raw-mode FFs.
2446	*/
2447	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2448	{
2449	rc = emR3RawForcedActions(pVM, pCtx);
2450	if (VBOX_FAILURE(rc))
2451	break;
2452	}
2453
2454	/*
2455	* If we're going to execute ring-0 code, the guest state needs to
2456	* be modified a bit and some of the state components (IF, SS/CS RPL,
2457	* and perhaps EIP) needs to be stored with PATM.
2458	*/
2459	rc = CPUMRawEnter(pVM, NULL);
2460	if (rc != VINF_SUCCESS)
2461	{
2462	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2463	break;
2464	}
2465
2466	/*
2467	* Scan code before executing it. Don't bother with user mode or V86 code
2468	*/
2469	if ( (pCtx->ss & X86_SEL_RPL) <= 1
2470	&& !pCtx->eflags.Bits.u1VM
2471	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2472	{
2473	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2474	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
2475	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2476	}
2477
2478	#ifdef LOG_ENABLED
2479	/*
2480	* Log important stuff before entering GC.
2481	*/
2482	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2483	if (pCtx->eflags.Bits.u1VM)
2484	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2485	else if ((pCtx->ss & X86_SEL_RPL) == 1)
2486	{
2487	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2488	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2489	}
2490	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2491	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2492	#endif /* LOG_ENABLED */
2493
2494
2495
2496	/*
2497	* Execute the code.
2498	*/
2499	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2500	STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2501	VMMR3Unlock(pVM);
2502	rc = VMMR3RawRunGC(pVM);
2503	VMMR3Lock(pVM);
2504	STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2505	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2506
2507	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2508	LogFlow(("VMMR3RawRunGC returned %Vrc\n", rc));
2509
2510	/*
2511	* Restore the real CPU state and deal with high priority post
2512	* execution FFs before doing anything else.
2513	*/
2514	rc = CPUMRawLeave(pVM, NULL, rc);
2515	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2516	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2517	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2518
2519	#ifdef PGM_CACHE_VERY_STRICT
2520	/*
2521	* Page manager cache checks.
2522	*/
2523	if ( rc == VINF_EM_RAW_INTERRUPT
2524	\|\| rc == VINF_EM_RAW_GUEST_TRAP
2525	\|\| rc == VINF_IOM_HC_IOPORT_READ
2526	\|\| rc == VINF_IOM_HC_IOPORT_WRITE
2527	\|\| rc == VINF_IOM_HC_IOPORT_READWRITE
2528	//\|\| rc == VINF_PATM_PATCH_INT3
2529	)
2530	pgmCacheCheckPD(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4);
2531	#endif
2532
2533	#ifdef VBOX_STRICT
2534	/*
2535	* Assert TSS consistency & rc vs patch code.
2536	*/
2537	if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS \| VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2538	&& EMIsRawRing0Enabled(pVM))
2539	SELMR3CheckTSS(pVM);
2540	switch (rc)
2541	{
2542	case VINF_SUCCESS:
2543	case VINF_EM_RAW_INTERRUPT:
2544	case VINF_PATM_PATCH_TRAP_PF:
2545	case VINF_PATM_PATCH_TRAP_GP:
2546	case VINF_PATM_PATCH_INT3:
2547	case VINF_PATM_CHECK_PATCH_PAGE:
2548	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2549	case VINF_EM_RAW_GUEST_TRAP:
2550	case VINF_EM_RESCHEDULE_RAW:
2551	break;
2552
2553	default:
2554	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2555	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %VGv for reason %Vrc\n", CPUMGetGuestEIP(pVM), rc));
2556	break;
2557	}
2558	/*
2559	* Let's go paranoid!
2560	*/
2561	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2562	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2563	{
2564	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2565	return VERR_INTERNAL_ERROR;
2566	}
2567	#endif /* VBOX_STRICT */
2568
2569	/*
2570	* Process the returned status code.
2571	*/
2572	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2573	{
2574	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2575	break;
2576	}
2577	rc = emR3RawHandleRC(pVM, pCtx, rc);
2578	if (rc != VINF_SUCCESS)
2579	{
2580	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2581	if (rc != VINF_SUCCESS)
2582	{
2583	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2584	break;
2585	}
2586	}
2587
2588	/*
2589	* Check and execute forced actions.
2590	*/
2591	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2592	TMTimerPoll(pVM);
2593	#endif
2594	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2595	if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2596	{
2597	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
2598
2599	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2600	rc = emR3ForcedActions(pVM, rc);
2601	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2602	if ( rc != VINF_SUCCESS
2603	&& rc != VINF_EM_RESCHEDULE_RAW)
2604	{
2605	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2606	if (rc != VINF_SUCCESS)
2607	{
2608	*pfFFDone = true;
2609	break;
2610	}
2611	}
2612	}
2613	}
2614
2615	/*
2616	* Return to outer loop.
2617	*/
2618	#if defined(LOG_ENABLED) && defined(DEBUG)
2619	RTLogFlush(NULL);
2620	#endif
2621	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2622	return rc;
2623	}
2624
2625
2626	/**
2627	* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2628	*
2629	* This function contains the raw-mode version of the inner
2630	* execution loop (the outer loop being in EMR3ExecuteVM()).
2631	*
2632	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2633	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2634	*
2635	* @param pVM VM handle.
2636	* @param pfFFDone Where to store an indicator telling whether or not
2637	* FFs were done before returning.
2638	*/
2639	static int emR3HwAccExecute(PVM pVM, bool *pfFFDone)
2640	{
2641	int rc = VERR_INTERNAL_ERROR;
2642	PCPUMCTX pCtx = pVM->em.s.pCtx;
2643
2644	LogFlow(("emR3HwAccExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2645	*pfFFDone = false;
2646
2647	STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2648
2649	/*
2650	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
2651	*/
2652	for (;;)
2653	{
2654	STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2655
2656	/*
2657	* Check various preconditions.
2658	*/
2659	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
2660
2661	/*
2662	* Process high priority pre-execution raw-mode FFs.
2663	*/
2664	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2665	{
2666	rc = emR3RawForcedActions(pVM, pCtx);
2667	if (VBOX_FAILURE(rc))
2668	break;
2669	}
2670
2671	#ifdef LOG_ENABLED
2672	uint8_t u8Vector;
2673
2674	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
2675	if (rc == VINF_SUCCESS)
2676	{
2677	Log(("Pending hardware interrupt %d\n", u8Vector));
2678	}
2679	/*
2680	* Log important stuff before entering GC.
2681	*/
2682	if (pCtx->eflags.Bits.u1VM)
2683	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2684	else if ((pCtx->ss & X86_SEL_RPL) == 0)
2685	Log(("HWR0: %08X ESP=%08X IF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (pCtx->ss & X86_SEL_RPL)));
2686	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2687	Log(("HWR3: %08X ESP=%08X IF=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF));
2688	#endif
2689
2690	/*
2691	* Execute the code.
2692	*/
2693	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2694	STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2695	VMMR3Unlock(pVM);
2696	rc = VMMR3HwAccRunGC(pVM);
2697	VMMR3Lock(pVM);
2698	STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2699
2700	/*
2701	* Deal with high priority post execution FFs before doing anything else.
2702	*/
2703	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2704	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2705	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2706
2707	/*
2708	* Process the returned status code.
2709	*/
2710	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2711	break;
2712
2713	rc = emR3RawHandleRC(pVM, pCtx, rc);
2714	if (rc != VINF_SUCCESS)
2715	break;
2716
2717	/*
2718	* Check and execute forced actions.
2719	*/
2720	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2721	TMTimerPoll(pVM);
2722	#endif
2723	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2724	{
2725	rc = emR3ForcedActions(pVM, rc);
2726	if ( rc != VINF_SUCCESS
2727	&& rc != VINF_EM_RESCHEDULE_HWACC)
2728	{
2729	*pfFFDone = true;
2730	break;
2731	}
2732	}
2733	}
2734	/*
2735	* Return to outer loop.
2736	*/
2737	#if defined(LOG_ENABLED) && defined(DEBUG)
2738	RTLogFlush(NULL);
2739	#endif
2740	return rc;
2741	}
2742
2743
2744	/**
2745	* Decides whether to execute RAW, HWACC or REM.
2746	*
2747	* @returns new EM state
2748	* @param pVM The VM.
2749	* @param pCtx The CPU context.
2750	*/
2751	inline EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2752	{
2753	/*
2754	* When forcing raw-mode execution, things are simple.
2755	*/
2756	if (pVM->em.s.fForceRAW)
2757	return EMSTATE_RAW;
2758
2759	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2760	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2761	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2762
2763	X86EFLAGS EFlags = pCtx->eflags;
2764	if (HWACCMIsEnabled(pVM))
2765	{
2766	/* Hardware accelerated raw-mode:
2767	*
2768	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2769	*/
2770	if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2771	return EMSTATE_HWACC;
2772
2773	/** @note Raw mode and hw accelerated mode are incompatible. The latter turns off monitoring features essential for raw mode! */
2774	return EMSTATE_REM;
2775	}
2776
2777	/* Standard raw-mode:
2778	*
2779	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2780	* or 32 bits protected mode ring 0 code
2781	*
2782	* The tests are ordered by the likelyhood of being true during normal execution.
2783	*/
2784	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
2785	{
2786	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2787	return EMSTATE_REM;
2788	}
2789
2790	#ifndef VBOX_RAW_V86
2791	if (EFlags.u32 & X86_EFL_VM) {
2792	Log2(("raw mode refused: VM_MASK\n"));
2793	return EMSTATE_REM;
2794	}
2795	#endif
2796
2797	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2798	uint32_t u32CR0 = pCtx->cr0;
2799	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
2800	{
2801	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2802	return EMSTATE_REM;
2803	}
2804
2805	if (pCtx->cr4 & X86_CR4_PAE)
2806	{
2807	//Log2(("raw mode refused: PAE\n"));
2808	return EMSTATE_REM;
2809	}
2810
2811	unsigned uSS = pCtx->ss;
2812	if ( pCtx->eflags.Bits.u1VM
2813	\|\| (uSS & X86_SEL_RPL) == 3)
2814	{
2815	if (!EMIsRawRing3Enabled(pVM))
2816	return EMSTATE_REM;
2817
2818	if (!(EFlags.u32 & X86_EFL_IF))
2819	{
2820	Log2(("raw mode refused: IF (RawR3)\n"));
2821	return EMSTATE_REM;
2822	}
2823
2824	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
2825	{
2826	Log2(("raw mode refused: CR0.WP + RawR0\n"));
2827	return EMSTATE_REM;
2828	}
2829	}
2830	else
2831	{
2832	if (!EMIsRawRing0Enabled(pVM))
2833	return EMSTATE_REM;
2834
2835	/* Only ring 0 supervisor code. */
2836	if ((uSS & X86_SEL_RPL) != 0)
2837	{
2838	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
2839	return EMSTATE_REM;
2840	}
2841
2842	// Let's start with pure 32 bits ring 0 code first
2843	/** @todo What's pure 32-bit mode? flat? */
2844	if ( !(pCtx->ssHid.Attr.n.u1DefBig)
2845	\|\| !(pCtx->csHid.Attr.n.u1DefBig))
2846	{
2847	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
2848	return EMSTATE_REM;
2849	}
2850
2851	/* Write protection muts be turned on, or else the guest can overwrite our hypervisor code and data. */
2852	if (!(u32CR0 & X86_CR0_WP))
2853	{
2854	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
2855	return EMSTATE_REM;
2856	}
2857
2858	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
2859	{
2860	Log2(("raw r0 mode forced: patch code\n"));
2861	return EMSTATE_RAW;
2862	}
2863
2864	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
2865	if (!(EFlags.u32 & X86_EFL_IF))
2866	{
2867	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
2868	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
2869	return EMSTATE_REM;
2870	}
2871	#endif
2872
2873	/** @todo still necessary??? */
2874	if (EFlags.Bits.u2IOPL != 0)
2875	{
2876	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
2877	return EMSTATE_REM;
2878	}
2879	}
2880
2881	Assert(PGMPhysIsA20Enabled(pVM));
2882	return EMSTATE_RAW;
2883	}
2884
2885
2886	/**
2887	* Executes all high priority post execution force actions.
2888	*
2889	* @returns rc or a fatal status code.
2890	*
2891	* @param pVM VM handle.
2892	* @param rc The current rc.
2893	*/
2894	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
2895	{
2896	if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
2897	PDMR3CritSectFF(pVM);
2898
2899	if (VM_FF_ISSET(pVM, VM_FF_CSAM_PENDING_ACTION))
2900	CSAMR3DoPendingAction(pVM);
2901
2902	return rc;
2903	}
2904
2905
2906	/**
2907	* Executes all pending forced actions.
2908	*
2909	* Forced actions can cause execution delays and execution
2910	* rescheduling. The first we deal with using action priority, so
2911	* that for instance pending timers aren't scheduled and ran until
2912	* right before execution. The rescheduling we deal with using
2913	* return codes. The same goes for VM termination, only in that case
2914	* we exit everything.
2915	*
2916	* @returns VBox status code of equal or greater importance/severity than rc.
2917	* The most important ones are: VINF_EM_RESCHEDULE,
2918	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2919	*
2920	* @param pVM VM handle.
2921	* @param rc The current rc.
2922	*
2923	*/
2924	static int emR3ForcedActions(PVM pVM, int rc)
2925	{
2926	#ifdef VBOX_STRICT
2927	int rcIrq = VINF_SUCCESS;
2928	#endif
2929	STAM_PROFILE_START(&pVM->em.s.StatForcedActions, a);
2930
2931	#define UPDATE_RC() \
2932	do { \
2933	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Vra\n", rc2)); \
2934	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
2935	break; \
2936	if (!rc \|\| rc2 < rc) \
2937	rc = rc2; \
2938	} while (0)
2939
2940	int rc2;
2941
2942	/*
2943	* Post execution chunk first.
2944	*/
2945	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
2946	{
2947	/*
2948	* Termination request.
2949	*/
2950	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
2951	{
2952	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
2953	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
2954	return VINF_EM_TERMINATE;
2955	}
2956
2957	/*
2958	* Debugger Facility polling.
2959	*/
2960	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
2961	{
2962	rc2 = DBGFR3VMMForcedAction(pVM);
2963	UPDATE_RC();
2964	}
2965
2966	/*
2967	* Postponed reset request.
2968	*/
2969	if (VM_FF_ISSET(pVM, VM_FF_RESET))
2970	{
2971	rc2 = VMR3Reset(pVM);
2972	UPDATE_RC();
2973	VM_FF_CLEAR(pVM, VM_FF_RESET);
2974	}
2975
2976	/*
2977	* CSAM page scanning.
2978	*/
2979	if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
2980	{
2981	PCPUMCTX pCtx = pVM->em.s.pCtx;
2982
2983	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
2984	Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
2985
2986	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
2987	VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
2988	}
2989
2990	/* check that we got them all */
2991	Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_CSAM_SCAN_PAGE)));
2992	}
2993
2994	/*
2995	* Normal priority then.
2996	* (Executed in no particular order.)
2997	*/
2998	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
2999	{
3000	/*
3001	* PDM Queues are pending.
3002	*/
3003	if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
3004	PDMR3QueueFlushAll(pVM);
3005
3006	/*
3007	* PDM DMA transfers are pending.
3008	*/
3009	if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
3010	PDMR3DmaRun(pVM);
3011
3012	/*
3013	* Requests from other threads.
3014	*/
3015	if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
3016	{
3017	rc2 = VMR3ReqProcess(pVM);
3018	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3019	{
3020	Log2(("emR3ForcedActions: returns %Vrc\n", rc2));
3021	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3022	return rc2;
3023	}
3024	UPDATE_RC();
3025	}
3026
3027	/* check that we got them all */
3028	Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA)));
3029	}
3030
3031	/*
3032	* Execute polling function ever so often.
3033	* THIS IS A HACK, IT WILL BE REPLACED BY PROPER ASYNC NETWORKING SOON!
3034	*/
3035	static unsigned cLast = 0;
3036	if (!((++cLast) % 4))
3037	PDMR3Poll(pVM);
3038
3039	/*
3040	* High priority pre execution chunk last.
3041	* (Executed in ascending priority order.)
3042	*/
3043	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3044	{
3045	/*
3046	* Timers before interrupts.
3047	*/
3048	if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3049	TMR3TimerQueuesDo(pVM);
3050
3051	/*
3052	* The instruction following an emulated STI should always be executed!
3053	*/
3054	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3055	{
3056	Log(("VM_FF_EMULATED_STI at %VGv successor %VGv\n", CPUMGetGuestEIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3057	if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3058	{
3059	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3060	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3061	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3062	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3063	*/
3064	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3065	}
3066	if (HWACCMR3IsActive(pVM))
3067	rc2 = VINF_EM_RESCHEDULE_HWACC;
3068	else
3069	rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3070
3071	UPDATE_RC();
3072	}
3073
3074	/*
3075	* Interrupts.
3076	*/
3077	if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3078	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_RAW)
3079	&& !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3080	&& PATMAreInterruptsEnabled(pVM)
3081	&& !HWACCMR3IsEventPending(pVM))
3082	{
3083	if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
3084	{
3085	/** @note it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3086	/** @todo this really isn't nice, should properly handle this */
3087	rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3088	#ifdef VBOX_STRICT
3089	rcIrq = rc2;
3090	#endif
3091	UPDATE_RC();
3092	}
3093	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3094	else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3095	{
3096	rc2 = VINF_EM_RESCHEDULE_REM;
3097	UPDATE_RC();
3098	}
3099	}
3100
3101	/*
3102	* Debugger Facility request.
3103	*/
3104	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3105	{
3106	rc2 = DBGFR3VMMForcedAction(pVM);
3107	UPDATE_RC();
3108	}
3109
3110	/*
3111	* Termination request.
3112	*/
3113	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3114	{
3115	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3116	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3117	return VINF_EM_TERMINATE;
3118	}
3119
3120	#ifdef DEBUG
3121	/*
3122	* Debug, pause the VM.
3123	*/
3124	if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3125	{
3126	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3127	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3128	return VINF_EM_SUSPEND;
3129	}
3130
3131	#endif
3132	/* check that we got them all */
3133	Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER \| VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC \| VM_FF_DBGF \| VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL \| VM_FF_SELM_SYNC_TSS \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TERMINATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_INHIBIT_INTERRUPTS)));
3134	}
3135
3136	#undef UPDATE_RC
3137	Log2(("emR3ForcedActions: returns %Vrc\n", rc));
3138	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3139	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
3140	return rc;
3141	}
3142
3143
3144	/**
3145	* Execute VM.
3146	*
3147	* This function is the main loop of the VM. The emulation thread
3148	* calls this function when the VM has been successfully constructed
3149	* and we're ready for executing the VM.
3150	*
3151	* Returning from this function means that the VM is turned off or
3152	* suspended (state already saved) and deconstruction in next in line.
3153	*
3154	* All interaction from other thread are done using forced actions
3155	* and signaling of the wait object.
3156	*
3157	* @returns VBox status code.
3158	* @param pVM The VM to operate on.
3159	*/
3160	EMR3DECL(int) EMR3ExecuteVM(PVM pVM)
3161	{
3162	LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3163	pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3164	VM_ASSERT_EMT(pVM);
3165	Assert(pVM->em.s.enmState == EMSTATE_NONE \|\| pVM->em.s.enmState == EMSTATE_SUSPENDED);
3166
3167	VMMR3Lock(pVM);
3168
3169	int rc = setjmp(pVM->em.s.u.FatalLongJump);
3170	if (rc == 0)
3171	{
3172	/*
3173	* Start the virtual time.
3174	*/
3175	rc = TMVirtualResume(pVM);
3176	Assert(rc == VINF_SUCCESS);
3177	rc = TMCpuTickResume(pVM);
3178	Assert(rc == VINF_SUCCESS);
3179
3180	/*
3181	* The Outer Main Loop.
3182	*/
3183	bool fFFDone = false;
3184	rc = VINF_EM_RESCHEDULE;
3185	pVM->em.s.enmState = EMSTATE_REM;
3186	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3187	for (;;)
3188	{
3189	/*
3190	* Before we can schedule anything (we're here because
3191	* scheduling is required) we must service any pending
3192	* forced actions to avoid any pending action causing
3193	* immidate rescheduling upon entering an inner loop
3194	*
3195	* Do forced actions.
3196	*/
3197	if ( !fFFDone
3198	&& rc != VINF_EM_TERMINATE
3199	&& rc != VINF_EM_OFF
3200	&& VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3201	{
3202	rc = emR3ForcedActions(pVM, rc);
3203	if ( ( rc == VINF_EM_RESCHEDULE_REM
3204	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
3205	&& pVM->em.s.fForceRAW)
3206	rc = VINF_EM_RESCHEDULE_RAW;
3207	}
3208	else if (fFFDone)
3209	fFFDone = false;
3210
3211	/*
3212	* Now what to do?
3213	*/
3214	Log2(("EMR3ExecuteVM: rc=%Vrc\n", rc));
3215	switch (rc)
3216	{
3217	/*
3218	* Keep doing what we're currently doing.
3219	*/
3220	case VINF_SUCCESS:
3221	break;
3222
3223	/*
3224	* Reschedule - to raw-mode execution.
3225	*/
3226	case VINF_EM_RESCHEDULE_RAW:
3227	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3228	pVM->em.s.enmState = EMSTATE_RAW;
3229	break;
3230
3231	/*
3232	* Reschedule - to hardware accelerated raw-mode execution.
3233	*/
3234	case VINF_EM_RESCHEDULE_HWACC:
3235	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3236	Assert(!pVM->em.s.fForceRAW);
3237	pVM->em.s.enmState = EMSTATE_HWACC;
3238	break;
3239
3240	/*
3241	* Reschedule - to recompiled execution.
3242	*/
3243	case VINF_EM_RESCHEDULE_REM:
3244	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3245	pVM->em.s.enmState = EMSTATE_REM;
3246	break;
3247
3248	/*
3249	* Resume.
3250	*/
3251	case VINF_EM_RESUME:
3252	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3253	/* fall through and get scheduled. */
3254
3255	/*
3256	* Reschedule.
3257	*/
3258	case VINF_EM_RESCHEDULE:
3259	{
3260	EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3261	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3262	pVM->em.s.enmState = enmState;
3263	break;
3264	}
3265
3266	/*
3267	* Halted.
3268	*/
3269	case VINF_EM_HALT:
3270	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3271	pVM->em.s.enmState = EMSTATE_HALTED;
3272	break;
3273
3274	/*
3275	* Suspend.
3276	*/
3277	case VINF_EM_SUSPEND:
3278	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3279	pVM->em.s.enmState = EMSTATE_SUSPENDED;
3280	break;
3281
3282	/*
3283	* Reset.
3284	* We might end up doing a double reset for now, we'll have to clean up the mess later.
3285	*/
3286	case VINF_EM_RESET:
3287	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d\n", pVM->em.s.enmState, EMSTATE_REM));
3288	pVM->em.s.enmState = EMSTATE_REM;
3289	break;
3290
3291	/*
3292	* Power Off.
3293	*/
3294	case VINF_EM_OFF:
3295	pVM->em.s.enmState = EMSTATE_TERMINATING;
3296	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3297	TMVirtualPause(pVM);
3298	TMCpuTickPause(pVM);
3299	VMMR3Unlock(pVM);
3300	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3301	return rc;
3302
3303	/*
3304	* Terminate the VM.
3305	*/
3306	case VINF_EM_TERMINATE:
3307	pVM->em.s.enmState = EMSTATE_TERMINATING;
3308	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3309	TMVirtualPause(pVM);
3310	TMCpuTickPause(pVM);
3311	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3312	return rc;
3313
3314	/*
3315	* Guest debug events.
3316	*/
3317	case VINF_EM_DBG_STEPPED:
3318	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3319	case VINF_EM_DBG_STOP:
3320	case VINF_EM_DBG_BREAKPOINT:
3321	case VINF_EM_DBG_STEP:
3322	if (pVM->em.s.enmState == EMSTATE_RAW)
3323	{
3324	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3325	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3326	}
3327	else
3328	{
3329	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3330	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3331	}
3332	break;
3333
3334	/*
3335	* Hypervisor debug events.
3336	*/
3337	case VINF_EM_DBG_HYPER_STEPPED:
3338	case VINF_EM_DBG_HYPER_BREAKPOINT:
3339	case VINF_EM_DBG_HYPER_ASSERTION:
3340	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3341	pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3342	break;
3343
3344	/*
3345	* Any error code showing up here other than the ones we
3346	* know and process above are considered to be FATAL.
3347	*
3348	* Unknown warnings and informational status codes are also
3349	* included in this.
3350	*/
3351	default:
3352	if (VBOX_SUCCESS(rc))
3353	{
3354	AssertMsgFailed(("Unexpected warning or informational status code %Vra!\n", rc));
3355	rc = VERR_EM_INTERNAL_ERROR;
3356	}
3357	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3358	Log(("EMR3ExecuteVM returns %d\n", rc));
3359	break;
3360	}
3361
3362
3363	/*
3364	* Any waiters can now be woken up
3365	*/
3366	VMMR3Unlock(pVM);
3367	VMMR3Lock(pVM);
3368
3369	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3370	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3371
3372	/*
3373	* Act on the state.
3374	*/
3375	switch (pVM->em.s.enmState)
3376	{
3377	/*
3378	* Execute raw.
3379	*/
3380	case EMSTATE_RAW:
3381	rc = emR3RawExecute(pVM, &fFFDone);
3382	break;
3383
3384	/*
3385	* Execute hardware accelerated raw.
3386	*/
3387	case EMSTATE_HWACC:
3388	rc = emR3HwAccExecute(pVM, &fFFDone);
3389	break;
3390
3391	/*
3392	* Execute recompiled.
3393	*/
3394	case EMSTATE_REM:
3395	rc = emR3RemExecute(pVM, &fFFDone);
3396	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Vrc\n", rc));
3397	break;
3398
3399	/*
3400	* hlt - execution halted until interrupt.
3401	*/
3402	case EMSTATE_HALTED:
3403	{
3404	STAM_PROFILE_START(&pVM->em.s.StatHalted, y);
3405	rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3406	STAM_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3407	break;
3408	}
3409
3410	/*
3411	* Suspended - return to VM.cpp.
3412	*/
3413	case EMSTATE_SUSPENDED:
3414	TMVirtualPause(pVM);
3415	TMCpuTickPause(pVM);
3416	VMMR3Unlock(pVM);
3417	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3418	return VINF_EM_SUSPEND;
3419
3420	/*
3421	* Debugging in the guest.
3422	*/
3423	case EMSTATE_DEBUG_GUEST_REM:
3424	case EMSTATE_DEBUG_GUEST_RAW:
3425	TMVirtualPause(pVM);
3426	TMCpuTickPause(pVM);
3427	rc = emR3Debug(pVM, rc);
3428	TMVirtualResume(pVM);
3429	TMCpuTickResume(pVM);
3430	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3431	break;
3432
3433	/*
3434	* Debugging in the hypervisor.
3435	*/
3436	case EMSTATE_DEBUG_HYPER:
3437	{
3438	TMVirtualPause(pVM);
3439	TMCpuTickPause(pVM);
3440	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3441
3442	rc = emR3Debug(pVM, rc);
3443	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3444	if (rc != VINF_SUCCESS)
3445	{
3446	/* switch to guru meditation mode */
3447	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3448	VMMR3FatalDump(pVM, rc);
3449	return rc;
3450	}
3451
3452	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3453	TMVirtualResume(pVM);
3454	TMCpuTickResume(pVM);
3455	break;
3456	}
3457
3458	/*
3459	* Guru meditation takes place in the debugger.
3460	*/
3461	case EMSTATE_GURU_MEDITATION:
3462	{
3463	/** @todo this ain't entirely safe. make a better return code check and specify this in DBGF/emR3Debug. */
3464	TMVirtualPause(pVM);
3465	TMCpuTickPause(pVM);
3466	VMMR3FatalDump(pVM, rc);
3467	int rc2 = emR3Debug(pVM, rc);
3468	if (rc2 == VERR_DBGF_NOT_ATTACHED)
3469	{
3470	VMMR3Unlock(pVM);
3471	/** @todo change the VM state! */
3472	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3473	return rc;
3474	}
3475	TMVirtualResume(pVM);
3476	TMCpuTickResume(pVM);
3477	rc = rc2;
3478	/** @todo we're not doing the right thing in emR3Debug and will cause code to be executed on disconnect and stuff.. */
3479	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3480	break;
3481	}
3482
3483	/*
3484	* The states we don't expect here.
3485	*/
3486	case EMSTATE_NONE:
3487	case EMSTATE_TERMINATING:
3488	default:
3489	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3490	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3491	TMVirtualPause(pVM);
3492	TMCpuTickPause(pVM);
3493	VMMR3Unlock(pVM);
3494	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3495	return VERR_EM_INTERNAL_ERROR;
3496	}
3497	} /* The Outer Main Loop */
3498	}
3499	else
3500	{
3501	/*
3502	* Fatal error.
3503	*/
3504	LogFlow(("EMR3ExecuteVM: returns %Vrc (longjmp / fatal error)\n", rc));
3505	TMVirtualPause(pVM);
3506	TMCpuTickPause(pVM);
3507	VMMR3FatalDump(pVM, rc);
3508	emR3Debug(pVM, rc);
3509	VMMR3Unlock(pVM);
3510	/** @todo change the VM state! */
3511	return rc;
3512	}
3513
3514	/* (won't ever get here). */
3515	AssertFailed();
3516	}
3517

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/EM.cpp@ 2397

Download in other formats: