VirtualBox

source: vbox/trunk/src/VBox/VMM/EM.cpp@ 25942

Last change on this file since 25942 was 25825, checked in by vboxsync, 15 years ago

r=bird: hot-plug review and code style cleanup. check out the @todos
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1/* $Id: EM.cpp 25825 2010-01-14 10:39:12Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_em EM - The Execution Monitor / Manager
23 *
24 * The Execution Monitor/Manager is responsible for running the VM, scheduling
25 * the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
26 * Interpreted), and keeping the CPU states in sync. The function
27 * EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
28 * modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
29 * emR3RemExecute).
30 *
31 * The interpreted execution is only used to avoid switching between
32 * raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
33 * The interpretation is thus implemented as part of EM.
34 *
35 * @see grp_em
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_EM
42#include <VBox/em.h>
43#include <VBox/vmm.h>
44#ifdef VBOX_WITH_VMI
45# include <VBox/parav.h>
46#endif
47#include <VBox/patm.h>
48#include <VBox/csam.h>
49#include <VBox/selm.h>
50#include <VBox/trpm.h>
51#include <VBox/iom.h>
52#include <VBox/dbgf.h>
53#include <VBox/pgm.h>
54#include <VBox/rem.h>
55#include <VBox/tm.h>
56#include <VBox/mm.h>
57#include <VBox/ssm.h>
58#include <VBox/pdmapi.h>
59#include <VBox/pdmcritsect.h>
60#include <VBox/pdmqueue.h>
61#include <VBox/hwaccm.h>
62#include <VBox/patm.h>
63#include "EMInternal.h"
64#include <VBox/vm.h>
65#include <VBox/cpumdis.h>
66#include <VBox/dis.h>
67#include <VBox/disopcode.h>
68#include <VBox/dbgf.h>
69
70#include <iprt/string.h>
71#include <iprt/stream.h>
72
73
74/*******************************************************************************
75* Defined Constants And Macros *
76*******************************************************************************/
77#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
78#define EM_NOTIFY_HWACCM
79#endif
80
81
82/*******************************************************************************
83* Internal Functions *
84*******************************************************************************/
85static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
86static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
87static const char *emR3GetStateName(EMSTATE enmState);
88static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc);
89static int emR3RemStep(PVM pVM, PVMCPU pVCpu);
90static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
91DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
92int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
93
94
95/**
96 * Initializes the EM.
97 *
98 * @returns VBox status code.
99 * @param pVM The VM to operate on.
100 */
101VMMR3DECL(int) EMR3Init(PVM pVM)
102{
103 LogFlow(("EMR3Init\n"));
104 /*
105 * Assert alignment and sizes.
106 */
107 AssertCompileMemberAlignment(VM, em.s, 32);
108 AssertCompile(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
109 AssertCompile(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump));
110 AssertCompileMemberAlignment(EM, CritSectREM, sizeof(uintptr_t));
111
112 /*
113 * Init the structure.
114 */
115 pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
116 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
117 if (RT_FAILURE(rc))
118 pVM->fRawR3Enabled = true;
119 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
120 if (RT_FAILURE(rc))
121 pVM->fRawR0Enabled = true;
122 Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
123
124 /*
125 * Initialize the REM critical section.
126 */
127 rc = PDMR3CritSectInit(pVM, &pVM->em.s.CritSectREM, RT_SRC_POS, "EM-REM");
128 AssertRCReturn(rc, rc);
129
130 /*
131 * Saved state.
132 */
133 rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
134 NULL, NULL, NULL,
135 NULL, emR3Save, NULL,
136 NULL, emR3Load, NULL);
137 if (RT_FAILURE(rc))
138 return rc;
139
140 for (VMCPUID i = 0; i < pVM->cCpus; i++)
141 {
142 PVMCPU pVCpu = &pVM->aCpus[i];
143
144 pVCpu->em.s.offVMCPU = RT_OFFSETOF(VMCPU, em.s);
145
146 pVCpu->em.s.enmState = (i == 0) ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
147 pVCpu->em.s.enmPrevState = EMSTATE_NONE;
148 pVCpu->em.s.fForceRAW = false;
149
150 pVCpu->em.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
151 pVCpu->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
152 AssertMsg(pVCpu->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
153
154# define EM_REG_COUNTER(a, b, c) \
155 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
156 AssertRC(rc);
157
158# define EM_REG_COUNTER_USED(a, b, c) \
159 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, c, b, i); \
160 AssertRC(rc);
161
162# define EM_REG_PROFILE(a, b, c) \
163 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
164 AssertRC(rc);
165
166# define EM_REG_PROFILE_ADV(a, b, c) \
167 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
168 AssertRC(rc);
169
170 /*
171 * Statistics.
172 */
173#ifdef VBOX_WITH_STATISTICS
174 PEMSTATS pStats;
175 rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
176 if (RT_FAILURE(rc))
177 return rc;
178
179 pVCpu->em.s.pStatsR3 = pStats;
180 pVCpu->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
181 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
182
183 EM_REG_PROFILE(&pStats->StatRZEmulate, "/EM/CPU%d/RZ/Interpret", "Profiling of EMInterpretInstruction.");
184 EM_REG_PROFILE(&pStats->StatR3Emulate, "/EM/CPU%d/R3/Interpret", "Profiling of EMInterpretInstruction.");
185
186 EM_REG_PROFILE(&pStats->StatRZInterpretSucceeded, "/EM/CPU%d/RZ/Interpret/Success", "The number of times an instruction was successfully interpreted.");
187 EM_REG_PROFILE(&pStats->StatR3InterpretSucceeded, "/EM/CPU%d/R3/Interpret/Success", "The number of times an instruction was successfully interpreted.");
188
189 EM_REG_COUNTER_USED(&pStats->StatRZAnd, "/EM/CPU%d/RZ/Interpret/Success/And", "The number of times AND was successfully interpreted.");
190 EM_REG_COUNTER_USED(&pStats->StatR3And, "/EM/CPU%d/R3/Interpret/Success/And", "The number of times AND was successfully interpreted.");
191 EM_REG_COUNTER_USED(&pStats->StatRZAdd, "/EM/CPU%d/RZ/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
192 EM_REG_COUNTER_USED(&pStats->StatR3Add, "/EM/CPU%d/R3/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
193 EM_REG_COUNTER_USED(&pStats->StatRZAdc, "/EM/CPU%d/RZ/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
194 EM_REG_COUNTER_USED(&pStats->StatR3Adc, "/EM/CPU%d/R3/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
195 EM_REG_COUNTER_USED(&pStats->StatRZSub, "/EM/CPU%d/RZ/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
196 EM_REG_COUNTER_USED(&pStats->StatR3Sub, "/EM/CPU%d/R3/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
197 EM_REG_COUNTER_USED(&pStats->StatRZCpuId, "/EM/CPU%d/RZ/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
198 EM_REG_COUNTER_USED(&pStats->StatR3CpuId, "/EM/CPU%d/R3/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
199 EM_REG_COUNTER_USED(&pStats->StatRZDec, "/EM/CPU%d/RZ/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
200 EM_REG_COUNTER_USED(&pStats->StatR3Dec, "/EM/CPU%d/R3/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
201 EM_REG_COUNTER_USED(&pStats->StatRZHlt, "/EM/CPU%d/RZ/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
202 EM_REG_COUNTER_USED(&pStats->StatR3Hlt, "/EM/CPU%d/R3/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
203 EM_REG_COUNTER_USED(&pStats->StatRZInc, "/EM/CPU%d/RZ/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
204 EM_REG_COUNTER_USED(&pStats->StatR3Inc, "/EM/CPU%d/R3/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
205 EM_REG_COUNTER_USED(&pStats->StatRZInvlPg, "/EM/CPU%d/RZ/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
206 EM_REG_COUNTER_USED(&pStats->StatR3InvlPg, "/EM/CPU%d/R3/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
207 EM_REG_COUNTER_USED(&pStats->StatRZIret, "/EM/CPU%d/RZ/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
208 EM_REG_COUNTER_USED(&pStats->StatR3Iret, "/EM/CPU%d/R3/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
209 EM_REG_COUNTER_USED(&pStats->StatRZLLdt, "/EM/CPU%d/RZ/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
210 EM_REG_COUNTER_USED(&pStats->StatR3LLdt, "/EM/CPU%d/R3/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
211 EM_REG_COUNTER_USED(&pStats->StatRZLIdt, "/EM/CPU%d/RZ/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
212 EM_REG_COUNTER_USED(&pStats->StatR3LIdt, "/EM/CPU%d/R3/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
213 EM_REG_COUNTER_USED(&pStats->StatRZLGdt, "/EM/CPU%d/RZ/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
214 EM_REG_COUNTER_USED(&pStats->StatR3LGdt, "/EM/CPU%d/R3/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
215 EM_REG_COUNTER_USED(&pStats->StatRZMov, "/EM/CPU%d/RZ/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
216 EM_REG_COUNTER_USED(&pStats->StatR3Mov, "/EM/CPU%d/R3/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
217 EM_REG_COUNTER_USED(&pStats->StatRZMovCRx, "/EM/CPU%d/RZ/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
218 EM_REG_COUNTER_USED(&pStats->StatR3MovCRx, "/EM/CPU%d/R3/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
219 EM_REG_COUNTER_USED(&pStats->StatRZMovDRx, "/EM/CPU%d/RZ/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
220 EM_REG_COUNTER_USED(&pStats->StatR3MovDRx, "/EM/CPU%d/R3/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
221 EM_REG_COUNTER_USED(&pStats->StatRZOr, "/EM/CPU%d/RZ/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
222 EM_REG_COUNTER_USED(&pStats->StatR3Or, "/EM/CPU%d/R3/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
223 EM_REG_COUNTER_USED(&pStats->StatRZPop, "/EM/CPU%d/RZ/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
224 EM_REG_COUNTER_USED(&pStats->StatR3Pop, "/EM/CPU%d/R3/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
225 EM_REG_COUNTER_USED(&pStats->StatRZRdtsc, "/EM/CPU%d/RZ/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
226 EM_REG_COUNTER_USED(&pStats->StatR3Rdtsc, "/EM/CPU%d/R3/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
227 EM_REG_COUNTER_USED(&pStats->StatRZRdpmc, "/EM/CPU%d/RZ/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
228 EM_REG_COUNTER_USED(&pStats->StatR3Rdpmc, "/EM/CPU%d/R3/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
229 EM_REG_COUNTER_USED(&pStats->StatRZSti, "/EM/CPU%d/RZ/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
230 EM_REG_COUNTER_USED(&pStats->StatR3Sti, "/EM/CPU%d/R3/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
231 EM_REG_COUNTER_USED(&pStats->StatRZXchg, "/EM/CPU%d/RZ/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
232 EM_REG_COUNTER_USED(&pStats->StatR3Xchg, "/EM/CPU%d/R3/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
233 EM_REG_COUNTER_USED(&pStats->StatRZXor, "/EM/CPU%d/RZ/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
234 EM_REG_COUNTER_USED(&pStats->StatR3Xor, "/EM/CPU%d/R3/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
235 EM_REG_COUNTER_USED(&pStats->StatRZMonitor, "/EM/CPU%d/RZ/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
236 EM_REG_COUNTER_USED(&pStats->StatR3Monitor, "/EM/CPU%d/R3/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
237 EM_REG_COUNTER_USED(&pStats->StatRZMWait, "/EM/CPU%d/RZ/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
238 EM_REG_COUNTER_USED(&pStats->StatR3MWait, "/EM/CPU%d/R3/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
239 EM_REG_COUNTER_USED(&pStats->StatRZBtr, "/EM/CPU%d/RZ/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
240 EM_REG_COUNTER_USED(&pStats->StatR3Btr, "/EM/CPU%d/R3/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
241 EM_REG_COUNTER_USED(&pStats->StatRZBts, "/EM/CPU%d/RZ/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
242 EM_REG_COUNTER_USED(&pStats->StatR3Bts, "/EM/CPU%d/R3/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
243 EM_REG_COUNTER_USED(&pStats->StatRZBtc, "/EM/CPU%d/RZ/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
244 EM_REG_COUNTER_USED(&pStats->StatR3Btc, "/EM/CPU%d/R3/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
245 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
246 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg, "/EM/CPU%d/R3/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
247 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
248 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg8b, "/EM/CPU%d/R3/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
249 EM_REG_COUNTER_USED(&pStats->StatRZXAdd, "/EM/CPU%d/RZ/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
250 EM_REG_COUNTER_USED(&pStats->StatR3XAdd, "/EM/CPU%d/R3/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
251 EM_REG_COUNTER_USED(&pStats->StatR3Rdmsr, "/EM/CPU%d/R3/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
252 EM_REG_COUNTER_USED(&pStats->StatRZRdmsr, "/EM/CPU%d/RZ/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
253 EM_REG_COUNTER_USED(&pStats->StatR3Wrmsr, "/EM/CPU%d/R3/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
254 EM_REG_COUNTER_USED(&pStats->StatRZWrmsr, "/EM/CPU%d/RZ/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
255 EM_REG_COUNTER_USED(&pStats->StatR3StosWD, "/EM/CPU%d/R3/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
256 EM_REG_COUNTER_USED(&pStats->StatRZStosWD, "/EM/CPU%d/RZ/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
257 EM_REG_COUNTER_USED(&pStats->StatRZWbInvd, "/EM/CPU%d/RZ/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
258 EM_REG_COUNTER_USED(&pStats->StatR3WbInvd, "/EM/CPU%d/R3/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
259 EM_REG_COUNTER_USED(&pStats->StatRZLmsw, "/EM/CPU%d/RZ/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
260 EM_REG_COUNTER_USED(&pStats->StatR3Lmsw, "/EM/CPU%d/R3/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
261
262 EM_REG_COUNTER(&pStats->StatRZInterpretFailed, "/EM/CPU%d/RZ/Interpret/Failed", "The number of times an instruction was not interpreted.");
263 EM_REG_COUNTER(&pStats->StatR3InterpretFailed, "/EM/CPU%d/R3/Interpret/Failed", "The number of times an instruction was not interpreted.");
264
265 EM_REG_COUNTER_USED(&pStats->StatRZFailedAnd, "/EM/CPU%d/RZ/Interpret/Failed/And", "The number of times AND was not interpreted.");
266 EM_REG_COUNTER_USED(&pStats->StatR3FailedAnd, "/EM/CPU%d/R3/Interpret/Failed/And", "The number of times AND was not interpreted.");
267 EM_REG_COUNTER_USED(&pStats->StatRZFailedCpuId, "/EM/CPU%d/RZ/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
268 EM_REG_COUNTER_USED(&pStats->StatR3FailedCpuId, "/EM/CPU%d/R3/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
269 EM_REG_COUNTER_USED(&pStats->StatRZFailedDec, "/EM/CPU%d/RZ/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
270 EM_REG_COUNTER_USED(&pStats->StatR3FailedDec, "/EM/CPU%d/R3/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
271 EM_REG_COUNTER_USED(&pStats->StatRZFailedHlt, "/EM/CPU%d/RZ/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
272 EM_REG_COUNTER_USED(&pStats->StatR3FailedHlt, "/EM/CPU%d/R3/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
273 EM_REG_COUNTER_USED(&pStats->StatRZFailedInc, "/EM/CPU%d/RZ/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
274 EM_REG_COUNTER_USED(&pStats->StatR3FailedInc, "/EM/CPU%d/R3/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
275 EM_REG_COUNTER_USED(&pStats->StatRZFailedInvlPg, "/EM/CPU%d/RZ/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
276 EM_REG_COUNTER_USED(&pStats->StatR3FailedInvlPg, "/EM/CPU%d/R3/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
277 EM_REG_COUNTER_USED(&pStats->StatRZFailedIret, "/EM/CPU%d/RZ/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
278 EM_REG_COUNTER_USED(&pStats->StatR3FailedIret, "/EM/CPU%d/R3/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
279 EM_REG_COUNTER_USED(&pStats->StatRZFailedLLdt, "/EM/CPU%d/RZ/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
280 EM_REG_COUNTER_USED(&pStats->StatR3FailedLLdt, "/EM/CPU%d/R3/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
281 EM_REG_COUNTER_USED(&pStats->StatRZFailedLIdt, "/EM/CPU%d/RZ/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
282 EM_REG_COUNTER_USED(&pStats->StatR3FailedLIdt, "/EM/CPU%d/R3/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
283 EM_REG_COUNTER_USED(&pStats->StatRZFailedLGdt, "/EM/CPU%d/RZ/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
284 EM_REG_COUNTER_USED(&pStats->StatR3FailedLGdt, "/EM/CPU%d/R3/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
285 EM_REG_COUNTER_USED(&pStats->StatRZFailedMov, "/EM/CPU%d/RZ/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
286 EM_REG_COUNTER_USED(&pStats->StatR3FailedMov, "/EM/CPU%d/R3/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
287 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovCRx, "/EM/CPU%d/RZ/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
288 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovCRx, "/EM/CPU%d/R3/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
289 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovDRx, "/EM/CPU%d/RZ/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
290 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovDRx, "/EM/CPU%d/R3/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
291 EM_REG_COUNTER_USED(&pStats->StatRZFailedOr, "/EM/CPU%d/RZ/Interpret/Failed/Or", "The number of times OR was not interpreted.");
292 EM_REG_COUNTER_USED(&pStats->StatR3FailedOr, "/EM/CPU%d/R3/Interpret/Failed/Or", "The number of times OR was not interpreted.");
293 EM_REG_COUNTER_USED(&pStats->StatRZFailedPop, "/EM/CPU%d/RZ/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
294 EM_REG_COUNTER_USED(&pStats->StatR3FailedPop, "/EM/CPU%d/R3/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
295 EM_REG_COUNTER_USED(&pStats->StatRZFailedSti, "/EM/CPU%d/RZ/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
296 EM_REG_COUNTER_USED(&pStats->StatR3FailedSti, "/EM/CPU%d/R3/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
297 EM_REG_COUNTER_USED(&pStats->StatRZFailedXchg, "/EM/CPU%d/RZ/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
298 EM_REG_COUNTER_USED(&pStats->StatR3FailedXchg, "/EM/CPU%d/R3/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
299 EM_REG_COUNTER_USED(&pStats->StatRZFailedXor, "/EM/CPU%d/RZ/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
300 EM_REG_COUNTER_USED(&pStats->StatR3FailedXor, "/EM/CPU%d/R3/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
301 EM_REG_COUNTER_USED(&pStats->StatRZFailedMonitor, "/EM/CPU%d/RZ/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
302 EM_REG_COUNTER_USED(&pStats->StatR3FailedMonitor, "/EM/CPU%d/R3/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
303 EM_REG_COUNTER_USED(&pStats->StatRZFailedMWait, "/EM/CPU%d/RZ/Interpret/Failed/MWait", "The number of times MONITOR was not interpreted.");
304 EM_REG_COUNTER_USED(&pStats->StatR3FailedMWait, "/EM/CPU%d/R3/Interpret/Failed/MWait", "The number of times MONITOR was not interpreted.");
305 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdtsc, "/EM/CPU%d/RZ/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
306 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdtsc, "/EM/CPU%d/R3/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
307 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdpmc, "/EM/CPU%d/RZ/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
308 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdpmc, "/EM/CPU%d/R3/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
309 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdmsr, "/EM/CPU%d/RZ/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
310 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdmsr, "/EM/CPU%d/R3/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
311 EM_REG_COUNTER_USED(&pStats->StatRZFailedWrmsr, "/EM/CPU%d/RZ/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
312 EM_REG_COUNTER_USED(&pStats->StatR3FailedWrmsr, "/EM/CPU%d/R3/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
313 EM_REG_COUNTER_USED(&pStats->StatRZFailedLmsw, "/EM/CPU%d/RZ/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
314 EM_REG_COUNTER_USED(&pStats->StatR3FailedLmsw, "/EM/CPU%d/R3/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
315
316 EM_REG_COUNTER_USED(&pStats->StatRZFailedMisc, "/EM/CPU%d/RZ/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
317 EM_REG_COUNTER_USED(&pStats->StatR3FailedMisc, "/EM/CPU%d/R3/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
318 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdd, "/EM/CPU%d/RZ/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
319 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdd, "/EM/CPU%d/R3/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
320 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdc, "/EM/CPU%d/RZ/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
321 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdc, "/EM/CPU%d/R3/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
322 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtr, "/EM/CPU%d/RZ/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
323 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtr, "/EM/CPU%d/R3/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
324 EM_REG_COUNTER_USED(&pStats->StatRZFailedBts, "/EM/CPU%d/RZ/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
325 EM_REG_COUNTER_USED(&pStats->StatR3FailedBts, "/EM/CPU%d/R3/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
326 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtc, "/EM/CPU%d/RZ/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
327 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtc, "/EM/CPU%d/R3/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
328 EM_REG_COUNTER_USED(&pStats->StatRZFailedCli, "/EM/CPU%d/RZ/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
329 EM_REG_COUNTER_USED(&pStats->StatR3FailedCli, "/EM/CPU%d/R3/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
330 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
331 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
332 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
333 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg8b, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
334 EM_REG_COUNTER_USED(&pStats->StatRZFailedXAdd, "/EM/CPU%d/RZ/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
335 EM_REG_COUNTER_USED(&pStats->StatR3FailedXAdd, "/EM/CPU%d/R3/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
336 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovNTPS, "/EM/CPU%d/RZ/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
337 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovNTPS, "/EM/CPU%d/R3/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
338 EM_REG_COUNTER_USED(&pStats->StatRZFailedStosWD, "/EM/CPU%d/RZ/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
339 EM_REG_COUNTER_USED(&pStats->StatR3FailedStosWD, "/EM/CPU%d/R3/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
340 EM_REG_COUNTER_USED(&pStats->StatRZFailedSub, "/EM/CPU%d/RZ/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
341 EM_REG_COUNTER_USED(&pStats->StatR3FailedSub, "/EM/CPU%d/R3/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
342 EM_REG_COUNTER_USED(&pStats->StatRZFailedWbInvd, "/EM/CPU%d/RZ/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
343 EM_REG_COUNTER_USED(&pStats->StatR3FailedWbInvd, "/EM/CPU%d/R3/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
344
345 EM_REG_COUNTER_USED(&pStats->StatRZFailedUserMode, "/EM/CPU%d/RZ/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
346 EM_REG_COUNTER_USED(&pStats->StatR3FailedUserMode, "/EM/CPU%d/R3/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
347 EM_REG_COUNTER_USED(&pStats->StatRZFailedPrefix, "/EM/CPU%d/RZ/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
348 EM_REG_COUNTER_USED(&pStats->StatR3FailedPrefix, "/EM/CPU%d/R3/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
349
350 EM_REG_COUNTER_USED(&pStats->StatCli, "/EM/CPU%d/R3/PrivInst/Cli", "Number of cli instructions.");
351 EM_REG_COUNTER_USED(&pStats->StatSti, "/EM/CPU%d/R3/PrivInst/Sti", "Number of sli instructions.");
352 EM_REG_COUNTER_USED(&pStats->StatIn, "/EM/CPU%d/R3/PrivInst/In", "Number of in instructions.");
353 EM_REG_COUNTER_USED(&pStats->StatOut, "/EM/CPU%d/R3/PrivInst/Out", "Number of out instructions.");
354 EM_REG_COUNTER_USED(&pStats->StatIoRestarted, "/EM/CPU%d/R3/PrivInst/IoRestarted", "Number of restarted i/o instructions.");
355 EM_REG_COUNTER_USED(&pStats->StatHlt, "/EM/CPU%d/R3/PrivInst/Hlt", "Number of hlt instructions not handled in GC because of PATM.");
356 EM_REG_COUNTER_USED(&pStats->StatInvlpg, "/EM/CPU%d/R3/PrivInst/Invlpg", "Number of invlpg instructions.");
357 EM_REG_COUNTER_USED(&pStats->StatMisc, "/EM/CPU%d/R3/PrivInst/Misc", "Number of misc. instructions.");
358 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[0], "/EM/CPU%d/R3/PrivInst/Mov CR0, X", "Number of mov CR0 read instructions.");
359 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[1], "/EM/CPU%d/R3/PrivInst/Mov CR1, X", "Number of mov CR1 read instructions.");
360 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[2], "/EM/CPU%d/R3/PrivInst/Mov CR2, X", "Number of mov CR2 read instructions.");
361 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[3], "/EM/CPU%d/R3/PrivInst/Mov CR3, X", "Number of mov CR3 read instructions.");
362 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[4], "/EM/CPU%d/R3/PrivInst/Mov CR4, X", "Number of mov CR4 read instructions.");
363 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[0], "/EM/CPU%d/R3/PrivInst/Mov X, CR0", "Number of mov CR0 write instructions.");
364 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[1], "/EM/CPU%d/R3/PrivInst/Mov X, CR1", "Number of mov CR1 write instructions.");
365 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[2], "/EM/CPU%d/R3/PrivInst/Mov X, CR2", "Number of mov CR2 write instructions.");
366 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[3], "/EM/CPU%d/R3/PrivInst/Mov X, CR3", "Number of mov CR3 write instructions.");
367 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[4], "/EM/CPU%d/R3/PrivInst/Mov X, CR4", "Number of mov CR4 write instructions.");
368 EM_REG_COUNTER_USED(&pStats->StatMovDRx, "/EM/CPU%d/R3/PrivInst/MovDRx", "Number of mov DRx instructions.");
369 EM_REG_COUNTER_USED(&pStats->StatIret, "/EM/CPU%d/R3/PrivInst/Iret", "Number of iret instructions.");
370 EM_REG_COUNTER_USED(&pStats->StatMovLgdt, "/EM/CPU%d/R3/PrivInst/Lgdt", "Number of lgdt instructions.");
371 EM_REG_COUNTER_USED(&pStats->StatMovLidt, "/EM/CPU%d/R3/PrivInst/Lidt", "Number of lidt instructions.");
372 EM_REG_COUNTER_USED(&pStats->StatMovLldt, "/EM/CPU%d/R3/PrivInst/Lldt", "Number of lldt instructions.");
373 EM_REG_COUNTER_USED(&pStats->StatSysEnter, "/EM/CPU%d/R3/PrivInst/Sysenter", "Number of sysenter instructions.");
374 EM_REG_COUNTER_USED(&pStats->StatSysExit, "/EM/CPU%d/R3/PrivInst/Sysexit", "Number of sysexit instructions.");
375 EM_REG_COUNTER_USED(&pStats->StatSysCall, "/EM/CPU%d/R3/PrivInst/Syscall", "Number of syscall instructions.");
376 EM_REG_COUNTER_USED(&pStats->StatSysRet, "/EM/CPU%d/R3/PrivInst/Sysret", "Number of sysret instructions.");
377
378 EM_REG_COUNTER(&pVCpu->em.s.StatTotalClis, "/EM/CPU%d/Cli/Total", "Total number of cli instructions executed.");
379 pVCpu->em.s.pCliStatTree = 0;
380
381 /* these should be considered for release statistics. */
382 EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction.");
383 EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged.");
384 EM_REG_COUNTER(&pVCpu->em.s.StatMiscEmu, "/PROF/CPU%d/EM/Emulation/Misc", "Profiling of emR3RawExecuteInstruction.");
385 EM_REG_PROFILE(&pVCpu->em.s.StatHwAccEntry, "/PROF/CPU%d/EM/HwAccEnter", "Profiling Hardware Accelerated Mode entry overhead.");
386 EM_REG_PROFILE(&pVCpu->em.s.StatHwAccExec, "/PROF/CPU%d/EM/HwAccExec", "Profiling Hardware Accelerated Mode execution.");
387 EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution.");
388 EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%d/EM/REMExec", "Profiling REM execution.");
389 EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing.");
390 EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead.");
391 EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution.");
392 EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead.");
393
394#endif /* VBOX_WITH_STATISTICS */
395
396 EM_REG_COUNTER(&pVCpu->em.s.StatForcedActions, "/PROF/CPU%d/EM/ForcedActions", "Profiling forced action execution.");
397 EM_REG_COUNTER(&pVCpu->em.s.StatHalted, "/PROF/CPU%d/EM/Halted", "Profiling halted state (VMR3WaitHalted).");
398 EM_REG_COUNTER(&pVCpu->em.s.StatREMTotal, "/PROF/CPU%d/EM/REMTotal", "Profiling emR3RemExecute (excluding FFs).");
399 EM_REG_COUNTER(&pVCpu->em.s.StatRAWTotal, "/PROF/CPU%d/EM/RAWTotal", "Profiling emR3RawExecute (excluding FFs).");
400
401 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatTotal, "/PROF/CPU%d/EM/Total", "Profiling EMR3ExecuteVM.");
402 }
403
404 return VINF_SUCCESS;
405}
406
407
408/**
409 * Initializes the per-VCPU EM.
410 *
411 * @returns VBox status code.
412 * @param pVM The VM to operate on.
413 */
414VMMR3DECL(int) EMR3InitCPU(PVM pVM)
415{
416 LogFlow(("EMR3InitCPU\n"));
417 return VINF_SUCCESS;
418}
419
420
421/**
422 * Applies relocations to data and code managed by this
423 * component. This function will be called at init and
424 * whenever the VMM need to relocate it self inside the GC.
425 *
426 * @param pVM The VM.
427 */
428VMMR3DECL(void) EMR3Relocate(PVM pVM)
429{
430 LogFlow(("EMR3Relocate\n"));
431 for (VMCPUID i = 0; i < pVM->cCpus; i++)
432 {
433 PVMCPU pVCpu = &pVM->aCpus[i];
434 if (pVCpu->em.s.pStatsR3)
435 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVCpu->em.s.pStatsR3);
436 }
437}
438
439
440/**
441 * Reset the EM state for a CPU.
442 *
443 * Called by EMR3Reset and hot plugging.
444 *
445 * @param pVCpu The virtual CPU.
446 */
447VMMR3DECL(void) EMR3ResetCpu(PVMCPU pVCpu)
448{
449 pVCpu->em.s.fForceRAW = false;
450
451 /* VMR3Reset may return VINF_EM_RESET or VINF_EM_SUSPEND, so transition
452 out of the HALTED state here so that enmPrevState doesn't end up as
453 HALTED when EMR3Execute returns. */
454 if (pVCpu->em.s.enmState == EMSTATE_HALTED)
455 {
456 Log(("EMR3ResetCpu: Cpu#%u %s -> %s\n", pVCpu->idCpu, emR3GetStateName(pVCpu->em.s.enmState), pVCpu->idCpu == 0 ? "EMSTATE_NONE" : "EMSTATE_WAIT_SIPI"));
457 pVCpu->em.s.enmState = pVCpu->idCpu == 0 ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
458 }
459}
460
461
462/**
463 * Reset notification.
464 *
465 * @param pVM The VM handle.
466 */
467VMMR3DECL(void) EMR3Reset(PVM pVM)
468{
469 Log(("EMR3Reset: \n"));
470 for (VMCPUID i = 0; i < pVM->cCpus; i++)
471 EMR3ResetCpu(&pVM->aCpus[i]);
472}
473
474
475/**
476 * Terminates the EM.
477 *
478 * Termination means cleaning up and freeing all resources,
479 * the VM it self is at this point powered off or suspended.
480 *
481 * @returns VBox status code.
482 * @param pVM The VM to operate on.
483 */
484VMMR3DECL(int) EMR3Term(PVM pVM)
485{
486 AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
487
488 PDMR3CritSectDelete(&pVM->em.s.CritSectREM);
489 return VINF_SUCCESS;
490}
491
492/**
493 * Terminates the per-VCPU EM.
494 *
495 * Termination means cleaning up and freeing all resources,
496 * the VM it self is at this point powered off or suspended.
497 *
498 * @returns VBox status code.
499 * @param pVM The VM to operate on.
500 */
501VMMR3DECL(int) EMR3TermCPU(PVM pVM)
502{
503 return 0;
504}
505
506/**
507 * Execute state save operation.
508 *
509 * @returns VBox status code.
510 * @param pVM VM Handle.
511 * @param pSSM SSM operation handle.
512 */
513static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
514{
515 for (VMCPUID i = 0; i < pVM->cCpus; i++)
516 {
517 PVMCPU pVCpu = &pVM->aCpus[i];
518
519 int rc = SSMR3PutBool(pSSM, pVCpu->em.s.fForceRAW);
520 AssertRCReturn(rc, rc);
521
522 Assert(pVCpu->em.s.enmState == EMSTATE_SUSPENDED);
523 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
524 rc = SSMR3PutU32(pSSM, pVCpu->em.s.enmPrevState);
525 AssertRCReturn(rc, rc);
526 }
527 return VINF_SUCCESS;
528}
529
530
531/**
532 * Execute state load operation.
533 *
534 * @returns VBox status code.
535 * @param pVM VM Handle.
536 * @param pSSM SSM operation handle.
537 * @param uVersion Data layout version.
538 * @param uPass The data pass.
539 */
540static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
541{
542 /*
543 * Validate version.
544 */
545 if ( uVersion != EM_SAVED_STATE_VERSION
546 && uVersion != EM_SAVED_STATE_VERSION_PRE_SMP)
547 {
548 AssertMsgFailed(("emR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, EM_SAVED_STATE_VERSION));
549 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
550 }
551 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
552
553 /*
554 * Load the saved state.
555 */
556 for (VMCPUID i = 0; i < pVM->cCpus; i++)
557 {
558 PVMCPU pVCpu = &pVM->aCpus[i];
559
560 int rc = SSMR3GetBool(pSSM, &pVCpu->em.s.fForceRAW);
561 if (RT_FAILURE(rc))
562 pVCpu->em.s.fForceRAW = false;
563 AssertRCReturn(rc, rc);
564
565 if (uVersion > EM_SAVED_STATE_VERSION_PRE_SMP)
566 {
567 AssertCompile(sizeof(pVCpu->em.s.enmPrevState) == sizeof(uint32_t));
568 rc = SSMR3GetU32(pSSM, (uint32_t *)&pVCpu->em.s.enmPrevState);
569 AssertRCReturn(rc, rc);
570 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
571
572 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
573 }
574 Assert(!pVCpu->em.s.pCliStatTree);
575 }
576 return VINF_SUCCESS;
577}
578
579
580/**
581 * Raise a fatal error.
582 *
583 * Safely terminate the VM with full state report and stuff. This function
584 * will naturally never return.
585 *
586 * @param pVCpu VMCPU handle.
587 * @param rc VBox status code.
588 */
589VMMR3DECL(void) EMR3FatalError(PVMCPU pVCpu, int rc)
590{
591 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
592 longjmp(pVCpu->em.s.u.FatalLongJump, rc);
593 AssertReleaseMsgFailed(("longjmp returned!\n"));
594}
595
596
597/**
598 * Gets the EM state name.
599 *
600 * @returns pointer to read only state name,
601 * @param enmState The state.
602 */
603static const char *emR3GetStateName(EMSTATE enmState)
604{
605 switch (enmState)
606 {
607 case EMSTATE_NONE: return "EMSTATE_NONE";
608 case EMSTATE_RAW: return "EMSTATE_RAW";
609 case EMSTATE_HWACC: return "EMSTATE_HWACC";
610 case EMSTATE_REM: return "EMSTATE_REM";
611 case EMSTATE_PARAV: return "EMSTATE_PARAV";
612 case EMSTATE_HALTED: return "EMSTATE_HALTED";
613 case EMSTATE_WAIT_SIPI: return "EMSTATE_WAIT_SIPI";
614 case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
615 case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
616 case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
617 case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
618 case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
619 case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
620 default: return "Unknown!";
621 }
622}
623
624
625#ifdef VBOX_WITH_STATISTICS
626/**
627 * Just a braindead function to keep track of cli addresses.
628 * @param pVM VM handle.
629 * @param pVMCPU VMCPU handle.
630 * @param GCPtrInstr The EIP of the cli instruction.
631 */
632static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
633{
634 PCLISTAT pRec;
635
636 pRec = (PCLISTAT)RTAvlPVGet(&pVCpu->em.s.pCliStatTree, (AVLPVKEY)GCPtrInstr);
637 if (!pRec)
638 {
639 /* New cli instruction; insert into the tree. */
640 pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
641 Assert(pRec);
642 if (!pRec)
643 return;
644 pRec->Core.Key = (AVLPVKEY)GCPtrInstr;
645
646 char szCliStatName[32];
647 RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
648 STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
649
650 bool fRc = RTAvlPVInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
651 Assert(fRc); NOREF(fRc);
652 }
653 STAM_COUNTER_INC(&pRec->Counter);
654 STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
655}
656#endif /* VBOX_WITH_STATISTICS */
657
658
659/**
660 * Debug loop.
661 *
662 * @returns VBox status code for EM.
663 * @param pVM VM handle.
664 * @param pVCpu VMCPU handle.
665 * @param rc Current EM VBox status code..
666 */
667static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc)
668{
669 for (;;)
670 {
671 Log(("emR3Debug: rc=%Rrc\n", rc));
672 const int rcLast = rc;
673
674 /*
675 * Debug related RC.
676 */
677 switch (rc)
678 {
679 /*
680 * Single step an instruction.
681 */
682 case VINF_EM_DBG_STEP:
683 if ( pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
684 || pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
685 || pVCpu->em.s.fForceRAW /* paranoia */)
686 rc = emR3RawStep(pVM, pVCpu);
687 else
688 {
689 Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
690 rc = emR3RemStep(pVM, pVCpu);
691 }
692 break;
693
694 /*
695 * Simple events: stepped, breakpoint, stop/assertion.
696 */
697 case VINF_EM_DBG_STEPPED:
698 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
699 break;
700
701 case VINF_EM_DBG_BREAKPOINT:
702 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
703 break;
704
705 case VINF_EM_DBG_STOP:
706 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
707 break;
708
709 case VINF_EM_DBG_HYPER_STEPPED:
710 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
711 break;
712
713 case VINF_EM_DBG_HYPER_BREAKPOINT:
714 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
715 break;
716
717 case VINF_EM_DBG_HYPER_ASSERTION:
718 RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
719 rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
720 break;
721
722 /*
723 * Guru meditation.
724 */
725 case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
726 rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
727 break;
728 case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
729 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
730 break;
731
732 default: /** @todo don't use default for guru, but make special errors code! */
733 rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
734 break;
735 }
736
737 /*
738 * Process the result.
739 */
740 do
741 {
742 switch (rc)
743 {
744 /*
745 * Continue the debugging loop.
746 */
747 case VINF_EM_DBG_STEP:
748 case VINF_EM_DBG_STOP:
749 case VINF_EM_DBG_STEPPED:
750 case VINF_EM_DBG_BREAKPOINT:
751 case VINF_EM_DBG_HYPER_STEPPED:
752 case VINF_EM_DBG_HYPER_BREAKPOINT:
753 case VINF_EM_DBG_HYPER_ASSERTION:
754 break;
755
756 /*
757 * Resuming execution (in some form) has to be done here if we got
758 * a hypervisor debug event.
759 */
760 case VINF_SUCCESS:
761 case VINF_EM_RESUME:
762 case VINF_EM_SUSPEND:
763 case VINF_EM_RESCHEDULE:
764 case VINF_EM_RESCHEDULE_RAW:
765 case VINF_EM_RESCHEDULE_REM:
766 case VINF_EM_HALT:
767 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
768 {
769 rc = emR3RawResumeHyper(pVM, pVCpu);
770 if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
771 continue;
772 }
773 if (rc == VINF_SUCCESS)
774 rc = VINF_EM_RESCHEDULE;
775 return rc;
776
777 /*
778 * The debugger isn't attached.
779 * We'll simply turn the thing off since that's the easiest thing to do.
780 */
781 case VERR_DBGF_NOT_ATTACHED:
782 switch (rcLast)
783 {
784 case VINF_EM_DBG_HYPER_STEPPED:
785 case VINF_EM_DBG_HYPER_BREAKPOINT:
786 case VINF_EM_DBG_HYPER_ASSERTION:
787 case VERR_TRPM_PANIC:
788 case VERR_TRPM_DONT_PANIC:
789 case VERR_VMM_RING0_ASSERTION:
790 case VERR_VMM_HYPER_CR3_MISMATCH:
791 case VERR_VMM_RING3_CALL_DISABLED:
792 return rcLast;
793 }
794 return VINF_EM_OFF;
795
796 /*
797 * Status codes terminating the VM in one or another sense.
798 */
799 case VINF_EM_TERMINATE:
800 case VINF_EM_OFF:
801 case VINF_EM_RESET:
802 case VINF_EM_NO_MEMORY:
803 case VINF_EM_RAW_STALE_SELECTOR:
804 case VINF_EM_RAW_IRET_TRAP:
805 case VERR_TRPM_PANIC:
806 case VERR_TRPM_DONT_PANIC:
807 case VERR_VMM_RING0_ASSERTION:
808 case VERR_VMM_HYPER_CR3_MISMATCH:
809 case VERR_VMM_RING3_CALL_DISABLED:
810 case VERR_INTERNAL_ERROR:
811 case VERR_INTERNAL_ERROR_2:
812 case VERR_INTERNAL_ERROR_3:
813 case VERR_INTERNAL_ERROR_4:
814 case VERR_INTERNAL_ERROR_5:
815 case VERR_IPE_UNEXPECTED_STATUS:
816 case VERR_IPE_UNEXPECTED_INFO_STATUS:
817 case VERR_IPE_UNEXPECTED_ERROR_STATUS:
818 return rc;
819
820 /*
821 * The rest is unexpected, and will keep us here.
822 */
823 default:
824 AssertMsgFailed(("Unxpected rc %Rrc!\n", rc));
825 break;
826 }
827 } while (false);
828 } /* debug for ever */
829}
830
831/**
832 * Steps recompiled code.
833 *
834 * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
835 * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
836 *
837 * @param pVM VM handle.
838 * @param pVCpu VMCPU handle.
839 */
840static int emR3RemStep(PVM pVM, PVMCPU pVCpu)
841{
842 LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
843
844 EMRemLock(pVM);
845
846 /*
847 * Switch to REM, step instruction, switch back.
848 */
849 int rc = REMR3State(pVM, pVCpu);
850 if (RT_SUCCESS(rc))
851 {
852 rc = REMR3Step(pVM, pVCpu);
853 REMR3StateBack(pVM, pVCpu);
854 }
855 EMRemUnlock(pVM);
856
857 LogFlow(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
858 return rc;
859}
860
861
862/**
863 * Executes recompiled code.
864 *
865 * This function contains the recompiler version of the inner
866 * execution loop (the outer loop being in EMR3ExecuteVM()).
867 *
868 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
869 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
870 *
871 * @param pVM VM handle.
872 * @param pVCpu VMCPU handle.
873 * @param pfFFDone Where to store an indicator telling wheter or not
874 * FFs were done before returning.
875 *
876 */
877static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
878{
879#ifdef LOG_ENABLED
880 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
881 uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
882
883 if (pCtx->eflags.Bits.u1VM)
884 Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
885 else
886 Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0));
887#endif
888 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatREMTotal, a);
889
890#if defined(VBOX_STRICT) && defined(DEBUG_bird)
891 AssertMsg( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
892 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVCpu)), /** @todo #1419 - get flat address. */
893 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
894#endif
895
896 /* Big lock, but you are not supposed to own any lock when coming in here. */
897 EMRemLock(pVM);
898
899 /*
900 * Spin till we get a forced action which returns anything but VINF_SUCCESS
901 * or the REM suggests raw-mode execution.
902 */
903 *pfFFDone = false;
904 bool fInREMState = false;
905 int rc = VINF_SUCCESS;
906
907 /* Flush the recompiler TLB if the VCPU has changed. */
908 if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
909 {
910 REMFlushTBs(pVM);
911 /* Also sync the entire state. */
912 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
913 }
914 pVM->em.s.idLastRemCpu = pVCpu->idCpu;
915
916 for (;;)
917 {
918 /*
919 * Update REM state if not already in sync.
920 */
921 if (!fInREMState)
922 {
923 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, b);
924 rc = REMR3State(pVM, pVCpu);
925 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, b);
926 if (RT_FAILURE(rc))
927 break;
928 fInREMState = true;
929
930 /*
931 * We might have missed the raising of VMREQ, TIMER and some other
932 * imporant FFs while we were busy switching the state. So, check again.
933 */
934 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_TERMINATE | VM_FF_RESET)
935 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER | VMCPU_FF_REQUEST))
936 {
937 LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fGlobalForcedActions));
938 goto l_REMDoForcedActions;
939 }
940 }
941
942
943 /*
944 * Execute REM.
945 */
946 STAM_PROFILE_START(&pVCpu->em.s.StatREMExec, c);
947 rc = REMR3Run(pVM, pVCpu);
948 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMExec, c);
949
950
951 /*
952 * Deal with high priority post execution FFs before doing anything else.
953 */
954 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
955 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
956 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
957
958 /*
959 * Process the returned status code.
960 * (Try keep this short! Call functions!)
961 */
962 if (rc != VINF_SUCCESS)
963 {
964 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
965 break;
966 if (rc != VINF_REM_INTERRUPED_FF)
967 {
968 /*
969 * Anything which is not known to us means an internal error
970 * and the termination of the VM!
971 */
972 AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
973 break;
974 }
975 }
976
977
978 /*
979 * Check and execute forced actions.
980 * Sync back the VM state before calling any of these.
981 */
982#ifdef VBOX_HIGH_RES_TIMERS_HACK
983 TMTimerPollVoid(pVM, pVCpu);
984#endif
985 AssertCompile((VMCPU_FF_ALL_BUT_RAW_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE)) & VMCPU_FF_TIMER);
986 if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK)
987 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_BUT_RAW_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE)))
988 {
989l_REMDoForcedActions:
990 if (fInREMState)
991 {
992 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, d);
993 REMR3StateBack(pVM, pVCpu);
994 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, d);
995 fInREMState = false;
996 }
997 STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatREMTotal, a);
998 rc = emR3ForcedActions(pVM, pVCpu, rc);
999 STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatREMTotal, a);
1000 if ( rc != VINF_SUCCESS
1001 && rc != VINF_EM_RESCHEDULE_REM)
1002 {
1003 *pfFFDone = true;
1004 break;
1005 }
1006 }
1007
1008 } /* The Inner Loop, recompiled execution mode version. */
1009
1010
1011 /*
1012 * Returning. Sync back the VM state if required.
1013 */
1014 if (fInREMState)
1015 {
1016 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, e);
1017 REMR3StateBack(pVM, pVCpu);
1018 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, e);
1019 }
1020 EMRemUnlock(pVM);
1021
1022 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatREMTotal, a);
1023 return rc;
1024}
1025
1026
1027#ifdef DEBUG
1028
1029int emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1030{
1031 EMSTATE enmOldState = pVCpu->em.s.enmState;
1032
1033 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1034
1035 Log(("Single step BEGIN:\n"));
1036 for (uint32_t i = 0; i < cIterations; i++)
1037 {
1038 DBGFR3PrgStep(pVCpu);
1039 DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
1040 emR3RemStep(pVM, pVCpu);
1041 if (emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx) != EMSTATE_REM)
1042 break;
1043 }
1044 Log(("Single step END:\n"));
1045 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1046 pVCpu->em.s.enmState = enmOldState;
1047 return VINF_EM_RESCHEDULE;
1048}
1049
1050#endif /* DEBUG */
1051
1052
1053/**
1054 * Decides whether to execute RAW, HWACC or REM.
1055 *
1056 * @returns new EM state
1057 * @param pVM The VM.
1058 * @param pVCpu The VMCPU handle.
1059 * @param pCtx The CPU context.
1060 */
1061EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1062{
1063 /*
1064 * When forcing raw-mode execution, things are simple.
1065 */
1066 if (pVCpu->em.s.fForceRAW)
1067 return EMSTATE_RAW;
1068
1069 /*
1070 * We stay in the wait for SIPI state unless explicitly told otherwise.
1071 */
1072 if (pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI)
1073 return EMSTATE_WAIT_SIPI;
1074
1075 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1076 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1077 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1078
1079 X86EFLAGS EFlags = pCtx->eflags;
1080 if (HWACCMIsEnabled(pVM))
1081 {
1082 /* Hardware accelerated raw-mode:
1083 *
1084 * Typically only 32-bits protected mode, with paging enabled, code is allowed here.
1085 */
1086 if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
1087 return EMSTATE_HWACC;
1088
1089 /* Note: Raw mode and hw accelerated mode are incompatible. The latter turns
1090 * off monitoring features essential for raw mode! */
1091 return EMSTATE_REM;
1092 }
1093
1094 /*
1095 * Standard raw-mode:
1096 *
1097 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1098 * or 32 bits protected mode ring 0 code
1099 *
1100 * The tests are ordered by the likelyhood of being true during normal execution.
1101 */
1102 if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
1103 {
1104 Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
1105 return EMSTATE_REM;
1106 }
1107
1108#ifndef VBOX_RAW_V86
1109 if (EFlags.u32 & X86_EFL_VM) {
1110 Log2(("raw mode refused: VM_MASK\n"));
1111 return EMSTATE_REM;
1112 }
1113#endif
1114
1115 /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
1116 uint32_t u32CR0 = pCtx->cr0;
1117 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
1118 {
1119 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1120 return EMSTATE_REM;
1121 }
1122
1123 if (pCtx->cr4 & X86_CR4_PAE)
1124 {
1125 uint32_t u32Dummy, u32Features;
1126
1127 CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1128 if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
1129 return EMSTATE_REM;
1130 }
1131
1132 unsigned uSS = pCtx->ss;
1133 if ( pCtx->eflags.Bits.u1VM
1134 || (uSS & X86_SEL_RPL) == 3)
1135 {
1136 if (!EMIsRawRing3Enabled(pVM))
1137 return EMSTATE_REM;
1138
1139 if (!(EFlags.u32 & X86_EFL_IF))
1140 {
1141 Log2(("raw mode refused: IF (RawR3)\n"));
1142 return EMSTATE_REM;
1143 }
1144
1145 if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
1146 {
1147 Log2(("raw mode refused: CR0.WP + RawR0\n"));
1148 return EMSTATE_REM;
1149 }
1150 }
1151 else
1152 {
1153 if (!EMIsRawRing0Enabled(pVM))
1154 return EMSTATE_REM;
1155
1156 /* Only ring 0 supervisor code. */
1157 if ((uSS & X86_SEL_RPL) != 0)
1158 {
1159 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
1160 return EMSTATE_REM;
1161 }
1162
1163 // Let's start with pure 32 bits ring 0 code first
1164 /** @todo What's pure 32-bit mode? flat? */
1165 if ( !(pCtx->ssHid.Attr.n.u1DefBig)
1166 || !(pCtx->csHid.Attr.n.u1DefBig))
1167 {
1168 Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
1169 return EMSTATE_REM;
1170 }
1171
1172 /* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
1173 if (!(u32CR0 & X86_CR0_WP))
1174 {
1175 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1176 return EMSTATE_REM;
1177 }
1178
1179 if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
1180 {
1181 Log2(("raw r0 mode forced: patch code\n"));
1182 return EMSTATE_RAW;
1183 }
1184
1185#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1186 if (!(EFlags.u32 & X86_EFL_IF))
1187 {
1188 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
1189 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1190 return EMSTATE_REM;
1191 }
1192#endif
1193
1194 /** @todo still necessary??? */
1195 if (EFlags.Bits.u2IOPL != 0)
1196 {
1197 Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
1198 return EMSTATE_REM;
1199 }
1200 }
1201
1202 Assert(PGMPhysIsA20Enabled(pVCpu));
1203 return EMSTATE_RAW;
1204}
1205
1206
1207/**
1208 * Executes all high priority post execution force actions.
1209 *
1210 * @returns rc or a fatal status code.
1211 *
1212 * @param pVM VM handle.
1213 * @param pVCpu VMCPU handle.
1214 * @param rc The current rc.
1215 */
1216int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1217{
1218 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PDM_CRITSECT))
1219 PDMCritSectFF(pVCpu);
1220
1221 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION))
1222 CSAMR3DoPendingAction(pVM, pVCpu);
1223
1224 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1225 {
1226 if ( rc > VINF_EM_NO_MEMORY
1227 && rc <= VINF_EM_LAST)
1228 rc = VINF_EM_NO_MEMORY;
1229 }
1230
1231 return rc;
1232}
1233
1234
1235/**
1236 * Executes all pending forced actions.
1237 *
1238 * Forced actions can cause execution delays and execution
1239 * rescheduling. The first we deal with using action priority, so
1240 * that for instance pending timers aren't scheduled and ran until
1241 * right before execution. The rescheduling we deal with using
1242 * return codes. The same goes for VM termination, only in that case
1243 * we exit everything.
1244 *
1245 * @returns VBox status code of equal or greater importance/severity than rc.
1246 * The most important ones are: VINF_EM_RESCHEDULE,
1247 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1248 *
1249 * @param pVM VM handle.
1250 * @param pVCpu VMCPU handle.
1251 * @param rc The current rc.
1252 *
1253 */
1254int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1255{
1256 STAM_REL_PROFILE_START(&pVCpu->em.s.StatForcedActions, a);
1257#ifdef VBOX_STRICT
1258 int rcIrq = VINF_SUCCESS;
1259#endif
1260 int rc2;
1261#define UPDATE_RC() \
1262 do { \
1263 AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
1264 if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
1265 break; \
1266 if (!rc || rc2 < rc) \
1267 rc = rc2; \
1268 } while (0)
1269
1270 /*
1271 * Post execution chunk first.
1272 */
1273 if ( VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK)
1274 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK))
1275 {
1276 /*
1277 * EMT Rendezvous (must be serviced before termination).
1278 */
1279 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1280 {
1281 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1282 UPDATE_RC();
1283 /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
1284 * stopped/reset before the next VM state change is made. We need a better
1285 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1286 * && rc >= VINF_EM_SUSPEND). */
1287 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1288 {
1289 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1290 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1291 return rc;
1292 }
1293 }
1294
1295 /*
1296 * Termination request.
1297 */
1298 if (VM_FF_ISPENDING(pVM, VM_FF_TERMINATE))
1299 {
1300 Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
1301 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1302 return VINF_EM_TERMINATE;
1303 }
1304
1305 /*
1306 * Debugger Facility polling.
1307 */
1308 if (VM_FF_ISPENDING(pVM, VM_FF_DBGF))
1309 {
1310 rc2 = DBGFR3VMMForcedAction(pVM);
1311 UPDATE_RC();
1312 }
1313
1314 /*
1315 * Postponed reset request.
1316 */
1317 if (VM_FF_TESTANDCLEAR(pVM, VM_FF_RESET))
1318 {
1319 rc2 = VMR3Reset(pVM);
1320 UPDATE_RC();
1321 }
1322
1323 /*
1324 * CSAM page scanning.
1325 */
1326 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1327 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE))
1328 {
1329 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1330
1331 /** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
1332 Log(("Forced action VMCPU_FF_CSAM_SCAN_PAGE\n"));
1333
1334 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1335 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE);
1336 }
1337
1338 /*
1339 * Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
1340 */
1341 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1342 {
1343 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1344 UPDATE_RC();
1345 if (rc == VINF_EM_NO_MEMORY)
1346 return rc;
1347 }
1348
1349 /* check that we got them all */
1350 AssertCompile(VM_FF_NORMAL_PRIORITY_POST_MASK == (VM_FF_TERMINATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1351 AssertCompile(VMCPU_FF_NORMAL_PRIORITY_POST_MASK == VMCPU_FF_CSAM_SCAN_PAGE);
1352 }
1353
1354 /*
1355 * Normal priority then.
1356 * (Executed in no particular order.)
1357 */
1358 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
1359 {
1360 /*
1361 * PDM Queues are pending.
1362 */
1363 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
1364 PDMR3QueueFlushAll(pVM);
1365
1366 /*
1367 * PDM DMA transfers are pending.
1368 */
1369 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
1370 PDMR3DmaRun(pVM);
1371
1372 /*
1373 * EMT Rendezvous (make sure they are handled before the requests).
1374 */
1375 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1376 {
1377 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1378 UPDATE_RC();
1379 /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
1380 * stopped/reset before the next VM state change is made. We need a better
1381 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1382 * && rc >= VINF_EM_SUSPEND). */
1383 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1384 {
1385 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1386 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1387 return rc;
1388 }
1389 }
1390
1391 /*
1392 * Requests from other threads.
1393 */
1394 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
1395 {
1396 rc2 = VMR3ReqProcessU(pVM->pUVM, VMCPUID_ANY);
1397 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE) /** @todo this shouldn't be necessary */
1398 {
1399 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1400 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1401 return rc2;
1402 }
1403 UPDATE_RC();
1404 /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
1405 * stopped/reset before the next VM state change is made. We need a better
1406 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1407 * && rc >= VINF_EM_SUSPEND). */
1408 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1409 {
1410 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1411 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1412 return rc;
1413 }
1414 }
1415
1416 /* Replay the handler notification changes. */
1417 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REM_HANDLER_NOTIFY, VM_FF_PGM_NO_MEMORY))
1418 {
1419 /* Try not to cause deadlocks. */
1420 if ( pVM->cCpus == 1
1421 || ( !PGMIsLockOwner(pVM)
1422 && !IOMIsLockOwner(pVM))
1423 )
1424 {
1425 EMRemLock(pVM);
1426 REMR3ReplayHandlerNotifications(pVM);
1427 EMRemUnlock(pVM);
1428 }
1429 }
1430
1431 /* check that we got them all */
1432 AssertCompile(VM_FF_NORMAL_PRIORITY_MASK == (VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_REM_HANDLER_NOTIFY | VM_FF_EMT_RENDEZVOUS));
1433 }
1434
1435 /*
1436 * Normal priority then. (per-VCPU)
1437 * (Executed in no particular order.)
1438 */
1439 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1440 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK))
1441 {
1442 /*
1443 * Requests from other threads.
1444 */
1445 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1446 {
1447 rc2 = VMR3ReqProcessU(pVM->pUVM, pVCpu->idCpu);
1448 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE || rc2 == VINF_EM_RESET)
1449 {
1450 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1451 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1452 return rc2;
1453 }
1454 UPDATE_RC();
1455 /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
1456 * stopped/reset before the next VM state change is made. We need a better
1457 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1458 * && rc >= VINF_EM_SUSPEND). */
1459 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1460 {
1461 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1462 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1463 return rc;
1464 }
1465 }
1466
1467 /* check that we got them all */
1468 Assert(!(VMCPU_FF_NORMAL_PRIORITY_MASK & ~(VMCPU_FF_REQUEST)));
1469 }
1470
1471 /*
1472 * High priority pre execution chunk last.
1473 * (Executed in ascending priority order.)
1474 */
1475 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK)
1476 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK))
1477 {
1478 /*
1479 * Timers before interrupts.
1480 */
1481 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER)
1482 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1483 TMR3TimerQueuesDo(pVM);
1484
1485 /*
1486 * The instruction following an emulated STI should *always* be executed!
1487 */
1488 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1489 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1490 {
1491 Log(("VM_FF_EMULATED_STI at %RGv successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu), EMGetInhibitInterruptsPC(pVCpu)));
1492 if (CPUMGetGuestEIP(pVCpu) != EMGetInhibitInterruptsPC(pVCpu))
1493 {
1494 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
1495 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1496 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1497 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1498 */
1499 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1500 }
1501 if (HWACCMR3IsActive(pVCpu))
1502 rc2 = VINF_EM_RESCHEDULE_HWACC;
1503 else
1504 rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
1505
1506 UPDATE_RC();
1507 }
1508
1509 /*
1510 * Interrupts.
1511 */
1512 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1513 && !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1514 && (!rc || rc >= VINF_EM_RESCHEDULE_HWACC)
1515 && !TRPMHasTrap(pVCpu) /* an interrupt could already be scheduled for dispatching in the recompiler. */
1516 && PATMAreInterruptsEnabled(pVM)
1517 && !HWACCMR3IsEventPending(pVCpu))
1518 {
1519 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1520 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
1521 {
1522 /* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
1523 /** @todo this really isn't nice, should properly handle this */
1524 rc2 = TRPMR3InjectEvent(pVM, pVCpu, TRPM_HARDWARE_INT);
1525#ifdef VBOX_STRICT
1526 rcIrq = rc2;
1527#endif
1528 UPDATE_RC();
1529 }
1530 /** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
1531 else if (REMR3QueryPendingInterrupt(pVM, pVCpu) != REM_NO_PENDING_IRQ)
1532 {
1533 rc2 = VINF_EM_RESCHEDULE_REM;
1534 UPDATE_RC();
1535 }
1536 }
1537
1538 /*
1539 * Allocate handy pages.
1540 */
1541 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1542 {
1543 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1544 UPDATE_RC();
1545 }
1546
1547 /*
1548 * Debugger Facility request.
1549 */
1550 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_DBGF, VM_FF_PGM_NO_MEMORY))
1551 {
1552 rc2 = DBGFR3VMMForcedAction(pVM);
1553 UPDATE_RC();
1554 }
1555
1556 /*
1557 * EMT Rendezvous (must be serviced before termination).
1558 */
1559 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1560 {
1561 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1562 UPDATE_RC();
1563 /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
1564 * stopped/reset before the next VM state change is made. We need a better
1565 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1566 * && rc >= VINF_EM_SUSPEND). */
1567 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1568 {
1569 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1570 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1571 return rc;
1572 }
1573 }
1574
1575 /*
1576 * Termination request.
1577 */
1578 if (VM_FF_ISPENDING(pVM, VM_FF_TERMINATE))
1579 {
1580 Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
1581 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1582 return VINF_EM_TERMINATE;
1583 }
1584
1585 /*
1586 * Out of memory? Since most of our fellow high priority actions may cause us
1587 * to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
1588 * at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
1589 * than us since we can terminate without allocating more memory.
1590 */
1591 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1592 {
1593 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1594 UPDATE_RC();
1595 if (rc == VINF_EM_NO_MEMORY)
1596 return rc;
1597 }
1598
1599 /*
1600 * If the virtual sync clock is still stopped, make TM restart it.
1601 */
1602 if (VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
1603 TMR3VirtualSyncFF(pVM, pVCpu);
1604
1605#ifdef DEBUG
1606 /*
1607 * Debug, pause the VM.
1608 */
1609 if (VM_FF_ISPENDING(pVM, VM_FF_DEBUG_SUSPEND))
1610 {
1611 VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
1612 Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
1613 return VINF_EM_SUSPEND;
1614 }
1615#endif
1616
1617 /* check that we got them all */
1618 AssertCompile(VM_FF_HIGH_PRIORITY_PRE_MASK == (VM_FF_TM_VIRTUAL_SYNC | VM_FF_DBGF | VM_FF_TERMINATE | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1619 AssertCompile(VMCPU_FF_HIGH_PRIORITY_PRE_MASK == (VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_INHIBIT_INTERRUPTS));
1620 }
1621
1622#undef UPDATE_RC
1623 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1624 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1625 Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
1626 return rc;
1627}
1628
1629/**
1630 * Release the IOM lock if owned by the current VCPU
1631 *
1632 * @param pVM The VM to operate on.
1633 */
1634VMMR3DECL(void) EMR3ReleaseOwnedLocks(PVM pVM)
1635{
1636 while (PDMCritSectIsOwner(&pVM->em.s.CritSectREM))
1637 PDMCritSectLeave(&pVM->em.s.CritSectREM);
1638}
1639
1640
1641/**
1642 * Execute VM.
1643 *
1644 * This function is the main loop of the VM. The emulation thread
1645 * calls this function when the VM has been successfully constructed
1646 * and we're ready for executing the VM.
1647 *
1648 * Returning from this function means that the VM is turned off or
1649 * suspended (state already saved) and deconstruction in next in line.
1650 *
1651 * All interaction from other thread are done using forced actions
1652 * and signaling of the wait object.
1653 *
1654 * @returns VBox status code, informational status codes may indicate failure.
1655 * @param pVM The VM to operate on.
1656 * @param pVCpu The VMCPU to operate on.
1657 */
1658VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
1659{
1660 Log(("EMR3ExecuteVM: pVM=%p enmVMState=%d (%s) enmState=%d (%s) enmPrevState=%d (%s) fForceRAW=%RTbool\n",
1661 pVM,
1662 pVM->enmVMState, VMR3GetStateName(pVM->enmVMState),
1663 pVCpu->em.s.enmState, emR3GetStateName(pVCpu->em.s.enmState),
1664 pVCpu->em.s.enmPrevState, emR3GetStateName(pVCpu->em.s.enmPrevState),
1665 pVCpu->em.s.fForceRAW));
1666 VM_ASSERT_EMT(pVM);
1667 AssertMsg( pVCpu->em.s.enmState == EMSTATE_NONE
1668 || pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI
1669 || pVCpu->em.s.enmState == EMSTATE_SUSPENDED,
1670 ("%s\n", emR3GetStateName(pVCpu->em.s.enmState)));
1671
1672 int rc = setjmp(pVCpu->em.s.u.FatalLongJump);
1673 if (rc == 0)
1674 {
1675 /*
1676 * Start the virtual time.
1677 */
1678 TMR3NotifyResume(pVM, pVCpu);
1679
1680 /*
1681 * The Outer Main Loop.
1682 */
1683 bool fFFDone = false;
1684
1685 /* Reschedule right away to start in the right state. */
1686 rc = VINF_SUCCESS;
1687
1688 /* If resuming after a pause or a state load, restore the previous
1689 state or else we'll start executing code. Else, just reschedule. */
1690 if ( pVCpu->em.s.enmState == EMSTATE_SUSPENDED
1691 && ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
1692 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED))
1693 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
1694 else
1695 pVCpu->em.s.enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1696
1697 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
1698 for (;;)
1699 {
1700 /*
1701 * Before we can schedule anything (we're here because
1702 * scheduling is required) we must service any pending
1703 * forced actions to avoid any pending action causing
1704 * immediate rescheduling upon entering an inner loop
1705 *
1706 * Do forced actions.
1707 */
1708 if ( !fFFDone
1709 && rc != VINF_EM_TERMINATE
1710 && rc != VINF_EM_OFF
1711 && ( VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK)
1712 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_BUT_RAW_MASK)))
1713 {
1714 rc = emR3ForcedActions(pVM, pVCpu, rc);
1715 if ( ( rc == VINF_EM_RESCHEDULE_REM
1716 || rc == VINF_EM_RESCHEDULE_HWACC)
1717 && pVCpu->em.s.fForceRAW)
1718 rc = VINF_EM_RESCHEDULE_RAW;
1719 }
1720 else if (fFFDone)
1721 fFFDone = false;
1722
1723 /*
1724 * Now what to do?
1725 */
1726 Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
1727 switch (rc)
1728 {
1729 /*
1730 * Keep doing what we're currently doing.
1731 */
1732 case VINF_SUCCESS:
1733 break;
1734
1735 /*
1736 * Reschedule - to raw-mode execution.
1737 */
1738 case VINF_EM_RESCHEDULE_RAW:
1739 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVCpu->em.s.enmState, EMSTATE_RAW));
1740 pVCpu->em.s.enmState = EMSTATE_RAW;
1741 break;
1742
1743 /*
1744 * Reschedule - to hardware accelerated raw-mode execution.
1745 */
1746 case VINF_EM_RESCHEDULE_HWACC:
1747 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVCpu->em.s.enmState, EMSTATE_HWACC));
1748 Assert(!pVCpu->em.s.fForceRAW);
1749 pVCpu->em.s.enmState = EMSTATE_HWACC;
1750 break;
1751
1752 /*
1753 * Reschedule - to recompiled execution.
1754 */
1755 case VINF_EM_RESCHEDULE_REM:
1756 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVCpu->em.s.enmState, EMSTATE_REM));
1757 pVCpu->em.s.enmState = EMSTATE_REM;
1758 break;
1759
1760#ifdef VBOX_WITH_VMI
1761 /*
1762 * Reschedule - parav call.
1763 */
1764 case VINF_EM_RESCHEDULE_PARAV:
1765 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_PARAV: %d -> %d (EMSTATE_PARAV)\n", pVCpu->em.s.enmState, EMSTATE_PARAV));
1766 pVCpu->em.s.enmState = EMSTATE_PARAV;
1767 break;
1768#endif
1769
1770 /*
1771 * Resume.
1772 */
1773 case VINF_EM_RESUME:
1774 Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVCpu->em.s.enmState));
1775 /* Don't reschedule in the halted or wait for SIPI case. */
1776 if ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
1777 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED)
1778 break;
1779 /* fall through and get scheduled. */
1780
1781 /*
1782 * Reschedule.
1783 */
1784 case VINF_EM_RESCHEDULE:
1785 {
1786 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1787 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, emR3GetStateName(enmState)));
1788 pVCpu->em.s.enmState = enmState;
1789 break;
1790 }
1791
1792 /*
1793 * Halted.
1794 */
1795 case VINF_EM_HALT:
1796 Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_HALTED));
1797 pVCpu->em.s.enmState = EMSTATE_HALTED;
1798 break;
1799
1800 /*
1801 * Switch to the wait for SIPI state (application processor only)
1802 */
1803 case VINF_EM_WAIT_SIPI:
1804 Assert(pVCpu->idCpu != 0);
1805 Log2(("EMR3ExecuteVM: VINF_EM_WAIT_SIPI: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_WAIT_SIPI));
1806 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
1807 break;
1808
1809
1810 /*
1811 * Suspend.
1812 */
1813 case VINF_EM_SUSPEND:
1814 Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
1815 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
1816 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
1817 break;
1818
1819 /*
1820 * Reset.
1821 * We might end up doing a double reset for now, we'll have to clean up the mess later.
1822 */
1823 case VINF_EM_RESET:
1824 {
1825 if (pVCpu->idCpu == 0)
1826 {
1827 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1828 Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, emR3GetStateName(enmState)));
1829 pVCpu->em.s.enmState = enmState;
1830 }
1831 else
1832 {
1833 /* All other VCPUs go into the wait for SIPI state. */
1834 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
1835 }
1836 break;
1837 }
1838
1839 /*
1840 * Power Off.
1841 */
1842 case VINF_EM_OFF:
1843 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
1844 Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
1845 TMR3NotifySuspend(pVM, pVCpu);
1846 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1847 return rc;
1848
1849 /*
1850 * Terminate the VM.
1851 */
1852 case VINF_EM_TERMINATE:
1853 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
1854 Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
1855 if (pVM->enmVMState < VMSTATE_DESTROYING) /* ugly */
1856 TMR3NotifySuspend(pVM, pVCpu);
1857 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1858 return rc;
1859
1860
1861 /*
1862 * Out of memory, suspend the VM and stuff.
1863 */
1864 case VINF_EM_NO_MEMORY:
1865 Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
1866 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
1867 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
1868 TMR3NotifySuspend(pVM, pVCpu);
1869 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1870
1871 rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
1872 N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
1873 if (rc != VINF_EM_SUSPEND)
1874 {
1875 if (RT_SUCCESS_NP(rc))
1876 {
1877 AssertLogRelMsgFailed(("%Rrc\n", rc));
1878 rc = VERR_EM_INTERNAL_ERROR;
1879 }
1880 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
1881 }
1882 return rc;
1883
1884 /*
1885 * Guest debug events.
1886 */
1887 case VINF_EM_DBG_STEPPED:
1888 AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
1889 case VINF_EM_DBG_STOP:
1890 case VINF_EM_DBG_BREAKPOINT:
1891 case VINF_EM_DBG_STEP:
1892 if (pVCpu->em.s.enmState == EMSTATE_RAW)
1893 {
1894 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
1895 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1896 }
1897 else
1898 {
1899 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
1900 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1901 }
1902 break;
1903
1904 /*
1905 * Hypervisor debug events.
1906 */
1907 case VINF_EM_DBG_HYPER_STEPPED:
1908 case VINF_EM_DBG_HYPER_BREAKPOINT:
1909 case VINF_EM_DBG_HYPER_ASSERTION:
1910 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_HYPER));
1911 pVCpu->em.s.enmState = EMSTATE_DEBUG_HYPER;
1912 break;
1913
1914 /*
1915 * Guru mediations.
1916 */
1917 case VERR_VMM_RING0_ASSERTION:
1918 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVCpu->em.s.enmState, EMSTATE_GURU_MEDITATION));
1919 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
1920 break;
1921
1922 /*
1923 * Any error code showing up here other than the ones we
1924 * know and process above are considered to be FATAL.
1925 *
1926 * Unknown warnings and informational status codes are also
1927 * included in this.
1928 */
1929 default:
1930 if (RT_SUCCESS_NP(rc))
1931 {
1932 AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
1933 rc = VERR_EM_INTERNAL_ERROR;
1934 }
1935 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVCpu->em.s.enmState, EMSTATE_GURU_MEDITATION));
1936 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
1937 break;
1938 }
1939
1940 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x); /* (skip this in release) */
1941 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
1942
1943 /*
1944 * Act on the state.
1945 */
1946 switch (pVCpu->em.s.enmState)
1947 {
1948 /*
1949 * Execute raw.
1950 */
1951 case EMSTATE_RAW:
1952 rc = emR3RawExecute(pVM, pVCpu, &fFFDone);
1953 break;
1954
1955 /*
1956 * Execute hardware accelerated raw.
1957 */
1958 case EMSTATE_HWACC:
1959 rc = emR3HwAccExecute(pVM, pVCpu, &fFFDone);
1960 break;
1961
1962 /*
1963 * Execute recompiled.
1964 */
1965 case EMSTATE_REM:
1966 rc = emR3RemExecute(pVM, pVCpu, &fFFDone);
1967 Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
1968 break;
1969
1970#ifdef VBOX_WITH_VMI
1971 /*
1972 * Execute PARAV function.
1973 */
1974 case EMSTATE_PARAV:
1975 rc = PARAVCallFunction(pVM);
1976 pVCpu->em.s.enmState = EMSTATE_REM;
1977 break;
1978#endif
1979
1980 /*
1981 * Application processor execution halted until SIPI.
1982 */
1983 case EMSTATE_WAIT_SIPI:
1984 /* no break */
1985 /*
1986 * hlt - execution halted until interrupt.
1987 */
1988 case EMSTATE_HALTED:
1989 {
1990 STAM_REL_PROFILE_START(&pVCpu->em.s.StatHalted, y);
1991 rc = VMR3WaitHalted(pVM, pVCpu, !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
1992 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHalted, y);
1993 break;
1994 }
1995
1996 /*
1997 * Suspended - return to VM.cpp.
1998 */
1999 case EMSTATE_SUSPENDED:
2000 TMR3NotifySuspend(pVM, pVCpu);
2001 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2002 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2003 return VINF_EM_SUSPEND;
2004
2005 /*
2006 * Debugging in the guest.
2007 */
2008 case EMSTATE_DEBUG_GUEST_REM:
2009 case EMSTATE_DEBUG_GUEST_RAW:
2010 TMR3NotifySuspend(pVM, pVCpu);
2011 rc = emR3Debug(pVM, pVCpu, rc);
2012 TMR3NotifyResume(pVM, pVCpu);
2013 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2014 break;
2015
2016 /*
2017 * Debugging in the hypervisor.
2018 */
2019 case EMSTATE_DEBUG_HYPER:
2020 {
2021 TMR3NotifySuspend(pVM, pVCpu);
2022 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2023
2024 rc = emR3Debug(pVM, pVCpu, rc);
2025 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2026 if (rc != VINF_SUCCESS)
2027 {
2028 /* switch to guru meditation mode */
2029 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2030 VMMR3FatalDump(pVM, pVCpu, rc);
2031 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2032 return rc;
2033 }
2034
2035 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2036 TMR3NotifyResume(pVM, pVCpu);
2037 break;
2038 }
2039
2040 /*
2041 * Guru meditation takes place in the debugger.
2042 */
2043 case EMSTATE_GURU_MEDITATION:
2044 {
2045 TMR3NotifySuspend(pVM, pVCpu);
2046 VMMR3FatalDump(pVM, pVCpu, rc);
2047 emR3Debug(pVM, pVCpu, rc);
2048 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2049 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2050 return rc;
2051 }
2052
2053 /*
2054 * The states we don't expect here.
2055 */
2056 case EMSTATE_NONE:
2057 case EMSTATE_TERMINATING:
2058 default:
2059 AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVCpu->em.s.enmState));
2060 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2061 TMR3NotifySuspend(pVM, pVCpu);
2062 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2063 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2064 return VERR_EM_INTERNAL_ERROR;
2065 }
2066 } /* The Outer Main Loop */
2067 }
2068 else
2069 {
2070 /*
2071 * Fatal error.
2072 */
2073 Log(("EMR3ExecuteVM: returns %Rrc because of longjmp / fatal error; (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2074 TMR3NotifySuspend(pVM, pVCpu);
2075 VMMR3FatalDump(pVM, pVCpu, rc);
2076 emR3Debug(pVM, pVCpu, rc);
2077 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2078 /** @todo change the VM state! */
2079 return rc;
2080 }
2081
2082 /* (won't ever get here). */
2083 AssertFailed();
2084}
2085
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