1 | /* $Id: EM.cpp 30050 2010-06-07 07:11:15Z vboxsync $ */
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2 | /** @file
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3 | * EM - Execution Monitor / Manager.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2007 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | */
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17 |
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18 | /** @page pg_em EM - The Execution Monitor / Manager
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19 | *
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20 | * The Execution Monitor/Manager is responsible for running the VM, scheduling
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21 | * the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
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22 | * Interpreted), and keeping the CPU states in sync. The function
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23 | * EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
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24 | * modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
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25 | * emR3RemExecute).
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26 | *
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27 | * The interpreted execution is only used to avoid switching between
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28 | * raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
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29 | * The interpretation is thus implemented as part of EM.
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30 | *
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31 | * @see grp_em
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32 | */
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33 |
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34 | /*******************************************************************************
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35 | * Header Files *
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36 | *******************************************************************************/
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37 | #define LOG_GROUP LOG_GROUP_EM
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38 | #include <VBox/em.h>
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39 | #include <VBox/vmm.h>
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40 | #include <VBox/patm.h>
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41 | #include <VBox/csam.h>
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42 | #include <VBox/selm.h>
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43 | #include <VBox/trpm.h>
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44 | #include <VBox/iom.h>
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45 | #include <VBox/dbgf.h>
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46 | #include <VBox/pgm.h>
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47 | #include <VBox/rem.h>
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48 | #include <VBox/tm.h>
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49 | #include <VBox/mm.h>
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50 | #include <VBox/ssm.h>
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51 | #include <VBox/pdmapi.h>
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52 | #include <VBox/pdmcritsect.h>
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53 | #include <VBox/pdmqueue.h>
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54 | #include <VBox/hwaccm.h>
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55 | #include <VBox/patm.h>
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56 | #include "EMInternal.h"
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57 | #include <VBox/vm.h>
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58 | #include <VBox/cpumdis.h>
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59 | #include <VBox/dis.h>
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60 | #include <VBox/disopcode.h>
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61 | #include <VBox/dbgf.h>
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62 |
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63 | #include <iprt/asm.h>
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64 | #include <iprt/string.h>
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65 | #include <iprt/stream.h>
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66 |
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67 |
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68 | /*******************************************************************************
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69 | * Defined Constants And Macros *
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70 | *******************************************************************************/
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71 | #if 0 /* Disabled till after 2.1.0 when we've time to test it. */
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72 | #define EM_NOTIFY_HWACCM
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73 | #endif
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74 |
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75 |
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76 | /*******************************************************************************
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77 | * Internal Functions *
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78 | *******************************************************************************/
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79 | static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
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80 | static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
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81 | static const char *emR3GetStateName(EMSTATE enmState);
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82 | static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc);
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83 | static int emR3RemStep(PVM pVM, PVMCPU pVCpu);
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84 | static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
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85 | int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
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86 |
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87 |
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88 | /**
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89 | * Initializes the EM.
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90 | *
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91 | * @returns VBox status code.
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92 | * @param pVM The VM to operate on.
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93 | */
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94 | VMMR3DECL(int) EMR3Init(PVM pVM)
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95 | {
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96 | LogFlow(("EMR3Init\n"));
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97 | /*
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98 | * Assert alignment and sizes.
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99 | */
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100 | AssertCompileMemberAlignment(VM, em.s, 32);
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101 | AssertCompile(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
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102 | AssertCompile(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump));
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103 | AssertCompileMemberAlignment(EM, CritSectREM, sizeof(uintptr_t));
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104 |
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105 | /*
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106 | * Init the structure.
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107 | */
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108 | pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
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109 | int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
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110 | if (RT_FAILURE(rc))
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111 | pVM->fRawR3Enabled = true;
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112 | rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
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113 | if (RT_FAILURE(rc))
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114 | pVM->fRawR0Enabled = true;
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115 | Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
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116 |
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117 | /*
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118 | * Initialize the REM critical section.
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119 | */
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120 | rc = PDMR3CritSectInit(pVM, &pVM->em.s.CritSectREM, RT_SRC_POS, "EM-REM");
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121 | AssertRCReturn(rc, rc);
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122 |
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123 | /*
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124 | * Saved state.
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125 | */
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126 | rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
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127 | NULL, NULL, NULL,
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128 | NULL, emR3Save, NULL,
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129 | NULL, emR3Load, NULL);
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130 | if (RT_FAILURE(rc))
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131 | return rc;
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132 |
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133 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
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134 | {
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135 | PVMCPU pVCpu = &pVM->aCpus[i];
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136 |
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137 | pVCpu->em.s.offVMCPU = RT_OFFSETOF(VMCPU, em.s);
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138 |
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139 | pVCpu->em.s.enmState = (i == 0) ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
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140 | pVCpu->em.s.enmPrevState = EMSTATE_NONE;
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141 | pVCpu->em.s.fForceRAW = false;
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142 |
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143 | pVCpu->em.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
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144 | pVCpu->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
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145 | AssertMsg(pVCpu->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
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146 |
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147 | # define EM_REG_COUNTER(a, b, c) \
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148 | rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
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149 | AssertRC(rc);
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150 |
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151 | # define EM_REG_COUNTER_USED(a, b, c) \
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152 | rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, c, b, i); \
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153 | AssertRC(rc);
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154 |
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155 | # define EM_REG_PROFILE(a, b, c) \
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156 | rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
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157 | AssertRC(rc);
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158 |
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159 | # define EM_REG_PROFILE_ADV(a, b, c) \
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160 | rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
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161 | AssertRC(rc);
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162 |
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163 | /*
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164 | * Statistics.
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165 | */
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166 | #ifdef VBOX_WITH_STATISTICS
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167 | PEMSTATS pStats;
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168 | rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
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169 | if (RT_FAILURE(rc))
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170 | return rc;
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171 |
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172 | pVCpu->em.s.pStatsR3 = pStats;
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173 | pVCpu->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
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174 | pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
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175 |
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176 | EM_REG_PROFILE(&pStats->StatRZEmulate, "/EM/CPU%d/RZ/Interpret", "Profiling of EMInterpretInstruction.");
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177 | EM_REG_PROFILE(&pStats->StatR3Emulate, "/EM/CPU%d/R3/Interpret", "Profiling of EMInterpretInstruction.");
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178 |
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179 | EM_REG_PROFILE(&pStats->StatRZInterpretSucceeded, "/EM/CPU%d/RZ/Interpret/Success", "The number of times an instruction was successfully interpreted.");
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180 | EM_REG_PROFILE(&pStats->StatR3InterpretSucceeded, "/EM/CPU%d/R3/Interpret/Success", "The number of times an instruction was successfully interpreted.");
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181 |
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182 | EM_REG_COUNTER_USED(&pStats->StatRZAnd, "/EM/CPU%d/RZ/Interpret/Success/And", "The number of times AND was successfully interpreted.");
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183 | EM_REG_COUNTER_USED(&pStats->StatR3And, "/EM/CPU%d/R3/Interpret/Success/And", "The number of times AND was successfully interpreted.");
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184 | EM_REG_COUNTER_USED(&pStats->StatRZAdd, "/EM/CPU%d/RZ/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
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185 | EM_REG_COUNTER_USED(&pStats->StatR3Add, "/EM/CPU%d/R3/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
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186 | EM_REG_COUNTER_USED(&pStats->StatRZAdc, "/EM/CPU%d/RZ/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
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187 | EM_REG_COUNTER_USED(&pStats->StatR3Adc, "/EM/CPU%d/R3/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
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188 | EM_REG_COUNTER_USED(&pStats->StatRZSub, "/EM/CPU%d/RZ/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
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189 | EM_REG_COUNTER_USED(&pStats->StatR3Sub, "/EM/CPU%d/R3/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
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190 | EM_REG_COUNTER_USED(&pStats->StatRZCpuId, "/EM/CPU%d/RZ/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
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191 | EM_REG_COUNTER_USED(&pStats->StatR3CpuId, "/EM/CPU%d/R3/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
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192 | EM_REG_COUNTER_USED(&pStats->StatRZDec, "/EM/CPU%d/RZ/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
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193 | EM_REG_COUNTER_USED(&pStats->StatR3Dec, "/EM/CPU%d/R3/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
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194 | EM_REG_COUNTER_USED(&pStats->StatRZHlt, "/EM/CPU%d/RZ/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
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195 | EM_REG_COUNTER_USED(&pStats->StatR3Hlt, "/EM/CPU%d/R3/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
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196 | EM_REG_COUNTER_USED(&pStats->StatRZInc, "/EM/CPU%d/RZ/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
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197 | EM_REG_COUNTER_USED(&pStats->StatR3Inc, "/EM/CPU%d/R3/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
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198 | EM_REG_COUNTER_USED(&pStats->StatRZInvlPg, "/EM/CPU%d/RZ/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
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199 | EM_REG_COUNTER_USED(&pStats->StatR3InvlPg, "/EM/CPU%d/R3/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
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200 | EM_REG_COUNTER_USED(&pStats->StatRZIret, "/EM/CPU%d/RZ/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
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201 | EM_REG_COUNTER_USED(&pStats->StatR3Iret, "/EM/CPU%d/R3/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
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202 | EM_REG_COUNTER_USED(&pStats->StatRZLLdt, "/EM/CPU%d/RZ/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
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203 | EM_REG_COUNTER_USED(&pStats->StatR3LLdt, "/EM/CPU%d/R3/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
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204 | EM_REG_COUNTER_USED(&pStats->StatRZLIdt, "/EM/CPU%d/RZ/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
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205 | EM_REG_COUNTER_USED(&pStats->StatR3LIdt, "/EM/CPU%d/R3/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
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206 | EM_REG_COUNTER_USED(&pStats->StatRZLGdt, "/EM/CPU%d/RZ/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
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207 | EM_REG_COUNTER_USED(&pStats->StatR3LGdt, "/EM/CPU%d/R3/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
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208 | EM_REG_COUNTER_USED(&pStats->StatRZMov, "/EM/CPU%d/RZ/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
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209 | EM_REG_COUNTER_USED(&pStats->StatR3Mov, "/EM/CPU%d/R3/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
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210 | EM_REG_COUNTER_USED(&pStats->StatRZMovCRx, "/EM/CPU%d/RZ/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
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211 | EM_REG_COUNTER_USED(&pStats->StatR3MovCRx, "/EM/CPU%d/R3/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
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212 | EM_REG_COUNTER_USED(&pStats->StatRZMovDRx, "/EM/CPU%d/RZ/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
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213 | EM_REG_COUNTER_USED(&pStats->StatR3MovDRx, "/EM/CPU%d/R3/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
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214 | EM_REG_COUNTER_USED(&pStats->StatRZOr, "/EM/CPU%d/RZ/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
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215 | EM_REG_COUNTER_USED(&pStats->StatR3Or, "/EM/CPU%d/R3/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
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216 | EM_REG_COUNTER_USED(&pStats->StatRZPop, "/EM/CPU%d/RZ/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
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217 | EM_REG_COUNTER_USED(&pStats->StatR3Pop, "/EM/CPU%d/R3/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
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218 | EM_REG_COUNTER_USED(&pStats->StatRZRdtsc, "/EM/CPU%d/RZ/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
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219 | EM_REG_COUNTER_USED(&pStats->StatR3Rdtsc, "/EM/CPU%d/R3/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
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220 | EM_REG_COUNTER_USED(&pStats->StatRZRdpmc, "/EM/CPU%d/RZ/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
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221 | EM_REG_COUNTER_USED(&pStats->StatR3Rdpmc, "/EM/CPU%d/R3/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
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222 | EM_REG_COUNTER_USED(&pStats->StatRZSti, "/EM/CPU%d/RZ/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
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223 | EM_REG_COUNTER_USED(&pStats->StatR3Sti, "/EM/CPU%d/R3/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
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224 | EM_REG_COUNTER_USED(&pStats->StatRZXchg, "/EM/CPU%d/RZ/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
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225 | EM_REG_COUNTER_USED(&pStats->StatR3Xchg, "/EM/CPU%d/R3/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
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226 | EM_REG_COUNTER_USED(&pStats->StatRZXor, "/EM/CPU%d/RZ/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
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227 | EM_REG_COUNTER_USED(&pStats->StatR3Xor, "/EM/CPU%d/R3/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
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228 | EM_REG_COUNTER_USED(&pStats->StatRZMonitor, "/EM/CPU%d/RZ/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
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229 | EM_REG_COUNTER_USED(&pStats->StatR3Monitor, "/EM/CPU%d/R3/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
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230 | EM_REG_COUNTER_USED(&pStats->StatRZMWait, "/EM/CPU%d/RZ/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
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231 | EM_REG_COUNTER_USED(&pStats->StatR3MWait, "/EM/CPU%d/R3/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
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232 | EM_REG_COUNTER_USED(&pStats->StatRZBtr, "/EM/CPU%d/RZ/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
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233 | EM_REG_COUNTER_USED(&pStats->StatR3Btr, "/EM/CPU%d/R3/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
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234 | EM_REG_COUNTER_USED(&pStats->StatRZBts, "/EM/CPU%d/RZ/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
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235 | EM_REG_COUNTER_USED(&pStats->StatR3Bts, "/EM/CPU%d/R3/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
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236 | EM_REG_COUNTER_USED(&pStats->StatRZBtc, "/EM/CPU%d/RZ/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
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237 | EM_REG_COUNTER_USED(&pStats->StatR3Btc, "/EM/CPU%d/R3/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
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238 | EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
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239 | EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg, "/EM/CPU%d/R3/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
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240 | EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
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241 | EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg8b, "/EM/CPU%d/R3/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
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242 | EM_REG_COUNTER_USED(&pStats->StatRZXAdd, "/EM/CPU%d/RZ/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
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243 | EM_REG_COUNTER_USED(&pStats->StatR3XAdd, "/EM/CPU%d/R3/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
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244 | EM_REG_COUNTER_USED(&pStats->StatR3Rdmsr, "/EM/CPU%d/R3/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
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245 | EM_REG_COUNTER_USED(&pStats->StatRZRdmsr, "/EM/CPU%d/RZ/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
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246 | EM_REG_COUNTER_USED(&pStats->StatR3Wrmsr, "/EM/CPU%d/R3/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
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247 | EM_REG_COUNTER_USED(&pStats->StatRZWrmsr, "/EM/CPU%d/RZ/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
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248 | EM_REG_COUNTER_USED(&pStats->StatR3StosWD, "/EM/CPU%d/R3/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
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249 | EM_REG_COUNTER_USED(&pStats->StatRZStosWD, "/EM/CPU%d/RZ/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
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250 | EM_REG_COUNTER_USED(&pStats->StatRZWbInvd, "/EM/CPU%d/RZ/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
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251 | EM_REG_COUNTER_USED(&pStats->StatR3WbInvd, "/EM/CPU%d/R3/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
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252 | EM_REG_COUNTER_USED(&pStats->StatRZLmsw, "/EM/CPU%d/RZ/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
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253 | EM_REG_COUNTER_USED(&pStats->StatR3Lmsw, "/EM/CPU%d/R3/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
|
---|
254 |
|
---|
255 | EM_REG_COUNTER(&pStats->StatRZInterpretFailed, "/EM/CPU%d/RZ/Interpret/Failed", "The number of times an instruction was not interpreted.");
|
---|
256 | EM_REG_COUNTER(&pStats->StatR3InterpretFailed, "/EM/CPU%d/R3/Interpret/Failed", "The number of times an instruction was not interpreted.");
|
---|
257 |
|
---|
258 | EM_REG_COUNTER_USED(&pStats->StatRZFailedAnd, "/EM/CPU%d/RZ/Interpret/Failed/And", "The number of times AND was not interpreted.");
|
---|
259 | EM_REG_COUNTER_USED(&pStats->StatR3FailedAnd, "/EM/CPU%d/R3/Interpret/Failed/And", "The number of times AND was not interpreted.");
|
---|
260 | EM_REG_COUNTER_USED(&pStats->StatRZFailedCpuId, "/EM/CPU%d/RZ/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
|
---|
261 | EM_REG_COUNTER_USED(&pStats->StatR3FailedCpuId, "/EM/CPU%d/R3/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
|
---|
262 | EM_REG_COUNTER_USED(&pStats->StatRZFailedDec, "/EM/CPU%d/RZ/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
|
---|
263 | EM_REG_COUNTER_USED(&pStats->StatR3FailedDec, "/EM/CPU%d/R3/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
|
---|
264 | EM_REG_COUNTER_USED(&pStats->StatRZFailedHlt, "/EM/CPU%d/RZ/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
|
---|
265 | EM_REG_COUNTER_USED(&pStats->StatR3FailedHlt, "/EM/CPU%d/R3/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
|
---|
266 | EM_REG_COUNTER_USED(&pStats->StatRZFailedInc, "/EM/CPU%d/RZ/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
|
---|
267 | EM_REG_COUNTER_USED(&pStats->StatR3FailedInc, "/EM/CPU%d/R3/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
|
---|
268 | EM_REG_COUNTER_USED(&pStats->StatRZFailedInvlPg, "/EM/CPU%d/RZ/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
|
---|
269 | EM_REG_COUNTER_USED(&pStats->StatR3FailedInvlPg, "/EM/CPU%d/R3/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
|
---|
270 | EM_REG_COUNTER_USED(&pStats->StatRZFailedIret, "/EM/CPU%d/RZ/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
|
---|
271 | EM_REG_COUNTER_USED(&pStats->StatR3FailedIret, "/EM/CPU%d/R3/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
|
---|
272 | EM_REG_COUNTER_USED(&pStats->StatRZFailedLLdt, "/EM/CPU%d/RZ/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
|
---|
273 | EM_REG_COUNTER_USED(&pStats->StatR3FailedLLdt, "/EM/CPU%d/R3/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
|
---|
274 | EM_REG_COUNTER_USED(&pStats->StatRZFailedLIdt, "/EM/CPU%d/RZ/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
|
---|
275 | EM_REG_COUNTER_USED(&pStats->StatR3FailedLIdt, "/EM/CPU%d/R3/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
|
---|
276 | EM_REG_COUNTER_USED(&pStats->StatRZFailedLGdt, "/EM/CPU%d/RZ/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
|
---|
277 | EM_REG_COUNTER_USED(&pStats->StatR3FailedLGdt, "/EM/CPU%d/R3/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
|
---|
278 | EM_REG_COUNTER_USED(&pStats->StatRZFailedMov, "/EM/CPU%d/RZ/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
|
---|
279 | EM_REG_COUNTER_USED(&pStats->StatR3FailedMov, "/EM/CPU%d/R3/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
|
---|
280 | EM_REG_COUNTER_USED(&pStats->StatRZFailedMovCRx, "/EM/CPU%d/RZ/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
|
---|
281 | EM_REG_COUNTER_USED(&pStats->StatR3FailedMovCRx, "/EM/CPU%d/R3/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
|
---|
282 | EM_REG_COUNTER_USED(&pStats->StatRZFailedMovDRx, "/EM/CPU%d/RZ/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
|
---|
283 | EM_REG_COUNTER_USED(&pStats->StatR3FailedMovDRx, "/EM/CPU%d/R3/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
|
---|
284 | EM_REG_COUNTER_USED(&pStats->StatRZFailedOr, "/EM/CPU%d/RZ/Interpret/Failed/Or", "The number of times OR was not interpreted.");
|
---|
285 | EM_REG_COUNTER_USED(&pStats->StatR3FailedOr, "/EM/CPU%d/R3/Interpret/Failed/Or", "The number of times OR was not interpreted.");
|
---|
286 | EM_REG_COUNTER_USED(&pStats->StatRZFailedPop, "/EM/CPU%d/RZ/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
|
---|
287 | EM_REG_COUNTER_USED(&pStats->StatR3FailedPop, "/EM/CPU%d/R3/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
|
---|
288 | EM_REG_COUNTER_USED(&pStats->StatRZFailedSti, "/EM/CPU%d/RZ/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
|
---|
289 | EM_REG_COUNTER_USED(&pStats->StatR3FailedSti, "/EM/CPU%d/R3/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
|
---|
290 | EM_REG_COUNTER_USED(&pStats->StatRZFailedXchg, "/EM/CPU%d/RZ/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
|
---|
291 | EM_REG_COUNTER_USED(&pStats->StatR3FailedXchg, "/EM/CPU%d/R3/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
|
---|
292 | EM_REG_COUNTER_USED(&pStats->StatRZFailedXor, "/EM/CPU%d/RZ/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
|
---|
293 | EM_REG_COUNTER_USED(&pStats->StatR3FailedXor, "/EM/CPU%d/R3/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
|
---|
294 | EM_REG_COUNTER_USED(&pStats->StatRZFailedMonitor, "/EM/CPU%d/RZ/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
|
---|
295 | EM_REG_COUNTER_USED(&pStats->StatR3FailedMonitor, "/EM/CPU%d/R3/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
|
---|
296 | EM_REG_COUNTER_USED(&pStats->StatRZFailedMWait, "/EM/CPU%d/RZ/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
|
---|
297 | EM_REG_COUNTER_USED(&pStats->StatR3FailedMWait, "/EM/CPU%d/R3/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
|
---|
298 | EM_REG_COUNTER_USED(&pStats->StatRZFailedRdtsc, "/EM/CPU%d/RZ/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
|
---|
299 | EM_REG_COUNTER_USED(&pStats->StatR3FailedRdtsc, "/EM/CPU%d/R3/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
|
---|
300 | EM_REG_COUNTER_USED(&pStats->StatRZFailedRdpmc, "/EM/CPU%d/RZ/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
|
---|
301 | EM_REG_COUNTER_USED(&pStats->StatR3FailedRdpmc, "/EM/CPU%d/R3/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
|
---|
302 | EM_REG_COUNTER_USED(&pStats->StatRZFailedRdmsr, "/EM/CPU%d/RZ/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
|
---|
303 | EM_REG_COUNTER_USED(&pStats->StatR3FailedRdmsr, "/EM/CPU%d/R3/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
|
---|
304 | EM_REG_COUNTER_USED(&pStats->StatRZFailedWrmsr, "/EM/CPU%d/RZ/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
|
---|
305 | EM_REG_COUNTER_USED(&pStats->StatR3FailedWrmsr, "/EM/CPU%d/R3/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
|
---|
306 | EM_REG_COUNTER_USED(&pStats->StatRZFailedLmsw, "/EM/CPU%d/RZ/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
|
---|
307 | EM_REG_COUNTER_USED(&pStats->StatR3FailedLmsw, "/EM/CPU%d/R3/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
|
---|
308 |
|
---|
309 | EM_REG_COUNTER_USED(&pStats->StatRZFailedMisc, "/EM/CPU%d/RZ/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
|
---|
310 | EM_REG_COUNTER_USED(&pStats->StatR3FailedMisc, "/EM/CPU%d/R3/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
|
---|
311 | EM_REG_COUNTER_USED(&pStats->StatRZFailedAdd, "/EM/CPU%d/RZ/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
|
---|
312 | EM_REG_COUNTER_USED(&pStats->StatR3FailedAdd, "/EM/CPU%d/R3/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
|
---|
313 | EM_REG_COUNTER_USED(&pStats->StatRZFailedAdc, "/EM/CPU%d/RZ/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
|
---|
314 | EM_REG_COUNTER_USED(&pStats->StatR3FailedAdc, "/EM/CPU%d/R3/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
|
---|
315 | EM_REG_COUNTER_USED(&pStats->StatRZFailedBtr, "/EM/CPU%d/RZ/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
|
---|
316 | EM_REG_COUNTER_USED(&pStats->StatR3FailedBtr, "/EM/CPU%d/R3/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
|
---|
317 | EM_REG_COUNTER_USED(&pStats->StatRZFailedBts, "/EM/CPU%d/RZ/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
|
---|
318 | EM_REG_COUNTER_USED(&pStats->StatR3FailedBts, "/EM/CPU%d/R3/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
|
---|
319 | EM_REG_COUNTER_USED(&pStats->StatRZFailedBtc, "/EM/CPU%d/RZ/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
|
---|
320 | EM_REG_COUNTER_USED(&pStats->StatR3FailedBtc, "/EM/CPU%d/R3/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
|
---|
321 | EM_REG_COUNTER_USED(&pStats->StatRZFailedCli, "/EM/CPU%d/RZ/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
|
---|
322 | EM_REG_COUNTER_USED(&pStats->StatR3FailedCli, "/EM/CPU%d/R3/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
|
---|
323 | EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
|
---|
324 | EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
|
---|
325 | EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
|
---|
326 | EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg8b, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
|
---|
327 | EM_REG_COUNTER_USED(&pStats->StatRZFailedXAdd, "/EM/CPU%d/RZ/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
|
---|
328 | EM_REG_COUNTER_USED(&pStats->StatR3FailedXAdd, "/EM/CPU%d/R3/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
|
---|
329 | EM_REG_COUNTER_USED(&pStats->StatRZFailedMovNTPS, "/EM/CPU%d/RZ/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
|
---|
330 | EM_REG_COUNTER_USED(&pStats->StatR3FailedMovNTPS, "/EM/CPU%d/R3/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
|
---|
331 | EM_REG_COUNTER_USED(&pStats->StatRZFailedStosWD, "/EM/CPU%d/RZ/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
|
---|
332 | EM_REG_COUNTER_USED(&pStats->StatR3FailedStosWD, "/EM/CPU%d/R3/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
|
---|
333 | EM_REG_COUNTER_USED(&pStats->StatRZFailedSub, "/EM/CPU%d/RZ/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
|
---|
334 | EM_REG_COUNTER_USED(&pStats->StatR3FailedSub, "/EM/CPU%d/R3/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
|
---|
335 | EM_REG_COUNTER_USED(&pStats->StatRZFailedWbInvd, "/EM/CPU%d/RZ/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
|
---|
336 | EM_REG_COUNTER_USED(&pStats->StatR3FailedWbInvd, "/EM/CPU%d/R3/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
|
---|
337 |
|
---|
338 | EM_REG_COUNTER_USED(&pStats->StatRZFailedUserMode, "/EM/CPU%d/RZ/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
|
---|
339 | EM_REG_COUNTER_USED(&pStats->StatR3FailedUserMode, "/EM/CPU%d/R3/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
|
---|
340 | EM_REG_COUNTER_USED(&pStats->StatRZFailedPrefix, "/EM/CPU%d/RZ/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
|
---|
341 | EM_REG_COUNTER_USED(&pStats->StatR3FailedPrefix, "/EM/CPU%d/R3/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
|
---|
342 |
|
---|
343 | EM_REG_COUNTER_USED(&pStats->StatCli, "/EM/CPU%d/R3/PrivInst/Cli", "Number of cli instructions.");
|
---|
344 | EM_REG_COUNTER_USED(&pStats->StatSti, "/EM/CPU%d/R3/PrivInst/Sti", "Number of sli instructions.");
|
---|
345 | EM_REG_COUNTER_USED(&pStats->StatIn, "/EM/CPU%d/R3/PrivInst/In", "Number of in instructions.");
|
---|
346 | EM_REG_COUNTER_USED(&pStats->StatOut, "/EM/CPU%d/R3/PrivInst/Out", "Number of out instructions.");
|
---|
347 | EM_REG_COUNTER_USED(&pStats->StatIoRestarted, "/EM/CPU%d/R3/PrivInst/IoRestarted", "Number of restarted i/o instructions.");
|
---|
348 | EM_REG_COUNTER_USED(&pStats->StatHlt, "/EM/CPU%d/R3/PrivInst/Hlt", "Number of hlt instructions not handled in GC because of PATM.");
|
---|
349 | EM_REG_COUNTER_USED(&pStats->StatInvlpg, "/EM/CPU%d/R3/PrivInst/Invlpg", "Number of invlpg instructions.");
|
---|
350 | EM_REG_COUNTER_USED(&pStats->StatMisc, "/EM/CPU%d/R3/PrivInst/Misc", "Number of misc. instructions.");
|
---|
351 | EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[0], "/EM/CPU%d/R3/PrivInst/Mov CR0, X", "Number of mov CR0 read instructions.");
|
---|
352 | EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[1], "/EM/CPU%d/R3/PrivInst/Mov CR1, X", "Number of mov CR1 read instructions.");
|
---|
353 | EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[2], "/EM/CPU%d/R3/PrivInst/Mov CR2, X", "Number of mov CR2 read instructions.");
|
---|
354 | EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[3], "/EM/CPU%d/R3/PrivInst/Mov CR3, X", "Number of mov CR3 read instructions.");
|
---|
355 | EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[4], "/EM/CPU%d/R3/PrivInst/Mov CR4, X", "Number of mov CR4 read instructions.");
|
---|
356 | EM_REG_COUNTER_USED(&pStats->StatMovReadCR[0], "/EM/CPU%d/R3/PrivInst/Mov X, CR0", "Number of mov CR0 write instructions.");
|
---|
357 | EM_REG_COUNTER_USED(&pStats->StatMovReadCR[1], "/EM/CPU%d/R3/PrivInst/Mov X, CR1", "Number of mov CR1 write instructions.");
|
---|
358 | EM_REG_COUNTER_USED(&pStats->StatMovReadCR[2], "/EM/CPU%d/R3/PrivInst/Mov X, CR2", "Number of mov CR2 write instructions.");
|
---|
359 | EM_REG_COUNTER_USED(&pStats->StatMovReadCR[3], "/EM/CPU%d/R3/PrivInst/Mov X, CR3", "Number of mov CR3 write instructions.");
|
---|
360 | EM_REG_COUNTER_USED(&pStats->StatMovReadCR[4], "/EM/CPU%d/R3/PrivInst/Mov X, CR4", "Number of mov CR4 write instructions.");
|
---|
361 | EM_REG_COUNTER_USED(&pStats->StatMovDRx, "/EM/CPU%d/R3/PrivInst/MovDRx", "Number of mov DRx instructions.");
|
---|
362 | EM_REG_COUNTER_USED(&pStats->StatIret, "/EM/CPU%d/R3/PrivInst/Iret", "Number of iret instructions.");
|
---|
363 | EM_REG_COUNTER_USED(&pStats->StatMovLgdt, "/EM/CPU%d/R3/PrivInst/Lgdt", "Number of lgdt instructions.");
|
---|
364 | EM_REG_COUNTER_USED(&pStats->StatMovLidt, "/EM/CPU%d/R3/PrivInst/Lidt", "Number of lidt instructions.");
|
---|
365 | EM_REG_COUNTER_USED(&pStats->StatMovLldt, "/EM/CPU%d/R3/PrivInst/Lldt", "Number of lldt instructions.");
|
---|
366 | EM_REG_COUNTER_USED(&pStats->StatSysEnter, "/EM/CPU%d/R3/PrivInst/Sysenter", "Number of sysenter instructions.");
|
---|
367 | EM_REG_COUNTER_USED(&pStats->StatSysExit, "/EM/CPU%d/R3/PrivInst/Sysexit", "Number of sysexit instructions.");
|
---|
368 | EM_REG_COUNTER_USED(&pStats->StatSysCall, "/EM/CPU%d/R3/PrivInst/Syscall", "Number of syscall instructions.");
|
---|
369 | EM_REG_COUNTER_USED(&pStats->StatSysRet, "/EM/CPU%d/R3/PrivInst/Sysret", "Number of sysret instructions.");
|
---|
370 |
|
---|
371 | EM_REG_COUNTER(&pVCpu->em.s.StatTotalClis, "/EM/CPU%d/Cli/Total", "Total number of cli instructions executed.");
|
---|
372 | pVCpu->em.s.pCliStatTree = 0;
|
---|
373 |
|
---|
374 | /* these should be considered for release statistics. */
|
---|
375 | EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction.");
|
---|
376 | EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged.");
|
---|
377 | EM_REG_PROFILE(&pVCpu->em.s.StatHwAccEntry, "/PROF/CPU%d/EM/HwAccEnter", "Profiling Hardware Accelerated Mode entry overhead.");
|
---|
378 | EM_REG_PROFILE(&pVCpu->em.s.StatHwAccExec, "/PROF/CPU%d/EM/HwAccExec", "Profiling Hardware Accelerated Mode execution.");
|
---|
379 | EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution.");
|
---|
380 | EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%d/EM/REMExec", "Profiling REM execution.");
|
---|
381 | EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing.");
|
---|
382 | EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead.");
|
---|
383 | EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution.");
|
---|
384 | EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead.");
|
---|
385 |
|
---|
386 | #endif /* VBOX_WITH_STATISTICS */
|
---|
387 |
|
---|
388 | EM_REG_COUNTER(&pVCpu->em.s.StatForcedActions, "/PROF/CPU%d/EM/ForcedActions", "Profiling forced action execution.");
|
---|
389 | EM_REG_COUNTER(&pVCpu->em.s.StatHalted, "/PROF/CPU%d/EM/Halted", "Profiling halted state (VMR3WaitHalted).");
|
---|
390 | EM_REG_COUNTER(&pVCpu->em.s.StatREMTotal, "/PROF/CPU%d/EM/REMTotal", "Profiling emR3RemExecute (excluding FFs).");
|
---|
391 | EM_REG_COUNTER(&pVCpu->em.s.StatRAWTotal, "/PROF/CPU%d/EM/RAWTotal", "Profiling emR3RawExecute (excluding FFs).");
|
---|
392 |
|
---|
393 | EM_REG_PROFILE_ADV(&pVCpu->em.s.StatTotal, "/PROF/CPU%d/EM/Total", "Profiling EMR3ExecuteVM.");
|
---|
394 | }
|
---|
395 |
|
---|
396 | return VINF_SUCCESS;
|
---|
397 | }
|
---|
398 |
|
---|
399 |
|
---|
400 | /**
|
---|
401 | * Initializes the per-VCPU EM.
|
---|
402 | *
|
---|
403 | * @returns VBox status code.
|
---|
404 | * @param pVM The VM to operate on.
|
---|
405 | */
|
---|
406 | VMMR3DECL(int) EMR3InitCPU(PVM pVM)
|
---|
407 | {
|
---|
408 | LogFlow(("EMR3InitCPU\n"));
|
---|
409 | return VINF_SUCCESS;
|
---|
410 | }
|
---|
411 |
|
---|
412 |
|
---|
413 | /**
|
---|
414 | * Applies relocations to data and code managed by this
|
---|
415 | * component. This function will be called at init and
|
---|
416 | * whenever the VMM need to relocate it self inside the GC.
|
---|
417 | *
|
---|
418 | * @param pVM The VM.
|
---|
419 | */
|
---|
420 | VMMR3DECL(void) EMR3Relocate(PVM pVM)
|
---|
421 | {
|
---|
422 | LogFlow(("EMR3Relocate\n"));
|
---|
423 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
424 | {
|
---|
425 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
426 | if (pVCpu->em.s.pStatsR3)
|
---|
427 | pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVCpu->em.s.pStatsR3);
|
---|
428 | }
|
---|
429 | }
|
---|
430 |
|
---|
431 |
|
---|
432 | /**
|
---|
433 | * Reset the EM state for a CPU.
|
---|
434 | *
|
---|
435 | * Called by EMR3Reset and hot plugging.
|
---|
436 | *
|
---|
437 | * @param pVCpu The virtual CPU.
|
---|
438 | */
|
---|
439 | VMMR3DECL(void) EMR3ResetCpu(PVMCPU pVCpu)
|
---|
440 | {
|
---|
441 | pVCpu->em.s.fForceRAW = false;
|
---|
442 |
|
---|
443 | /* VMR3Reset may return VINF_EM_RESET or VINF_EM_SUSPEND, so transition
|
---|
444 | out of the HALTED state here so that enmPrevState doesn't end up as
|
---|
445 | HALTED when EMR3Execute returns. */
|
---|
446 | if (pVCpu->em.s.enmState == EMSTATE_HALTED)
|
---|
447 | {
|
---|
448 | Log(("EMR3ResetCpu: Cpu#%u %s -> %s\n", pVCpu->idCpu, emR3GetStateName(pVCpu->em.s.enmState), pVCpu->idCpu == 0 ? "EMSTATE_NONE" : "EMSTATE_WAIT_SIPI"));
|
---|
449 | pVCpu->em.s.enmState = pVCpu->idCpu == 0 ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
|
---|
450 | }
|
---|
451 | }
|
---|
452 |
|
---|
453 |
|
---|
454 | /**
|
---|
455 | * Reset notification.
|
---|
456 | *
|
---|
457 | * @param pVM The VM handle.
|
---|
458 | */
|
---|
459 | VMMR3DECL(void) EMR3Reset(PVM pVM)
|
---|
460 | {
|
---|
461 | Log(("EMR3Reset: \n"));
|
---|
462 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
463 | EMR3ResetCpu(&pVM->aCpus[i]);
|
---|
464 | }
|
---|
465 |
|
---|
466 |
|
---|
467 | /**
|
---|
468 | * Terminates the EM.
|
---|
469 | *
|
---|
470 | * Termination means cleaning up and freeing all resources,
|
---|
471 | * the VM it self is at this point powered off or suspended.
|
---|
472 | *
|
---|
473 | * @returns VBox status code.
|
---|
474 | * @param pVM The VM to operate on.
|
---|
475 | */
|
---|
476 | VMMR3DECL(int) EMR3Term(PVM pVM)
|
---|
477 | {
|
---|
478 | AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
|
---|
479 |
|
---|
480 | PDMR3CritSectDelete(&pVM->em.s.CritSectREM);
|
---|
481 | return VINF_SUCCESS;
|
---|
482 | }
|
---|
483 |
|
---|
484 | /**
|
---|
485 | * Terminates the per-VCPU EM.
|
---|
486 | *
|
---|
487 | * Termination means cleaning up and freeing all resources,
|
---|
488 | * the VM it self is at this point powered off or suspended.
|
---|
489 | *
|
---|
490 | * @returns VBox status code.
|
---|
491 | * @param pVM The VM to operate on.
|
---|
492 | */
|
---|
493 | VMMR3DECL(int) EMR3TermCPU(PVM pVM)
|
---|
494 | {
|
---|
495 | return 0;
|
---|
496 | }
|
---|
497 |
|
---|
498 | /**
|
---|
499 | * Execute state save operation.
|
---|
500 | *
|
---|
501 | * @returns VBox status code.
|
---|
502 | * @param pVM VM Handle.
|
---|
503 | * @param pSSM SSM operation handle.
|
---|
504 | */
|
---|
505 | static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
|
---|
506 | {
|
---|
507 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
508 | {
|
---|
509 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
510 |
|
---|
511 | int rc = SSMR3PutBool(pSSM, pVCpu->em.s.fForceRAW);
|
---|
512 | AssertRCReturn(rc, rc);
|
---|
513 |
|
---|
514 | Assert(pVCpu->em.s.enmState == EMSTATE_SUSPENDED);
|
---|
515 | Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
|
---|
516 | rc = SSMR3PutU32(pSSM, pVCpu->em.s.enmPrevState);
|
---|
517 | AssertRCReturn(rc, rc);
|
---|
518 |
|
---|
519 | /* Save mwait state. */
|
---|
520 | rc = SSMR3PutU32(pSSM, pVCpu->em.s.mwait.fWait);
|
---|
521 | AssertRCReturn(rc, rc);
|
---|
522 | rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.mwait.uMWaitEAX);
|
---|
523 | AssertRCReturn(rc, rc);
|
---|
524 | rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.mwait.uMWaitECX);
|
---|
525 | AssertRCReturn(rc, rc);
|
---|
526 | rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.mwait.uMonitorEAX);
|
---|
527 | AssertRCReturn(rc, rc);
|
---|
528 | rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.mwait.uMonitorECX);
|
---|
529 | AssertRCReturn(rc, rc);
|
---|
530 | rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.mwait.uMonitorEDX);
|
---|
531 | AssertRCReturn(rc, rc);
|
---|
532 | }
|
---|
533 | return VINF_SUCCESS;
|
---|
534 | }
|
---|
535 |
|
---|
536 |
|
---|
537 | /**
|
---|
538 | * Execute state load operation.
|
---|
539 | *
|
---|
540 | * @returns VBox status code.
|
---|
541 | * @param pVM VM Handle.
|
---|
542 | * @param pSSM SSM operation handle.
|
---|
543 | * @param uVersion Data layout version.
|
---|
544 | * @param uPass The data pass.
|
---|
545 | */
|
---|
546 | static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
|
---|
547 | {
|
---|
548 | /*
|
---|
549 | * Validate version.
|
---|
550 | */
|
---|
551 | if ( uVersion != EM_SAVED_STATE_VERSION
|
---|
552 | && uVersion != EM_SAVED_STATE_VERSION_PRE_MWAIT
|
---|
553 | && uVersion != EM_SAVED_STATE_VERSION_PRE_SMP)
|
---|
554 | {
|
---|
555 | AssertMsgFailed(("emR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, EM_SAVED_STATE_VERSION));
|
---|
556 | return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
|
---|
557 | }
|
---|
558 | Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
|
---|
559 |
|
---|
560 | /*
|
---|
561 | * Load the saved state.
|
---|
562 | */
|
---|
563 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
564 | {
|
---|
565 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
566 |
|
---|
567 | int rc = SSMR3GetBool(pSSM, &pVCpu->em.s.fForceRAW);
|
---|
568 | if (RT_FAILURE(rc))
|
---|
569 | pVCpu->em.s.fForceRAW = false;
|
---|
570 | AssertRCReturn(rc, rc);
|
---|
571 |
|
---|
572 | if (uVersion > EM_SAVED_STATE_VERSION_PRE_SMP)
|
---|
573 | {
|
---|
574 | AssertCompile(sizeof(pVCpu->em.s.enmPrevState) == sizeof(uint32_t));
|
---|
575 | rc = SSMR3GetU32(pSSM, (uint32_t *)&pVCpu->em.s.enmPrevState);
|
---|
576 | AssertRCReturn(rc, rc);
|
---|
577 | Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
|
---|
578 |
|
---|
579 | pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
|
---|
580 | }
|
---|
581 | if (uVersion > EM_SAVED_STATE_VERSION_PRE_MWAIT)
|
---|
582 | {
|
---|
583 | /* Load mwait state. */
|
---|
584 | rc = SSMR3GetU32(pSSM, &pVCpu->em.s.mwait.fWait);
|
---|
585 | AssertRCReturn(rc, rc);
|
---|
586 | rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.mwait.uMWaitEAX);
|
---|
587 | AssertRCReturn(rc, rc);
|
---|
588 | rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.mwait.uMWaitECX);
|
---|
589 | AssertRCReturn(rc, rc);
|
---|
590 | rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.mwait.uMonitorEAX);
|
---|
591 | AssertRCReturn(rc, rc);
|
---|
592 | rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.mwait.uMonitorECX);
|
---|
593 | AssertRCReturn(rc, rc);
|
---|
594 | rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.mwait.uMonitorEDX);
|
---|
595 | AssertRCReturn(rc, rc);
|
---|
596 | }
|
---|
597 |
|
---|
598 | Assert(!pVCpu->em.s.pCliStatTree);
|
---|
599 | }
|
---|
600 | return VINF_SUCCESS;
|
---|
601 | }
|
---|
602 |
|
---|
603 |
|
---|
604 | /**
|
---|
605 | * Raise a fatal error.
|
---|
606 | *
|
---|
607 | * Safely terminate the VM with full state report and stuff. This function
|
---|
608 | * will naturally never return.
|
---|
609 | *
|
---|
610 | * @param pVCpu VMCPU handle.
|
---|
611 | * @param rc VBox status code.
|
---|
612 | */
|
---|
613 | VMMR3DECL(void) EMR3FatalError(PVMCPU pVCpu, int rc)
|
---|
614 | {
|
---|
615 | pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
|
---|
616 | longjmp(pVCpu->em.s.u.FatalLongJump, rc);
|
---|
617 | AssertReleaseMsgFailed(("longjmp returned!\n"));
|
---|
618 | }
|
---|
619 |
|
---|
620 |
|
---|
621 | /**
|
---|
622 | * Gets the EM state name.
|
---|
623 | *
|
---|
624 | * @returns pointer to read only state name,
|
---|
625 | * @param enmState The state.
|
---|
626 | */
|
---|
627 | static const char *emR3GetStateName(EMSTATE enmState)
|
---|
628 | {
|
---|
629 | switch (enmState)
|
---|
630 | {
|
---|
631 | case EMSTATE_NONE: return "EMSTATE_NONE";
|
---|
632 | case EMSTATE_RAW: return "EMSTATE_RAW";
|
---|
633 | case EMSTATE_HWACC: return "EMSTATE_HWACC";
|
---|
634 | case EMSTATE_REM: return "EMSTATE_REM";
|
---|
635 | case EMSTATE_PARAV: return "EMSTATE_PARAV";
|
---|
636 | case EMSTATE_HALTED: return "EMSTATE_HALTED";
|
---|
637 | case EMSTATE_WAIT_SIPI: return "EMSTATE_WAIT_SIPI";
|
---|
638 | case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
|
---|
639 | case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
|
---|
640 | case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
|
---|
641 | case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
|
---|
642 | case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
|
---|
643 | case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
|
---|
644 | default: return "Unknown!";
|
---|
645 | }
|
---|
646 | }
|
---|
647 |
|
---|
648 |
|
---|
649 | /**
|
---|
650 | * Debug loop.
|
---|
651 | *
|
---|
652 | * @returns VBox status code for EM.
|
---|
653 | * @param pVM VM handle.
|
---|
654 | * @param pVCpu VMCPU handle.
|
---|
655 | * @param rc Current EM VBox status code..
|
---|
656 | */
|
---|
657 | static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc)
|
---|
658 | {
|
---|
659 | for (;;)
|
---|
660 | {
|
---|
661 | Log(("emR3Debug: rc=%Rrc\n", rc));
|
---|
662 | const int rcLast = rc;
|
---|
663 |
|
---|
664 | /*
|
---|
665 | * Debug related RC.
|
---|
666 | */
|
---|
667 | switch (rc)
|
---|
668 | {
|
---|
669 | /*
|
---|
670 | * Single step an instruction.
|
---|
671 | */
|
---|
672 | case VINF_EM_DBG_STEP:
|
---|
673 | if ( pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
|
---|
674 | || pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
|
---|
675 | || pVCpu->em.s.fForceRAW /* paranoia */)
|
---|
676 | rc = emR3RawStep(pVM, pVCpu);
|
---|
677 | else
|
---|
678 | {
|
---|
679 | Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
|
---|
680 | rc = emR3RemStep(pVM, pVCpu);
|
---|
681 | }
|
---|
682 | break;
|
---|
683 |
|
---|
684 | /*
|
---|
685 | * Simple events: stepped, breakpoint, stop/assertion.
|
---|
686 | */
|
---|
687 | case VINF_EM_DBG_STEPPED:
|
---|
688 | rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
|
---|
689 | break;
|
---|
690 |
|
---|
691 | case VINF_EM_DBG_BREAKPOINT:
|
---|
692 | rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
|
---|
693 | break;
|
---|
694 |
|
---|
695 | case VINF_EM_DBG_STOP:
|
---|
696 | rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
|
---|
697 | break;
|
---|
698 |
|
---|
699 | case VINF_EM_DBG_HYPER_STEPPED:
|
---|
700 | rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
|
---|
701 | break;
|
---|
702 |
|
---|
703 | case VINF_EM_DBG_HYPER_BREAKPOINT:
|
---|
704 | rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
|
---|
705 | break;
|
---|
706 |
|
---|
707 | case VINF_EM_DBG_HYPER_ASSERTION:
|
---|
708 | RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
|
---|
709 | rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
|
---|
710 | break;
|
---|
711 |
|
---|
712 | /*
|
---|
713 | * Guru meditation.
|
---|
714 | */
|
---|
715 | case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
|
---|
716 | rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
|
---|
717 | break;
|
---|
718 | case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
|
---|
719 | rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
|
---|
720 | break;
|
---|
721 |
|
---|
722 | default: /** @todo don't use default for guru, but make special errors code! */
|
---|
723 | rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
|
---|
724 | break;
|
---|
725 | }
|
---|
726 |
|
---|
727 | /*
|
---|
728 | * Process the result.
|
---|
729 | */
|
---|
730 | do
|
---|
731 | {
|
---|
732 | switch (rc)
|
---|
733 | {
|
---|
734 | /*
|
---|
735 | * Continue the debugging loop.
|
---|
736 | */
|
---|
737 | case VINF_EM_DBG_STEP:
|
---|
738 | case VINF_EM_DBG_STOP:
|
---|
739 | case VINF_EM_DBG_STEPPED:
|
---|
740 | case VINF_EM_DBG_BREAKPOINT:
|
---|
741 | case VINF_EM_DBG_HYPER_STEPPED:
|
---|
742 | case VINF_EM_DBG_HYPER_BREAKPOINT:
|
---|
743 | case VINF_EM_DBG_HYPER_ASSERTION:
|
---|
744 | break;
|
---|
745 |
|
---|
746 | /*
|
---|
747 | * Resuming execution (in some form) has to be done here if we got
|
---|
748 | * a hypervisor debug event.
|
---|
749 | */
|
---|
750 | case VINF_SUCCESS:
|
---|
751 | case VINF_EM_RESUME:
|
---|
752 | case VINF_EM_SUSPEND:
|
---|
753 | case VINF_EM_RESCHEDULE:
|
---|
754 | case VINF_EM_RESCHEDULE_RAW:
|
---|
755 | case VINF_EM_RESCHEDULE_REM:
|
---|
756 | case VINF_EM_HALT:
|
---|
757 | if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
|
---|
758 | {
|
---|
759 | rc = emR3RawResumeHyper(pVM, pVCpu);
|
---|
760 | if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
|
---|
761 | continue;
|
---|
762 | }
|
---|
763 | if (rc == VINF_SUCCESS)
|
---|
764 | rc = VINF_EM_RESCHEDULE;
|
---|
765 | return rc;
|
---|
766 |
|
---|
767 | /*
|
---|
768 | * The debugger isn't attached.
|
---|
769 | * We'll simply turn the thing off since that's the easiest thing to do.
|
---|
770 | */
|
---|
771 | case VERR_DBGF_NOT_ATTACHED:
|
---|
772 | switch (rcLast)
|
---|
773 | {
|
---|
774 | case VINF_EM_DBG_HYPER_STEPPED:
|
---|
775 | case VINF_EM_DBG_HYPER_BREAKPOINT:
|
---|
776 | case VINF_EM_DBG_HYPER_ASSERTION:
|
---|
777 | case VERR_TRPM_PANIC:
|
---|
778 | case VERR_TRPM_DONT_PANIC:
|
---|
779 | case VERR_VMM_RING0_ASSERTION:
|
---|
780 | case VERR_VMM_HYPER_CR3_MISMATCH:
|
---|
781 | case VERR_VMM_RING3_CALL_DISABLED:
|
---|
782 | return rcLast;
|
---|
783 | }
|
---|
784 | return VINF_EM_OFF;
|
---|
785 |
|
---|
786 | /*
|
---|
787 | * Status codes terminating the VM in one or another sense.
|
---|
788 | */
|
---|
789 | case VINF_EM_TERMINATE:
|
---|
790 | case VINF_EM_OFF:
|
---|
791 | case VINF_EM_RESET:
|
---|
792 | case VINF_EM_NO_MEMORY:
|
---|
793 | case VINF_EM_RAW_STALE_SELECTOR:
|
---|
794 | case VINF_EM_RAW_IRET_TRAP:
|
---|
795 | case VERR_TRPM_PANIC:
|
---|
796 | case VERR_TRPM_DONT_PANIC:
|
---|
797 | case VERR_VMM_RING0_ASSERTION:
|
---|
798 | case VERR_VMM_HYPER_CR3_MISMATCH:
|
---|
799 | case VERR_VMM_RING3_CALL_DISABLED:
|
---|
800 | case VERR_INTERNAL_ERROR:
|
---|
801 | case VERR_INTERNAL_ERROR_2:
|
---|
802 | case VERR_INTERNAL_ERROR_3:
|
---|
803 | case VERR_INTERNAL_ERROR_4:
|
---|
804 | case VERR_INTERNAL_ERROR_5:
|
---|
805 | case VERR_IPE_UNEXPECTED_STATUS:
|
---|
806 | case VERR_IPE_UNEXPECTED_INFO_STATUS:
|
---|
807 | case VERR_IPE_UNEXPECTED_ERROR_STATUS:
|
---|
808 | return rc;
|
---|
809 |
|
---|
810 | /*
|
---|
811 | * The rest is unexpected, and will keep us here.
|
---|
812 | */
|
---|
813 | default:
|
---|
814 | AssertMsgFailed(("Unxpected rc %Rrc!\n", rc));
|
---|
815 | break;
|
---|
816 | }
|
---|
817 | } while (false);
|
---|
818 | } /* debug for ever */
|
---|
819 | }
|
---|
820 |
|
---|
821 | /**
|
---|
822 | * Steps recompiled code.
|
---|
823 | *
|
---|
824 | * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
|
---|
825 | * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
|
---|
826 | *
|
---|
827 | * @param pVM VM handle.
|
---|
828 | * @param pVCpu VMCPU handle.
|
---|
829 | */
|
---|
830 | static int emR3RemStep(PVM pVM, PVMCPU pVCpu)
|
---|
831 | {
|
---|
832 | LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
|
---|
833 |
|
---|
834 | EMRemLock(pVM);
|
---|
835 |
|
---|
836 | /*
|
---|
837 | * Switch to REM, step instruction, switch back.
|
---|
838 | */
|
---|
839 | int rc = REMR3State(pVM, pVCpu);
|
---|
840 | if (RT_SUCCESS(rc))
|
---|
841 | {
|
---|
842 | rc = REMR3Step(pVM, pVCpu);
|
---|
843 | REMR3StateBack(pVM, pVCpu);
|
---|
844 | }
|
---|
845 | EMRemUnlock(pVM);
|
---|
846 |
|
---|
847 | LogFlow(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
|
---|
848 | return rc;
|
---|
849 | }
|
---|
850 |
|
---|
851 |
|
---|
852 | /**
|
---|
853 | * emR3RemExecute helper that syncs the state back from REM and leave the REM
|
---|
854 | * critical section.
|
---|
855 | *
|
---|
856 | * @returns false - new fInREMState value.
|
---|
857 | * @param pVM The VM handle.
|
---|
858 | * @param pVCpu The virtual CPU handle.
|
---|
859 | */
|
---|
860 | DECLINLINE(bool) emR3RemExecuteSyncBack(PVM pVM, PVMCPU pVCpu)
|
---|
861 | {
|
---|
862 | STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, a);
|
---|
863 | REMR3StateBack(pVM, pVCpu);
|
---|
864 | STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, a);
|
---|
865 |
|
---|
866 | EMRemUnlock(pVM);
|
---|
867 | return false;
|
---|
868 | }
|
---|
869 |
|
---|
870 |
|
---|
871 | /**
|
---|
872 | * Executes recompiled code.
|
---|
873 | *
|
---|
874 | * This function contains the recompiler version of the inner
|
---|
875 | * execution loop (the outer loop being in EMR3ExecuteVM()).
|
---|
876 | *
|
---|
877 | * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
|
---|
878 | * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
|
---|
879 | *
|
---|
880 | * @param pVM VM handle.
|
---|
881 | * @param pVCpu VMCPU handle.
|
---|
882 | * @param pfFFDone Where to store an indicator telling wheter or not
|
---|
883 | * FFs were done before returning.
|
---|
884 | *
|
---|
885 | */
|
---|
886 | static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
|
---|
887 | {
|
---|
888 | #ifdef LOG_ENABLED
|
---|
889 | PCPUMCTX pCtx = pVCpu->em.s.pCtx;
|
---|
890 | uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
|
---|
891 |
|
---|
892 | if (pCtx->eflags.Bits.u1VM)
|
---|
893 | Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
|
---|
894 | else
|
---|
895 | Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0));
|
---|
896 | #endif
|
---|
897 | STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatREMTotal, a);
|
---|
898 |
|
---|
899 | #if defined(VBOX_STRICT) && defined(DEBUG_bird)
|
---|
900 | AssertMsg( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
|
---|
901 | || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVCpu)), /** @todo #1419 - get flat address. */
|
---|
902 | ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
|
---|
903 | #endif
|
---|
904 |
|
---|
905 | /*
|
---|
906 | * Spin till we get a forced action which returns anything but VINF_SUCCESS
|
---|
907 | * or the REM suggests raw-mode execution.
|
---|
908 | */
|
---|
909 | *pfFFDone = false;
|
---|
910 | bool fInREMState = false;
|
---|
911 | int rc = VINF_SUCCESS;
|
---|
912 | for (;;)
|
---|
913 | {
|
---|
914 | /*
|
---|
915 | * Lock REM and update the state if not already in sync.
|
---|
916 | *
|
---|
917 | * Note! Big lock, but you are not supposed to own any lock when
|
---|
918 | * coming in here.
|
---|
919 | */
|
---|
920 | if (!fInREMState)
|
---|
921 | {
|
---|
922 | EMRemLock(pVM);
|
---|
923 | STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, b);
|
---|
924 |
|
---|
925 | /* Flush the recompiler translation blocks if the VCPU has changed,
|
---|
926 | also force a full CPU state resync. */
|
---|
927 | if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
|
---|
928 | {
|
---|
929 | REMFlushTBs(pVM);
|
---|
930 | CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
|
---|
931 | }
|
---|
932 | pVM->em.s.idLastRemCpu = pVCpu->idCpu;
|
---|
933 |
|
---|
934 | rc = REMR3State(pVM, pVCpu);
|
---|
935 |
|
---|
936 | STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, b);
|
---|
937 | if (RT_FAILURE(rc))
|
---|
938 | break;
|
---|
939 | fInREMState = true;
|
---|
940 |
|
---|
941 | /*
|
---|
942 | * We might have missed the raising of VMREQ, TIMER and some other
|
---|
943 | * imporant FFs while we were busy switching the state. So, check again.
|
---|
944 | */
|
---|
945 | if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_TERMINATE | VM_FF_RESET)
|
---|
946 | || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER | VMCPU_FF_REQUEST))
|
---|
947 | {
|
---|
948 | LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fGlobalForcedActions));
|
---|
949 | goto l_REMDoForcedActions;
|
---|
950 | }
|
---|
951 | }
|
---|
952 |
|
---|
953 |
|
---|
954 | /*
|
---|
955 | * Execute REM.
|
---|
956 | */
|
---|
957 | STAM_PROFILE_START(&pVCpu->em.s.StatREMExec, c);
|
---|
958 | rc = REMR3Run(pVM, pVCpu);
|
---|
959 | STAM_PROFILE_STOP(&pVCpu->em.s.StatREMExec, c);
|
---|
960 |
|
---|
961 |
|
---|
962 | /*
|
---|
963 | * Deal with high priority post execution FFs before doing anything
|
---|
964 | * else. Sync back the state and leave the lock to be on the safe side.
|
---|
965 | */
|
---|
966 | if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
|
---|
967 | || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
|
---|
968 | {
|
---|
969 | fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
|
---|
970 | rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
|
---|
971 | }
|
---|
972 |
|
---|
973 | /*
|
---|
974 | * Process the returned status code.
|
---|
975 | */
|
---|
976 | if (rc != VINF_SUCCESS)
|
---|
977 | {
|
---|
978 | if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
|
---|
979 | break;
|
---|
980 | if (rc != VINF_REM_INTERRUPED_FF)
|
---|
981 | {
|
---|
982 | /*
|
---|
983 | * Anything which is not known to us means an internal error
|
---|
984 | * and the termination of the VM!
|
---|
985 | */
|
---|
986 | AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
|
---|
987 | break;
|
---|
988 | }
|
---|
989 | }
|
---|
990 |
|
---|
991 |
|
---|
992 | /*
|
---|
993 | * Check and execute forced actions.
|
---|
994 | *
|
---|
995 | * Sync back the VM state and leave the lock before calling any of
|
---|
996 | * these, you never know what's going to happen here.
|
---|
997 | */
|
---|
998 | #ifdef VBOX_HIGH_RES_TIMERS_HACK
|
---|
999 | TMTimerPollVoid(pVM, pVCpu);
|
---|
1000 | #endif
|
---|
1001 | AssertCompile((VMCPU_FF_ALL_BUT_RAW_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE)) & VMCPU_FF_TIMER);
|
---|
1002 | if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK)
|
---|
1003 | || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_BUT_RAW_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE)))
|
---|
1004 | {
|
---|
1005 | l_REMDoForcedActions:
|
---|
1006 | if (fInREMState)
|
---|
1007 | fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
|
---|
1008 | STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatREMTotal, a);
|
---|
1009 | rc = emR3ForcedActions(pVM, pVCpu, rc);
|
---|
1010 | STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatREMTotal, a);
|
---|
1011 | if ( rc != VINF_SUCCESS
|
---|
1012 | && rc != VINF_EM_RESCHEDULE_REM)
|
---|
1013 | {
|
---|
1014 | *pfFFDone = true;
|
---|
1015 | break;
|
---|
1016 | }
|
---|
1017 | }
|
---|
1018 |
|
---|
1019 | } /* The Inner Loop, recompiled execution mode version. */
|
---|
1020 |
|
---|
1021 |
|
---|
1022 | /*
|
---|
1023 | * Returning. Sync back the VM state if required.
|
---|
1024 | */
|
---|
1025 | if (fInREMState)
|
---|
1026 | fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
|
---|
1027 |
|
---|
1028 | STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatREMTotal, a);
|
---|
1029 | return rc;
|
---|
1030 | }
|
---|
1031 |
|
---|
1032 |
|
---|
1033 | #ifdef DEBUG
|
---|
1034 |
|
---|
1035 | int emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
|
---|
1036 | {
|
---|
1037 | EMSTATE enmOldState = pVCpu->em.s.enmState;
|
---|
1038 |
|
---|
1039 | pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
|
---|
1040 |
|
---|
1041 | Log(("Single step BEGIN:\n"));
|
---|
1042 | for (uint32_t i = 0; i < cIterations; i++)
|
---|
1043 | {
|
---|
1044 | DBGFR3PrgStep(pVCpu);
|
---|
1045 | DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
|
---|
1046 | emR3RemStep(pVM, pVCpu);
|
---|
1047 | if (emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx) != EMSTATE_REM)
|
---|
1048 | break;
|
---|
1049 | }
|
---|
1050 | Log(("Single step END:\n"));
|
---|
1051 | CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
|
---|
1052 | pVCpu->em.s.enmState = enmOldState;
|
---|
1053 | return VINF_EM_RESCHEDULE;
|
---|
1054 | }
|
---|
1055 |
|
---|
1056 | #endif /* DEBUG */
|
---|
1057 |
|
---|
1058 |
|
---|
1059 | /**
|
---|
1060 | * Decides whether to execute RAW, HWACC or REM.
|
---|
1061 | *
|
---|
1062 | * @returns new EM state
|
---|
1063 | * @param pVM The VM.
|
---|
1064 | * @param pVCpu The VMCPU handle.
|
---|
1065 | * @param pCtx The CPU context.
|
---|
1066 | */
|
---|
1067 | EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
|
---|
1068 | {
|
---|
1069 | /*
|
---|
1070 | * When forcing raw-mode execution, things are simple.
|
---|
1071 | */
|
---|
1072 | if (pVCpu->em.s.fForceRAW)
|
---|
1073 | return EMSTATE_RAW;
|
---|
1074 |
|
---|
1075 | /*
|
---|
1076 | * We stay in the wait for SIPI state unless explicitly told otherwise.
|
---|
1077 | */
|
---|
1078 | if (pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI)
|
---|
1079 | return EMSTATE_WAIT_SIPI;
|
---|
1080 |
|
---|
1081 | /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
|
---|
1082 | /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
|
---|
1083 | /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
|
---|
1084 |
|
---|
1085 | X86EFLAGS EFlags = pCtx->eflags;
|
---|
1086 | if (HWACCMIsEnabled(pVM))
|
---|
1087 | {
|
---|
1088 | /* Hardware accelerated raw-mode:
|
---|
1089 | *
|
---|
1090 | * Typically only 32-bits protected mode, with paging enabled, code is allowed here.
|
---|
1091 | */
|
---|
1092 | if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
|
---|
1093 | return EMSTATE_HWACC;
|
---|
1094 |
|
---|
1095 | /* Note: Raw mode and hw accelerated mode are incompatible. The latter turns
|
---|
1096 | * off monitoring features essential for raw mode! */
|
---|
1097 | return EMSTATE_REM;
|
---|
1098 | }
|
---|
1099 |
|
---|
1100 | /*
|
---|
1101 | * Standard raw-mode:
|
---|
1102 | *
|
---|
1103 | * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
|
---|
1104 | * or 32 bits protected mode ring 0 code
|
---|
1105 | *
|
---|
1106 | * The tests are ordered by the likelyhood of being true during normal execution.
|
---|
1107 | */
|
---|
1108 | if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
|
---|
1109 | {
|
---|
1110 | Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
|
---|
1111 | return EMSTATE_REM;
|
---|
1112 | }
|
---|
1113 |
|
---|
1114 | #ifndef VBOX_RAW_V86
|
---|
1115 | if (EFlags.u32 & X86_EFL_VM) {
|
---|
1116 | Log2(("raw mode refused: VM_MASK\n"));
|
---|
1117 | return EMSTATE_REM;
|
---|
1118 | }
|
---|
1119 | #endif
|
---|
1120 |
|
---|
1121 | /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
|
---|
1122 | uint32_t u32CR0 = pCtx->cr0;
|
---|
1123 | if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
|
---|
1124 | {
|
---|
1125 | //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
|
---|
1126 | return EMSTATE_REM;
|
---|
1127 | }
|
---|
1128 |
|
---|
1129 | if (pCtx->cr4 & X86_CR4_PAE)
|
---|
1130 | {
|
---|
1131 | uint32_t u32Dummy, u32Features;
|
---|
1132 |
|
---|
1133 | CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
|
---|
1134 | if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
|
---|
1135 | return EMSTATE_REM;
|
---|
1136 | }
|
---|
1137 |
|
---|
1138 | unsigned uSS = pCtx->ss;
|
---|
1139 | if ( pCtx->eflags.Bits.u1VM
|
---|
1140 | || (uSS & X86_SEL_RPL) == 3)
|
---|
1141 | {
|
---|
1142 | if (!EMIsRawRing3Enabled(pVM))
|
---|
1143 | return EMSTATE_REM;
|
---|
1144 |
|
---|
1145 | if (!(EFlags.u32 & X86_EFL_IF))
|
---|
1146 | {
|
---|
1147 | Log2(("raw mode refused: IF (RawR3)\n"));
|
---|
1148 | return EMSTATE_REM;
|
---|
1149 | }
|
---|
1150 |
|
---|
1151 | if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
|
---|
1152 | {
|
---|
1153 | Log2(("raw mode refused: CR0.WP + RawR0\n"));
|
---|
1154 | return EMSTATE_REM;
|
---|
1155 | }
|
---|
1156 | }
|
---|
1157 | else
|
---|
1158 | {
|
---|
1159 | if (!EMIsRawRing0Enabled(pVM))
|
---|
1160 | return EMSTATE_REM;
|
---|
1161 |
|
---|
1162 | /* Only ring 0 supervisor code. */
|
---|
1163 | if ((uSS & X86_SEL_RPL) != 0)
|
---|
1164 | {
|
---|
1165 | Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
|
---|
1166 | return EMSTATE_REM;
|
---|
1167 | }
|
---|
1168 |
|
---|
1169 | // Let's start with pure 32 bits ring 0 code first
|
---|
1170 | /** @todo What's pure 32-bit mode? flat? */
|
---|
1171 | if ( !(pCtx->ssHid.Attr.n.u1DefBig)
|
---|
1172 | || !(pCtx->csHid.Attr.n.u1DefBig))
|
---|
1173 | {
|
---|
1174 | Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
|
---|
1175 | return EMSTATE_REM;
|
---|
1176 | }
|
---|
1177 |
|
---|
1178 | /* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
|
---|
1179 | if (!(u32CR0 & X86_CR0_WP))
|
---|
1180 | {
|
---|
1181 | Log2(("raw r0 mode refused: CR0.WP=0!\n"));
|
---|
1182 | return EMSTATE_REM;
|
---|
1183 | }
|
---|
1184 |
|
---|
1185 | if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
|
---|
1186 | {
|
---|
1187 | Log2(("raw r0 mode forced: patch code\n"));
|
---|
1188 | return EMSTATE_RAW;
|
---|
1189 | }
|
---|
1190 |
|
---|
1191 | #if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
|
---|
1192 | if (!(EFlags.u32 & X86_EFL_IF))
|
---|
1193 | {
|
---|
1194 | ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
|
---|
1195 | //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
|
---|
1196 | return EMSTATE_REM;
|
---|
1197 | }
|
---|
1198 | #endif
|
---|
1199 |
|
---|
1200 | /** @todo still necessary??? */
|
---|
1201 | if (EFlags.Bits.u2IOPL != 0)
|
---|
1202 | {
|
---|
1203 | Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
|
---|
1204 | return EMSTATE_REM;
|
---|
1205 | }
|
---|
1206 | }
|
---|
1207 |
|
---|
1208 | Assert(PGMPhysIsA20Enabled(pVCpu));
|
---|
1209 | return EMSTATE_RAW;
|
---|
1210 | }
|
---|
1211 |
|
---|
1212 |
|
---|
1213 | /**
|
---|
1214 | * Executes all high priority post execution force actions.
|
---|
1215 | *
|
---|
1216 | * @returns rc or a fatal status code.
|
---|
1217 | *
|
---|
1218 | * @param pVM VM handle.
|
---|
1219 | * @param pVCpu VMCPU handle.
|
---|
1220 | * @param rc The current rc.
|
---|
1221 | */
|
---|
1222 | int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
|
---|
1223 | {
|
---|
1224 | if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PDM_CRITSECT))
|
---|
1225 | PDMCritSectFF(pVCpu);
|
---|
1226 |
|
---|
1227 | if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION))
|
---|
1228 | CSAMR3DoPendingAction(pVM, pVCpu);
|
---|
1229 |
|
---|
1230 | if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
|
---|
1231 | {
|
---|
1232 | if ( rc > VINF_EM_NO_MEMORY
|
---|
1233 | && rc <= VINF_EM_LAST)
|
---|
1234 | rc = VINF_EM_NO_MEMORY;
|
---|
1235 | }
|
---|
1236 |
|
---|
1237 | return rc;
|
---|
1238 | }
|
---|
1239 |
|
---|
1240 |
|
---|
1241 | /**
|
---|
1242 | * Executes all pending forced actions.
|
---|
1243 | *
|
---|
1244 | * Forced actions can cause execution delays and execution
|
---|
1245 | * rescheduling. The first we deal with using action priority, so
|
---|
1246 | * that for instance pending timers aren't scheduled and ran until
|
---|
1247 | * right before execution. The rescheduling we deal with using
|
---|
1248 | * return codes. The same goes for VM termination, only in that case
|
---|
1249 | * we exit everything.
|
---|
1250 | *
|
---|
1251 | * @returns VBox status code of equal or greater importance/severity than rc.
|
---|
1252 | * The most important ones are: VINF_EM_RESCHEDULE,
|
---|
1253 | * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
|
---|
1254 | *
|
---|
1255 | * @param pVM VM handle.
|
---|
1256 | * @param pVCpu VMCPU handle.
|
---|
1257 | * @param rc The current rc.
|
---|
1258 | *
|
---|
1259 | */
|
---|
1260 | int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
|
---|
1261 | {
|
---|
1262 | STAM_REL_PROFILE_START(&pVCpu->em.s.StatForcedActions, a);
|
---|
1263 | #ifdef VBOX_STRICT
|
---|
1264 | int rcIrq = VINF_SUCCESS;
|
---|
1265 | #endif
|
---|
1266 | int rc2;
|
---|
1267 | #define UPDATE_RC() \
|
---|
1268 | do { \
|
---|
1269 | AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
|
---|
1270 | if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
|
---|
1271 | break; \
|
---|
1272 | if (!rc || rc2 < rc) \
|
---|
1273 | rc = rc2; \
|
---|
1274 | } while (0)
|
---|
1275 |
|
---|
1276 | /*
|
---|
1277 | * Post execution chunk first.
|
---|
1278 | */
|
---|
1279 | if ( VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK)
|
---|
1280 | || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK))
|
---|
1281 | {
|
---|
1282 | /*
|
---|
1283 | * EMT Rendezvous (must be serviced before termination).
|
---|
1284 | */
|
---|
1285 | if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
|
---|
1286 | {
|
---|
1287 | rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
|
---|
1288 | UPDATE_RC();
|
---|
1289 | /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
|
---|
1290 | * stopped/reset before the next VM state change is made. We need a better
|
---|
1291 | * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
|
---|
1292 | * && rc >= VINF_EM_SUSPEND). */
|
---|
1293 | if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
|
---|
1294 | {
|
---|
1295 | Log2(("emR3ForcedActions: returns %Rrc\n", rc));
|
---|
1296 | STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
|
---|
1297 | return rc;
|
---|
1298 | }
|
---|
1299 | }
|
---|
1300 |
|
---|
1301 | /*
|
---|
1302 | * Termination request.
|
---|
1303 | */
|
---|
1304 | if (VM_FF_ISPENDING(pVM, VM_FF_TERMINATE))
|
---|
1305 | {
|
---|
1306 | Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
|
---|
1307 | STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
|
---|
1308 | return VINF_EM_TERMINATE;
|
---|
1309 | }
|
---|
1310 |
|
---|
1311 | /*
|
---|
1312 | * Debugger Facility polling.
|
---|
1313 | */
|
---|
1314 | if (VM_FF_ISPENDING(pVM, VM_FF_DBGF))
|
---|
1315 | {
|
---|
1316 | rc2 = DBGFR3VMMForcedAction(pVM);
|
---|
1317 | UPDATE_RC();
|
---|
1318 | }
|
---|
1319 |
|
---|
1320 | /*
|
---|
1321 | * Postponed reset request.
|
---|
1322 | */
|
---|
1323 | if (VM_FF_TESTANDCLEAR(pVM, VM_FF_RESET))
|
---|
1324 | {
|
---|
1325 | rc2 = VMR3Reset(pVM);
|
---|
1326 | UPDATE_RC();
|
---|
1327 | }
|
---|
1328 |
|
---|
1329 | /*
|
---|
1330 | * CSAM page scanning.
|
---|
1331 | */
|
---|
1332 | if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
|
---|
1333 | && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE))
|
---|
1334 | {
|
---|
1335 | PCPUMCTX pCtx = pVCpu->em.s.pCtx;
|
---|
1336 |
|
---|
1337 | /** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
|
---|
1338 | Log(("Forced action VMCPU_FF_CSAM_SCAN_PAGE\n"));
|
---|
1339 |
|
---|
1340 | CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
|
---|
1341 | VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE);
|
---|
1342 | }
|
---|
1343 |
|
---|
1344 | /*
|
---|
1345 | * Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
|
---|
1346 | */
|
---|
1347 | if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
|
---|
1348 | {
|
---|
1349 | rc2 = PGMR3PhysAllocateHandyPages(pVM);
|
---|
1350 | UPDATE_RC();
|
---|
1351 | if (rc == VINF_EM_NO_MEMORY)
|
---|
1352 | return rc;
|
---|
1353 | }
|
---|
1354 |
|
---|
1355 | /* check that we got them all */
|
---|
1356 | AssertCompile(VM_FF_NORMAL_PRIORITY_POST_MASK == (VM_FF_TERMINATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
|
---|
1357 | AssertCompile(VMCPU_FF_NORMAL_PRIORITY_POST_MASK == VMCPU_FF_CSAM_SCAN_PAGE);
|
---|
1358 | }
|
---|
1359 |
|
---|
1360 | /*
|
---|
1361 | * Normal priority then.
|
---|
1362 | * (Executed in no particular order.)
|
---|
1363 | */
|
---|
1364 | if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
|
---|
1365 | {
|
---|
1366 | /*
|
---|
1367 | * PDM Queues are pending.
|
---|
1368 | */
|
---|
1369 | if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
|
---|
1370 | PDMR3QueueFlushAll(pVM);
|
---|
1371 |
|
---|
1372 | /*
|
---|
1373 | * PDM DMA transfers are pending.
|
---|
1374 | */
|
---|
1375 | if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
|
---|
1376 | PDMR3DmaRun(pVM);
|
---|
1377 |
|
---|
1378 | /*
|
---|
1379 | * EMT Rendezvous (make sure they are handled before the requests).
|
---|
1380 | */
|
---|
1381 | if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
|
---|
1382 | {
|
---|
1383 | rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
|
---|
1384 | UPDATE_RC();
|
---|
1385 | /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
|
---|
1386 | * stopped/reset before the next VM state change is made. We need a better
|
---|
1387 | * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
|
---|
1388 | * && rc >= VINF_EM_SUSPEND). */
|
---|
1389 | if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
|
---|
1390 | {
|
---|
1391 | Log2(("emR3ForcedActions: returns %Rrc\n", rc));
|
---|
1392 | STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
|
---|
1393 | return rc;
|
---|
1394 | }
|
---|
1395 | }
|
---|
1396 |
|
---|
1397 | /*
|
---|
1398 | * Requests from other threads.
|
---|
1399 | */
|
---|
1400 | if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
|
---|
1401 | {
|
---|
1402 | rc2 = VMR3ReqProcessU(pVM->pUVM, VMCPUID_ANY);
|
---|
1403 | if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE) /** @todo this shouldn't be necessary */
|
---|
1404 | {
|
---|
1405 | Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
|
---|
1406 | STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
|
---|
1407 | return rc2;
|
---|
1408 | }
|
---|
1409 | UPDATE_RC();
|
---|
1410 | /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
|
---|
1411 | * stopped/reset before the next VM state change is made. We need a better
|
---|
1412 | * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
|
---|
1413 | * && rc >= VINF_EM_SUSPEND). */
|
---|
1414 | if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
|
---|
1415 | {
|
---|
1416 | Log2(("emR3ForcedActions: returns %Rrc\n", rc));
|
---|
1417 | STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
|
---|
1418 | return rc;
|
---|
1419 | }
|
---|
1420 | }
|
---|
1421 |
|
---|
1422 | /* Replay the handler notification changes. */
|
---|
1423 | if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REM_HANDLER_NOTIFY, VM_FF_PGM_NO_MEMORY))
|
---|
1424 | {
|
---|
1425 | /* Try not to cause deadlocks. */
|
---|
1426 | if ( pVM->cCpus == 1
|
---|
1427 | || ( !PGMIsLockOwner(pVM)
|
---|
1428 | && !IOMIsLockOwner(pVM))
|
---|
1429 | )
|
---|
1430 | {
|
---|
1431 | EMRemLock(pVM);
|
---|
1432 | REMR3ReplayHandlerNotifications(pVM);
|
---|
1433 | EMRemUnlock(pVM);
|
---|
1434 | }
|
---|
1435 | }
|
---|
1436 |
|
---|
1437 | /* check that we got them all */
|
---|
1438 | AssertCompile(VM_FF_NORMAL_PRIORITY_MASK == (VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_REM_HANDLER_NOTIFY | VM_FF_EMT_RENDEZVOUS));
|
---|
1439 | }
|
---|
1440 |
|
---|
1441 | /*
|
---|
1442 | * Normal priority then. (per-VCPU)
|
---|
1443 | * (Executed in no particular order.)
|
---|
1444 | */
|
---|
1445 | if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
|
---|
1446 | && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK))
|
---|
1447 | {
|
---|
1448 | /*
|
---|
1449 | * Requests from other threads.
|
---|
1450 | */
|
---|
1451 | if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
|
---|
1452 | {
|
---|
1453 | rc2 = VMR3ReqProcessU(pVM->pUVM, pVCpu->idCpu);
|
---|
1454 | if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE || rc2 == VINF_EM_RESET)
|
---|
1455 | {
|
---|
1456 | Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
|
---|
1457 | STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
|
---|
1458 | return rc2;
|
---|
1459 | }
|
---|
1460 | UPDATE_RC();
|
---|
1461 | /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
|
---|
1462 | * stopped/reset before the next VM state change is made. We need a better
|
---|
1463 | * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
|
---|
1464 | * && rc >= VINF_EM_SUSPEND). */
|
---|
1465 | if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
|
---|
1466 | {
|
---|
1467 | Log2(("emR3ForcedActions: returns %Rrc\n", rc));
|
---|
1468 | STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
|
---|
1469 | return rc;
|
---|
1470 | }
|
---|
1471 | }
|
---|
1472 |
|
---|
1473 | /* check that we got them all */
|
---|
1474 | Assert(!(VMCPU_FF_NORMAL_PRIORITY_MASK & ~(VMCPU_FF_REQUEST)));
|
---|
1475 | }
|
---|
1476 |
|
---|
1477 | /*
|
---|
1478 | * High priority pre execution chunk last.
|
---|
1479 | * (Executed in ascending priority order.)
|
---|
1480 | */
|
---|
1481 | if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK)
|
---|
1482 | || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK))
|
---|
1483 | {
|
---|
1484 | /*
|
---|
1485 | * Timers before interrupts.
|
---|
1486 | */
|
---|
1487 | if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER)
|
---|
1488 | && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
|
---|
1489 | TMR3TimerQueuesDo(pVM);
|
---|
1490 |
|
---|
1491 | /*
|
---|
1492 | * The instruction following an emulated STI should *always* be executed!
|
---|
1493 | */
|
---|
1494 | if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
|
---|
1495 | && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
|
---|
1496 | {
|
---|
1497 | Log(("VM_FF_EMULATED_STI at %RGv successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu), EMGetInhibitInterruptsPC(pVCpu)));
|
---|
1498 | if (CPUMGetGuestEIP(pVCpu) != EMGetInhibitInterruptsPC(pVCpu))
|
---|
1499 | {
|
---|
1500 | /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
|
---|
1501 | * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
|
---|
1502 | * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
|
---|
1503 | * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
|
---|
1504 | */
|
---|
1505 | VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
|
---|
1506 | }
|
---|
1507 | if (HWACCMR3IsActive(pVCpu))
|
---|
1508 | rc2 = VINF_EM_RESCHEDULE_HWACC;
|
---|
1509 | else
|
---|
1510 | rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
|
---|
1511 |
|
---|
1512 | UPDATE_RC();
|
---|
1513 | }
|
---|
1514 |
|
---|
1515 | /*
|
---|
1516 | * Interrupts.
|
---|
1517 | */
|
---|
1518 | if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
|
---|
1519 | && !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
|
---|
1520 | && (!rc || rc >= VINF_EM_RESCHEDULE_HWACC)
|
---|
1521 | && !TRPMHasTrap(pVCpu) /* an interrupt could already be scheduled for dispatching in the recompiler. */
|
---|
1522 | && PATMAreInterruptsEnabled(pVM)
|
---|
1523 | && !HWACCMR3IsEventPending(pVCpu))
|
---|
1524 | {
|
---|
1525 | Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
|
---|
1526 | if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
|
---|
1527 | {
|
---|
1528 | /* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
|
---|
1529 | /** @todo this really isn't nice, should properly handle this */
|
---|
1530 | rc2 = TRPMR3InjectEvent(pVM, pVCpu, TRPM_HARDWARE_INT);
|
---|
1531 | #ifdef VBOX_STRICT
|
---|
1532 | rcIrq = rc2;
|
---|
1533 | #endif
|
---|
1534 | UPDATE_RC();
|
---|
1535 | }
|
---|
1536 | /** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
|
---|
1537 | else if (REMR3QueryPendingInterrupt(pVM, pVCpu) != REM_NO_PENDING_IRQ)
|
---|
1538 | {
|
---|
1539 | rc2 = VINF_EM_RESCHEDULE_REM;
|
---|
1540 | UPDATE_RC();
|
---|
1541 | }
|
---|
1542 | }
|
---|
1543 |
|
---|
1544 | /*
|
---|
1545 | * Allocate handy pages.
|
---|
1546 | */
|
---|
1547 | if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
|
---|
1548 | {
|
---|
1549 | rc2 = PGMR3PhysAllocateHandyPages(pVM);
|
---|
1550 | UPDATE_RC();
|
---|
1551 | }
|
---|
1552 |
|
---|
1553 | /*
|
---|
1554 | * Debugger Facility request.
|
---|
1555 | */
|
---|
1556 | if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_DBGF, VM_FF_PGM_NO_MEMORY))
|
---|
1557 | {
|
---|
1558 | rc2 = DBGFR3VMMForcedAction(pVM);
|
---|
1559 | UPDATE_RC();
|
---|
1560 | }
|
---|
1561 |
|
---|
1562 | /*
|
---|
1563 | * EMT Rendezvous (must be serviced before termination).
|
---|
1564 | */
|
---|
1565 | if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
|
---|
1566 | {
|
---|
1567 | rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
|
---|
1568 | UPDATE_RC();
|
---|
1569 | /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
|
---|
1570 | * stopped/reset before the next VM state change is made. We need a better
|
---|
1571 | * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
|
---|
1572 | * && rc >= VINF_EM_SUSPEND). */
|
---|
1573 | if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
|
---|
1574 | {
|
---|
1575 | Log2(("emR3ForcedActions: returns %Rrc\n", rc));
|
---|
1576 | STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
|
---|
1577 | return rc;
|
---|
1578 | }
|
---|
1579 | }
|
---|
1580 |
|
---|
1581 | /*
|
---|
1582 | * Termination request.
|
---|
1583 | */
|
---|
1584 | if (VM_FF_ISPENDING(pVM, VM_FF_TERMINATE))
|
---|
1585 | {
|
---|
1586 | Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
|
---|
1587 | STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
|
---|
1588 | return VINF_EM_TERMINATE;
|
---|
1589 | }
|
---|
1590 |
|
---|
1591 | /*
|
---|
1592 | * Out of memory? Since most of our fellow high priority actions may cause us
|
---|
1593 | * to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
|
---|
1594 | * at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
|
---|
1595 | * than us since we can terminate without allocating more memory.
|
---|
1596 | */
|
---|
1597 | if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
|
---|
1598 | {
|
---|
1599 | rc2 = PGMR3PhysAllocateHandyPages(pVM);
|
---|
1600 | UPDATE_RC();
|
---|
1601 | if (rc == VINF_EM_NO_MEMORY)
|
---|
1602 | return rc;
|
---|
1603 | }
|
---|
1604 |
|
---|
1605 | /*
|
---|
1606 | * If the virtual sync clock is still stopped, make TM restart it.
|
---|
1607 | */
|
---|
1608 | if (VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
|
---|
1609 | TMR3VirtualSyncFF(pVM, pVCpu);
|
---|
1610 |
|
---|
1611 | #ifdef DEBUG
|
---|
1612 | /*
|
---|
1613 | * Debug, pause the VM.
|
---|
1614 | */
|
---|
1615 | if (VM_FF_ISPENDING(pVM, VM_FF_DEBUG_SUSPEND))
|
---|
1616 | {
|
---|
1617 | VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
|
---|
1618 | Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
|
---|
1619 | return VINF_EM_SUSPEND;
|
---|
1620 | }
|
---|
1621 | #endif
|
---|
1622 |
|
---|
1623 | /* check that we got them all */
|
---|
1624 | AssertCompile(VM_FF_HIGH_PRIORITY_PRE_MASK == (VM_FF_TM_VIRTUAL_SYNC | VM_FF_DBGF | VM_FF_TERMINATE | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
|
---|
1625 | AssertCompile(VMCPU_FF_HIGH_PRIORITY_PRE_MASK == (VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_INHIBIT_INTERRUPTS));
|
---|
1626 | }
|
---|
1627 |
|
---|
1628 | #undef UPDATE_RC
|
---|
1629 | Log2(("emR3ForcedActions: returns %Rrc\n", rc));
|
---|
1630 | STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
|
---|
1631 | Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
|
---|
1632 | return rc;
|
---|
1633 | }
|
---|
1634 |
|
---|
1635 |
|
---|
1636 | /**
|
---|
1637 | * Execute VM.
|
---|
1638 | *
|
---|
1639 | * This function is the main loop of the VM. The emulation thread
|
---|
1640 | * calls this function when the VM has been successfully constructed
|
---|
1641 | * and we're ready for executing the VM.
|
---|
1642 | *
|
---|
1643 | * Returning from this function means that the VM is turned off or
|
---|
1644 | * suspended (state already saved) and deconstruction in next in line.
|
---|
1645 | *
|
---|
1646 | * All interaction from other thread are done using forced actions
|
---|
1647 | * and signaling of the wait object.
|
---|
1648 | *
|
---|
1649 | * @returns VBox status code, informational status codes may indicate failure.
|
---|
1650 | * @param pVM The VM to operate on.
|
---|
1651 | * @param pVCpu The VMCPU to operate on.
|
---|
1652 | */
|
---|
1653 | VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
|
---|
1654 | {
|
---|
1655 | Log(("EMR3ExecuteVM: pVM=%p enmVMState=%d (%s) enmState=%d (%s) enmPrevState=%d (%s) fForceRAW=%RTbool\n",
|
---|
1656 | pVM,
|
---|
1657 | pVM->enmVMState, VMR3GetStateName(pVM->enmVMState),
|
---|
1658 | pVCpu->em.s.enmState, emR3GetStateName(pVCpu->em.s.enmState),
|
---|
1659 | pVCpu->em.s.enmPrevState, emR3GetStateName(pVCpu->em.s.enmPrevState),
|
---|
1660 | pVCpu->em.s.fForceRAW));
|
---|
1661 | VM_ASSERT_EMT(pVM);
|
---|
1662 | AssertMsg( pVCpu->em.s.enmState == EMSTATE_NONE
|
---|
1663 | || pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI
|
---|
1664 | || pVCpu->em.s.enmState == EMSTATE_SUSPENDED,
|
---|
1665 | ("%s\n", emR3GetStateName(pVCpu->em.s.enmState)));
|
---|
1666 |
|
---|
1667 | int rc = setjmp(pVCpu->em.s.u.FatalLongJump);
|
---|
1668 | if (rc == 0)
|
---|
1669 | {
|
---|
1670 | /*
|
---|
1671 | * Start the virtual time.
|
---|
1672 | */
|
---|
1673 | TMR3NotifyResume(pVM, pVCpu);
|
---|
1674 |
|
---|
1675 | /*
|
---|
1676 | * The Outer Main Loop.
|
---|
1677 | */
|
---|
1678 | bool fFFDone = false;
|
---|
1679 |
|
---|
1680 | /* Reschedule right away to start in the right state. */
|
---|
1681 | rc = VINF_SUCCESS;
|
---|
1682 |
|
---|
1683 | /* If resuming after a pause or a state load, restore the previous
|
---|
1684 | state or else we'll start executing code. Else, just reschedule. */
|
---|
1685 | if ( pVCpu->em.s.enmState == EMSTATE_SUSPENDED
|
---|
1686 | && ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
|
---|
1687 | || pVCpu->em.s.enmPrevState == EMSTATE_HALTED))
|
---|
1688 | pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
|
---|
1689 | else
|
---|
1690 | pVCpu->em.s.enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
|
---|
1691 |
|
---|
1692 | STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
|
---|
1693 | for (;;)
|
---|
1694 | {
|
---|
1695 | /*
|
---|
1696 | * Before we can schedule anything (we're here because
|
---|
1697 | * scheduling is required) we must service any pending
|
---|
1698 | * forced actions to avoid any pending action causing
|
---|
1699 | * immediate rescheduling upon entering an inner loop
|
---|
1700 | *
|
---|
1701 | * Do forced actions.
|
---|
1702 | */
|
---|
1703 | if ( !fFFDone
|
---|
1704 | && rc != VINF_EM_TERMINATE
|
---|
1705 | && rc != VINF_EM_OFF
|
---|
1706 | && ( VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK)
|
---|
1707 | || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_BUT_RAW_MASK)))
|
---|
1708 | {
|
---|
1709 | rc = emR3ForcedActions(pVM, pVCpu, rc);
|
---|
1710 | if ( ( rc == VINF_EM_RESCHEDULE_REM
|
---|
1711 | || rc == VINF_EM_RESCHEDULE_HWACC)
|
---|
1712 | && pVCpu->em.s.fForceRAW)
|
---|
1713 | rc = VINF_EM_RESCHEDULE_RAW;
|
---|
1714 | }
|
---|
1715 | else if (fFFDone)
|
---|
1716 | fFFDone = false;
|
---|
1717 |
|
---|
1718 | /*
|
---|
1719 | * Now what to do?
|
---|
1720 | */
|
---|
1721 | Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
|
---|
1722 | switch (rc)
|
---|
1723 | {
|
---|
1724 | /*
|
---|
1725 | * Keep doing what we're currently doing.
|
---|
1726 | */
|
---|
1727 | case VINF_SUCCESS:
|
---|
1728 | break;
|
---|
1729 |
|
---|
1730 | /*
|
---|
1731 | * Reschedule - to raw-mode execution.
|
---|
1732 | */
|
---|
1733 | case VINF_EM_RESCHEDULE_RAW:
|
---|
1734 | Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVCpu->em.s.enmState, EMSTATE_RAW));
|
---|
1735 | pVCpu->em.s.enmState = EMSTATE_RAW;
|
---|
1736 | break;
|
---|
1737 |
|
---|
1738 | /*
|
---|
1739 | * Reschedule - to hardware accelerated raw-mode execution.
|
---|
1740 | */
|
---|
1741 | case VINF_EM_RESCHEDULE_HWACC:
|
---|
1742 | Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVCpu->em.s.enmState, EMSTATE_HWACC));
|
---|
1743 | Assert(!pVCpu->em.s.fForceRAW);
|
---|
1744 | pVCpu->em.s.enmState = EMSTATE_HWACC;
|
---|
1745 | break;
|
---|
1746 |
|
---|
1747 | /*
|
---|
1748 | * Reschedule - to recompiled execution.
|
---|
1749 | */
|
---|
1750 | case VINF_EM_RESCHEDULE_REM:
|
---|
1751 | Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVCpu->em.s.enmState, EMSTATE_REM));
|
---|
1752 | pVCpu->em.s.enmState = EMSTATE_REM;
|
---|
1753 | break;
|
---|
1754 |
|
---|
1755 | /*
|
---|
1756 | * Resume.
|
---|
1757 | */
|
---|
1758 | case VINF_EM_RESUME:
|
---|
1759 | Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVCpu->em.s.enmState));
|
---|
1760 | /* Don't reschedule in the halted or wait for SIPI case. */
|
---|
1761 | if ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
|
---|
1762 | || pVCpu->em.s.enmPrevState == EMSTATE_HALTED)
|
---|
1763 | break;
|
---|
1764 | /* fall through and get scheduled. */
|
---|
1765 |
|
---|
1766 | /*
|
---|
1767 | * Reschedule.
|
---|
1768 | */
|
---|
1769 | case VINF_EM_RESCHEDULE:
|
---|
1770 | {
|
---|
1771 | EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
|
---|
1772 | Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, emR3GetStateName(enmState)));
|
---|
1773 | pVCpu->em.s.enmState = enmState;
|
---|
1774 | break;
|
---|
1775 | }
|
---|
1776 |
|
---|
1777 | /*
|
---|
1778 | * Halted.
|
---|
1779 | */
|
---|
1780 | case VINF_EM_HALT:
|
---|
1781 | Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_HALTED));
|
---|
1782 | pVCpu->em.s.enmState = EMSTATE_HALTED;
|
---|
1783 | break;
|
---|
1784 |
|
---|
1785 | /*
|
---|
1786 | * Switch to the wait for SIPI state (application processor only)
|
---|
1787 | */
|
---|
1788 | case VINF_EM_WAIT_SIPI:
|
---|
1789 | Assert(pVCpu->idCpu != 0);
|
---|
1790 | Log2(("EMR3ExecuteVM: VINF_EM_WAIT_SIPI: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_WAIT_SIPI));
|
---|
1791 | pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
|
---|
1792 | break;
|
---|
1793 |
|
---|
1794 |
|
---|
1795 | /*
|
---|
1796 | * Suspend.
|
---|
1797 | */
|
---|
1798 | case VINF_EM_SUSPEND:
|
---|
1799 | Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
|
---|
1800 | pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
|
---|
1801 | pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
|
---|
1802 | break;
|
---|
1803 |
|
---|
1804 | /*
|
---|
1805 | * Reset.
|
---|
1806 | * We might end up doing a double reset for now, we'll have to clean up the mess later.
|
---|
1807 | */
|
---|
1808 | case VINF_EM_RESET:
|
---|
1809 | {
|
---|
1810 | if (pVCpu->idCpu == 0)
|
---|
1811 | {
|
---|
1812 | EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
|
---|
1813 | Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, emR3GetStateName(enmState)));
|
---|
1814 | pVCpu->em.s.enmState = enmState;
|
---|
1815 | }
|
---|
1816 | else
|
---|
1817 | {
|
---|
1818 | /* All other VCPUs go into the wait for SIPI state. */
|
---|
1819 | pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
|
---|
1820 | }
|
---|
1821 | break;
|
---|
1822 | }
|
---|
1823 |
|
---|
1824 | /*
|
---|
1825 | * Power Off.
|
---|
1826 | */
|
---|
1827 | case VINF_EM_OFF:
|
---|
1828 | pVCpu->em.s.enmState = EMSTATE_TERMINATING;
|
---|
1829 | Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
|
---|
1830 | TMR3NotifySuspend(pVM, pVCpu);
|
---|
1831 | STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
|
---|
1832 | return rc;
|
---|
1833 |
|
---|
1834 | /*
|
---|
1835 | * Terminate the VM.
|
---|
1836 | */
|
---|
1837 | case VINF_EM_TERMINATE:
|
---|
1838 | pVCpu->em.s.enmState = EMSTATE_TERMINATING;
|
---|
1839 | Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
|
---|
1840 | if (pVM->enmVMState < VMSTATE_DESTROYING) /* ugly */
|
---|
1841 | TMR3NotifySuspend(pVM, pVCpu);
|
---|
1842 | STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
|
---|
1843 | return rc;
|
---|
1844 |
|
---|
1845 |
|
---|
1846 | /*
|
---|
1847 | * Out of memory, suspend the VM and stuff.
|
---|
1848 | */
|
---|
1849 | case VINF_EM_NO_MEMORY:
|
---|
1850 | Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
|
---|
1851 | pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
|
---|
1852 | pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
|
---|
1853 | TMR3NotifySuspend(pVM, pVCpu);
|
---|
1854 | STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
|
---|
1855 |
|
---|
1856 | rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
|
---|
1857 | N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
|
---|
1858 | if (rc != VINF_EM_SUSPEND)
|
---|
1859 | {
|
---|
1860 | if (RT_SUCCESS_NP(rc))
|
---|
1861 | {
|
---|
1862 | AssertLogRelMsgFailed(("%Rrc\n", rc));
|
---|
1863 | rc = VERR_EM_INTERNAL_ERROR;
|
---|
1864 | }
|
---|
1865 | pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
|
---|
1866 | }
|
---|
1867 | return rc;
|
---|
1868 |
|
---|
1869 | /*
|
---|
1870 | * Guest debug events.
|
---|
1871 | */
|
---|
1872 | case VINF_EM_DBG_STEPPED:
|
---|
1873 | AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
|
---|
1874 | case VINF_EM_DBG_STOP:
|
---|
1875 | case VINF_EM_DBG_BREAKPOINT:
|
---|
1876 | case VINF_EM_DBG_STEP:
|
---|
1877 | if (pVCpu->em.s.enmState == EMSTATE_RAW)
|
---|
1878 | {
|
---|
1879 | Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
|
---|
1880 | pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
|
---|
1881 | }
|
---|
1882 | else
|
---|
1883 | {
|
---|
1884 | Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
|
---|
1885 | pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
|
---|
1886 | }
|
---|
1887 | break;
|
---|
1888 |
|
---|
1889 | /*
|
---|
1890 | * Hypervisor debug events.
|
---|
1891 | */
|
---|
1892 | case VINF_EM_DBG_HYPER_STEPPED:
|
---|
1893 | case VINF_EM_DBG_HYPER_BREAKPOINT:
|
---|
1894 | case VINF_EM_DBG_HYPER_ASSERTION:
|
---|
1895 | Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_HYPER));
|
---|
1896 | pVCpu->em.s.enmState = EMSTATE_DEBUG_HYPER;
|
---|
1897 | break;
|
---|
1898 |
|
---|
1899 | /*
|
---|
1900 | * Guru mediations.
|
---|
1901 | */
|
---|
1902 | case VERR_VMM_RING0_ASSERTION:
|
---|
1903 | Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVCpu->em.s.enmState, EMSTATE_GURU_MEDITATION));
|
---|
1904 | pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
|
---|
1905 | break;
|
---|
1906 |
|
---|
1907 | /*
|
---|
1908 | * Any error code showing up here other than the ones we
|
---|
1909 | * know and process above are considered to be FATAL.
|
---|
1910 | *
|
---|
1911 | * Unknown warnings and informational status codes are also
|
---|
1912 | * included in this.
|
---|
1913 | */
|
---|
1914 | default:
|
---|
1915 | if (RT_SUCCESS_NP(rc))
|
---|
1916 | {
|
---|
1917 | AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
|
---|
1918 | rc = VERR_EM_INTERNAL_ERROR;
|
---|
1919 | }
|
---|
1920 | Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVCpu->em.s.enmState, EMSTATE_GURU_MEDITATION));
|
---|
1921 | pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
|
---|
1922 | break;
|
---|
1923 | }
|
---|
1924 |
|
---|
1925 | STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x); /* (skip this in release) */
|
---|
1926 | STAM_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
|
---|
1927 |
|
---|
1928 | /*
|
---|
1929 | * Act on the state.
|
---|
1930 | */
|
---|
1931 | switch (pVCpu->em.s.enmState)
|
---|
1932 | {
|
---|
1933 | /*
|
---|
1934 | * Execute raw.
|
---|
1935 | */
|
---|
1936 | case EMSTATE_RAW:
|
---|
1937 | rc = emR3RawExecute(pVM, pVCpu, &fFFDone);
|
---|
1938 | break;
|
---|
1939 |
|
---|
1940 | /*
|
---|
1941 | * Execute hardware accelerated raw.
|
---|
1942 | */
|
---|
1943 | case EMSTATE_HWACC:
|
---|
1944 | rc = emR3HwAccExecute(pVM, pVCpu, &fFFDone);
|
---|
1945 | break;
|
---|
1946 |
|
---|
1947 | /*
|
---|
1948 | * Execute recompiled.
|
---|
1949 | */
|
---|
1950 | case EMSTATE_REM:
|
---|
1951 | rc = emR3RemExecute(pVM, pVCpu, &fFFDone);
|
---|
1952 | Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
|
---|
1953 | break;
|
---|
1954 |
|
---|
1955 | /*
|
---|
1956 | * Application processor execution halted until SIPI.
|
---|
1957 | */
|
---|
1958 | case EMSTATE_WAIT_SIPI:
|
---|
1959 | /* no break */
|
---|
1960 | /*
|
---|
1961 | * hlt - execution halted until interrupt.
|
---|
1962 | */
|
---|
1963 | case EMSTATE_HALTED:
|
---|
1964 | {
|
---|
1965 | STAM_REL_PROFILE_START(&pVCpu->em.s.StatHalted, y);
|
---|
1966 | if (pVCpu->em.s.mwait.fWait & EMMWAIT_FLAG_ACTIVE)
|
---|
1967 | {
|
---|
1968 | /* mwait has a special extension where it's woken up when an interrupt is pending even when IF=0. */
|
---|
1969 | rc = VMR3WaitHalted(pVM, pVCpu, !(pVCpu->em.s.mwait.fWait & EMMWAIT_FLAG_BREAKIRQIF0) && !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
|
---|
1970 | pVCpu->em.s.mwait.fWait &= ~(EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0);
|
---|
1971 | }
|
---|
1972 | else
|
---|
1973 | rc = VMR3WaitHalted(pVM, pVCpu, !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
|
---|
1974 |
|
---|
1975 | STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHalted, y);
|
---|
1976 | break;
|
---|
1977 | }
|
---|
1978 |
|
---|
1979 | /*
|
---|
1980 | * Suspended - return to VM.cpp.
|
---|
1981 | */
|
---|
1982 | case EMSTATE_SUSPENDED:
|
---|
1983 | TMR3NotifySuspend(pVM, pVCpu);
|
---|
1984 | STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
|
---|
1985 | Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
|
---|
1986 | return VINF_EM_SUSPEND;
|
---|
1987 |
|
---|
1988 | /*
|
---|
1989 | * Debugging in the guest.
|
---|
1990 | */
|
---|
1991 | case EMSTATE_DEBUG_GUEST_REM:
|
---|
1992 | case EMSTATE_DEBUG_GUEST_RAW:
|
---|
1993 | TMR3NotifySuspend(pVM, pVCpu);
|
---|
1994 | rc = emR3Debug(pVM, pVCpu, rc);
|
---|
1995 | TMR3NotifyResume(pVM, pVCpu);
|
---|
1996 | Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
|
---|
1997 | break;
|
---|
1998 |
|
---|
1999 | /*
|
---|
2000 | * Debugging in the hypervisor.
|
---|
2001 | */
|
---|
2002 | case EMSTATE_DEBUG_HYPER:
|
---|
2003 | {
|
---|
2004 | TMR3NotifySuspend(pVM, pVCpu);
|
---|
2005 | STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
|
---|
2006 |
|
---|
2007 | rc = emR3Debug(pVM, pVCpu, rc);
|
---|
2008 | Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
|
---|
2009 | if (rc != VINF_SUCCESS)
|
---|
2010 | {
|
---|
2011 | /* switch to guru meditation mode */
|
---|
2012 | pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
|
---|
2013 | VMMR3FatalDump(pVM, pVCpu, rc);
|
---|
2014 | Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
|
---|
2015 | return rc;
|
---|
2016 | }
|
---|
2017 |
|
---|
2018 | STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
|
---|
2019 | TMR3NotifyResume(pVM, pVCpu);
|
---|
2020 | break;
|
---|
2021 | }
|
---|
2022 |
|
---|
2023 | /*
|
---|
2024 | * Guru meditation takes place in the debugger.
|
---|
2025 | */
|
---|
2026 | case EMSTATE_GURU_MEDITATION:
|
---|
2027 | {
|
---|
2028 | TMR3NotifySuspend(pVM, pVCpu);
|
---|
2029 | VMMR3FatalDump(pVM, pVCpu, rc);
|
---|
2030 | emR3Debug(pVM, pVCpu, rc);
|
---|
2031 | STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
|
---|
2032 | Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
|
---|
2033 | return rc;
|
---|
2034 | }
|
---|
2035 |
|
---|
2036 | /*
|
---|
2037 | * The states we don't expect here.
|
---|
2038 | */
|
---|
2039 | case EMSTATE_NONE:
|
---|
2040 | case EMSTATE_TERMINATING:
|
---|
2041 | default:
|
---|
2042 | AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVCpu->em.s.enmState));
|
---|
2043 | pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
|
---|
2044 | TMR3NotifySuspend(pVM, pVCpu);
|
---|
2045 | STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
|
---|
2046 | Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
|
---|
2047 | return VERR_EM_INTERNAL_ERROR;
|
---|
2048 | }
|
---|
2049 | } /* The Outer Main Loop */
|
---|
2050 | }
|
---|
2051 | else
|
---|
2052 | {
|
---|
2053 | /*
|
---|
2054 | * Fatal error.
|
---|
2055 | */
|
---|
2056 | Log(("EMR3ExecuteVM: returns %Rrc because of longjmp / fatal error; (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
|
---|
2057 | TMR3NotifySuspend(pVM, pVCpu);
|
---|
2058 | VMMR3FatalDump(pVM, pVCpu, rc);
|
---|
2059 | emR3Debug(pVM, pVCpu, rc);
|
---|
2060 | STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
|
---|
2061 | /** @todo change the VM state! */
|
---|
2062 | return rc;
|
---|
2063 | }
|
---|
2064 |
|
---|
2065 | /* (won't ever get here). */
|
---|
2066 | AssertFailed();
|
---|
2067 | }
|
---|
2068 |
|
---|