EMHwaccm.cpp@ 29287

Last change on this file since 29287 was 29250, checked in by vboxsync, 15 years ago
iprt/asm.h: split out asm-math.h, don't include asm-.h from asm.h, don't include asm.h from sup.h. Fixed a couple file headers.
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1	/* $Id: EMHwaccm.cpp 29250 2010-05-09 17:53:58Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager - hardware virtualization
4	*/
5
6	/*
7	* Copyright (C) 2006-2009 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_em EM - The Execution Monitor / Manager
19	*
20	* The Execution Monitor/Manager is responsible for running the VM, scheduling
21	* the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
22	* Interpreted), and keeping the CPU states in sync. The function
23	* EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
24	* modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
25	* emR3RemExecute).
26	*
27	* The interpreted execution is only used to avoid switching between
28	* raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
29	* The interpretation is thus implemented as part of EM.
30	*
31	* @see grp_em
32	*/
33
34	/*******************************************************************************
35	* Header Files *
36	*******************************************************************************/
37	#define LOG_GROUP LOG_GROUP_EM
38	#include <VBox/em.h>
39	#include <VBox/vmm.h>
40	#ifdef VBOX_WITH_VMI
41	# include <VBox/parav.h>
42	#endif
43	#include <VBox/csam.h>
44	#include <VBox/selm.h>
45	#include <VBox/trpm.h>
46	#include <VBox/iom.h>
47	#include <VBox/dbgf.h>
48	#include <VBox/pgm.h>
49	#include <VBox/rem.h>
50	#include <VBox/tm.h>
51	#include <VBox/mm.h>
52	#include <VBox/ssm.h>
53	#include <VBox/pdmapi.h>
54	#include <VBox/pdmcritsect.h>
55	#include <VBox/pdmqueue.h>
56	#include <VBox/hwaccm.h>
57	#include "EMInternal.h"
58	#include <VBox/vm.h>
59	#include <VBox/cpumdis.h>
60	#include <VBox/dis.h>
61	#include <VBox/disopcode.h>
62	#include <VBox/dbgf.h>
63
64	#include <iprt/asm.h>
65
66
67	/*******************************************************************************
68	* Defined Constants And Macros *
69	*******************************************************************************/
70	#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
71	#define EM_NOTIFY_HWACCM
72	#endif
73
74
75	/*******************************************************************************
76	* Internal Functions *
77	*******************************************************************************/
78	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
79	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
80	static int emR3HwaccmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
81
82	#define EMHANDLERC_WITH_HWACCM
83	#include "EMHandleRCTmpl.h"
84
85
86	#ifdef DEBUG
87
88	/**
89	* Steps hardware accelerated mode.
90	*
91	* @returns VBox status code.
92	* @param pVM The VM handle.
93	* @param pVCpu The VMCPU handle.
94	*/
95	static int emR3HwAccStep(PVM pVM, PVMCPU pVCpu)
96	{
97	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
98
99	int rc;
100	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
101	VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS));
102
103	/*
104	* Check vital forced actions, but ignore pending interrupts and timers.
105	*/
106	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
107	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
108	{
109	rc = emR3HwaccmForcedActions(pVM, pVCpu, pCtx);
110	if (rc != VINF_SUCCESS)
111	return rc;
112	}
113	/*
114	* Set flags for single stepping.
115	*/
116	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
117
118	/*
119	* Single step.
120	* We do not start time or anything, if anything we should just do a few nanoseconds.
121	*/
122	do
123	{
124	rc = VMMR3HwAccRunGC(pVM, pVCpu);
125	} while ( rc == VINF_SUCCESS
126	\|\| rc == VINF_EM_RAW_INTERRUPT);
127	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
128
129	/*
130	* Make sure the trap flag is cleared.
131	* (Too bad if the guest is trying to single step too.)
132	*/
133	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
134
135	/*
136	* Deal with the return codes.
137	*/
138	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
139	rc = emR3HwaccmHandleRC(pVM, pVCpu, pCtx, rc);
140	return rc;
141	}
142
143
144	static int emR3SingleStepExecHwAcc(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
145	{
146	int rc = VINF_SUCCESS;
147	EMSTATE enmOldState = pVCpu->em.s.enmState;
148	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
149
150	Log(("Single step BEGIN:\n"));
151	for (uint32_t i = 0; i < cIterations; i++)
152	{
153	DBGFR3PrgStep(pVCpu);
154	DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
155	rc = emR3HwAccStep(pVM, pVCpu);
156	if ( rc != VINF_SUCCESS
157	\|\| !HWACCMR3CanExecuteGuest(pVM, pVCpu->em.s.pCtx))
158	break;
159	}
160	Log(("Single step END: rc=%Rrc\n", rc));
161	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
162	pVCpu->em.s.enmState = enmOldState;
163	return rc == VINF_SUCCESS ? VINF_EM_RESCHEDULE_REM : rc;
164	}
165
166	#endif /* DEBUG */
167
168
169	/**
170	* Executes one (or perhaps a few more) instruction(s).
171	*
172	* @returns VBox status code suitable for EM.
173	*
174	* @param pVM VM handle.
175	* @param pVCpu VMCPU handle
176	* @param rcGC GC return code
177	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
178	* instruction and prefix the log output with this text.
179	*/
180	#ifdef LOG_ENABLED
181	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
182	#else
183	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
184	#endif
185	{
186	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
187	int rc;
188
189	/*
190	*
191	* The simple solution is to use the recompiler.
192	* The better solution is to disassemble the current instruction and
193	* try handle as many as possible without using REM.
194	*
195	*/
196
197	#ifdef LOG_ENABLED
198	/*
199	* Disassemble the instruction if requested.
200	*/
201	if (pszPrefix)
202	{
203	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
204	DBGFR3DisasInstrCurrentLog(pVCpu, pszPrefix);
205	}
206	#endif /* LOG_ENABLED */
207
208	#if 0
209	/* Try our own instruction emulator before falling back to the recompiler. */
210	DISCPUSTATE Cpu;
211	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "GEN EMU");
212	if (RT_SUCCESS(rc))
213	{
214	uint32_t size;
215
216	switch (Cpu.pCurInstr->opcode)
217	{
218	/* @todo we can do more now */
219	case OP_MOV:
220	case OP_AND:
221	case OP_OR:
222	case OP_XOR:
223	case OP_POP:
224	case OP_INC:
225	case OP_DEC:
226	case OP_XCHG:
227	STAM_PROFILE_START(&pVCpu->em.s.StatMiscEmu, a);
228	rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
229	if (RT_SUCCESS(rc))
230	{
231	pCtx->rip += Cpu.opsize;
232	#ifdef EM_NOTIFY_HWACCM
233	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
234	HWACCMR3NotifyEmulated(pVCpu);
235	#endif
236	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
237	return rc;
238	}
239	if (rc != VERR_EM_INTERPRETER)
240	AssertMsgFailedReturn(("rc=%Rrc\n", rc), rc);
241	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
242	break;
243	}
244	}
245	#endif /* 0 */
246	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
247	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
248	EMRemLock(pVM);
249	/* Flush the recompiler TLB if the VCPU has changed. */
250	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
251	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
252	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
253
254	rc = REMR3EmulateInstruction(pVM, pVCpu);
255	EMRemUnlock(pVM);
256	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
257
258	#ifdef EM_NOTIFY_HWACCM
259	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
260	HWACCMR3NotifyEmulated(pVCpu);
261	#endif
262	return rc;
263	}
264
265
266	/**
267	* Executes one (or perhaps a few more) instruction(s).
268	* This is just a wrapper for discarding pszPrefix in non-logging builds.
269	*
270	* @returns VBox status code suitable for EM.
271	* @param pVM VM handle.
272	* @param pVCpu VMCPU handle.
273	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
274	* instruction and prefix the log output with this text.
275	* @param rcGC GC return code
276	*/
277	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
278	{
279	#ifdef LOG_ENABLED
280	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
281	#else
282	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC);
283	#endif
284	}
285
286	/**
287	* Executes one (or perhaps a few more) IO instruction(s).
288	*
289	* @returns VBox status code suitable for EM.
290	* @param pVM VM handle.
291	* @param pVCpu VMCPU handle.
292	*/
293	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
294	{
295	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
296
297	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
298
299	/* Try to restart the io instruction that was refused in ring-0. */
300	VBOXSTRICTRC rcStrict = HWACCMR3RestartPendingIOInstr(pVM, pVCpu, pCtx);
301	if (IOM_SUCCESS(rcStrict))
302	{
303	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoRestarted);
304	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
305	return VBOXSTRICTRC_TODO(rcStrict); /* rip already updated. */
306	}
307	AssertMsgReturn(rcStrict == VERR_NOT_FOUND, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)),
308	RT_SUCCESS_NP(rcStrict) ? VERR_INTERNAL_ERROR_5 : VBOXSTRICTRC_TODO(rcStrict));
309
310	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
311	* as io instructions tend to come in packages of more than one
312	*/
313	DISCPUSTATE Cpu;
314	int rc2 = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
315	if (RT_SUCCESS(rc2))
316	{
317	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
318
319	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
320	{
321	switch (Cpu.pCurInstr->opcode)
322	{
323	case OP_IN:
324	{
325	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
326	rcStrict = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
327	break;
328	}
329
330	case OP_OUT:
331	{
332	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
333	rcStrict = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
334	break;
335	}
336	}
337	}
338	else if (Cpu.prefix & PREFIX_REP)
339	{
340	switch (Cpu.pCurInstr->opcode)
341	{
342	case OP_INSB:
343	case OP_INSWD:
344	{
345	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
346	rcStrict = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
347	break;
348	}
349
350	case OP_OUTSB:
351	case OP_OUTSWD:
352	{
353	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
354	rcStrict = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
355	break;
356	}
357	}
358	}
359
360	/*
361	* Handled the I/O return codes.
362	* (The unhandled cases end up with rcStrict == VINF_EM_RAW_EMULATE_INSTR.)
363	*/
364	if (IOM_SUCCESS(rcStrict))
365	{
366	pCtx->rip += Cpu.opsize;
367	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
368	return VBOXSTRICTRC_TODO(rcStrict);
369	}
370
371	if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
372	{
373	/* The active trap will be dispatched. */
374	Assert(TRPMHasTrap(pVCpu));
375	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
376	return VINF_SUCCESS;
377	}
378	AssertMsg(rcStrict != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
379
380	if (RT_FAILURE(rcStrict))
381	{
382	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
383	return VBOXSTRICTRC_TODO(rcStrict);
384	}
385	AssertMsg(rcStrict == VINF_EM_RAW_EMULATE_INSTR \|\| rcStrict == VINF_EM_RESCHEDULE_REM, ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
386	}
387
388	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
389	return emR3ExecuteInstruction(pVM, pVCpu, "IO: ");
390	}
391
392
393	/**
394	* Process raw-mode specific forced actions.
395	*
396	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
397	*
398	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
399	* EM statuses.
400	* @param pVM The VM handle.
401	* @param pVCpu The VMCPU handle.
402	* @param pCtx The guest CPUM register context.
403	*/
404	static int emR3HwaccmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
405	{
406	/*
407	* Sync page directory.
408	*/
409	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
410	{
411	Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
412	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
413	if (RT_FAILURE(rc))
414	return rc;
415
416	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
417
418	/* Prefetch pages for EIP and ESP. */
419	/** @todo This is rather expensive. Should investigate if it really helps at all. */
420	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
421	if (rc == VINF_SUCCESS)
422	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
423	if (rc != VINF_SUCCESS)
424	{
425	if (rc != VINF_PGM_SYNC_CR3)
426	{
427	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
428	return rc;
429	}
430	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
431	if (RT_FAILURE(rc))
432	return rc;
433	}
434	/** @todo maybe prefetch the supervisor stack page as well */
435	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
436	}
437
438	/*
439	* Allocate handy pages (just in case the above actions have consumed some pages).
440	*/
441	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
442	{
443	int rc = PGMR3PhysAllocateHandyPages(pVM);
444	if (RT_FAILURE(rc))
445	return rc;
446	}
447
448	/*
449	* Check whether we're out of memory now.
450	*
451	* This may stem from some of the above actions or operations that has been executed
452	* since we ran FFs. The allocate handy pages must for instance always be followed by
453	* this check.
454	*/
455	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
456	return VINF_EM_NO_MEMORY;
457
458	return VINF_SUCCESS;
459	}
460
461
462	/**
463	* Executes hardware accelerated raw code. (Intel VT-x & AMD-V)
464	*
465	* This function contains the raw-mode version of the inner
466	* execution loop (the outer loop being in EMR3ExecuteVM()).
467	*
468	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
469	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
470	*
471	* @param pVM VM handle.
472	* @param pVCpu VMCPU handle.
473	* @param pfFFDone Where to store an indicator telling whether or not
474	* FFs were done before returning.
475	*/
476	int emR3HwAccExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
477	{
478	int rc = VERR_INTERNAL_ERROR;
479	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
480
481	LogFlow(("emR3HwAccExecute%d: (cs:eip=%04x:%RGv)\n", pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip));
482	*pfFFDone = false;
483
484	STAM_COUNTER_INC(&pVCpu->em.s.StatHwAccExecuteEntry);
485
486	#ifdef EM_NOTIFY_HWACCM
487	HWACCMR3NotifyScheduled(pVCpu);
488	#endif
489
490	/*
491	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
492	*/
493	for (;;)
494	{
495	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatHwAccEntry, a);
496
497	/* Check if a forced reschedule is pending. */
498	if (HWACCMR3IsRescheduleRequired(pVM, pCtx))
499	{
500	rc = VINF_EM_RESCHEDULE;
501	break;
502	}
503
504	/*
505	* Process high priority pre-execution raw-mode FFs.
506	*/
507	VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS)); /* not relevant in HWACCM mode; shouldn't be set really. */
508	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
509	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
510	{
511	rc = emR3HwaccmForcedActions(pVM, pVCpu, pCtx);
512	if (rc != VINF_SUCCESS)
513	break;
514	}
515
516	#ifdef LOG_ENABLED
517	/*
518	* Log important stuff before entering GC.
519	*/
520	if (TRPMHasTrap(pVCpu))
521	Log(("CPU%d: Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", pVCpu->idCpu, TRPMGetTrapNo(pVCpu), pCtx->cs, (RTGCPTR)pCtx->rip));
522
523	uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
524
525	if (pVM->cCpus == 1)
526	{
527	if (pCtx->eflags.Bits.u1VM)
528	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
529	else if (CPUMIsGuestIn64BitCodeEx(pCtx))
530	Log(("HWR%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
531	else
532	Log(("HWR%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
533	}
534	else
535	{
536	if (pCtx->eflags.Bits.u1VM)
537	Log(("HWV86-CPU%d: %08X IF=%d\n", pVCpu->idCpu, pCtx->eip, pCtx->eflags.Bits.u1IF));
538	else if (CPUMIsGuestIn64BitCodeEx(pCtx))
539	Log(("HWR%d-CPU%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
540	else
541	Log(("HWR%d-CPU%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
542	}
543	#endif /* LOG_ENABLED */
544
545	/*
546	* Execute the code.
547	*/
548	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatHwAccEntry, a);
549	STAM_PROFILE_START(&pVCpu->em.s.StatHwAccExec, x);
550	rc = VMMR3HwAccRunGC(pVM, pVCpu);
551	STAM_PROFILE_STOP(&pVCpu->em.s.StatHwAccExec, x);
552
553	/*
554	* Deal with high priority post execution FFs before doing anything else.
555	*/
556	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
557	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
558	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
559	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
560
561	/*
562	* Process the returned status code.
563	*/
564	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
565	break;
566
567	rc = emR3HwaccmHandleRC(pVM, pVCpu, pCtx, rc);
568	if (rc != VINF_SUCCESS)
569	break;
570
571	/*
572	* Check and execute forced actions.
573	*/
574	#ifdef VBOX_HIGH_RES_TIMERS_HACK
575	TMTimerPollVoid(pVM, pVCpu);
576	#endif
577	if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK)
578	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_MASK))
579	{
580	rc = emR3ForcedActions(pVM, pVCpu, rc);
581	if ( rc != VINF_SUCCESS
582	&& rc != VINF_EM_RESCHEDULE_HWACC)
583	{
584	*pfFFDone = true;
585	break;
586	}
587	}
588	}
589
590	/*
591	* Return to outer loop.
592	*/
593	#if defined(LOG_ENABLED) && defined(DEBUG)
594	RTLogFlush(NULL);
595	#endif
596	return rc;
597	}
598

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source: vbox/trunk/src/VBox/VMM/EMHwaccm.cpp@ 29287

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