1 | /* $Id: EM.cpp 49491 2009-07-03 11:39:50Z sandervl $ */
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2 | /** @file
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3 | * EM - Execution Monitor / Manager - hardware virtualization
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2009 Sun Microsystems, Inc.
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | *
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17 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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18 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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19 | * additional information or have any questions.
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20 | */
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21 |
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22 | /** @page pg_em EM - The Execution Monitor / Manager
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23 | *
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24 | * The Execution Monitor/Manager is responsible for running the VM, scheduling
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25 | * the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
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26 | * Interpreted), and keeping the CPU states in sync. The function
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27 | * EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
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28 | * modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
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29 | * emR3RemExecute).
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30 | *
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31 | * The interpreted execution is only used to avoid switching between
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32 | * raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
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33 | * The interpretation is thus implemented as part of EM.
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34 | *
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35 | * @see grp_em
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36 | */
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37 |
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38 | /*******************************************************************************
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39 | * Header Files *
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40 | *******************************************************************************/
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41 | #define LOG_GROUP LOG_GROUP_EM
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42 | #include <VBox/em.h>
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43 | #include <VBox/vmm.h>
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44 | #ifdef VBOX_WITH_VMI
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45 | # include <VBox/parav.h>
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46 | #endif
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47 | #include <VBox/csam.h>
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48 | #include <VBox/selm.h>
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49 | #include <VBox/trpm.h>
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50 | #include <VBox/iom.h>
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51 | #include <VBox/dbgf.h>
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52 | #include <VBox/pgm.h>
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53 | #include <VBox/rem.h>
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54 | #include <VBox/tm.h>
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55 | #include <VBox/mm.h>
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56 | #include <VBox/ssm.h>
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57 | #include <VBox/pdmapi.h>
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58 | #include <VBox/pdmcritsect.h>
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59 | #include <VBox/pdmqueue.h>
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60 | #include <VBox/hwaccm.h>
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61 | #include "EMInternal.h"
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62 | #include <VBox/vm.h>
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63 | #include <VBox/cpumdis.h>
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64 | #include <VBox/dis.h>
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65 | #include <VBox/disopcode.h>
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66 | #include <VBox/dbgf.h>
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67 |
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68 |
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69 | /*******************************************************************************
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70 | * Defined Constants And Macros *
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71 | *******************************************************************************/
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72 | #if 0 /* Disabled till after 2.1.0 when we've time to test it. */
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73 | #define EM_NOTIFY_HWACCM
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74 | #endif
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75 |
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76 |
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77 | /*******************************************************************************
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78 | * Internal Functions *
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79 | *******************************************************************************/
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80 | DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
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81 | static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
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82 | static int emR3HwaccmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
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83 |
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84 | #define EMHANDLERC_WITH_HWACCM
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85 | #include "EMHandleRCTmpl.h"
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86 |
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87 |
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88 | #ifdef DEBUG
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89 |
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90 | /**
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91 | * Steps hardware accelerated mode.
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92 | *
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93 | * @returns VBox status code.
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94 | * @param pVM The VM handle.
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95 | * @param pVCpu The VMCPU handle.
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96 | */
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97 | static int emR3HwAccStep(PVM pVM, PVMCPU pVCpu)
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98 | {
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99 | Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
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100 |
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101 | int rc;
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102 | PCPUMCTX pCtx = pVCpu->em.s.pCtx;
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103 | VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS));
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104 |
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105 | /*
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106 | * Check vital forced actions, but ignore pending interrupts and timers.
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107 | */
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108 | if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
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109 | || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
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110 | {
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111 | rc = emR3HwaccmForcedActions(pVM, pVCpu, pCtx);
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112 | if (rc != VINF_SUCCESS)
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113 | return rc;
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114 | }
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115 | /*
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116 | * Set flags for single stepping.
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117 | */
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118 | CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) | X86_EFL_TF | X86_EFL_RF);
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119 |
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120 | /*
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121 | * Single step.
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122 | * We do not start time or anything, if anything we should just do a few nanoseconds.
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123 | */
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124 | do
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125 | {
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126 | rc = VMMR3HwAccRunGC(pVM, pVCpu);
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127 | } while ( rc == VINF_SUCCESS
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128 | || rc == VINF_EM_RAW_INTERRUPT);
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129 | VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
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130 |
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131 | /*
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132 | * Make sure the trap flag is cleared.
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133 | * (Too bad if the guest is trying to single step too.)
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134 | */
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135 | CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
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136 |
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137 | /*
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138 | * Deal with the return codes.
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139 | */
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140 | rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
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141 | rc = emR3HwaccmHandleRC(pVM, pVCpu, pCtx, rc);
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142 | return rc;
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143 | }
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144 |
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145 |
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146 | static int emR3SingleStepExecHwAcc(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
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147 | {
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148 | int rc = VINF_SUCCESS;
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149 | EMSTATE enmOldState = pVCpu->em.s.enmState;
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150 | pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
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151 |
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152 | Log(("Single step BEGIN:\n"));
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153 | for (uint32_t i = 0; i < cIterations; i++)
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154 | {
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155 | DBGFR3PrgStep(pVCpu);
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156 | DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
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157 | rc = emR3HwAccStep(pVM, pVCpu);
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158 | if ( rc != VINF_SUCCESS
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159 | || !HWACCMR3CanExecuteGuest(pVM, pVCpu->em.s.pCtx))
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160 | break;
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161 | }
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162 | Log(("Single step END: rc=%Rrc\n", rc));
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163 | CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
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164 | pVCpu->em.s.enmState = enmOldState;
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165 | return rc == VINF_SUCCESS ? VINF_EM_RESCHEDULE_REM : rc;
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166 | }
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167 |
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168 | #endif /* DEBUG */
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169 |
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170 |
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171 | /**
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172 | * Executes one (or perhaps a few more) instruction(s).
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173 | *
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174 | * @returns VBox status code suitable for EM.
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175 | *
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176 | * @param pVM VM handle.
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177 | * @param pVCpu VMCPU handle
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178 | * @param rcGC GC return code
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179 | * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
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180 | * instruction and prefix the log output with this text.
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181 | */
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182 | #ifdef LOG_ENABLED
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183 | static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
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184 | #else
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185 | static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
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186 | #endif
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187 | {
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188 | PCPUMCTX pCtx = pVCpu->em.s.pCtx;
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189 | int rc;
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190 |
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191 | /*
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192 | *
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193 | * The simple solution is to use the recompiler.
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194 | * The better solution is to disassemble the current instruction and
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195 | * try handle as many as possible without using REM.
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196 | *
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197 | */
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198 |
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199 | #ifdef LOG_ENABLED
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200 | /*
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201 | * Disassemble the instruction if requested.
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202 | */
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203 | if (pszPrefix)
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204 | {
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205 | DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
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206 | DBGFR3DisasInstrCurrentLog(pVCpu, pszPrefix);
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207 | }
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208 | #endif /* LOG_ENABLED */
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209 |
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210 | #if 0
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211 | /* Try our own instruction emulator before falling back to the recompiler. */
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212 | DISCPUSTATE Cpu;
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213 | rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "GEN EMU");
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214 | if (RT_SUCCESS(rc))
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215 | {
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216 | uint32_t size;
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217 |
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218 | switch (Cpu.pCurInstr->opcode)
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219 | {
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220 | /* @todo we can do more now */
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221 | case OP_MOV:
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222 | case OP_AND:
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223 | case OP_OR:
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224 | case OP_XOR:
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225 | case OP_POP:
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226 | case OP_INC:
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227 | case OP_DEC:
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228 | case OP_XCHG:
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229 | STAM_PROFILE_START(&pVCpu->em.s.StatMiscEmu, a);
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230 | rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
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231 | if (RT_SUCCESS(rc))
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232 | {
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233 | pCtx->rip += Cpu.opsize;
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234 | #ifdef EM_NOTIFY_HWACCM
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235 | if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
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236 | HWACCMR3NotifyEmulated(pVCpu);
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237 | #endif
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238 | STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
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239 | return rc;
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240 | }
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241 | if (rc != VERR_EM_INTERPRETER)
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242 | AssertMsgFailedReturn(("rc=%Rrc\n", rc), rc);
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243 | STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
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244 | break;
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245 | }
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246 | }
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247 | #endif /* 0 */
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248 | STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
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249 | Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
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250 | EMRemLock(pVM);
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251 | /* Flush the recompiler TLB if the VCPU has changed. */
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252 | if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
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253 | CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
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254 | pVM->em.s.idLastRemCpu = pVCpu->idCpu;
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255 |
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256 | rc = REMR3EmulateInstruction(pVM, pVCpu);
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257 | EMRemUnlock(pVM);
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258 | STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
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259 |
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260 | #ifdef EM_NOTIFY_HWACCM
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261 | if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
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262 | HWACCMR3NotifyEmulated(pVCpu);
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263 | #endif
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264 | return rc;
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265 | }
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266 |
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267 |
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268 | /**
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269 | * Executes one (or perhaps a few more) instruction(s).
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270 | * This is just a wrapper for discarding pszPrefix in non-logging builds.
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271 | *
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272 | * @returns VBox status code suitable for EM.
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273 | * @param pVM VM handle.
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274 | * @param pVCpu VMCPU handle.
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275 | * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
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276 | * instruction and prefix the log output with this text.
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277 | * @param rcGC GC return code
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278 | */
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279 | DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
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280 | {
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281 | #ifdef LOG_ENABLED
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282 | return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
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283 | #else
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284 | return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC);
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285 | #endif
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286 | }
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287 |
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288 | /**
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289 | * Executes one (or perhaps a few more) IO instruction(s).
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290 | *
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291 | * @returns VBox status code suitable for EM.
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292 | * @param pVM VM handle.
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293 | * @param pVCpu VMCPU handle.
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294 | */
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295 | static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
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296 | {
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297 | int rc;
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298 | PCPUMCTX pCtx = pVCpu->em.s.pCtx;
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299 |
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300 | STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
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301 |
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302 | /* Try to restart the io instruction that was refused in ring-0. */
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303 | rc = HWACCMR3RestartPendingIOInstr(pVM, pVCpu);
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304 | if (rc == VINF_SUCCESS)
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305 | {
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306 | STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoRestarted);
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307 | STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
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308 | return rc; /* rip already updated. */
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309 | }
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310 |
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311 | /** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
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312 | * as io instructions tend to come in packages of more than one
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313 | */
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314 | DISCPUSTATE Cpu;
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315 | rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
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316 | if (RT_SUCCESS(rc))
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317 | {
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318 | rc = VINF_EM_RAW_EMULATE_INSTR;
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319 |
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320 | if (!(Cpu.prefix & (PREFIX_REP | PREFIX_REPNE)))
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321 | {
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322 | switch (Cpu.pCurInstr->opcode)
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323 | {
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324 | case OP_IN:
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325 | {
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326 | STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
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327 | rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
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328 | break;
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329 | }
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330 |
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331 | case OP_OUT:
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332 | {
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333 | STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
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334 | rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
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335 | break;
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336 | }
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337 | }
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338 | }
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339 | else if (Cpu.prefix & PREFIX_REP)
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340 | {
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341 | switch (Cpu.pCurInstr->opcode)
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342 | {
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343 | case OP_INSB:
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344 | case OP_INSWD:
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345 | {
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346 | STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
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347 | rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
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348 | break;
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349 | }
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350 |
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351 | case OP_OUTSB:
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352 | case OP_OUTSWD:
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353 | {
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354 | STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
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355 | rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
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356 | break;
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357 | }
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358 | }
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359 | }
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360 |
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361 | /*
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362 | * Handled the I/O return codes.
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363 | * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
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364 | */
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365 | if (IOM_SUCCESS(rc))
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366 | {
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367 | pCtx->rip += Cpu.opsize;
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368 | STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
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369 | return rc;
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370 | }
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371 |
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372 | if (rc == VINF_EM_RAW_GUEST_TRAP)
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373 | {
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374 | /* The active trap will be dispatched. */
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375 | Assert(TRPMHasTrap(pVCpu));
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376 | STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
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377 | return VINF_SUCCESS;
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378 | }
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379 | AssertMsg(rc != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
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380 |
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381 | if (RT_FAILURE(rc))
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382 | {
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383 | STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
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384 | return rc;
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385 | }
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386 | AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RESCHEDULE_REM, ("rc=%Rrc\n", rc));
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387 | }
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388 | STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
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389 | return emR3ExecuteInstruction(pVM, pVCpu, "IO: ");
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390 | }
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391 |
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392 |
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393 | /**
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394 | * Process raw-mode specific forced actions.
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395 | *
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396 | * This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
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397 | *
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398 | * @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
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399 | * EM statuses.
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400 | * @param pVM The VM handle.
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401 | * @param pVCpu The VMCPU handle.
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402 | * @param pCtx The guest CPUM register context.
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403 | */
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404 | static int emR3HwaccmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
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405 | {
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406 | /*
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407 | * Sync page directory.
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408 | */
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409 | if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
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410 | {
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411 | Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
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412 | int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
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413 | if (RT_FAILURE(rc))
|
---|
414 | return rc;
|
---|
415 |
|
---|
416 | Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));
|
---|
417 |
|
---|
418 | /* Prefetch pages for EIP and ESP. */
|
---|
419 | /** @todo This is rather expensive. Should investigate if it really helps at all. */
|
---|
420 | rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
|
---|
421 | if (rc == VINF_SUCCESS)
|
---|
422 | rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
|
---|
423 | if (rc != VINF_SUCCESS)
|
---|
424 | {
|
---|
425 | if (rc != VINF_PGM_SYNC_CR3)
|
---|
426 | {
|
---|
427 | AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
|
---|
428 | return rc;
|
---|
429 | }
|
---|
430 | rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
|
---|
431 | if (RT_FAILURE(rc))
|
---|
432 | return rc;
|
---|
433 | }
|
---|
434 | /** @todo maybe prefetch the supervisor stack page as well */
|
---|
435 | Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));
|
---|
436 | }
|
---|
437 |
|
---|
438 | /*
|
---|
439 | * Allocate handy pages (just in case the above actions have consumed some pages).
|
---|
440 | */
|
---|
441 | if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
|
---|
442 | {
|
---|
443 | int rc = PGMR3PhysAllocateHandyPages(pVM);
|
---|
444 | if (RT_FAILURE(rc))
|
---|
445 | return rc;
|
---|
446 | }
|
---|
447 |
|
---|
448 | /*
|
---|
449 | * Check whether we're out of memory now.
|
---|
450 | *
|
---|
451 | * This may stem from some of the above actions or operations that has been executed
|
---|
452 | * since we ran FFs. The allocate handy pages must for instance always be followed by
|
---|
453 | * this check.
|
---|
454 | */
|
---|
455 | if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
|
---|
456 | return VINF_EM_NO_MEMORY;
|
---|
457 |
|
---|
458 | return VINF_SUCCESS;
|
---|
459 | }
|
---|
460 |
|
---|
461 |
|
---|
462 | /**
|
---|
463 | * Executes hardware accelerated raw code. (Intel VT-x & AMD-V)
|
---|
464 | *
|
---|
465 | * This function contains the raw-mode version of the inner
|
---|
466 | * execution loop (the outer loop being in EMR3ExecuteVM()).
|
---|
467 | *
|
---|
468 | * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
|
---|
469 | * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
|
---|
470 | *
|
---|
471 | * @param pVM VM handle.
|
---|
472 | * @param pVCpu VMCPU handle.
|
---|
473 | * @param pfFFDone Where to store an indicator telling whether or not
|
---|
474 | * FFs were done before returning.
|
---|
475 | */
|
---|
476 | int emR3HwAccExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
|
---|
477 | {
|
---|
478 | int rc = VERR_INTERNAL_ERROR;
|
---|
479 | PCPUMCTX pCtx = pVCpu->em.s.pCtx;
|
---|
480 |
|
---|
481 | LogFlow(("emR3HwAccExecute%d: (cs:eip=%04x:%RGv)\n", pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip));
|
---|
482 | *pfFFDone = false;
|
---|
483 |
|
---|
484 | STAM_COUNTER_INC(&pVCpu->em.s.StatHwAccExecuteEntry);
|
---|
485 |
|
---|
486 | #ifdef EM_NOTIFY_HWACCM
|
---|
487 | HWACCMR3NotifyScheduled(pVCpu);
|
---|
488 | #endif
|
---|
489 |
|
---|
490 | /*
|
---|
491 | * Spin till we get a forced action which returns anything but VINF_SUCCESS.
|
---|
492 | */
|
---|
493 | for (;;)
|
---|
494 | {
|
---|
495 | STAM_PROFILE_ADV_START(&pVCpu->em.s.StatHwAccEntry, a);
|
---|
496 |
|
---|
497 | /*
|
---|
498 | * Process high priority pre-execution raw-mode FFs.
|
---|
499 | */
|
---|
500 | VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS)); /* not relevant in HWACCM mode; shouldn't be set really. */
|
---|
501 | if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
|
---|
502 | || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
|
---|
503 | {
|
---|
504 | rc = emR3HwaccmForcedActions(pVM, pVCpu, pCtx);
|
---|
505 | if (rc != VINF_SUCCESS)
|
---|
506 | break;
|
---|
507 | }
|
---|
508 |
|
---|
509 | #ifdef LOG_ENABLED
|
---|
510 | /*
|
---|
511 | * Log important stuff before entering GC.
|
---|
512 | */
|
---|
513 | if (TRPMHasTrap(pVCpu))
|
---|
514 | Log(("CPU%d: Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", pVCpu->idCpu, TRPMGetTrapNo(pVCpu), pCtx->cs, (RTGCPTR)pCtx->rip));
|
---|
515 |
|
---|
516 | uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
|
---|
517 |
|
---|
518 | if (pVM->cCPUs == 1)
|
---|
519 | {
|
---|
520 | if (pCtx->eflags.Bits.u1VM)
|
---|
521 | Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
|
---|
522 | else if (CPUMIsGuestIn64BitCodeEx(pCtx))
|
---|
523 | Log(("HWR%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
|
---|
524 | else
|
---|
525 | Log(("HWR%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
|
---|
526 | }
|
---|
527 | else
|
---|
528 | {
|
---|
529 | if (pCtx->eflags.Bits.u1VM)
|
---|
530 | Log(("HWV86-CPU%d: %08X IF=%d\n", pVCpu->idCpu, pCtx->eip, pCtx->eflags.Bits.u1IF));
|
---|
531 | else if (CPUMIsGuestIn64BitCodeEx(pCtx))
|
---|
532 | Log(("HWR%d-CPU%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
|
---|
533 | else
|
---|
534 | Log(("HWR%d-CPU%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
|
---|
535 | }
|
---|
536 | #endif /* LOG_ENABLED */
|
---|
537 |
|
---|
538 | /*
|
---|
539 | * Execute the code.
|
---|
540 | */
|
---|
541 | STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatHwAccEntry, a);
|
---|
542 | STAM_PROFILE_START(&pVCpu->em.s.StatHwAccExec, x);
|
---|
543 | rc = VMMR3HwAccRunGC(pVM, pVCpu);
|
---|
544 | STAM_PROFILE_STOP(&pVCpu->em.s.StatHwAccExec, x);
|
---|
545 |
|
---|
546 | /*
|
---|
547 | * Deal with high priority post execution FFs before doing anything else.
|
---|
548 | */
|
---|
549 | VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
|
---|
550 | if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
|
---|
551 | || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
|
---|
552 | rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
|
---|
553 |
|
---|
554 | /*
|
---|
555 | * Process the returned status code.
|
---|
556 | */
|
---|
557 | if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
|
---|
558 | break;
|
---|
559 |
|
---|
560 | rc = emR3HwaccmHandleRC(pVM, pVCpu, pCtx, rc);
|
---|
561 | if (rc != VINF_SUCCESS)
|
---|
562 | break;
|
---|
563 |
|
---|
564 | /*
|
---|
565 | * Check and execute forced actions.
|
---|
566 | */
|
---|
567 | #ifdef VBOX_HIGH_RES_TIMERS_HACK
|
---|
568 | TMTimerPollVoid(pVM, pVCpu);
|
---|
569 | #endif
|
---|
570 | if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK)
|
---|
571 | || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_MASK))
|
---|
572 | {
|
---|
573 | rc = emR3ForcedActions(pVM, pVCpu, rc);
|
---|
574 | if ( rc != VINF_SUCCESS
|
---|
575 | && rc != VINF_EM_RESCHEDULE_HWACC)
|
---|
576 | {
|
---|
577 | *pfFFDone = true;
|
---|
578 | break;
|
---|
579 | }
|
---|
580 | }
|
---|
581 | }
|
---|
582 |
|
---|
583 | /*
|
---|
584 | * Return to outer loop.
|
---|
585 | */
|
---|
586 | #if defined(LOG_ENABLED) && defined(DEBUG)
|
---|
587 | RTLogFlush(NULL);
|
---|
588 | #endif
|
---|
589 | return rc;
|
---|
590 | }
|
---|
591 |
|
---|
592 |
|
---|