HWACCM.cpp@ 15747

Last change on this file since 15747 was 15737, checked in by vboxsync, 16 years ago
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1	/* $Id: HWACCM.cpp 15737 2008-12-23 16:49:38Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_HWACCM
26	#include <VBox/cpum.h>
27	#include <VBox/stam.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/trpm.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/patm.h>
34	#include <VBox/csam.h>
35	#include <VBox/selm.h>
36	#include <VBox/rem.h>
37	#include <VBox/hwacc_vmx.h>
38	#include <VBox/hwacc_svm.h>
39	#include "HWACCMInternal.h"
40	#include <VBox/vm.h>
41	#include <VBox/err.h>
42	#include <VBox/param.h>
43
44	#include <iprt/assert.h>
45	#include <VBox/log.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48	#include <iprt/thread.h>
49
50	/*******************************************************************************
51	* Global Variables *
52	*******************************************************************************/
53	#ifdef VBOX_WITH_STATISTICS
54	# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55	# define EXIT_REASON_NIL() NULL
56	/** Exit reason descriptions for VT-x, used to describe statistics. */
57	static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58	{
59	EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60	EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61	EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62	EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63	EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64	EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65	EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66	EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67	EXIT_REASON_NIL(),
68	EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69	EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70	EXIT_REASON_NIL(),
71	EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72	EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73	EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74	EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75	EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76	EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77	EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78	EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79	EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80	EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81	EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82	EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83	EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84	EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85	EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86	EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87	EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88	EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89	EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90	EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91	EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92	EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93	EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94	EXIT_REASON_NIL(),
95	EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96	EXIT_REASON_NIL(),
97	EXIT_REASON_NIL(),
98	EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99	EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100	EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101	EXIT_REASON_NIL(),
102	EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103	EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104	EXIT_REASON_NIL(),
105	EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106	EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107	EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108	EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109	EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110	EXIT_REASON_NIL(),
111	EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112	EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113	EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114	EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115	EXIT_REASON_NIL()
116	};
117	/** Exit reason descriptions for AMD-V, used to describe statistics. */
118	static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119	{
120	/** @todo fill in these. */
121	EXIT_REASON_NIL()
122	};
123	# undef EXIT_REASON
124	# undef EXIT_REASON_NIL
125	#endif /* VBOX_WITH_STATISTICS */
126
127	/*******************************************************************************
128	* Internal Functions *
129	*******************************************************************************/
130	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
131	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
132
133
134	/**
135	* Initializes the HWACCM.
136	*
137	* @returns VBox status code.
138	* @param pVM The VM to operate on.
139	*/
140	VMMR3DECL(int) HWACCMR3Init(PVM pVM)
141	{
142	LogFlow(("HWACCMR3Init\n"));
143
144	/*
145	* Assert alignment and sizes.
146	*/
147	AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
148	AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
149
150	/* Some structure checks. */
151	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
152	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
153	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
154	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
155
156	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
157	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
158	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
159	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
160	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
161	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
162	AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
163
164
165	/*
166	* Register the saved state data unit.
167	*/
168	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
169	NULL, hwaccmR3Save, NULL,
170	NULL, hwaccmR3Load, NULL);
171	if (RT_FAILURE(rc))
172	return rc;
173
174	/* Misc initialisation. */
175	pVM->hwaccm.s.vmx.fSupported = false;
176	pVM->hwaccm.s.svm.fSupported = false;
177	pVM->hwaccm.s.vmx.fEnabled = false;
178	pVM->hwaccm.s.svm.fEnabled = false;
179
180	pVM->hwaccm.s.fActive = false;
181	pVM->hwaccm.s.fNestedPaging = false;
182
183	/* Disabled by default. */
184	pVM->fHWACCMEnabled = false;
185
186	/*
187	* Check CFGM options.
188	*/
189	PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
190	PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
191	/* Nested paging: disabled by default. */
192	rc = CFGMR3QueryBoolDef(pRoot, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
193	AssertRC(rc);
194
195	/* VT-x VPID: disabled by default. */
196	rc = CFGMR3QueryBoolDef(pRoot, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
197	AssertRC(rc);
198
199	/* HWACCM support must be explicitely enabled in the configuration file. */
200	rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
201	AssertRC(rc);
202
203	#ifdef RT_OS_DARWIN
204	if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
205	#else
206	if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
207	#endif
208	{
209	AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
210	VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
211	return VERR_HWACCM_CONFIG_MISMATCH;
212	}
213
214	if (VMMIsHwVirtExtForced(pVM))
215	pVM->fHWACCMEnabled = true;
216
217	#if HC_ARCH_BITS == 32
218	/* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
219	* (To use the default, don't set 64bitEnabled in CFGM.) */
220	rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
221	AssertLogRelRCReturn(rc, rc);
222	if (pVM->hwaccm.s.fAllow64BitGuests)
223	{
224	# ifdef RT_OS_DARWIN
225	if (!VMMIsHwVirtExtForced(pVM))
226	# else
227	if (!pVM->hwaccm.s.fAllowed)
228	# endif
229	return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling VT-x.");
230	}
231	#else
232	/* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
233	* via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
234	rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
235	AssertLogRelRCReturn(rc, rc);
236	#endif
237
238	return VINF_SUCCESS;
239	}
240
241	/**
242	* Initializes the per-VCPU HWACCM.
243	*
244	* @returns VBox status code.
245	* @param pVM The VM to operate on.
246	*/
247	VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
248	{
249	LogFlow(("HWACCMR3InitCPU\n"));
250
251	#ifdef VBOX_WITH_STATISTICS
252	/*
253	* Statistics.
254	*/
255	for (unsigned i=0;i<pVM->cCPUs;i++)
256	{
257	PVMCPU pVCpu = &pVM->aCpus[i];
258	int rc;
259
260	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
261	"/PROF/HWACCM/CPU%d/SwitchToGC", i);
262	AssertRC(rc);
263	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
264	"/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
265	AssertRC(rc);
266	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
267	"/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
268	AssertRC(rc);
269	# if 1 /* temporary for tracking down darwin holdup. */
270	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
271	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
272	AssertRC(rc);
273	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
274	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
275	AssertRC(rc);
276	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
277	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
278	AssertRC(rc);
279	# endif
280	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
281	"/PROF/HWACCM/CPU%d/InGC", i);
282	AssertRC(rc);
283
284	# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
285	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
286	"/PROF/HWACCM/CPU%d/Switcher3264", i);
287	AssertRC(rc);
288	# endif
289
290	# define HWACCM_REG_COUNTER(a, b) \
291	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
292	AssertRC(rc);
293
294	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
295	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
296	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
297	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
298	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
299	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
300	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
301	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
302	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
303	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
304	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
305	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
306	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
307	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
308	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
309	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
310	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
311	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
312	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
313	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
314	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
315	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
316	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
317	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
318	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
319
320	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
321	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
322
323	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
324	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
325	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
326
327	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
328	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
329	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
330	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
331	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
332	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
333	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
334	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
335	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
336
337	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
338	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
339
340	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
341	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
342	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
343
344	for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
345	{
346	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
347	"/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
348	AssertRC(rc);
349	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
350	"/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
351	AssertRC(rc);
352	}
353
354	#undef HWACCM_REG_COUNTER
355
356	pVCpu->hwaccm.s.paStatExitReason = NULL;
357
358	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
359	AssertRC(rc);
360	if (RT_SUCCESS(rc))
361	{
362	const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
363	for (int j=0;j<MAX_EXITREASON_STAT;j++)
364	{
365	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
366	papszDesc[j] ? papszDesc[j] : "Exit reason",
367	"/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
368	AssertRC(rc);
369	}
370	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
371	AssertRC(rc);
372	}
373	pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
374	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
375	Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
376	# else
377	Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
378	# endif
379	}
380	#endif /* VBOX_WITH_STATISTICS */
381	return VINF_SUCCESS;
382	}
383
384	/**
385	* Turns off normal raw mode features
386	*
387	* @param pVM The VM to operate on.
388	*/
389	static void hwaccmR3DisableRawMode(PVM pVM)
390	{
391	/* Disable PATM & CSAM. */
392	PATMR3AllowPatching(pVM, false);
393	CSAMDisableScanning(pVM);
394
395	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
396	SELMR3DisableMonitoring(pVM);
397	TRPMR3DisableMonitoring(pVM);
398
399	/* The hidden selector registers are now valid. */
400	CPUMSetHiddenSelRegsValid(pVM, true);
401
402	/* Disable the switcher code (safety precaution). */
403	VMMR3DisableSwitcher(pVM);
404
405	/* Disable mapping of the hypervisor into the shadow page table. */
406	PGMR3ChangeShwPDMappings(pVM, false);
407
408	/* Disable the switcher */
409	VMMR3DisableSwitcher(pVM);
410
411	if (pVM->hwaccm.s.fNestedPaging)
412	{
413	/* Reinit the paging mode to force the new shadow mode. */
414	PGMR3ChangeMode(pVM, PGMMODE_REAL);
415	}
416	}
417
418	/**
419	* Initialize VT-x or AMD-V.
420	*
421	* @returns VBox status code.
422	* @param pVM The VM handle.
423	*/
424	VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
425	{
426	int rc;
427
428	if ( !pVM->hwaccm.s.vmx.fSupported
429	&& !pVM->hwaccm.s.svm.fSupported)
430	{
431	LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
432	LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
433	#ifdef RT_OS_DARWIN
434	if (VMMIsHwVirtExtForced(pVM))
435	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
436	#endif
437	return VINF_SUCCESS;
438	}
439
440	/*
441	* Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
442	* because it turns off paging, which is not allowed in VMX root mode.
443	*
444	* To simplify matters we'll just force all running VMs to either use raw or VT-x mode. No mixing allowed in the VT-x case.
445	* There's no such problem with AMD-V. (@todo)
446	*
447	*/
448	/* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
449	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
450	if (RT_FAILURE(rc))
451	{
452	LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
453	LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
454
455	#ifdef RT_OS_DARWIN
456	/*
457	* This is 100% fatal if we didn't prepare for a HwVirtExt setup because of
458	* missing ring-0 allocations. For VMs that require HwVirtExt it doesn't normally
459	* make sense to try run them in software mode, so fail that too.
460	*/
461	if (VMMIsHwVirtExtForced(pVM))
462	VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to "
463	"simultaneously use VT-x.");
464	else
465	VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not "
466	"allowed to simultaneously use software virtualization.");
467	return rc;
468
469	#else /* !RT_OS_DARWIN */
470
471	/* Invert the selection */
472	pVM->hwaccm.s.fAllowed ^= 1;
473	if (pVM->hwaccm.s.fAllowed)
474	{
475	if (pVM->hwaccm.s.vmx.fSupported)
476	VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not allowed "
477	"to simultaneously use software virtualization.\n");
478	else
479	VM_SET_ERROR(pVM, rc, "An active VM already uses AMD-V hardware acceleration. It is not allowed to "
480	"simultaneously use software virtualization.\n");
481	}
482	else
483	VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to simultaneously "
484	"use VT-x or AMD-V.\n");
485	return rc;
486	#endif /* !RT_OS_DARWIN */
487	}
488
489	if (pVM->hwaccm.s.fAllowed == false)
490	return VINF_SUCCESS; /* disabled */
491
492	Assert(!pVM->fHWACCMEnabled \|\| VMMIsHwVirtExtForced(pVM));
493
494	if (pVM->hwaccm.s.vmx.fSupported)
495	{
496	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
497
498	if ( pVM->hwaccm.s.fInitialized == false
499	&& pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
500	{
501	uint64_t val;
502	RTGCPHYS GCPhys = 0;
503
504	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
505	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
506	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
507	LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
508	LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
509	LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
510	LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
511	LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
512
513	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
514	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
515	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
516	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
517	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
518	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
519	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
520	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
521	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
522	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
523	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
524	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
525	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT must be set\n"));
526	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
527	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT must be set\n"));
528	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
529	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI must be set\n"));
530	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
531	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER must be set\n"));
532
533	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
534	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
535	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
536	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
537	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
538	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
539	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
540	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
541	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
542	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
543	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
544	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
545	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
546	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
547	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
548	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
549	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
550	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
551	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
552	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
553	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
554	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
555	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
556	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
557	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
558	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
559	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
560	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
561	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
562	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
563	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
564	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
565	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
566	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
567	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
568	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
569	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
570	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
571	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
572	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
573	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
574	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
575
576	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
577	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
578	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT must be set\n"));
579	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
580	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET must be set\n"));
581	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
582	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT must be set\n"));
583	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
584	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT must be set\n"));
585	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
586	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT must be set\n"));
587	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
588	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT must be set\n"));
589	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
590	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT must be set\n"));
591	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
592	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT must be set\n"));
593	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
594	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT must be set\n"));
595	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
596	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT must be set\n"));
597	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
598	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT must be set\n"));
599	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
600	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW must be set\n"));
601	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
602	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT must be set\n"));
603	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
604	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT must be set\n"));
605	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
606	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS must be set\n"));
607	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
608	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG must be set\n"));
609	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
610	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS must be set\n"));
611	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
612	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT must be set\n"));
613	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
614	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT must be set\n"));
615	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
616	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL must be set\n"));
617
618	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
619	{
620	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
621	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
622	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
623	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
624	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
625	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
626	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
627	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
628	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
629	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
630
631	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
632	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
633	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC must be set\n"));
634	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
635	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT must be set\n"));
636	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
637	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID must be set\n"));
638	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
639	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT must be set\n"));
640	}
641
642	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
643	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
644	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
645	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
646	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
647	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
648	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
649	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
650	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
651	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
652	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
653	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
654	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
655	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
656	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
657	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
658	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
659	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
660	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG must be set\n"));
661	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
662	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE must be set\n"));
663	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
664	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM must be set\n"));
665	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
666	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON must be set\n"));
667	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
668	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR must be set\n"));
669	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
670	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR must be set\n"));
671	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
672	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR must be set\n"));
673
674	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
675	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
676	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
677	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
678	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
679	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
680	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
681	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
682	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
683	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
684	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
685	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
686	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
687	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
688	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
689	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
690	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
691	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
692	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
693	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
694	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG must be set\n"));
695	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
696	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 must be set\n"));
697	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
698	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ must be set\n"));
699	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
700	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR must be set\n"));
701	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
702	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR must be set\n"));
703	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
704	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR must be set\n"));
705	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
706	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR must be set\n"));
707	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
708	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER must be set\n"));
709
710	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
711	{
712	LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
713
714	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
715	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
716	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
717	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
718	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
719	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
720	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
721	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
722	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
723	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
724	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
725	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
726	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
727	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
728	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
729	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
730	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
731	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
732	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
733	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
734	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
735	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
736	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
737	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
738	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
739	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
740	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
741	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
742	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
743	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
744	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
745	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
746	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
747	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
748	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
749	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
750	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
751	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
752	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
753	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
754	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
755	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
756	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
757	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
758	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
759	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
760	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
761	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
762	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
763	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
764	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
765	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
766	}
767
768	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
769	LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
770	LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
771	LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
772	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
773	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
774
775	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
776	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
777	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
778	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
779	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
780
781	LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
782	LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
783
784	for (unsigned i=0;i<pVM->cCPUs;i++)
785	LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
786
787	#ifdef HWACCM_VTX_WITH_EPT
788	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
789	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
790	#endif /* HWACCM_VTX_WITH_EPT */
791	#ifdef HWACCM_VTX_WITH_VPID
792	if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
793	&& !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
794	pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
795	#endif /* HWACCM_VTX_WITH_VPID */
796
797	/* Only try once. */
798	pVM->hwaccm.s.fInitialized = true;
799
800	/* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
801	#if 1
802	rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
803	#else
804	rc = VERR_NO_MEMORY; /* simulation of no VMMDev Heap. */
805	#endif
806	if (RT_SUCCESS(rc))
807	{
808	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
809	ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
810	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
811	/* Bit set to 0 means redirection enabled. */
812	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
813	/* Allow all port IO, so the VT-x IO intercepts do their job. */
814	memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
815	((unsigned char )pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
816
817	/* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
818	* real and protected mode without paging with EPT.
819	*/
820	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
821	for (unsigned i=0;i<X86_PG_ENTRIES;i++)
822	{
823	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
824	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_G;
825	}
826
827	/* We convert it here every time as pci regions could be reconfigured. */
828	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
829	AssertRC(rc);
830	LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
831
832	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
833	AssertRC(rc);
834	LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
835	}
836	else
837	{
838	LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
839	pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
840	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
841	}
842
843	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
844	AssertRC(rc);
845	if (rc == VINF_SUCCESS)
846	{
847	pVM->fHWACCMEnabled = true;
848	pVM->hwaccm.s.vmx.fEnabled = true;
849	hwaccmR3DisableRawMode(pVM);
850
851	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
852	#ifdef VBOX_ENABLE_64_BITS_GUESTS
853	if (pVM->hwaccm.s.fAllow64BitGuests)
854	{
855	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
856	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
857	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
858	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
859	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
860	}
861	LogRel((pVM->hwaccm.s.fAllow64BitGuests
862	? "HWACCM: 32-bit and 64-bit guest supported.\n"
863	: "HWACCM: 32-bit guest supported.\n"));
864	#else
865	LogRel(("HWACCM: 32-bit guest supported.\n"));
866	#endif
867	LogRel(("HWACCM: VMX enabled!\n"));
868	if (pVM->hwaccm.s.fNestedPaging)
869	{
870	LogRel(("HWACCM: Enabled nested paging\n"));
871	LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetEPTCR3(pVM)));
872	}
873	if (pVM->hwaccm.s.vmx.fVPID)
874	LogRel(("HWACCM: Enabled VPID\n"));
875
876	if ( pVM->hwaccm.s.fNestedPaging
877	\|\| pVM->hwaccm.s.vmx.fVPID)
878	{
879	LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
880	LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
881	}
882	}
883	else
884	{
885	LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
886	LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
887	pVM->fHWACCMEnabled = false;
888	}
889	}
890	}
891	else
892	if (pVM->hwaccm.s.svm.fSupported)
893	{
894	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
895
896	if (pVM->hwaccm.s.fInitialized == false)
897	{
898	/* Erratum 170 which requires a forced TLB flush for each world switch:
899	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
900	*
901	* All BH-G1/2 and DH-G1/2 models include a fix:
902	* Athlon X2: 0x6b 1/2
903	* 0x68 1/2
904	* Athlon 64: 0x7f 1
905	* 0x6f 2
906	* Sempron: 0x7f 1/2
907	* 0x6f 2
908	* 0x6c 2
909	* 0x7c 2
910	* Turion 64: 0x68 2
911	*
912	*/
913	uint32_t u32Dummy;
914	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
915	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
916	u32BaseFamily= (u32Version >> 8) & 0xf;
917	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
918	u32Model = ((u32Version >> 4) & 0xf);
919	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
920	u32Stepping = u32Version & 0xf;
921	if ( u32Family == 0xf
922	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
923	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
924	{
925	LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
926	}
927
928	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
929	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
930	LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
931	LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
932	LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
933
934	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
935	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
936	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
937	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
938	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
939	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
940	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
941	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
942	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
943	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
944
945	/* Only try once. */
946	pVM->hwaccm.s.fInitialized = true;
947
948	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
949	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
950
951	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
952	AssertRC(rc);
953	if (rc == VINF_SUCCESS)
954	{
955	pVM->fHWACCMEnabled = true;
956	pVM->hwaccm.s.svm.fEnabled = true;
957
958	if (pVM->hwaccm.s.fNestedPaging)
959	LogRel(("HWACCM: Enabled nested paging\n"));
960
961	hwaccmR3DisableRawMode(pVM);
962	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
963	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
964	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
965	#ifdef VBOX_ENABLE_64_BITS_GUESTS
966	if (pVM->hwaccm.s.fAllow64BitGuests)
967	{
968	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
969	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
970	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
971	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
972	}
973	#endif
974	LogRel((pVM->hwaccm.s.fAllow64BitGuests
975	? "HWACCM: 32-bit and 64-bit guest supported.\n"
976	: "HWACCM: 32-bit guest supported.\n"));
977	}
978	else
979	{
980	pVM->fHWACCMEnabled = false;
981	}
982	}
983	}
984	return VINF_SUCCESS;
985	}
986
987	/**
988	* Applies relocations to data and code managed by this
989	* component. This function will be called at init and
990	* whenever the VMM need to relocate it self inside the GC.
991	*
992	* @param pVM The VM.
993	*/
994	VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
995	{
996	Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
997
998	/* Fetch the current paging mode during the relocate callback during state loading. */
999	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1000	{
1001	for (unsigned i=0;i<pVM->cCPUs;i++)
1002	{
1003	PVMCPU pVCpu = &pVM->aCpus[i];
1004	/* @todo SMP */
1005	pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVM);
1006	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMGetGuestMode(pVM);
1007	}
1008	}
1009	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1010	if (pVM->fHWACCMEnabled)
1011	{
1012	int rc;
1013
1014	switch(PGMGetHostMode(pVM))
1015	{
1016	case PGMMODE_32_BIT:
1017	pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1018	break;
1019
1020	case PGMMODE_PAE:
1021	case PGMMODE_PAE_NX:
1022	pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1023	break;
1024
1025	default:
1026	AssertFailed();
1027	break;
1028	}
1029	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1030	AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1031
1032	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1033	AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1034
1035	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1036	AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1037
1038	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1039	AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1040
1041	# ifdef DEBUG
1042	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1043	AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1044	# endif
1045	}
1046	#endif
1047	return;
1048	}
1049
1050	/**
1051	* Checks hardware accelerated raw mode is allowed.
1052	*
1053	* @returns boolean
1054	* @param pVM The VM to operate on.
1055	*/
1056	VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1057	{
1058	return pVM->hwaccm.s.fAllowed;
1059	}
1060
1061	/**
1062	* Notification callback which is called whenever there is a chance that a CR3
1063	* value might have changed.
1064	*
1065	* This is called by PGM.
1066	*
1067	* @param pVM The VM to operate on.
1068	* @param enmShadowMode New shadow paging mode.
1069	* @param enmGuestMode New guest paging mode.
1070	*/
1071	VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1072	{
1073	/* Ignore page mode changes during state loading. */
1074	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1075	return;
1076
1077	PVMCPU pVCpu = VMMGetCpu(pVM);
1078	pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1079
1080	if ( pVM->hwaccm.s.vmx.fEnabled
1081	&& pVM->fHWACCMEnabled)
1082	{
1083	if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1084	&& enmGuestMode >= PGMMODE_PROTECTED)
1085	{
1086	PCPUMCTX pCtx;
1087
1088	pCtx = CPUMQueryGuestCtxPtr(pVM);
1089
1090	/* After a real mode switch to protected mode we must force
1091	* CPL to 0. Our real mode emulation had to set it to 3.
1092	*/
1093	pCtx->ssHid.Attr.n.u2Dpl = 0;
1094	}
1095	}
1096
1097	if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1098	{
1099	/* Keep track of paging mode changes. */
1100	pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1101	pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1102
1103	/* Did we miss a change, because all code was executed in the recompiler? */
1104	if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1105	{
1106	Log(("HWACCMR3PagingModeChanged missed %s->%s transition (last seen %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1107	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1108	}
1109	}
1110
1111	/* Reset the contents of the read cache. */
1112	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1113	for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1114	pCache->Read.aFieldVal[j] = 0;
1115	}
1116
1117	/**
1118	* Terminates the HWACCM.
1119	*
1120	* Termination means cleaning up and freeing all resources,
1121	* the VM it self is at this point powered off or suspended.
1122	*
1123	* @returns VBox status code.
1124	* @param pVM The VM to operate on.
1125	*/
1126	VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1127	{
1128	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1129	{
1130	PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1131	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1132	}
1133	return 0;
1134	}
1135
1136	/**
1137	* Terminates the per-VCPU HWACCM.
1138	*
1139	* Termination means cleaning up and freeing all resources,
1140	* the VM it self is at this point powered off or suspended.
1141	*
1142	* @returns VBox status code.
1143	* @param pVM The VM to operate on.
1144	*/
1145	VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1146	{
1147	for (unsigned i=0;i<pVM->cCPUs;i++)
1148	{
1149	PVMCPU pVCpu = &pVM->aCpus[i];
1150
1151	if (pVCpu->hwaccm.s.paStatExitReason)
1152	{
1153	MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1154	pVCpu->hwaccm.s.paStatExitReason = NULL;
1155	pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1156	}
1157	}
1158	return 0;
1159	}
1160
1161	/**
1162	* The VM is being reset.
1163	*
1164	* For the HWACCM component this means that any GDT/LDT/TSS monitors
1165	* needs to be removed.
1166	*
1167	* @param pVM VM handle.
1168	*/
1169	VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1170	{
1171	LogFlow(("HWACCMR3Reset:\n"));
1172
1173	if (pVM->fHWACCMEnabled)
1174	hwaccmR3DisableRawMode(pVM);
1175
1176	for (unsigned i=0;i<pVM->cCPUs;i++)
1177	{
1178	PVMCPU pVCpu = &pVM->aCpus[i];
1179
1180	/* On first entry we'll sync everything. */
1181	pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1182
1183	pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1184	pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1185
1186	pVCpu->hwaccm.s.Event.fPending = false;
1187
1188	/* Reset state information for real-mode emulation in VT-x. */
1189	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1190	pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1191	pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1192
1193	/* Reset the contents of the read cache. */
1194	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1195	for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1196	pCache->Read.aFieldVal[j] = 0;
1197
1198	/* Magic marker for searching in crash dumps. */
1199	strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1200
1201	}
1202	}
1203
1204	/**
1205	* Checks if we can currently use hardware accelerated raw mode.
1206	*
1207	* @returns boolean
1208	* @param pVM The VM to operate on.
1209	* @param pCtx Partial VM execution context
1210	*/
1211	VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
1212	{
1213	Assert(pVM->fHWACCMEnabled);
1214
1215	/* AMD SVM supports real & protected mode with or without paging. */
1216	if (pVM->hwaccm.s.svm.fEnabled)
1217	{
1218	pVM->hwaccm.s.fActive = true;
1219	return true;
1220	}
1221
1222	pVM->hwaccm.s.fActive = false;
1223
1224	/* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
1225	#ifdef HWACCM_VMX_EMULATE_REALMODE
1226	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1227	{
1228	if (CPUMIsGuestInRealModeEx(pCtx))
1229	{
1230	/* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
1231	* The base must also be equal to (sel << 4).
1232	*/
1233	if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
1234	&& pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
1235	\|\| pCtx->ds != (pCtx->dsHid.u64Base >> 4)
1236	\|\| pCtx->es != (pCtx->esHid.u64Base >> 4)
1237	\|\| pCtx->fs != (pCtx->fsHid.u64Base >> 4)
1238	\|\| pCtx->gs != (pCtx->gsHid.u64Base >> 4)
1239	\|\| pCtx->ss != (pCtx->ssHid.u64Base >> 4))
1240	{
1241	return false;
1242	}
1243	}
1244	else
1245	{
1246	PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
1247	/* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
1248	* from real to protected mode. (all sorts of RPL & DPL assumptions)
1249	*/
1250	PVMCPU pVCpu = VMMGetCpu(pVM);
1251
1252	if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1253	&& enmGuestMode >= PGMMODE_PROTECTED)
1254	{
1255	if ( (pCtx->cs & X86_SEL_RPL)
1256	\|\| (pCtx->ds & X86_SEL_RPL)
1257	\|\| (pCtx->es & X86_SEL_RPL)
1258	\|\| (pCtx->fs & X86_SEL_RPL)
1259	\|\| (pCtx->gs & X86_SEL_RPL)
1260	\|\| (pCtx->ss & X86_SEL_RPL))
1261	{
1262	return false;
1263	}
1264	}
1265	}
1266	}
1267	else
1268	#endif /* HWACCM_VMX_EMULATE_REALMODE */
1269	{
1270	if (!CPUMIsGuestInLongModeEx(pCtx))
1271	{
1272	/** @todo This should (probably) be set on every excursion to the REM,
1273	* however it's too risky right now. So, only apply it when we go
1274	* back to REM for real mode execution. (The XP hack below doesn't
1275	* work reliably without this.)
1276	* Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
1277	pVM->aCpus[0].hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1278
1279	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
1280	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
1281	return false;
1282
1283	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
1284	/* Windows XP; switch to protected mode; all selectors are marked not present in the
1285	* hidden registers (possible recompiler bug; see load_seg_vm) */
1286	if (pCtx->csHid.Attr.n.u1Present == 0)
1287	return false;
1288	if (pCtx->ssHid.Attr.n.u1Present == 0)
1289	return false;
1290
1291	/* Windows XP: possible same as above, but new recompiler requires new heuristics?
1292	VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
1293	/** @todo This check is actually wrong, it doesn't take the direction of the
1294	* stack segment into account. But, it does the job for now. */
1295	if (pCtx->rsp >= pCtx->ssHid.u32Limit)
1296	return false;
1297	#if 0
1298	if ( pCtx->cs >= pCtx->gdtr.cbGdt
1299	\|\| pCtx->ss >= pCtx->gdtr.cbGdt
1300	\|\| pCtx->ds >= pCtx->gdtr.cbGdt
1301	\|\| pCtx->es >= pCtx->gdtr.cbGdt
1302	\|\| pCtx->fs >= pCtx->gdtr.cbGdt
1303	\|\| pCtx->gs >= pCtx->gdtr.cbGdt)
1304	return false;
1305	#endif
1306	}
1307	}
1308
1309	if (pVM->hwaccm.s.vmx.fEnabled)
1310	{
1311	uint32_t mask;
1312
1313	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
1314	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
1315	/* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
1316	mask &= ~X86_CR0_NE;
1317
1318	#ifdef HWACCM_VMX_EMULATE_REALMODE
1319	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1320	{
1321	/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
1322	mask &= ~(X86_CR0_PG\|X86_CR0_PE);
1323	}
1324	else
1325	#endif
1326	{
1327	/* We support protected mode without paging using identity mapping. */
1328	mask &= ~X86_CR0_PG;
1329	}
1330	if ((pCtx->cr0 & mask) != mask)
1331	return false;
1332
1333	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
1334	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
1335	if ((pCtx->cr0 & mask) != 0)
1336	return false;
1337
1338	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
1339	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1340	mask &= ~X86_CR4_VMXE;
1341	if ((pCtx->cr4 & mask) != mask)
1342	return false;
1343
1344	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
1345	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
1346	if ((pCtx->cr4 & mask) != 0)
1347	return false;
1348
1349	pVM->hwaccm.s.fActive = true;
1350	return true;
1351	}
1352
1353	return false;
1354	}
1355
1356	/**
1357	* Notifcation from EM about a rescheduling into hardware assisted execution
1358	* mode.
1359	*
1360	* @param pVCpu Pointer to the current virtual cpu structure.
1361	*/
1362	VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
1363	{
1364	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1365	}
1366
1367	/**
1368	* Notifcation from EM about returning from instruction emulation (REM / EM).
1369	*
1370	* @param pVCpu Pointer to the current virtual cpu structure.
1371	*/
1372	VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
1373	{
1374	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1375	}
1376
1377	/**
1378	* Checks if we are currently using hardware accelerated raw mode.
1379	*
1380	* @returns boolean
1381	* @param pVM The VM to operate on.
1382	*/
1383	VMMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
1384	{
1385	return pVM->hwaccm.s.fActive;
1386	}
1387
1388	/**
1389	* Checks if we are currently using nested paging.
1390	*
1391	* @returns boolean
1392	* @param pVM The VM to operate on.
1393	*/
1394	VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
1395	{
1396	return pVM->hwaccm.s.fNestedPaging;
1397	}
1398
1399	/**
1400	* Checks if we are currently using VPID in VT-x mode.
1401	*
1402	* @returns boolean
1403	* @param pVM The VM to operate on.
1404	*/
1405	VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
1406	{
1407	return pVM->hwaccm.s.vmx.fVPID;
1408	}
1409
1410
1411	/**
1412	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
1413	*
1414	* @returns boolean
1415	* @param pVM The VM to operate on.
1416	*/
1417	VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
1418	{
1419	/* @todo SMP */
1420	return HWACCMIsEnabled(pVM) && pVM->aCpus[0].hwaccm.s.Event.fPending;
1421	}
1422
1423
1424	/**
1425	* Inject an NMI into a running VM
1426	*
1427	* @returns boolean
1428	* @param pVM The VM to operate on.
1429	*/
1430	VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
1431	{
1432	pVM->hwaccm.s.fInjectNMI = true;
1433	return VINF_SUCCESS;
1434	}
1435
1436	/**
1437	* Check fatal VT-x/AMD-V error and produce some meaningful
1438	* log release message.
1439	*
1440	* @param pVM The VM to operate on.
1441	* @param iStatusCode VBox status code
1442	*/
1443	VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
1444	{
1445	for (unsigned i=0;i<pVM->cCPUs;i++)
1446	{
1447	switch(iStatusCode)
1448	{
1449	case VERR_VMX_INVALID_VMCS_FIELD:
1450	break;
1451
1452	case VERR_VMX_INVALID_VMCS_PTR:
1453	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1454	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
1455	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
1456	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
1457	break;
1458
1459	case VERR_VMX_UNABLE_TO_START_VM:
1460	LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1461	LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1462	#if 0 /* @todo dump the current control fields to the release log */
1463	if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
1464	{
1465
1466	}
1467	#endif
1468	break;
1469
1470	case VERR_VMX_UNABLE_TO_RESUME_VM:
1471	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1472	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1473	break;
1474
1475	case VERR_VMX_INVALID_VMXON_PTR:
1476	break;
1477	}
1478	}
1479	}
1480
1481	/**
1482	* Execute state save operation.
1483	*
1484	* @returns VBox status code.
1485	* @param pVM VM Handle.
1486	* @param pSSM SSM operation handle.
1487	*/
1488	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
1489	{
1490	int rc;
1491
1492	Log(("hwaccmR3Save:\n"));
1493
1494	for (unsigned i=0;i<pVM->cCPUs;i++)
1495	{
1496	/*
1497	* Save the basic bits - fortunately all the other things can be resynced on load.
1498	*/
1499	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
1500	AssertRCReturn(rc, rc);
1501	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
1502	AssertRCReturn(rc, rc);
1503	rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
1504	AssertRCReturn(rc, rc);
1505
1506	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
1507	AssertRCReturn(rc, rc);
1508	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
1509	AssertRCReturn(rc, rc);
1510	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
1511	AssertRCReturn(rc, rc);
1512	}
1513
1514	return VINF_SUCCESS;
1515	}
1516
1517	/**
1518	* Execute state load operation.
1519	*
1520	* @returns VBox status code.
1521	* @param pVM VM Handle.
1522	* @param pSSM SSM operation handle.
1523	* @param u32Version Data layout version.
1524	*/
1525	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1526	{
1527	int rc;
1528
1529	Log(("hwaccmR3Load:\n"));
1530
1531	/*
1532	* Validate version.
1533	*/
1534	if ( u32Version != HWACCM_SSM_VERSION
1535	&& u32Version != HWACCM_SSM_VERSION_2_0_X)
1536	{
1537	AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
1538	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1539	}
1540	for (unsigned i=0;i<pVM->cCPUs;i++)
1541	{
1542	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
1543	AssertRCReturn(rc, rc);
1544	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
1545	AssertRCReturn(rc, rc);
1546	rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
1547	AssertRCReturn(rc, rc);
1548
1549	if (u32Version >= HWACCM_SSM_VERSION)
1550	{
1551	uint32_t val;
1552
1553	rc = SSMR3GetU32(pSSM, &val);
1554	AssertRCReturn(rc, rc);
1555	pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
1556
1557	rc = SSMR3GetU32(pSSM, &val);
1558	AssertRCReturn(rc, rc);
1559	pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
1560
1561	rc = SSMR3GetU32(pSSM, &val);
1562	AssertRCReturn(rc, rc);
1563	pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
1564	}
1565	}
1566	return VINF_SUCCESS;
1567	}
1568

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source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 15747

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