HWACCM.cpp@ 19979

Last change on this file since 19979 was 19908, checked in by vboxsync, 16 years ago
VMM/HWACCM: amd-v exit reasons for debugger description.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
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1	/* $Id: HWACCM.cpp 19908 2009-05-22 11:19:38Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_HWACCM
26	#include <VBox/cpum.h>
27	#include <VBox/stam.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/trpm.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/patm.h>
34	#include <VBox/csam.h>
35	#include <VBox/selm.h>
36	#include <VBox/rem.h>
37	#include <VBox/hwacc_vmx.h>
38	#include <VBox/hwacc_svm.h>
39	#include "HWACCMInternal.h"
40	#include <VBox/vm.h>
41	#include <VBox/err.h>
42	#include <VBox/param.h>
43
44	#include <iprt/assert.h>
45	#include <VBox/log.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48	#include <iprt/thread.h>
49
50	/*******************************************************************************
51	* Global Variables *
52	*******************************************************************************/
53	#ifdef VBOX_WITH_STATISTICS
54	# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55	# define EXIT_REASON_NIL() NULL
56	/** Exit reason descriptions for VT-x, used to describe statistics. */
57	static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58	{
59	EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60	EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61	EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62	EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63	EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64	EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65	EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66	EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67	EXIT_REASON_NIL(),
68	EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69	EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70	EXIT_REASON_NIL(),
71	EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72	EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73	EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74	EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75	EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76	EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77	EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78	EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79	EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80	EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81	EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82	EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83	EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84	EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85	EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86	EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87	EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88	EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89	EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90	EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91	EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92	EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93	EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94	EXIT_REASON_NIL(),
95	EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96	EXIT_REASON_NIL(),
97	EXIT_REASON_NIL(),
98	EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99	EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100	EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101	EXIT_REASON_NIL(),
102	EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103	EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104	EXIT_REASON_NIL(),
105	EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106	EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107	EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108	EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109	EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110	EXIT_REASON_NIL(),
111	EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112	EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113	EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114	EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115	EXIT_REASON_NIL()
116	};
117	/** Exit reason descriptions for AMD-V, used to describe statistics. */
118	static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119	{
120	EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
121	EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
122	EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
123	EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
124	EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
125	EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
126	EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
127	EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
128	EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
129	EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
130	EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
131	EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
132	EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
133	EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
134	EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
135	EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
136	EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
137	EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
138	EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
139	EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
140	EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
141	EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
142	EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
143	EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
144	EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
145	EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
146	EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
147	EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
148	EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
149	EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
150	EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
151	EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
152	EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
153	EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
154	EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
155	EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
156	EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
157	EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
158	EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
159	EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
160	EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
161	EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
162	EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
163	EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
164	EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
165	EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
166	EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
167	EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
168	EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
169	EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
170	EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
171	EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
172	EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
173	EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
174	EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
175	EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
176	EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
177	EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
178	EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
179	EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
180	EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
181	EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
182	EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
183	EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
184	EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
185	EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
186	EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
187	EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
188	EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
189	EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
190	EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
191	EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
192	EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
193	EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
194	EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
195	EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
196	EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
197	EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
198	EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
199	EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
200	EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
201	EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
202	EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
203	EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
204	EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
205	EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
206	EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
207	EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
208	EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
209	EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
210	EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
211	EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
212	EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
213	EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
214	EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
215	EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
216	EXIT_REASON(SVM_EXIT_EXCEPTION_INTR , 96, "Physical maskable interrupt."),
217	EXIT_REASON(SVM_EXIT_EXCEPTION_NMI , 97, "Physical non-maskable interrupt."),
218	EXIT_REASON(SVM_EXIT_EXCEPTION_SMI , 98, "System management interrupt."),
219	EXIT_REASON(SVM_EXIT_EXCEPTION_INIT , 99, "Physical INIT signal."),
220	EXIT_REASON(SVM_EXIT_EXCEPTION_VINTR ,100, "Visual interrupt."),
221	EXIT_REASON(SVM_EXIT_EXCEPTION_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
222	EXIT_REASON(SVM_EXIT_EXCEPTION_IDTR_READ ,102, "Read IDTR"),
223	EXIT_REASON(SVM_EXIT_EXCEPTION_GDTR_READ ,103, "Read GDTR"),
224	EXIT_REASON(SVM_EXIT_EXCEPTION_LDTR_READ ,104, "Read LDTR."),
225	EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,105, "Read TR."),
226	EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,106, "Write IDTR."),
227	EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,107, "Write GDTR."),
228	EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,108, "Write LDTR."),
229	EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,109, "Write TR."),
230	EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
231	EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
232	EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
233	EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
234	EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
235	EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
236	EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
237	EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
238	EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
239	EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
240	EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
241	EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
242	EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
243	EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
244	EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
245	EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
246	EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
247	EXIT_REASON(SVM_EXIT_TASK_SHUTDOWN ,127, "Shutdown."),
248	EXIT_REASON(SVM_EXIT_TASK_VMRUN ,128, "VMRUN instruction."),
249	EXIT_REASON(SVM_EXIT_TASK_VMCALL ,129, "VMCALL instruction."),
250	EXIT_REASON(SVM_EXIT_TASK_VMLOAD ,130, "VMLOAD instruction."),
251	EXIT_REASON(SVM_EXIT_TASK_VMSAVE ,131, "VMSAVE instruction."),
252	EXIT_REASON(SVM_EXIT_TASK_STGI ,132, "STGI instruction."),
253	EXIT_REASON(SVM_EXIT_TASK_CLGI ,133, "CLGI instruction."),
254	EXIT_REASON(SVM_EXIT_TASK_SKINIT ,134, "SKINIT instruction."),
255	EXIT_REASON(SVM_EXIT_TASK_RDTSCP ,135, "RDTSCP instruction."),
256	EXIT_REASON(SVM_EXIT_TASK_ICEBP ,136, "ICEBP instruction."),
257	EXIT_REASON(SVM_EXIT_TASK_WBINVD ,137, "WBINVD instruction."),
258	EXIT_REASON(SVM_EXIT_TASK_MONITOR ,138, "MONITOR instruction."),
259	EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
260	EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
261	EXIT_REASON(SVM_EXIT_MWAIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
262	EXIT_REASON_NIL()
263	};
264	# undef EXIT_REASON
265	# undef EXIT_REASON_NIL
266	#endif /* VBOX_WITH_STATISTICS */
267
268	/*******************************************************************************
269	* Internal Functions *
270	*******************************************************************************/
271	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
272	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
273
274
275	/**
276	* Initializes the HWACCM.
277	*
278	* @returns VBox status code.
279	* @param pVM The VM to operate on.
280	*/
281	VMMR3DECL(int) HWACCMR3Init(PVM pVM)
282	{
283	LogFlow(("HWACCMR3Init\n"));
284
285	/*
286	* Assert alignment and sizes.
287	*/
288	AssertCompileMemberAlignment(VM, hwaccm.s, 32);
289	AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
290
291	/* Some structure checks. */
292	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
293	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
294	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
295	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
296
297	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
298	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
299	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
300	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
301	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
302	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
303	AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
304
305
306	/*
307	* Register the saved state data unit.
308	*/
309	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
310	NULL, hwaccmR3Save, NULL,
311	NULL, hwaccmR3Load, NULL);
312	if (RT_FAILURE(rc))
313	return rc;
314
315	/* Misc initialisation. */
316	pVM->hwaccm.s.vmx.fSupported = false;
317	pVM->hwaccm.s.svm.fSupported = false;
318	pVM->hwaccm.s.vmx.fEnabled = false;
319	pVM->hwaccm.s.svm.fEnabled = false;
320
321	pVM->hwaccm.s.fNestedPaging = false;
322
323	/* Disabled by default. */
324	pVM->fHWACCMEnabled = false;
325
326	/*
327	* Check CFGM options.
328	*/
329	PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
330	PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
331	/* Nested paging: disabled by default. */
332	rc = CFGMR3QueryBoolDef(pRoot, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
333	AssertRC(rc);
334
335	/* VT-x VPID: disabled by default. */
336	rc = CFGMR3QueryBoolDef(pRoot, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
337	AssertRC(rc);
338
339	/* HWACCM support must be explicitely enabled in the configuration file. */
340	rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
341	AssertRC(rc);
342
343	#ifdef RT_OS_DARWIN
344	if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
345	#else
346	if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
347	#endif
348	{
349	AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
350	VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
351	return VERR_HWACCM_CONFIG_MISMATCH;
352	}
353
354	if (VMMIsHwVirtExtForced(pVM))
355	pVM->fHWACCMEnabled = true;
356
357	#if HC_ARCH_BITS == 32
358	/* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
359	* (To use the default, don't set 64bitEnabled in CFGM.) */
360	rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
361	AssertLogRelRCReturn(rc, rc);
362	if (pVM->hwaccm.s.fAllow64BitGuests)
363	{
364	# ifdef RT_OS_DARWIN
365	if (!VMMIsHwVirtExtForced(pVM))
366	# else
367	if (!pVM->hwaccm.s.fAllowed)
368	# endif
369	return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
370	}
371	#else
372	/* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
373	* via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
374	rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
375	AssertLogRelRCReturn(rc, rc);
376	#endif
377
378	return VINF_SUCCESS;
379	}
380
381	/**
382	* Initializes the per-VCPU HWACCM.
383	*
384	* @returns VBox status code.
385	* @param pVM The VM to operate on.
386	*/
387	VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
388	{
389	LogFlow(("HWACCMR3InitCPU\n"));
390
391	for (unsigned i=0;i<pVM->cCPUs;i++)
392	{
393	PVMCPU pVCpu = &pVM->aCpus[i];
394
395	pVCpu->hwaccm.s.fActive = false;
396	}
397
398	#ifdef VBOX_WITH_STATISTICS
399	/*
400	* Statistics.
401	*/
402	for (unsigned i=0;i<pVM->cCPUs;i++)
403	{
404	PVMCPU pVCpu = &pVM->aCpus[i];
405	int rc;
406
407	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
408	"/PROF/HWACCM/CPU%d/SwitchToGC", i);
409	AssertRC(rc);
410	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
411	"/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
412	AssertRC(rc);
413	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
414	"/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
415	AssertRC(rc);
416	# if 1 /* temporary for tracking down darwin holdup. */
417	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
418	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
419	AssertRC(rc);
420	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
421	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
422	AssertRC(rc);
423	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
424	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
425	AssertRC(rc);
426	# endif
427	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
428	"/PROF/HWACCM/CPU%d/InGC", i);
429	AssertRC(rc);
430
431	# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
432	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
433	"/PROF/HWACCM/CPU%d/Switcher3264", i);
434	AssertRC(rc);
435	# endif
436
437	# define HWACCM_REG_COUNTER(a, b) \
438	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
439	AssertRC(rc);
440
441	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
442	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
443	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
444	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
445	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
446	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
447	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
448	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
449	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
450	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
451	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
452	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
453	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
454	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
455	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
456	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
457	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
458	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
459	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
460	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
461	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
462	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
463	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
464	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
465	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
466	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
467	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
468	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
469	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
470	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
471	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
472	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
473	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
474	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
475	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
476	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
477
478	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
479	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
480
481	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
482	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
483	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
484
485	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
486	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
487	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
488	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
489	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
490	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
491	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
492	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
493	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
494	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
495	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
496
497	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
498	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
499
500	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
501	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
502	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
503
504	for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
505	{
506	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
507	"/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
508	AssertRC(rc);
509	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
510	"/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
511	AssertRC(rc);
512	}
513
514	#undef HWACCM_REG_COUNTER
515
516	pVCpu->hwaccm.s.paStatExitReason = NULL;
517
518	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
519	AssertRC(rc);
520	if (RT_SUCCESS(rc))
521	{
522	const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
523	for (int j=0;j<MAX_EXITREASON_STAT;j++)
524	{
525	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
526	papszDesc[j] ? papszDesc[j] : "Exit reason",
527	"/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
528	AssertRC(rc);
529	}
530	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
531	AssertRC(rc);
532	}
533	pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
534	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
535	Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
536	# else
537	Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
538	# endif
539	}
540	#endif /* VBOX_WITH_STATISTICS */
541
542	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
543	/* Magic marker for searching in crash dumps. */
544	for (unsigned i=0;i<pVM->cCPUs;i++)
545	{
546	PVMCPU pVCpu = &pVM->aCpus[i];
547
548	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
549	strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
550	pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
551	}
552	#endif
553	return VINF_SUCCESS;
554	}
555
556	/**
557	* Turns off normal raw mode features
558	*
559	* @param pVM The VM to operate on.
560	*/
561	static void hwaccmR3DisableRawMode(PVM pVM)
562	{
563	/* Disable PATM & CSAM. */
564	PATMR3AllowPatching(pVM, false);
565	CSAMDisableScanning(pVM);
566
567	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
568	SELMR3DisableMonitoring(pVM);
569	TRPMR3DisableMonitoring(pVM);
570
571	/* Disable the switcher code (safety precaution). */
572	VMMR3DisableSwitcher(pVM);
573
574	/* Disable mapping of the hypervisor into the shadow page table. */
575	PGMR3MappingsDisable(pVM);
576
577	/* Disable the switcher */
578	VMMR3DisableSwitcher(pVM);
579
580	/* Reinit the paging mode to force the new shadow mode. */
581	for (unsigned i=0;i<pVM->cCPUs;i++)
582	{
583	PVMCPU pVCpu = &pVM->aCpus[i];
584
585	PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
586	}
587	}
588
589	/**
590	* Initialize VT-x or AMD-V.
591	*
592	* @returns VBox status code.
593	* @param pVM The VM handle.
594	*/
595	VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
596	{
597	int rc;
598
599	if ( !pVM->hwaccm.s.vmx.fSupported
600	&& !pVM->hwaccm.s.svm.fSupported)
601	{
602	LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
603	LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
604	if (VMMIsHwVirtExtForced(pVM))
605	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
606	return VINF_SUCCESS;
607	}
608
609	if (!pVM->hwaccm.s.fAllowed)
610	return VINF_SUCCESS; /* nothing to do */
611
612	/* Enable VT-x or AMD-V on all host CPUs. */
613	rc = SUPCallVMMR0Ex(pVM->pVMR0, 0 /* VCPU 0 */, VMMR0_DO_HWACC_ENABLE, 0, NULL);
614	if (RT_FAILURE(rc))
615	{
616	LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
617	return rc;
618	}
619	Assert(!pVM->fHWACCMEnabled \|\| VMMIsHwVirtExtForced(pVM));
620
621	if (pVM->hwaccm.s.vmx.fSupported)
622	{
623	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
624
625	if ( pVM->hwaccm.s.fInitialized == false
626	&& pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
627	{
628	uint64_t val;
629	RTGCPHYS GCPhys = 0;
630
631	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
632	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
633	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
634	LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
635	LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
636	LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
637	LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
638	LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
639
640	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
641	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
642	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
643	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
644	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
645	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
646	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
647	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
648	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
649	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
650	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
651	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
652	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT must be set\n"));
653	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
654	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT must be set\n"));
655	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
656	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI must be set\n"));
657	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
658	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER must be set\n"));
659
660	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
661	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
662	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
663	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
664	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
665	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
666	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
667	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
668	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
669	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
670	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
671	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
672	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
673	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
674	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
675	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
676	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
677	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
678	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
679	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
680	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
681	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
682	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
683	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
684	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
685	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
686	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
687	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
688	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
689	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
690	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
691	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
692	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
693	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
694	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
695	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
696	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
697	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
698	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
699	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
700	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
701	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
702	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
703	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
704
705	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
706	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
707	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT must be set\n"));
708	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
709	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET must be set\n"));
710	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
711	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT must be set\n"));
712	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
713	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT must be set\n"));
714	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
715	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT must be set\n"));
716	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
717	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT must be set\n"));
718	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
719	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT must be set\n"));
720	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
721	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT must be set\n"));
722	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
723	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT must be set\n"));
724	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
725	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT must be set\n"));
726	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
727	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT must be set\n"));
728	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
729	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW must be set\n"));
730	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
731	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT must be set\n"));
732	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
733	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT must be set\n"));
734	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
735	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT must be set\n"));
736	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
737	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS must be set\n"));
738	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
739	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG must be set\n"));
740	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
741	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS must be set\n"));
742	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
743	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT must be set\n"));
744	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
745	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT must be set\n"));
746	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
747	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL must be set\n"));
748
749	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
750	{
751	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
752	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
753	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
754	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
755	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
756	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
757	if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
758	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
759	if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
760	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
761	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
762	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
763	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
764	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
765
766	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
767	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
768	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC must be set\n"));
769	if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
770	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT must be set\n"));
771	if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
772	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC must be set\n"));
773	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
774	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT must be set\n"));
775	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
776	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID must be set\n"));
777	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
778	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT must be set\n"));
779	}
780
781	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
782	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
783	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
784	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
785	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
786	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
787	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
788	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
789	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
790	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
791	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
792	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
793	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
794	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
795	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
796	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
797	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
798	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
799	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG must be set\n"));
800	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
801	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE must be set\n"));
802	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
803	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM must be set\n"));
804	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
805	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON must be set\n"));
806	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
807	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR must be set\n"));
808	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
809	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR must be set\n"));
810	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
811	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR must be set\n"));
812
813	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
814	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
815	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
816	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
817	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
818	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
819	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
820	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
821	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
822	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
823	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
824	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
825	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
826	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
827	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
828	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
829	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
830	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
831	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
832	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
833	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG must be set\n"));
834	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
835	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 must be set\n"));
836	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
837	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ must be set\n"));
838	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
839	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR must be set\n"));
840	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
841	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR must be set\n"));
842	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
843	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR must be set\n"));
844	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
845	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR must be set\n"));
846	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
847	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER must be set\n"));
848
849	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
850	{
851	LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
852
853	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
854	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
855	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
856	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
857	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
858	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
859	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
860	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
861	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
862	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
863	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
864	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
865	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
866	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
867	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
868	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
869	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
870	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
871	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
872	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
873	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
874	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
875	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
876	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
877	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
878	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
879	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
880	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
881	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
882	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
883	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
884	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
885	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
886	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
887	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
888	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
889	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
890	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
891	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
892	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
893	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
894	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
895	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
896	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
897	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
898	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
899	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
900	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
901	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
902	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
903	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
904	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
905	}
906
907	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
908	LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
909	LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
910	LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
911	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
912	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
913
914	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
915	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
916	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
917	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
918	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
919
920	LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
921	LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
922
923	for (unsigned i=0;i<pVM->cCPUs;i++)
924	LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
925
926	#ifdef HWACCM_VTX_WITH_EPT
927	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
928	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
929	#endif /* HWACCM_VTX_WITH_EPT */
930	#ifdef HWACCM_VTX_WITH_VPID
931	if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
932	&& !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
933	pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
934	#endif /* HWACCM_VTX_WITH_VPID */
935
936	/* Only try once. */
937	pVM->hwaccm.s.fInitialized = true;
938
939	/* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
940	#if 1
941	rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
942	#else
943	rc = VERR_NO_MEMORY; /* simulation of no VMMDev Heap. */
944	#endif
945	if (RT_SUCCESS(rc))
946	{
947	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
948	ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
949	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
950	/* Bit set to 0 means redirection enabled. */
951	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
952	/* Allow all port IO, so the VT-x IO intercepts do their job. */
953	memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
954	((unsigned char )pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
955
956	/* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
957	* real and protected mode without paging with EPT.
958	*/
959	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
960	for (unsigned i=0;i<X86_PG_ENTRIES;i++)
961	{
962	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
963	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_G;
964	}
965
966	/* We convert it here every time as pci regions could be reconfigured. */
967	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
968	AssertRC(rc);
969	LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
970
971	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
972	AssertRC(rc);
973	LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
974	}
975	else
976	{
977	LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
978	pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
979	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
980	}
981
982	rc = SUPCallVMMR0Ex(pVM->pVMR0, 0 /* VCPU 0 */, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
983	AssertRC(rc);
984	if (rc == VINF_SUCCESS)
985	{
986	pVM->fHWACCMEnabled = true;
987	pVM->hwaccm.s.vmx.fEnabled = true;
988	hwaccmR3DisableRawMode(pVM);
989
990	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
991	#ifdef VBOX_ENABLE_64_BITS_GUESTS
992	if (pVM->hwaccm.s.fAllow64BitGuests)
993	{
994	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
995	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
996	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
997	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
998	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
999	}
1000	LogRel((pVM->hwaccm.s.fAllow64BitGuests
1001	? "HWACCM: 32-bit and 64-bit guests supported.\n"
1002	: "HWACCM: 32-bit guests supported.\n"));
1003	#else
1004	LogRel(("HWACCM: 32-bit guests supported.\n"));
1005	#endif
1006	LogRel(("HWACCM: VMX enabled!\n"));
1007	if (pVM->hwaccm.s.fNestedPaging)
1008	{
1009	LogRel(("HWACCM: Enabled nested paging\n"));
1010	LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1011	}
1012	if (pVM->hwaccm.s.vmx.fVPID)
1013	LogRel(("HWACCM: Enabled VPID\n"));
1014
1015	if ( pVM->hwaccm.s.fNestedPaging
1016	\|\| pVM->hwaccm.s.vmx.fVPID)
1017	{
1018	LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1019	LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1020	}
1021	}
1022	else
1023	{
1024	LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1025	LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1026	pVM->fHWACCMEnabled = false;
1027	}
1028	}
1029	}
1030	else
1031	if (pVM->hwaccm.s.svm.fSupported)
1032	{
1033	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1034
1035	if (pVM->hwaccm.s.fInitialized == false)
1036	{
1037	/* Erratum 170 which requires a forced TLB flush for each world switch:
1038	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1039	*
1040	* All BH-G1/2 and DH-G1/2 models include a fix:
1041	* Athlon X2: 0x6b 1/2
1042	* 0x68 1/2
1043	* Athlon 64: 0x7f 1
1044	* 0x6f 2
1045	* Sempron: 0x7f 1/2
1046	* 0x6f 2
1047	* 0x6c 2
1048	* 0x7c 2
1049	* Turion 64: 0x68 2
1050	*
1051	*/
1052	uint32_t u32Dummy;
1053	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1054	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1055	u32BaseFamily= (u32Version >> 8) & 0xf;
1056	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1057	u32Model = ((u32Version >> 4) & 0xf);
1058	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1059	u32Stepping = u32Version & 0xf;
1060	if ( u32Family == 0xf
1061	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
1062	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
1063	{
1064	LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1065	}
1066
1067	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1068	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1069	LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1070	LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1071	LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1072
1073	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1074	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
1075	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
1076	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
1077	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
1078	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
1079	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
1080	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
1081	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
1082	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
1083
1084	/* Only try once. */
1085	pVM->hwaccm.s.fInitialized = true;
1086
1087	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1088	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1089
1090	rc = SUPCallVMMR0Ex(pVM->pVMR0, 0 /* VCPU 0 */, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1091	AssertRC(rc);
1092	if (rc == VINF_SUCCESS)
1093	{
1094	pVM->fHWACCMEnabled = true;
1095	pVM->hwaccm.s.svm.fEnabled = true;
1096
1097	if (pVM->hwaccm.s.fNestedPaging)
1098	LogRel(("HWACCM: Enabled nested paging\n"));
1099
1100	hwaccmR3DisableRawMode(pVM);
1101	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1102	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1103	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1104	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1105	if (pVM->hwaccm.s.fAllow64BitGuests)
1106	{
1107	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1108	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1109	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1110	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1111	}
1112	#endif
1113	LogRel((pVM->hwaccm.s.fAllow64BitGuests
1114	? "HWACCM: 32-bit and 64-bit guest supported.\n"
1115	: "HWACCM: 32-bit guest supported.\n"));
1116	}
1117	else
1118	{
1119	pVM->fHWACCMEnabled = false;
1120	}
1121	}
1122	}
1123	return VINF_SUCCESS;
1124	}
1125
1126	/**
1127	* Applies relocations to data and code managed by this
1128	* component. This function will be called at init and
1129	* whenever the VMM need to relocate it self inside the GC.
1130	*
1131	* @param pVM The VM.
1132	*/
1133	VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1134	{
1135	Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1136
1137	/* Fetch the current paging mode during the relocate callback during state loading. */
1138	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1139	{
1140	for (unsigned i=0;i<pVM->cCPUs;i++)
1141	{
1142	PVMCPU pVCpu = &pVM->aCpus[i];
1143	/* @todo SMP */
1144	pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1145	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMGetGuestMode(pVCpu);
1146	}
1147	}
1148	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1149	if (pVM->fHWACCMEnabled)
1150	{
1151	int rc;
1152
1153	switch(PGMGetHostMode(pVM))
1154	{
1155	case PGMMODE_32_BIT:
1156	pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1157	break;
1158
1159	case PGMMODE_PAE:
1160	case PGMMODE_PAE_NX:
1161	pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1162	break;
1163
1164	default:
1165	AssertFailed();
1166	break;
1167	}
1168	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1169	AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1170
1171	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1172	AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1173
1174	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1175	AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1176
1177	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1178	AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1179
1180	# ifdef DEBUG
1181	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1182	AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1183	# endif
1184	}
1185	#endif
1186	return;
1187	}
1188
1189	/**
1190	* Checks hardware accelerated raw mode is allowed.
1191	*
1192	* @returns boolean
1193	* @param pVM The VM to operate on.
1194	*/
1195	VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1196	{
1197	return pVM->hwaccm.s.fAllowed;
1198	}
1199
1200	/**
1201	* Notification callback which is called whenever there is a chance that a CR3
1202	* value might have changed.
1203	*
1204	* This is called by PGM.
1205	*
1206	* @param pVM The VM to operate on.
1207	* @param pVCpu The VMCPU to operate on.
1208	* @param enmShadowMode New shadow paging mode.
1209	* @param enmGuestMode New guest paging mode.
1210	*/
1211	VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1212	{
1213	/* Ignore page mode changes during state loading. */
1214	if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1215	return;
1216
1217	pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1218
1219	if ( pVM->hwaccm.s.vmx.fEnabled
1220	&& pVM->fHWACCMEnabled)
1221	{
1222	if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1223	&& enmGuestMode >= PGMMODE_PROTECTED)
1224	{
1225	PCPUMCTX pCtx;
1226
1227	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1228
1229	/* After a real mode switch to protected mode we must force
1230	* CPL to 0. Our real mode emulation had to set it to 3.
1231	*/
1232	pCtx->ssHid.Attr.n.u2Dpl = 0;
1233	}
1234	}
1235
1236	if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1237	{
1238	/* Keep track of paging mode changes. */
1239	pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1240	pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1241
1242	/* Did we miss a change, because all code was executed in the recompiler? */
1243	if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1244	{
1245	Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1246	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1247	}
1248	}
1249
1250	/* Reset the contents of the read cache. */
1251	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1252	for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1253	pCache->Read.aFieldVal[j] = 0;
1254	}
1255
1256	/**
1257	* Terminates the HWACCM.
1258	*
1259	* Termination means cleaning up and freeing all resources,
1260	* the VM it self is at this point powered off or suspended.
1261	*
1262	* @returns VBox status code.
1263	* @param pVM The VM to operate on.
1264	*/
1265	VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1266	{
1267	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1268	{
1269	PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1270	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1271	}
1272	HWACCMR3TermCPU(pVM);
1273	return 0;
1274	}
1275
1276	/**
1277	* Terminates the per-VCPU HWACCM.
1278	*
1279	* Termination means cleaning up and freeing all resources,
1280	* the VM it self is at this point powered off or suspended.
1281	*
1282	* @returns VBox status code.
1283	* @param pVM The VM to operate on.
1284	*/
1285	VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1286	{
1287	for (unsigned i=0;i<pVM->cCPUs;i++)
1288	{
1289	PVMCPU pVCpu = &pVM->aCpus[i];
1290
1291	if (pVCpu->hwaccm.s.paStatExitReason)
1292	{
1293	MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1294	pVCpu->hwaccm.s.paStatExitReason = NULL;
1295	pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1296	}
1297	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1298	memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1299	pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1300	pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1301	#endif
1302	}
1303	return 0;
1304	}
1305
1306	/**
1307	* The VM is being reset.
1308	*
1309	* For the HWACCM component this means that any GDT/LDT/TSS monitors
1310	* needs to be removed.
1311	*
1312	* @param pVM VM handle.
1313	*/
1314	VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1315	{
1316	LogFlow(("HWACCMR3Reset:\n"));
1317
1318	if (pVM->fHWACCMEnabled)
1319	hwaccmR3DisableRawMode(pVM);
1320
1321	for (unsigned i=0;i<pVM->cCPUs;i++)
1322	{
1323	PVMCPU pVCpu = &pVM->aCpus[i];
1324
1325	/* On first entry we'll sync everything. */
1326	pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1327
1328	pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1329	pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1330
1331	pVCpu->hwaccm.s.fActive = false;
1332	pVCpu->hwaccm.s.Event.fPending = false;
1333
1334	/* Reset state information for real-mode emulation in VT-x. */
1335	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1336	pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1337	pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1338
1339	/* Reset the contents of the read cache. */
1340	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1341	for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1342	pCache->Read.aFieldVal[j] = 0;
1343
1344	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1345	/* Magic marker for searching in crash dumps. */
1346	strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1347	pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1348	#endif
1349	}
1350	}
1351
1352	/**
1353	* Force execution of the current IO code in the recompiler
1354	*
1355	* @returns VBox status code.
1356	* @param pVM The VM to operate on.
1357	* @param pCtx Partial VM execution context
1358	*/
1359	VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
1360	{
1361	PVMCPU pVCpu = VMMGetCpu(pVM);
1362
1363	Assert(pVM->fHWACCMEnabled);
1364	Log(("HWACCMR3EmulateIoBlock\n"));
1365
1366	/* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
1367	if (HWACCMCanEmulateIoBlockEx(pCtx))
1368	{
1369	Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
1370	pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
1371	pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
1372	pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
1373	return VINF_EM_RESCHEDULE_REM;
1374	}
1375	return VINF_SUCCESS;
1376	}
1377
1378	/**
1379	* Checks if we can currently use hardware accelerated raw mode.
1380	*
1381	* @returns boolean
1382	* @param pVM The VM to operate on.
1383	* @param pCtx Partial VM execution context
1384	*/
1385	VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
1386	{
1387	PVMCPU pVCpu = VMMGetCpu(pVM);
1388
1389	Assert(pVM->fHWACCMEnabled);
1390
1391	/* If we're still executing the IO code, then return false. */
1392	if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
1393	&& pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
1394	&& pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
1395	&& pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
1396	return false;
1397
1398	pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
1399
1400	/* AMD-V supports real & protected mode with or without paging. */
1401	if (pVM->hwaccm.s.svm.fEnabled)
1402	{
1403	pVCpu->hwaccm.s.fActive = true;
1404	return true;
1405	}
1406
1407	pVCpu->hwaccm.s.fActive = false;
1408
1409	/* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
1410	#ifdef HWACCM_VMX_EMULATE_REALMODE
1411	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1412	{
1413	if (CPUMIsGuestInRealModeEx(pCtx))
1414	{
1415	/* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
1416	* The base must also be equal to (sel << 4).
1417	*/
1418	if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
1419	&& pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
1420	\|\| pCtx->ds != (pCtx->dsHid.u64Base >> 4)
1421	\|\| pCtx->es != (pCtx->esHid.u64Base >> 4)
1422	\|\| pCtx->fs != (pCtx->fsHid.u64Base >> 4)
1423	\|\| pCtx->gs != (pCtx->gsHid.u64Base >> 4)
1424	\|\| pCtx->ss != (pCtx->ssHid.u64Base >> 4))
1425	{
1426	return false;
1427	}
1428	}
1429	else
1430	{
1431	PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
1432	/* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
1433	* from real to protected mode. (all sorts of RPL & DPL assumptions)
1434	*/
1435	if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1436	&& enmGuestMode >= PGMMODE_PROTECTED)
1437	{
1438	if ( (pCtx->cs & X86_SEL_RPL)
1439	\|\| (pCtx->ds & X86_SEL_RPL)
1440	\|\| (pCtx->es & X86_SEL_RPL)
1441	\|\| (pCtx->fs & X86_SEL_RPL)
1442	\|\| (pCtx->gs & X86_SEL_RPL)
1443	\|\| (pCtx->ss & X86_SEL_RPL))
1444	{
1445	return false;
1446	}
1447	}
1448	}
1449	}
1450	else
1451	#endif /* HWACCM_VMX_EMULATE_REALMODE */
1452	{
1453	if (!CPUMIsGuestInLongModeEx(pCtx))
1454	{
1455	/** @todo This should (probably) be set on every excursion to the REM,
1456	* however it's too risky right now. So, only apply it when we go
1457	* back to REM for real mode execution. (The XP hack below doesn't
1458	* work reliably without this.)
1459	* Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
1460	pVM->aCpus[0].hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1461
1462	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
1463	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
1464	return false;
1465
1466	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
1467	/* Windows XP; switch to protected mode; all selectors are marked not present in the
1468	* hidden registers (possible recompiler bug; see load_seg_vm) */
1469	if (pCtx->csHid.Attr.n.u1Present == 0)
1470	return false;
1471	if (pCtx->ssHid.Attr.n.u1Present == 0)
1472	return false;
1473
1474	/* Windows XP: possible same as above, but new recompiler requires new heuristics?
1475	VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
1476	/** @todo This check is actually wrong, it doesn't take the direction of the
1477	* stack segment into account. But, it does the job for now. */
1478	if (pCtx->rsp >= pCtx->ssHid.u32Limit)
1479	return false;
1480	#if 0
1481	if ( pCtx->cs >= pCtx->gdtr.cbGdt
1482	\|\| pCtx->ss >= pCtx->gdtr.cbGdt
1483	\|\| pCtx->ds >= pCtx->gdtr.cbGdt
1484	\|\| pCtx->es >= pCtx->gdtr.cbGdt
1485	\|\| pCtx->fs >= pCtx->gdtr.cbGdt
1486	\|\| pCtx->gs >= pCtx->gdtr.cbGdt)
1487	return false;
1488	#endif
1489	}
1490	}
1491
1492	if (pVM->hwaccm.s.vmx.fEnabled)
1493	{
1494	uint32_t mask;
1495
1496	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
1497	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
1498	/* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
1499	mask &= ~X86_CR0_NE;
1500
1501	#ifdef HWACCM_VMX_EMULATE_REALMODE
1502	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1503	{
1504	/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
1505	mask &= ~(X86_CR0_PG\|X86_CR0_PE);
1506	}
1507	else
1508	#endif
1509	{
1510	/* We support protected mode without paging using identity mapping. */
1511	mask &= ~X86_CR0_PG;
1512	}
1513	if ((pCtx->cr0 & mask) != mask)
1514	return false;
1515
1516	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
1517	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
1518	if ((pCtx->cr0 & mask) != 0)
1519	return false;
1520
1521	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
1522	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1523	mask &= ~X86_CR4_VMXE;
1524	if ((pCtx->cr4 & mask) != mask)
1525	return false;
1526
1527	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
1528	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
1529	if ((pCtx->cr4 & mask) != 0)
1530	return false;
1531
1532	pVCpu->hwaccm.s.fActive = true;
1533	return true;
1534	}
1535
1536	return false;
1537	}
1538
1539	/**
1540	* Notifcation from EM about a rescheduling into hardware assisted execution
1541	* mode.
1542	*
1543	* @param pVCpu Pointer to the current virtual cpu structure.
1544	*/
1545	VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
1546	{
1547	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1548	}
1549
1550	/**
1551	* Notifcation from EM about returning from instruction emulation (REM / EM).
1552	*
1553	* @param pVCpu Pointer to the current virtual cpu structure.
1554	*/
1555	VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
1556	{
1557	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1558	}
1559
1560	/**
1561	* Checks if we are currently using hardware accelerated raw mode.
1562	*
1563	* @returns boolean
1564	* @param pVCpu The VMCPU to operate on.
1565	*/
1566	VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
1567	{
1568	return pVCpu->hwaccm.s.fActive;
1569	}
1570
1571	/**
1572	* Checks if we are currently using nested paging.
1573	*
1574	* @returns boolean
1575	* @param pVM The VM to operate on.
1576	*/
1577	VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
1578	{
1579	return pVM->hwaccm.s.fNestedPaging;
1580	}
1581
1582	/**
1583	* Checks if we are currently using VPID in VT-x mode.
1584	*
1585	* @returns boolean
1586	* @param pVM The VM to operate on.
1587	*/
1588	VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
1589	{
1590	return pVM->hwaccm.s.vmx.fVPID;
1591	}
1592
1593
1594	/**
1595	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
1596	*
1597	* @returns boolean
1598	* @param pVM The VM to operate on.
1599	*/
1600	VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
1601	{
1602	/* @todo SMP */
1603	return HWACCMIsEnabled(pVM) && pVM->aCpus[0].hwaccm.s.Event.fPending;
1604	}
1605
1606
1607	/**
1608	* Inject an NMI into a running VM
1609	*
1610	* @returns boolean
1611	* @param pVM The VM to operate on.
1612	*/
1613	VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
1614	{
1615	pVM->hwaccm.s.fInjectNMI = true;
1616	return VINF_SUCCESS;
1617	}
1618
1619	/**
1620	* Check fatal VT-x/AMD-V error and produce some meaningful
1621	* log release message.
1622	*
1623	* @param pVM The VM to operate on.
1624	* @param iStatusCode VBox status code
1625	*/
1626	VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
1627	{
1628	for (unsigned i=0;i<pVM->cCPUs;i++)
1629	{
1630	switch(iStatusCode)
1631	{
1632	case VERR_VMX_INVALID_VMCS_FIELD:
1633	break;
1634
1635	case VERR_VMX_INVALID_VMCS_PTR:
1636	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1637	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
1638	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
1639	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
1640	break;
1641
1642	case VERR_VMX_UNABLE_TO_START_VM:
1643	LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1644	LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1645	#if 0 /* @todo dump the current control fields to the release log */
1646	if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
1647	{
1648
1649	}
1650	#endif
1651	break;
1652
1653	case VERR_VMX_UNABLE_TO_RESUME_VM:
1654	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1655	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1656	break;
1657
1658	case VERR_VMX_INVALID_VMXON_PTR:
1659	break;
1660	}
1661	}
1662	}
1663
1664	/**
1665	* Execute state save operation.
1666	*
1667	* @returns VBox status code.
1668	* @param pVM VM Handle.
1669	* @param pSSM SSM operation handle.
1670	*/
1671	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
1672	{
1673	int rc;
1674
1675	Log(("hwaccmR3Save:\n"));
1676
1677	for (unsigned i=0;i<pVM->cCPUs;i++)
1678	{
1679	/*
1680	* Save the basic bits - fortunately all the other things can be resynced on load.
1681	*/
1682	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
1683	AssertRCReturn(rc, rc);
1684	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
1685	AssertRCReturn(rc, rc);
1686	rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
1687	AssertRCReturn(rc, rc);
1688
1689	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
1690	AssertRCReturn(rc, rc);
1691	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
1692	AssertRCReturn(rc, rc);
1693	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
1694	AssertRCReturn(rc, rc);
1695	}
1696
1697	return VINF_SUCCESS;
1698	}
1699
1700	/**
1701	* Execute state load operation.
1702	*
1703	* @returns VBox status code.
1704	* @param pVM VM Handle.
1705	* @param pSSM SSM operation handle.
1706	* @param u32Version Data layout version.
1707	*/
1708	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1709	{
1710	int rc;
1711
1712	Log(("hwaccmR3Load:\n"));
1713
1714	/*
1715	* Validate version.
1716	*/
1717	if ( u32Version != HWACCM_SSM_VERSION
1718	&& u32Version != HWACCM_SSM_VERSION_2_0_X)
1719	{
1720	AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
1721	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1722	}
1723	for (unsigned i=0;i<pVM->cCPUs;i++)
1724	{
1725	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
1726	AssertRCReturn(rc, rc);
1727	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
1728	AssertRCReturn(rc, rc);
1729	rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
1730	AssertRCReturn(rc, rc);
1731
1732	if (u32Version >= HWACCM_SSM_VERSION)
1733	{
1734	uint32_t val;
1735
1736	rc = SSMR3GetU32(pSSM, &val);
1737	AssertRCReturn(rc, rc);
1738	pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
1739
1740	rc = SSMR3GetU32(pSSM, &val);
1741	AssertRCReturn(rc, rc);
1742	pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
1743
1744	rc = SSMR3GetU32(pSSM, &val);
1745	AssertRCReturn(rc, rc);
1746	pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
1747	}
1748	}
1749	return VINF_SUCCESS;
1750	}
1751

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source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 19979

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