HWACCM.cpp@ 2869

Last change on this file since 2869 was 2811, checked in by vboxsync, 18 years ago
Updates for 64 bits descriptors.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 33.0 KB

Line
1	/* $Id: HWACCM.cpp 2811 2007-05-23 14:48:38Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_HWACCM
26	#include <VBox/cpum.h>
27	#include <VBox/stam.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/trpm.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/hwacc_vmx.h>
34	#include <VBox/hwacc_svm.h>
35	#include "HWACCMInternal.h"
36	#include <VBox/vm.h>
37	#include <VBox/err.h>
38	#include <VBox/param.h>
39	#include <VBox/patm.h>
40	#include <VBox/csam.h>
41	#include <VBox/selm.h>
42
43	#include <iprt/assert.h>
44	#include <VBox/log.h>
45	#include <iprt/asm.h>
46	#include <iprt/string.h>
47	#include <iprt/thread.h>
48	#include "x86context.h"
49
50
51	/*******************************************************************************
52	* Internal Functions *
53	*******************************************************************************/
54	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
55	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
56
57
58	/**
59	* Initializes the HWACCM.
60	*
61	* @returns VBox status code.
62	* @param pVM The VM to operate on.
63	*/
64	HWACCMR3DECL(int) HWACCMR3Init(PVM pVM)
65	{
66	LogFlow(("HWACCMR3Init\n"));
67
68	/*
69	* Assert alignment and sizes.
70	*/
71	AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
72	AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
73
74	/* Some structure checks. */
75	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
76	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
77	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
78	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
79
80	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
81	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
82	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
83	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
84	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
85	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
86	AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
87
88
89	/*
90	* Register the saved state data unit.
91	*/
92	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
93	NULL, hwaccmR3Save, NULL,
94	NULL, hwaccmR3Load, NULL);
95	if (VBOX_FAILURE(rc))
96	return rc;
97
98	/** @todo Make sure both pages are either not accessible or readonly! */
99	/* Allocate one page for VMXON. */
100	pVM->hwaccm.s.vmx.pVMXON = SUPContAlloc(1, &pVM->hwaccm.s.vmx.pVMXONPhys);
101	if (pVM->hwaccm.s.vmx.pVMXON == 0)
102	{
103	AssertMsgFailed(("SUPContAlloc failed!!\n"));
104	return VERR_NO_MEMORY;
105	}
106	memset(pVM->hwaccm.s.vmx.pVMXON, 0, PAGE_SIZE);
107
108	/* Allocate one page for the VM control structure (VMCS). */
109	pVM->hwaccm.s.vmx.pVMCS = SUPContAlloc(1, &pVM->hwaccm.s.vmx.pVMCSPhys);
110	if (pVM->hwaccm.s.vmx.pVMCS == 0)
111	{
112	AssertMsgFailed(("SUPContAlloc failed!!\n"));
113	return VERR_NO_MEMORY;
114	}
115	memset(pVM->hwaccm.s.vmx.pVMCS, 0, PAGE_SIZE);
116
117	/* Reuse those two pages for AMD SVM. (one is active; never both) */
118	pVM->hwaccm.s.svm.pHState = pVM->hwaccm.s.vmx.pVMXON;
119	pVM->hwaccm.s.svm.pHStatePhys = pVM->hwaccm.s.vmx.pVMXONPhys;
120	pVM->hwaccm.s.svm.pVMCB = pVM->hwaccm.s.vmx.pVMCS;
121	pVM->hwaccm.s.svm.pVMCBPhys = pVM->hwaccm.s.vmx.pVMCSPhys;
122
123	/* Allocate one page for the SVM host control structure (used for vmsave/vmload). */
124	pVM->hwaccm.s.svm.pVMCBHost = SUPContAlloc(1, &pVM->hwaccm.s.svm.pVMCBHostPhys);
125	if (pVM->hwaccm.s.svm.pVMCBHost == 0)
126	{
127	AssertMsgFailed(("SUPContAlloc failed!!\n"));
128	return VERR_NO_MEMORY;
129	}
130	memset(pVM->hwaccm.s.svm.pVMCBHost, 0, PAGE_SIZE);
131
132	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
133	pVM->hwaccm.s.svm.pIOBitmap = SUPContAlloc(3, &pVM->hwaccm.s.svm.pIOBitmapPhys);
134	if (pVM->hwaccm.s.svm.pIOBitmap == 0)
135	{
136	AssertMsgFailed(("SUPContAlloc failed!!\n"));
137	return VERR_NO_MEMORY;
138	}
139	/* Set all bits to intercept all IO accesses. */
140	memset(pVM->hwaccm.s.svm.pIOBitmap, 0xff, PAGE_SIZE*3);
141
142	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
143	pVM->hwaccm.s.svm.pMSRBitmap = SUPContAlloc(2, &pVM->hwaccm.s.svm.pMSRBitmapPhys);
144	if (pVM->hwaccm.s.svm.pMSRBitmap == 0)
145	{
146	AssertMsgFailed(("SUPContAlloc failed!!\n"));
147	return VERR_NO_MEMORY;
148	}
149	/* Set all bits to intercept all MSR accesses. */
150	memset(pVM->hwaccm.s.svm.pMSRBitmap, 0xff, PAGE_SIZE*2);
151
152	/* Misc initialisation. */
153	pVM->hwaccm.s.vmx.fSupported = false;
154	pVM->hwaccm.s.svm.fSupported = false;
155	pVM->hwaccm.s.vmx.fEnabled = false;
156	pVM->hwaccm.s.svm.fEnabled = false;
157
158	pVM->hwaccm.s.fActive = false;
159
160	/* On first entry we'll sync everything. */
161	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
162
163	pVM->hwaccm.s.vmx.cr0_mask = 0;
164	pVM->hwaccm.s.vmx.cr4_mask = 0;
165
166	/*
167	* Statistics.
168	*/
169	STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
170	STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
171	STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
172
173	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
174	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
175	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
176	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
177	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
178	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
179	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
180	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
181	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
182	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
183	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
184	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
185	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
186	STAM_REG(pVM, &pVM->hwaccm.s.StatExitRdtsc, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Rdtsc", STAMUNIT_OCCURENCES, "Nr of occurances");
187	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
188	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
189	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
190	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
191	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
192	STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
193	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
194	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
195	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/WriteString", STAMUNIT_OCCURENCES, "Nr of occurances");
196	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringRead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/ReadString", STAMUNIT_OCCURENCES, "Nr of occurances");
197	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
198
199	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
200	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
201
202	STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
203	STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
204	STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
205
206	pVM->hwaccm.s.pStatExitReason = 0;
207
208	#ifdef VBOX_WITH_STATISTICS
209	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVM->hwaccm.s.pStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.pStatExitReason);
210	AssertRC(rc);
211	if (VBOX_SUCCESS(rc))
212	{
213	for (int i=0;i<MAX_EXITREASON_STAT;i++)
214	{
215	char szName[64];
216	RTStrPrintf(szName, sizeof(szName), "/HWACCM/Exit/Reason/%02x", i);
217	int rc = STAMR3Register(pVM, &pVM->hwaccm.s.pStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "Exit reason");
218	AssertRC(rc);
219	}
220	}
221	pVM->hwaccm.s.pStatExitReasonR0 = MMHyperR3ToR0(pVM, pVM->hwaccm.s.pStatExitReason);
222	Assert(pVM->hwaccm.s.pStatExitReasonR0);
223	#endif
224
225	/* Disabled by default. */
226	pVM->fHWACCMEnabled = false;
227
228	/* HWACCM support must be explicitely enabled in the configuration file. */
229	pVM->hwaccm.s.fAllowed = false;
230	CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed);
231
232	return VINF_SUCCESS;
233	}
234
235
236	/**
237	* Turns off normal raw mode features
238	*
239	* @param pVM The VM to operate on.
240	*/
241	static void hwaccmr3DisableRawMode(PVM pVM)
242	{
243	/* Disable PATM & CSAM. */
244	PATMR3AllowPatching(pVM, false);
245	CSAMDisableScanning(pVM);
246
247	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
248	SELMR3DisableMonitoring(pVM);
249	TRPMR3DisableMonitoring(pVM);
250
251	/* The hidden selector registers are now valid. */
252	CPUMSetHiddenSelRegsValid(pVM, true);
253
254	/* Disable the switcher code (safety precaution). */
255	VMMR3DisableSwitcher(pVM);
256
257	/* Disable mapping of the hypervisor into the shadow page table. */
258	PGMR3ChangeShwPDMappings(pVM, false);
259
260	/* Disable the switcher */
261	VMMR3DisableSwitcher(pVM);
262	}
263
264	/**
265	* Applies relocations to data and code managed by this
266	* component. This function will be called at init and
267	* whenever the VMM need to relocate it self inside the GC.
268	*
269	* @param pVM The VM.
270	*/
271	HWACCMR3DECL(void) HWACCMR3Relocate(PVM pVM)
272	{
273	#ifdef LOG_ENABLED
274	Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
275	#endif
276
277	if (pVM->hwaccm.s.fAllowed == false)
278	return ;
279
280	if (pVM->hwaccm.s.vmx.fSupported)
281	{
282	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
283
284	if ( pVM->hwaccm.s.fInitialized == false
285	&& pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
286	{
287	uint64_t val;
288
289	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
290	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
291	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
292	LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
293	LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
294	LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
295	LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
296	LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
297
298	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls));
299	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL;
300	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
301	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
302	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
303	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
304	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls;
305	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
306	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT must be set\n"));
307	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
308	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT must be set\n"));
309
310	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls));
311	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL;
312	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
313	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
314	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
315	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
316	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
317	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
318	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
319	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
320	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
321	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
322	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
323	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
324	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
325	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
326	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
327	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
328	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
329	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
330	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
331	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
332	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
333	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
334	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
335	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
336	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
337	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
338	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
339	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
340	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
341	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
342	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
343	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
344	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls;
345	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
346	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT must be set\n"));
347	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
348	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET must be set\n"));
349	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
350	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT must be set\n"));
351	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
352	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT must be set\n"));
353	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
354	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT must be set\n"));
355	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
356	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT must be set\n"));
357	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
358	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT must be set\n"));
359	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
360	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT must be set\n"));
361	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
362	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT must be set\n"));
363	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
364	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW must be set\n"));
365	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
366	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT must be set\n"));
367	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
368	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT must be set\n"));
369	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
370	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS must be set\n"));
371	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
372	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS must be set\n"));
373	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
374	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT must be set\n"));
375	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
376	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT must be set\n"));
377
378	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry));
379	val = pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL;
380	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
381	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
382	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
383	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
384	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
385	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
386	val = pVM->hwaccm.s.vmx.msr.vmx_entry;
387	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
388	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE must be set\n"));
389	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
390	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM must be set\n"));
391	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
392	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON must be set\n"));
393
394	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit));
395	val = pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL;
396	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
397	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
398	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
399	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
400	val = pVM->hwaccm.s.vmx.msr.vmx_exit;
401	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
402	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 must be set\n"));
403	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
404	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ must be set\n"));
405
406	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
407	LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
408	LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
409	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
410	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
411
412	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
413	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
414	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
415	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
416	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
417
418	/* Only try once. */
419	pVM->hwaccm.s.fInitialized = true;
420
421	int rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, NULL);
422	AssertRC(rc);
423	if (rc == VINF_SUCCESS)
424	{
425	hwaccmr3DisableRawMode(pVM);
426
427	pVM->fHWACCMEnabled = true;
428	pVM->hwaccm.s.vmx.fEnabled = true;
429	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
430	LogRel(("HWACCM: VMX enabled!\n"));
431	}
432	else
433	{
434	LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
435	pVM->fHWACCMEnabled = false;
436	}
437	}
438	}
439	else
440	if (pVM->hwaccm.s.svm.fSupported)
441	{
442	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
443
444	if (pVM->hwaccm.s.fInitialized == false)
445	{
446	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
447	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
448	LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
449	LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.svm.u32MaxASID));
450
451	/* Only try once. */
452	pVM->hwaccm.s.fInitialized = true;
453
454	int rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, NULL);
455	AssertRC(rc);
456	if (rc == VINF_SUCCESS)
457	{
458	hwaccmr3DisableRawMode(pVM);
459	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
460
461	pVM->fHWACCMEnabled = true;
462	pVM->hwaccm.s.svm.fEnabled = true;
463	}
464	else
465	{
466	pVM->fHWACCMEnabled = false;
467	}
468	}
469	}
470
471	}
472
473
474	/**
475	* Checks hardware accelerated raw mode is allowed.
476	*
477	* @returns boolean
478	* @param pVM The VM to operate on.
479	*/
480	HWACCMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
481	{
482	return pVM->hwaccm.s.fAllowed;
483	}
484
485
486	/**
487	* Notification callback which is called whenever there is a chance that a CR3
488	* value might have changed.
489	* This is called by PGM.
490	*
491	* @param pVM The VM to operate on.
492	* @param enmShadowMode New paging mode.
493	*/
494	HWACCMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode)
495	{
496	pVM->hwaccm.s.enmShadowMode = enmShadowMode;
497	}
498
499	/**
500	* Terminates the HWACCM.
501	*
502	* Termination means cleaning up and freeing all resources,
503	* the VM it self is at this point powered off or suspended.
504	*
505	* @returns VBox status code.
506	* @param pVM The VM to operate on.
507	*/
508	HWACCMR3DECL(int) HWACCMR3Term(PVM pVM)
509	{
510	if (pVM->hwaccm.s.pStatExitReason)
511	{
512	MMHyperFree(pVM, pVM->hwaccm.s.pStatExitReason);
513	pVM->hwaccm.s.pStatExitReason = 0;
514	}
515
516	if (pVM->hwaccm.s.vmx.pVMXON)
517	{
518	SUPContFree(pVM->hwaccm.s.vmx.pVMXON, 1);
519	pVM->hwaccm.s.vmx.pVMXON = 0;
520	}
521	if (pVM->hwaccm.s.vmx.pVMCS)
522	{
523	SUPContFree(pVM->hwaccm.s.vmx.pVMCS, 1);
524	pVM->hwaccm.s.vmx.pVMCS = 0;
525	}
526	if (pVM->hwaccm.s.svm.pVMCBHost)
527	{
528	SUPContFree(pVM->hwaccm.s.svm.pVMCBHost, 1);
529	pVM->hwaccm.s.svm.pVMCBHost = 0;
530	}
531	if (pVM->hwaccm.s.svm.pIOBitmap)
532	{
533	SUPContFree(pVM->hwaccm.s.svm.pIOBitmap, 3);
534	pVM->hwaccm.s.svm.pIOBitmap = 0;
535	}
536	if (pVM->hwaccm.s.svm.pMSRBitmap)
537	{
538	SUPContFree(pVM->hwaccm.s.svm.pMSRBitmap, 2);
539	pVM->hwaccm.s.svm.pMSRBitmap = 0;
540	}
541	return 0;
542	}
543
544
545	/**
546	* The VM is being reset.
547	*
548	* For the HWACCM component this means that any GDT/LDT/TSS monitors
549	* needs to be removed.
550	*
551	* @param pVM VM handle.
552	*/
553	HWACCMR3DECL(void) HWACCMR3Reset(PVM pVM)
554	{
555	LogFlow(("HWACCMR3Reset:\n"));
556
557	if (pVM->fHWACCMEnabled)
558	hwaccmr3DisableRawMode(pVM);
559
560	/* On first entry we'll sync everything. */
561	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
562
563	pVM->hwaccm.s.vmx.cr0_mask = 0;
564	pVM->hwaccm.s.vmx.cr4_mask = 0;
565
566	pVM->hwaccm.s.Event.fPending = false;
567	}
568
569	/**
570	* Checks if we can currently use hardware accelerated raw mode.
571	*
572	* @returns boolean
573	* @param pVM The VM to operate on.
574	* @param pCtx Partial VM execution context
575	*/
576	HWACCMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
577	{
578	uint32_t mask;
579
580	Assert(pVM->fHWACCMEnabled);
581
582	/* AMD SVM supports real & protected mode with or without paging. */
583	if (pVM->hwaccm.s.svm.fEnabled)
584	{
585	pVM->hwaccm.s.fActive = true;
586	return true;
587	}
588
589	/* @todo we can support real-mode by using v86 and protected mode without paging with identity mapped pages.
590	* (but do we really care?)
591	*/
592
593	pVM->hwaccm.s.fActive = false;
594
595	/** @note The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
596
597	/* Too early for VMX. */
598	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
599	return false;
600
601	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
602	if (pCtx->csHid.Attr.n.u1Present == 0)
603	return false;
604	if (pCtx->ssHid.Attr.n.u1Present == 0)
605	return false;
606
607	/** @todo if we remove this check, then Windows XP install fails during the textmode phase */
608	if (!(pCtx->cr0 & X86_CR0_WRITE_PROTECT))
609	return false;
610
611	if (pVM->hwaccm.s.vmx.fEnabled)
612	{
613	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
614	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
615	/** @note We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
616	mask &= ~X86_CR0_NE;
617
618	if ((pCtx->cr0 & mask) != mask)
619	return false;
620
621	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
622	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
623	if ((pCtx->cr0 & mask) != 0)
624	return false;
625
626	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
627	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
628	mask &= ~X86_CR4_VMXE;
629	if ((pCtx->cr4 & mask) != mask)
630	return false;
631
632	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
633	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
634	if ((pCtx->cr4 & mask) != 0)
635	return false;
636
637	pVM->hwaccm.s.fActive = true;
638	return true;
639	}
640	#if 0
641	else
642	if (pVM->hwaccm.s.svm.fEnabled)
643	{
644	pVM->hwaccm.s.fActive = true;
645	return true;
646	}
647	#endif
648
649	return false;
650	}
651
652	/**
653	* Checks if we are currently using hardware accelerated raw mode.
654	*
655	* @returns boolean
656	* @param pVM The VM to operate on.
657	*/
658	HWACCMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
659	{
660	return pVM->hwaccm.s.fActive;
661	}
662
663	/**
664	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
665	*
666	* @returns boolean
667	* @param pVM The VM to operate on.
668	*/
669	HWACCMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
670	{
671	return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
672	}
673
674	/**
675	* Execute state save operation.
676	*
677	* @returns VBox status code.
678	* @param pVM VM Handle.
679	* @param pSSM SSM operation handle.
680	*/
681	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
682	{
683	int rc;
684
685	Log(("hwaccmR3Save:\n"));
686
687	/*
688	* Save the basic bits - fortunately all the other things can be resynced on load.
689	*/
690	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
691	AssertRCReturn(rc, rc);
692	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
693	AssertRCReturn(rc, rc);
694	rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
695	AssertRCReturn(rc, rc);
696
697	return VINF_SUCCESS;
698	}
699
700
701	/**
702	* Execute state load operation.
703	*
704	* @returns VBox status code.
705	* @param pVM VM Handle.
706	* @param pSSM SSM operation handle.
707	* @param u32Version Data layout version.
708	*/
709	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
710	{
711	int rc;
712
713	Log(("hwaccmR3Load:\n"));
714
715	/*
716	* Validate version.
717	*/
718	if (u32Version != HWACCM_SSM_VERSION)
719	{
720	Log(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
721	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
722	}
723	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
724	AssertRCReturn(rc, rc);
725	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
726	AssertRCReturn(rc, rc);
727	rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
728	AssertRCReturn(rc, rc);
729
730	return VINF_SUCCESS;
731	}
732
733
734
735

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source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 2869

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