1 | /* $Id: HWACCM.cpp 10695 2008-07-16 12:17:31Z vboxsync $ */
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2 | /** @file
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3 | * HWACCM - Intel/AMD VM Hardware Support Manager
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2007 Sun Microsystems, Inc.
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | *
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17 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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18 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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19 | * additional information or have any questions.
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20 | */
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21 |
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22 | /*******************************************************************************
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23 | * Header Files *
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24 | *******************************************************************************/
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25 | #define LOG_GROUP LOG_GROUP_HWACCM
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26 | #include <VBox/cpum.h>
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27 | #include <VBox/stam.h>
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28 | #include <VBox/mm.h>
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29 | #include <VBox/pdm.h>
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30 | #include <VBox/pgm.h>
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31 | #include <VBox/trpm.h>
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32 | #include <VBox/dbgf.h>
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33 | #include <VBox/hwacc_vmx.h>
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34 | #include <VBox/hwacc_svm.h>
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35 | #include "HWACCMInternal.h"
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36 | #include <VBox/vm.h>
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37 | #include <VBox/err.h>
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38 | #include <VBox/param.h>
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39 | #include <VBox/patm.h>
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40 | #include <VBox/csam.h>
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41 | #include <VBox/selm.h>
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42 |
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43 | #include <iprt/assert.h>
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44 | #include <VBox/log.h>
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45 | #include <iprt/asm.h>
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46 | #include <iprt/string.h>
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47 | #include <iprt/thread.h>
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48 |
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49 | /*******************************************************************************
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50 | * Internal Functions *
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51 | *******************************************************************************/
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52 | static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
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53 | static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
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54 |
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55 |
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56 | /**
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57 | * Initializes the HWACCM.
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58 | *
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59 | * @returns VBox status code.
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60 | * @param pVM The VM to operate on.
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61 | */
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62 | HWACCMR3DECL(int) HWACCMR3Init(PVM pVM)
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63 | {
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64 | LogFlow(("HWACCMR3Init\n"));
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65 |
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66 | /*
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67 | * Assert alignment and sizes.
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68 | */
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69 | AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
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70 | AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
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71 |
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72 | /* Some structure checks. */
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73 | AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
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74 | AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
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75 | AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
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76 | AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
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77 |
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78 | AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
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79 | AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
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80 | AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
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81 | AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
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82 | AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
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83 | AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
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84 | AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
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85 |
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86 |
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87 | /*
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88 | * Register the saved state data unit.
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89 | */
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90 | int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
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91 | NULL, hwaccmR3Save, NULL,
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92 | NULL, hwaccmR3Load, NULL);
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93 | if (VBOX_FAILURE(rc))
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94 | return rc;
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95 |
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96 | /* Misc initialisation. */
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97 | pVM->hwaccm.s.vmx.fSupported = false;
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98 | pVM->hwaccm.s.svm.fSupported = false;
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99 | pVM->hwaccm.s.vmx.fEnabled = false;
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100 | pVM->hwaccm.s.svm.fEnabled = false;
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101 |
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102 | pVM->hwaccm.s.fActive = false;
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103 | pVM->hwaccm.s.fNestedPaging = false;
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104 |
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105 | /* On first entry we'll sync everything. */
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106 | pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
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107 |
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108 | pVM->hwaccm.s.vmx.cr0_mask = 0;
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109 | pVM->hwaccm.s.vmx.cr4_mask = 0;
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110 |
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111 | /*
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112 | * Statistics.
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113 | */
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114 | STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
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115 | STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
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116 | STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
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117 |
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118 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
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119 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
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120 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
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121 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
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122 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
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123 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
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124 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
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125 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
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126 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
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127 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
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128 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
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129 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
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130 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
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131 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitRdtsc, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Rdtsc", STAMUNIT_OCCURENCES, "Nr of occurances");
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132 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
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133 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
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134 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
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135 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
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136 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
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137 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
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138 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
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139 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
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140 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/WriteString", STAMUNIT_OCCURENCES, "Nr of occurances");
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141 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringRead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/ReadString", STAMUNIT_OCCURENCES, "Nr of occurances");
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142 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
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143 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitMaxResume, STAMTYPE_COUNTER, "/HWACCM/Exit/Safety/MaxResume", STAMUNIT_OCCURENCES, "Nr of occurances");
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144 |
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145 | STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
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146 | STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
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147 |
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148 | STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
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149 | STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
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150 | STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
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151 |
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152 | STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageManual, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Virt/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
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153 | STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPhysPageManual, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Phys/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
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154 | STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBManual, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
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155 | STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBCRxChange, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/CRx", STAMUNIT_OCCURENCES, "Nr of occurances");
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156 | STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageInvlpg, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
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157 | STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Switch", STAMUNIT_OCCURENCES, "Nr of occurances");
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158 | STAM_REG(pVM, &pVM->hwaccm.s.StatNoFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Skipped", STAMUNIT_OCCURENCES, "Nr of occurances");
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159 | STAM_REG(pVM, &pVM->hwaccm.s.StatFlushASID, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/ASID", STAMUNIT_OCCURENCES, "Nr of occurances");
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160 |
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161 | STAM_REG(pVM, &pVM->hwaccm.s.StatTSCOffset, STAMTYPE_COUNTER, "/HWACCM/TSC/Offset", STAMUNIT_OCCURENCES, "Nr of occurances");
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162 | STAM_REG(pVM, &pVM->hwaccm.s.StatTSCIntercept, STAMTYPE_COUNTER, "/HWACCM/TSC/Intercept", STAMUNIT_OCCURENCES, "Nr of occurances");
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163 |
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164 | pVM->hwaccm.s.pStatExitReason = 0;
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165 |
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166 | #ifdef VBOX_WITH_STATISTICS
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167 | rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVM->hwaccm.s.pStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.pStatExitReason);
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168 | AssertRC(rc);
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169 | if (VBOX_SUCCESS(rc))
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170 | {
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171 | for (int i=0;i<MAX_EXITREASON_STAT;i++)
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172 | {
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173 | char szName[64];
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174 | RTStrPrintf(szName, sizeof(szName), "/HWACCM/Exit/Reason/%02x", i);
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175 | int rc = STAMR3Register(pVM, &pVM->hwaccm.s.pStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "Exit reason");
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176 | AssertRC(rc);
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177 | }
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178 | int rc = STAMR3Register(pVM, &pVM->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, "/HWACCM/Exit/Reason/#NPF", STAMUNIT_OCCURENCES, "Exit reason");
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179 | AssertRC(rc);
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180 | }
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181 | pVM->hwaccm.s.pStatExitReasonR0 = MMHyperR3ToR0(pVM, pVM->hwaccm.s.pStatExitReason);
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182 | Assert(pVM->hwaccm.s.pStatExitReasonR0);
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183 | #endif
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184 |
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185 | /* Disabled by default. */
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186 | pVM->fHWACCMEnabled = false;
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187 |
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188 | /* Check CFGM options. */
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189 | rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging);
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190 | if (VBOX_FAILURE(rc))
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191 | pVM->hwaccm.s.fAllowNestedPaging = true; /* enabled by default now. */
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192 |
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193 | /* HWACCM support must be explicitely enabled in the configuration file. */
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194 | pVM->hwaccm.s.fAllowed = false;
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195 | CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed);
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196 |
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197 | return VINF_SUCCESS;
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198 | }
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199 |
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200 |
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201 | /**
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202 | * Turns off normal raw mode features
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203 | *
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204 | * @param pVM The VM to operate on.
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205 | */
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206 | static void hwaccmr3DisableRawMode(PVM pVM)
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207 | {
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208 | /* Disable PATM & CSAM. */
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209 | PATMR3AllowPatching(pVM, false);
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210 | CSAMDisableScanning(pVM);
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211 |
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212 | /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
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213 | SELMR3DisableMonitoring(pVM);
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214 | TRPMR3DisableMonitoring(pVM);
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215 |
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216 | /* The hidden selector registers are now valid. */
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217 | CPUMSetHiddenSelRegsValid(pVM, true);
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218 |
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219 | /* Disable the switcher code (safety precaution). */
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220 | VMMR3DisableSwitcher(pVM);
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221 |
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222 | /* Disable mapping of the hypervisor into the shadow page table. */
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223 | PGMR3ChangeShwPDMappings(pVM, false);
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224 |
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225 | /* Disable the switcher */
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226 | VMMR3DisableSwitcher(pVM);
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227 |
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228 | if (pVM->hwaccm.s.fNestedPaging)
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229 | {
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230 | /* Reinit the paging mode to force the new shadow mode. */
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231 | PGMR3ChangeMode(pVM, PGMMODE_REAL);
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232 | }
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233 | }
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234 |
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235 | /**
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236 | * Initialize VT-x or AMD-V.
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237 | *
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238 | * @returns VBox status code.
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239 | * @param pVM The VM handle.
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240 | */
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241 | HWACCMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
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242 | {
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243 | int rc;
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244 |
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245 | if ( !pVM->hwaccm.s.vmx.fSupported
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246 | && !pVM->hwaccm.s.svm.fSupported)
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247 | {
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248 | LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Vrc\n", pVM->hwaccm.s.lLastError));
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249 | LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
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250 | return VINF_SUCCESS;
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251 | }
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252 |
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253 | /*
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254 | * Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
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255 | * because it turns off paging, which is not allowed in VMX root mode.
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256 | *
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257 | * To simplify matters we'll just force all running VMs to either use raw or hwaccm mode. No mixing allowed.
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258 | *
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259 | */
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260 | /* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
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261 | rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
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262 | if (VBOX_FAILURE(rc))
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263 | {
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264 | LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Vrc\n", rc));
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265 | LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
|
---|
266 | /* Invert the selection */
|
---|
267 | pVM->hwaccm.s.fAllowed ^= 1;
|
---|
268 | LogRel(("HWACCMR3InitFinalize: new HWACCM status = %s\n", pVM->hwaccm.s.fAllowed ? "enabled" : "disabled"));
|
---|
269 |
|
---|
270 | if (pVM->hwaccm.s.fAllowed)
|
---|
271 | {
|
---|
272 | if (pVM->hwaccm.s.vmx.fSupported)
|
---|
273 | VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses Intel VT-x hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using VT-x as well.\n");
|
---|
274 | else
|
---|
275 | VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses AMD-V hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using AMD-V as well.\n");
|
---|
276 | }
|
---|
277 | else
|
---|
278 | VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses software virtualization. It is not allowed to simultaneously use VT-x or AMD-V, therefore this VM will be run using software virtualization as well.\n");
|
---|
279 | }
|
---|
280 |
|
---|
281 | if (pVM->hwaccm.s.fAllowed == false)
|
---|
282 | return VINF_SUCCESS; /* disabled */
|
---|
283 |
|
---|
284 | Assert(!pVM->fHWACCMEnabled);
|
---|
285 |
|
---|
286 | if (pVM->hwaccm.s.vmx.fSupported)
|
---|
287 | {
|
---|
288 | Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
|
---|
289 |
|
---|
290 | if ( pVM->hwaccm.s.fInitialized == false
|
---|
291 | && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
|
---|
292 | {
|
---|
293 | uint64_t val;
|
---|
294 |
|
---|
295 | LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
|
---|
296 | LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
|
---|
297 | LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
|
---|
298 | LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
|
---|
299 | LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
|
---|
300 | LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
|
---|
301 | LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
|
---|
302 | LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
|
---|
303 |
|
---|
304 | LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
|
---|
305 | val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
|
---|
306 | if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
|
---|
307 | LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
|
---|
308 | if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
|
---|
309 | LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
|
---|
310 | val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
|
---|
311 | if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
|
---|
312 | LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
|
---|
313 | if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
|
---|
314 | LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
|
---|
315 |
|
---|
316 | LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
|
---|
317 | val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
|
---|
318 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
|
---|
319 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
|
---|
320 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
|
---|
321 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
|
---|
322 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
|
---|
323 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
|
---|
324 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
|
---|
325 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
|
---|
326 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
|
---|
327 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
|
---|
328 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
|
---|
329 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
|
---|
330 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
|
---|
331 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
|
---|
332 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
|
---|
333 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
|
---|
334 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
|
---|
335 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
|
---|
336 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
|
---|
337 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
|
---|
338 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
|
---|
339 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
|
---|
340 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
|
---|
341 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
|
---|
342 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
|
---|
343 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
|
---|
344 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
|
---|
345 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
|
---|
346 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
|
---|
347 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
|
---|
348 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
|
---|
349 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
|
---|
350 |
|
---|
351 | val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
|
---|
352 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
|
---|
353 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
|
---|
354 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
|
---|
355 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
|
---|
356 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
|
---|
357 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
|
---|
358 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
|
---|
359 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
|
---|
360 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
|
---|
361 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
|
---|
362 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
|
---|
363 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
|
---|
364 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
|
---|
365 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
|
---|
366 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
|
---|
367 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
|
---|
368 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
|
---|
369 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
|
---|
370 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
|
---|
371 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
|
---|
372 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
|
---|
373 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
|
---|
374 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
|
---|
375 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
|
---|
376 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
|
---|
377 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
|
---|
378 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
|
---|
379 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
|
---|
380 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
|
---|
381 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
|
---|
382 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
|
---|
383 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
|
---|
384 |
|
---|
385 | LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
|
---|
386 | val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
|
---|
387 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
|
---|
388 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
|
---|
389 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
|
---|
390 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
|
---|
391 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
|
---|
392 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
|
---|
393 | val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
|
---|
394 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
|
---|
395 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
|
---|
396 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
|
---|
397 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
|
---|
398 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
|
---|
399 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
|
---|
400 |
|
---|
401 | LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
|
---|
402 | val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
|
---|
403 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
|
---|
404 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
|
---|
405 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
|
---|
406 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
|
---|
407 | val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
|
---|
408 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
|
---|
409 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
|
---|
410 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
|
---|
411 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
|
---|
412 |
|
---|
413 | LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
|
---|
414 | LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
|
---|
415 | LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
|
---|
416 | LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
|
---|
417 | LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
|
---|
418 |
|
---|
419 | LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
|
---|
420 | LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
|
---|
421 | LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
|
---|
422 | LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
|
---|
423 | LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
|
---|
424 |
|
---|
425 | /* Only try once. */
|
---|
426 | pVM->hwaccm.s.fInitialized = true;
|
---|
427 |
|
---|
428 | rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
|
---|
429 | AssertRC(rc);
|
---|
430 | if (rc == VINF_SUCCESS)
|
---|
431 | {
|
---|
432 | pVM->fHWACCMEnabled = true;
|
---|
433 | pVM->hwaccm.s.vmx.fEnabled = true;
|
---|
434 | hwaccmr3DisableRawMode(pVM);
|
---|
435 |
|
---|
436 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
|
---|
437 | #ifdef VBOX_ENABLE_64_BITS_GUESTS
|
---|
438 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
|
---|
439 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
|
---|
440 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
|
---|
441 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
|
---|
442 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
|
---|
443 | #endif
|
---|
444 | LogRel(("HWACCM: VMX enabled!\n"));
|
---|
445 | }
|
---|
446 | else
|
---|
447 | {
|
---|
448 | LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
|
---|
449 | LogRel(("HWACCM: Last instruction error %x\n", pVM->hwaccm.s.vmx.ulLastInstrError));
|
---|
450 | pVM->fHWACCMEnabled = false;
|
---|
451 | }
|
---|
452 | }
|
---|
453 | }
|
---|
454 | else
|
---|
455 | if (pVM->hwaccm.s.svm.fSupported)
|
---|
456 | {
|
---|
457 | Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
|
---|
458 |
|
---|
459 | if (pVM->hwaccm.s.fInitialized == false)
|
---|
460 | {
|
---|
461 | /* Erratum 170 which requires a forced TLB flush for each world switch:
|
---|
462 | * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
|
---|
463 | *
|
---|
464 | * All BH-G1/2 and DH-G1/2 models include a fix:
|
---|
465 | * Athlon X2: 0x6b 1/2
|
---|
466 | * 0x68 1/2
|
---|
467 | * Athlon 64: 0x7f 1
|
---|
468 | * 0x6f 2
|
---|
469 | * Sempron: 0x7f 1/2
|
---|
470 | * 0x6f 2
|
---|
471 | * 0x6c 2
|
---|
472 | * 0x7c 2
|
---|
473 | * Turion 64: 0x68 2
|
---|
474 | *
|
---|
475 | */
|
---|
476 | uint32_t u32Dummy;
|
---|
477 | uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
|
---|
478 | ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
|
---|
479 | u32BaseFamily= (u32Version >> 8) & 0xf;
|
---|
480 | u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
|
---|
481 | u32Model = ((u32Version >> 4) & 0xf);
|
---|
482 | u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
|
---|
483 | u32Stepping = u32Version & 0xf;
|
---|
484 | if ( u32Family == 0xf
|
---|
485 | && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
|
---|
486 | && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
|
---|
487 | {
|
---|
488 | LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
|
---|
489 | }
|
---|
490 |
|
---|
491 | LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
|
---|
492 | LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
|
---|
493 | LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
|
---|
494 | LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.svm.u32MaxASID));
|
---|
495 | LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
|
---|
496 |
|
---|
497 | if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
|
---|
498 | LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
|
---|
499 | if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
|
---|
500 | LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
|
---|
501 | if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
|
---|
502 | LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
|
---|
503 | if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
|
---|
504 | LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
|
---|
505 | if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
|
---|
506 | LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
|
---|
507 |
|
---|
508 | /* Only try once. */
|
---|
509 | pVM->hwaccm.s.fInitialized = true;
|
---|
510 |
|
---|
511 | if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
|
---|
512 | pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
|
---|
513 |
|
---|
514 | rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
|
---|
515 | AssertRC(rc);
|
---|
516 | if (rc == VINF_SUCCESS)
|
---|
517 | {
|
---|
518 | pVM->fHWACCMEnabled = true;
|
---|
519 | pVM->hwaccm.s.svm.fEnabled = true;
|
---|
520 |
|
---|
521 | hwaccmr3DisableRawMode(pVM);
|
---|
522 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
|
---|
523 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
|
---|
524 | #ifdef VBOX_ENABLE_64_BITS_GUESTS
|
---|
525 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
|
---|
526 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
|
---|
527 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
|
---|
528 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
|
---|
529 | #endif
|
---|
530 | }
|
---|
531 | else
|
---|
532 | {
|
---|
533 | pVM->fHWACCMEnabled = false;
|
---|
534 | }
|
---|
535 | }
|
---|
536 | }
|
---|
537 | return VINF_SUCCESS;
|
---|
538 | }
|
---|
539 |
|
---|
540 | /**
|
---|
541 | * Applies relocations to data and code managed by this
|
---|
542 | * component. This function will be called at init and
|
---|
543 | * whenever the VMM need to relocate it self inside the GC.
|
---|
544 | *
|
---|
545 | * @param pVM The VM.
|
---|
546 | */
|
---|
547 | HWACCMR3DECL(void) HWACCMR3Relocate(PVM pVM)
|
---|
548 | {
|
---|
549 | Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
|
---|
550 | return;
|
---|
551 | }
|
---|
552 |
|
---|
553 |
|
---|
554 | /**
|
---|
555 | * Checks hardware accelerated raw mode is allowed.
|
---|
556 | *
|
---|
557 | * @returns boolean
|
---|
558 | * @param pVM The VM to operate on.
|
---|
559 | */
|
---|
560 | HWACCMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
|
---|
561 | {
|
---|
562 | return pVM->hwaccm.s.fAllowed;
|
---|
563 | }
|
---|
564 |
|
---|
565 |
|
---|
566 | /**
|
---|
567 | * Notification callback which is called whenever there is a chance that a CR3
|
---|
568 | * value might have changed.
|
---|
569 | * This is called by PGM.
|
---|
570 | *
|
---|
571 | * @param pVM The VM to operate on.
|
---|
572 | * @param enmShadowMode New paging mode.
|
---|
573 | */
|
---|
574 | HWACCMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode)
|
---|
575 | {
|
---|
576 | pVM->hwaccm.s.enmShadowMode = enmShadowMode;
|
---|
577 | }
|
---|
578 |
|
---|
579 | /**
|
---|
580 | * Terminates the HWACCM.
|
---|
581 | *
|
---|
582 | * Termination means cleaning up and freeing all resources,
|
---|
583 | * the VM it self is at this point powered off or suspended.
|
---|
584 | *
|
---|
585 | * @returns VBox status code.
|
---|
586 | * @param pVM The VM to operate on.
|
---|
587 | */
|
---|
588 | HWACCMR3DECL(int) HWACCMR3Term(PVM pVM)
|
---|
589 | {
|
---|
590 | if (pVM->hwaccm.s.pStatExitReason)
|
---|
591 | {
|
---|
592 | MMHyperFree(pVM, pVM->hwaccm.s.pStatExitReason);
|
---|
593 | pVM->hwaccm.s.pStatExitReason = 0;
|
---|
594 | }
|
---|
595 | return 0;
|
---|
596 | }
|
---|
597 |
|
---|
598 |
|
---|
599 | /**
|
---|
600 | * The VM is being reset.
|
---|
601 | *
|
---|
602 | * For the HWACCM component this means that any GDT/LDT/TSS monitors
|
---|
603 | * needs to be removed.
|
---|
604 | *
|
---|
605 | * @param pVM VM handle.
|
---|
606 | */
|
---|
607 | HWACCMR3DECL(void) HWACCMR3Reset(PVM pVM)
|
---|
608 | {
|
---|
609 | LogFlow(("HWACCMR3Reset:\n"));
|
---|
610 |
|
---|
611 | if (pVM->fHWACCMEnabled)
|
---|
612 | hwaccmr3DisableRawMode(pVM);
|
---|
613 |
|
---|
614 | /* On first entry we'll sync everything. */
|
---|
615 | pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
|
---|
616 |
|
---|
617 | pVM->hwaccm.s.vmx.cr0_mask = 0;
|
---|
618 | pVM->hwaccm.s.vmx.cr4_mask = 0;
|
---|
619 |
|
---|
620 | pVM->hwaccm.s.Event.fPending = false;
|
---|
621 | }
|
---|
622 |
|
---|
623 | /**
|
---|
624 | * Checks if we can currently use hardware accelerated raw mode.
|
---|
625 | *
|
---|
626 | * @returns boolean
|
---|
627 | * @param pVM The VM to operate on.
|
---|
628 | * @param pCtx Partial VM execution context
|
---|
629 | */
|
---|
630 | HWACCMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
|
---|
631 | {
|
---|
632 | Assert(pVM->fHWACCMEnabled);
|
---|
633 |
|
---|
634 | /* AMD SVM supports real & protected mode with or without paging. */
|
---|
635 | if (pVM->hwaccm.s.svm.fEnabled)
|
---|
636 | {
|
---|
637 | pVM->hwaccm.s.fActive = true;
|
---|
638 | return true;
|
---|
639 | }
|
---|
640 |
|
---|
641 | /* @todo we can support real-mode by using v86 with identity mapped pages.
|
---|
642 | * (but do we really care?)
|
---|
643 | */
|
---|
644 |
|
---|
645 | pVM->hwaccm.s.fActive = false;
|
---|
646 |
|
---|
647 | /** @note The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
|
---|
648 |
|
---|
649 | if (!CPUMIsGuestInLongModeEx(pCtx))
|
---|
650 | {
|
---|
651 | /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
|
---|
652 | if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
|
---|
653 | return false;
|
---|
654 |
|
---|
655 | /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
|
---|
656 | /* Windows XP; switch to protected mode; all selectors are marked not present in the
|
---|
657 | * hidden registers (possible recompiler bug) */
|
---|
658 | if (pCtx->csHid.Attr.n.u1Present == 0)
|
---|
659 | return false;
|
---|
660 | if (pCtx->ssHid.Attr.n.u1Present == 0)
|
---|
661 | return false;
|
---|
662 | }
|
---|
663 |
|
---|
664 | if (pVM->hwaccm.s.vmx.fEnabled)
|
---|
665 | {
|
---|
666 | uint32_t mask;
|
---|
667 |
|
---|
668 | /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
|
---|
669 | mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
|
---|
670 | /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
|
---|
671 | mask &= ~X86_CR0_NE;
|
---|
672 | #ifdef HWACCM_VMX_EMULATE_ALL
|
---|
673 | /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
|
---|
674 | mask &= ~(X86_CR0_PG|X86_CR0_PE);
|
---|
675 | #endif
|
---|
676 | if ((pCtx->cr0 & mask) != mask)
|
---|
677 | return false;
|
---|
678 |
|
---|
679 | /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
|
---|
680 | mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
|
---|
681 | if ((pCtx->cr0 & mask) != 0)
|
---|
682 | return false;
|
---|
683 |
|
---|
684 | /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
|
---|
685 | mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
|
---|
686 | mask &= ~X86_CR4_VMXE;
|
---|
687 | if ((pCtx->cr4 & mask) != mask)
|
---|
688 | return false;
|
---|
689 |
|
---|
690 | /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
|
---|
691 | mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
|
---|
692 | if ((pCtx->cr4 & mask) != 0)
|
---|
693 | return false;
|
---|
694 |
|
---|
695 | pVM->hwaccm.s.fActive = true;
|
---|
696 | return true;
|
---|
697 | }
|
---|
698 |
|
---|
699 | return false;
|
---|
700 | }
|
---|
701 |
|
---|
702 | /**
|
---|
703 | * Checks if we are currently using hardware accelerated raw mode.
|
---|
704 | *
|
---|
705 | * @returns boolean
|
---|
706 | * @param pVM The VM to operate on.
|
---|
707 | */
|
---|
708 | HWACCMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
|
---|
709 | {
|
---|
710 | return pVM->hwaccm.s.fActive;
|
---|
711 | }
|
---|
712 |
|
---|
713 | /**
|
---|
714 | * Checks if we are currently using nested paging.
|
---|
715 | *
|
---|
716 | * @returns boolean
|
---|
717 | * @param pVM The VM to operate on.
|
---|
718 | */
|
---|
719 | HWACCMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
|
---|
720 | {
|
---|
721 | return pVM->hwaccm.s.fNestedPaging;
|
---|
722 | }
|
---|
723 |
|
---|
724 | /**
|
---|
725 | * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
|
---|
726 | *
|
---|
727 | * @returns boolean
|
---|
728 | * @param pVM The VM to operate on.
|
---|
729 | */
|
---|
730 | HWACCMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
|
---|
731 | {
|
---|
732 | return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
|
---|
733 | }
|
---|
734 |
|
---|
735 | /**
|
---|
736 | * Execute state save operation.
|
---|
737 | *
|
---|
738 | * @returns VBox status code.
|
---|
739 | * @param pVM VM Handle.
|
---|
740 | * @param pSSM SSM operation handle.
|
---|
741 | */
|
---|
742 | static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
|
---|
743 | {
|
---|
744 | int rc;
|
---|
745 |
|
---|
746 | Log(("hwaccmR3Save:\n"));
|
---|
747 |
|
---|
748 | /*
|
---|
749 | * Save the basic bits - fortunately all the other things can be resynced on load.
|
---|
750 | */
|
---|
751 | rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
|
---|
752 | AssertRCReturn(rc, rc);
|
---|
753 | rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
|
---|
754 | AssertRCReturn(rc, rc);
|
---|
755 | rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
|
---|
756 | AssertRCReturn(rc, rc);
|
---|
757 |
|
---|
758 | return VINF_SUCCESS;
|
---|
759 | }
|
---|
760 |
|
---|
761 |
|
---|
762 | /**
|
---|
763 | * Execute state load operation.
|
---|
764 | *
|
---|
765 | * @returns VBox status code.
|
---|
766 | * @param pVM VM Handle.
|
---|
767 | * @param pSSM SSM operation handle.
|
---|
768 | * @param u32Version Data layout version.
|
---|
769 | */
|
---|
770 | static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
|
---|
771 | {
|
---|
772 | int rc;
|
---|
773 |
|
---|
774 | Log(("hwaccmR3Load:\n"));
|
---|
775 |
|
---|
776 | /*
|
---|
777 | * Validate version.
|
---|
778 | */
|
---|
779 | if (u32Version != HWACCM_SSM_VERSION)
|
---|
780 | {
|
---|
781 | Log(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
|
---|
782 | return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
|
---|
783 | }
|
---|
784 | rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
|
---|
785 | AssertRCReturn(rc, rc);
|
---|
786 | rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
|
---|
787 | AssertRCReturn(rc, rc);
|
---|
788 | rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
|
---|
789 | AssertRCReturn(rc, rc);
|
---|
790 |
|
---|
791 | return VINF_SUCCESS;
|
---|
792 | }
|
---|
793 |
|
---|
794 |
|
---|
795 |
|
---|
796 |
|
---|