HWACCM.cpp@ 11043

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1	/* $Id: HWACCM.cpp 10853 2008-07-24 13:31:40Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_HWACCM
26	#include <VBox/cpum.h>
27	#include <VBox/stam.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/trpm.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/hwacc_vmx.h>
34	#include <VBox/hwacc_svm.h>
35	#include "HWACCMInternal.h"
36	#include <VBox/vm.h>
37	#include <VBox/err.h>
38	#include <VBox/param.h>
39	#include <VBox/patm.h>
40	#include <VBox/csam.h>
41	#include <VBox/selm.h>
42
43	#include <iprt/assert.h>
44	#include <VBox/log.h>
45	#include <iprt/asm.h>
46	#include <iprt/string.h>
47	#include <iprt/thread.h>
48
49	/*******************************************************************************
50	* Internal Functions *
51	*******************************************************************************/
52	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
53	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
54
55
56	/**
57	* Initializes the HWACCM.
58	*
59	* @returns VBox status code.
60	* @param pVM The VM to operate on.
61	*/
62	HWACCMR3DECL(int) HWACCMR3Init(PVM pVM)
63	{
64	LogFlow(("HWACCMR3Init\n"));
65
66	/*
67	* Assert alignment and sizes.
68	*/
69	AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
70	AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
71
72	/* Some structure checks. */
73	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
74	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
75	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
76	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
77
78	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
79	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
80	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
81	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
82	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
83	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
84	AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
85
86
87	/*
88	* Register the saved state data unit.
89	*/
90	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
91	NULL, hwaccmR3Save, NULL,
92	NULL, hwaccmR3Load, NULL);
93	if (VBOX_FAILURE(rc))
94	return rc;
95
96	/* Misc initialisation. */
97	pVM->hwaccm.s.vmx.fSupported = false;
98	pVM->hwaccm.s.svm.fSupported = false;
99	pVM->hwaccm.s.vmx.fEnabled = false;
100	pVM->hwaccm.s.svm.fEnabled = false;
101
102	pVM->hwaccm.s.fActive = false;
103	pVM->hwaccm.s.fNestedPaging = false;
104
105	/* On first entry we'll sync everything. */
106	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
107
108	pVM->hwaccm.s.vmx.cr0_mask = 0;
109	pVM->hwaccm.s.vmx.cr4_mask = 0;
110
111	/*
112	* Statistics.
113	*/
114	STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
115	STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
116	STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
117
118	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
119	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
120	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
121	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
122	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
123	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
124	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
125	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
126	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
127	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
128	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
129	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
130	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
131	STAM_REG(pVM, &pVM->hwaccm.s.StatExitRdtsc, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Rdtsc", STAMUNIT_OCCURENCES, "Nr of occurances");
132	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
133	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
134	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
135	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
136	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
137	STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
138	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
139	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
140	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/WriteString", STAMUNIT_OCCURENCES, "Nr of occurances");
141	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringRead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/ReadString", STAMUNIT_OCCURENCES, "Nr of occurances");
142	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
143	STAM_REG(pVM, &pVM->hwaccm.s.StatExitMaxResume, STAMTYPE_COUNTER, "/HWACCM/Exit/Safety/MaxResume", STAMUNIT_OCCURENCES, "Nr of occurances");
144
145	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
146	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
147
148	STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
149	STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
150	STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
151
152	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageManual, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Virt/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
153	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPhysPageManual, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Phys/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
154	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBManual, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
155	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBCRxChange, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/CRx", STAMUNIT_OCCURENCES, "Nr of occurances");
156	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageInvlpg, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
157	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Switch", STAMUNIT_OCCURENCES, "Nr of occurances");
158	STAM_REG(pVM, &pVM->hwaccm.s.StatNoFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Skipped", STAMUNIT_OCCURENCES, "Nr of occurances");
159	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushASID, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/ASID", STAMUNIT_OCCURENCES, "Nr of occurances");
160
161	STAM_REG(pVM, &pVM->hwaccm.s.StatTSCOffset, STAMTYPE_COUNTER, "/HWACCM/TSC/Offset", STAMUNIT_OCCURENCES, "Nr of occurances");
162	STAM_REG(pVM, &pVM->hwaccm.s.StatTSCIntercept, STAMTYPE_COUNTER, "/HWACCM/TSC/Intercept", STAMUNIT_OCCURENCES, "Nr of occurances");
163
164	pVM->hwaccm.s.pStatExitReason = 0;
165
166	#ifdef VBOX_WITH_STATISTICS
167	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVM->hwaccm.s.pStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.pStatExitReason);
168	AssertRC(rc);
169	if (VBOX_SUCCESS(rc))
170	{
171	for (int i=0;i<MAX_EXITREASON_STAT;i++)
172	{
173	char szName[64];
174	RTStrPrintf(szName, sizeof(szName), "/HWACCM/Exit/Reason/%02x", i);
175	int rc = STAMR3Register(pVM, &pVM->hwaccm.s.pStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "Exit reason");
176	AssertRC(rc);
177	}
178	int rc = STAMR3Register(pVM, &pVM->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, "/HWACCM/Exit/Reason/#NPF", STAMUNIT_OCCURENCES, "Exit reason");
179	AssertRC(rc);
180	}
181	pVM->hwaccm.s.pStatExitReasonR0 = MMHyperR3ToR0(pVM, pVM->hwaccm.s.pStatExitReason);
182	Assert(pVM->hwaccm.s.pStatExitReasonR0);
183	#endif
184
185	/* Disabled by default. */
186	pVM->fHWACCMEnabled = false;
187
188	/*
189	* Check CFGM options.
190	*/
191	#ifdef VBOX_WITH_NESTED_PAGING /* regressions on testboxlin */
192	/* Nested paging: enabled by default. */
193	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, true);
194	AssertRC(rc);
195	#endif
196
197	/* HWACCM support must be explicitely enabled in the configuration file. */
198	rc = CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed, false);
199	AssertRC(rc);
200
201	return VINF_SUCCESS;
202	}
203
204
205	/**
206	* Turns off normal raw mode features
207	*
208	* @param pVM The VM to operate on.
209	*/
210	static void hwaccmr3DisableRawMode(PVM pVM)
211	{
212	/* Disable PATM & CSAM. */
213	PATMR3AllowPatching(pVM, false);
214	CSAMDisableScanning(pVM);
215
216	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
217	SELMR3DisableMonitoring(pVM);
218	TRPMR3DisableMonitoring(pVM);
219
220	/* The hidden selector registers are now valid. */
221	CPUMSetHiddenSelRegsValid(pVM, true);
222
223	/* Disable the switcher code (safety precaution). */
224	VMMR3DisableSwitcher(pVM);
225
226	/* Disable mapping of the hypervisor into the shadow page table. */
227	PGMR3ChangeShwPDMappings(pVM, false);
228
229	/* Disable the switcher */
230	VMMR3DisableSwitcher(pVM);
231
232	if (pVM->hwaccm.s.fNestedPaging)
233	{
234	/* Reinit the paging mode to force the new shadow mode. */
235	PGMR3ChangeMode(pVM, PGMMODE_REAL);
236	}
237	}
238
239	/**
240	* Initialize VT-x or AMD-V.
241	*
242	* @returns VBox status code.
243	* @param pVM The VM handle.
244	*/
245	HWACCMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
246	{
247	int rc;
248
249	if ( !pVM->hwaccm.s.vmx.fSupported
250	&& !pVM->hwaccm.s.svm.fSupported)
251	{
252	LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Vrc\n", pVM->hwaccm.s.lLastError));
253	LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
254	return VINF_SUCCESS;
255	}
256
257	/*
258	* Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
259	* because it turns off paging, which is not allowed in VMX root mode.
260	*
261	* To simplify matters we'll just force all running VMs to either use raw or hwaccm mode. No mixing allowed.
262	*
263	*/
264	/* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
265	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
266	if (VBOX_FAILURE(rc))
267	{
268	LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Vrc\n", rc));
269	LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
270	/* Invert the selection */
271	pVM->hwaccm.s.fAllowed ^= 1;
272	LogRel(("HWACCMR3InitFinalize: new HWACCM status = %s\n", pVM->hwaccm.s.fAllowed ? "enabled" : "disabled"));
273
274	if (pVM->hwaccm.s.fAllowed)
275	{
276	if (pVM->hwaccm.s.vmx.fSupported)
277	VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses Intel VT-x hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using VT-x as well.\n");
278	else
279	VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses AMD-V hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using AMD-V as well.\n");
280	}
281	else
282	VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses software virtualization. It is not allowed to simultaneously use VT-x or AMD-V, therefore this VM will be run using software virtualization as well.\n");
283	}
284
285	if (pVM->hwaccm.s.fAllowed == false)
286	return VINF_SUCCESS; /* disabled */
287
288	Assert(!pVM->fHWACCMEnabled);
289
290	if (pVM->hwaccm.s.vmx.fSupported)
291	{
292	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
293
294	if ( pVM->hwaccm.s.fInitialized == false
295	&& pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
296	{
297	uint64_t val;
298
299	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
300	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
301	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
302	LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
303	LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
304	LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
305	LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
306	LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
307
308	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
309	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
310	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
311	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
312	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
313	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
314	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
315	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
316	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT must be set\n"));
317	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
318	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT must be set\n"));
319
320	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
321	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
322	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
323	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
324	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
325	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
326	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
327	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
328	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
329	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
330	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
331	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
332	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
333	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
334	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
335	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
336	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
337	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
338	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
339	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
340	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
341	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
342	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
343	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
344	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
345	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
346	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
347	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
348	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
349	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
350	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
351	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
352	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
353	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
354	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
355	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
356
357	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
358	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
359	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT must be set\n"));
360	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
361	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET must be set\n"));
362	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
363	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT must be set\n"));
364	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
365	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT must be set\n"));
366	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
367	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT must be set\n"));
368	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
369	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT must be set\n"));
370	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
371	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT must be set\n"));
372	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
373	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT must be set\n"));
374	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
375	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT must be set\n"));
376	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
377	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW must be set\n"));
378	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
379	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT must be set\n"));
380	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
381	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT must be set\n"));
382	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
383	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS must be set\n"));
384	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
385	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS must be set\n"));
386	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
387	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT must be set\n"));
388	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
389	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT must be set\n"));
390	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
391	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL must be set\n"));
392
393	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
394	{
395	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
396	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
397	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
398	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
399	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
400	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
401	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
402	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
403	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
404	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
405
406	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
407	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
408	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC must be set\n"));
409	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
410	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT must be set\n"));
411	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
412	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID must be set\n"));
413	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
414	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT must be set\n"));
415	}
416
417	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
418	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
419	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
420	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
421	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
422	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
423	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
424	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
425	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
426	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
427	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE must be set\n"));
428	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
429	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM must be set\n"));
430	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
431	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON must be set\n"));
432
433	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
434	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
435	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
436	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
437	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
438	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
439	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
440	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
441	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 must be set\n"));
442	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
443	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ must be set\n"));
444
445	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
446	{
447	LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
448
449	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
450	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
451	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
452	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
453	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
454	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
455	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
456	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
457	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
458	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
459	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
460	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
461	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
462	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
463	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
464	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
465	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
466	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
467	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
468	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
469	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
470	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
471	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
472	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
473	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
474	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
475	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
476	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
477	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
478	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
479	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
480	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
481	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
482	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
483	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
484	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
485	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
486	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
487	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
488	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
489	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
490	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
491	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
492	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
493	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
494	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
495	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
496	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
497	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
498	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
499	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
500	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
501	}
502
503	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
504	LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
505	LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
506	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
507	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
508
509	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
510	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
511	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
512	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
513	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
514
515	/* Only try once. */
516	pVM->hwaccm.s.fInitialized = true;
517
518	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
519	AssertRC(rc);
520	if (rc == VINF_SUCCESS)
521	{
522	pVM->fHWACCMEnabled = true;
523	pVM->hwaccm.s.vmx.fEnabled = true;
524	hwaccmr3DisableRawMode(pVM);
525
526	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
527	#ifdef VBOX_ENABLE_64_BITS_GUESTS
528	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
529	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
530	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
531	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
532	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
533	#endif
534	LogRel(("HWACCM: VMX enabled!\n"));
535	}
536	else
537	{
538	LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
539	LogRel(("HWACCM: Last instruction error %x\n", pVM->hwaccm.s.vmx.ulLastInstrError));
540	pVM->fHWACCMEnabled = false;
541	}
542	}
543	}
544	else
545	if (pVM->hwaccm.s.svm.fSupported)
546	{
547	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
548
549	if (pVM->hwaccm.s.fInitialized == false)
550	{
551	/* Erratum 170 which requires a forced TLB flush for each world switch:
552	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
553	*
554	* All BH-G1/2 and DH-G1/2 models include a fix:
555	* Athlon X2: 0x6b 1/2
556	* 0x68 1/2
557	* Athlon 64: 0x7f 1
558	* 0x6f 2
559	* Sempron: 0x7f 1/2
560	* 0x6f 2
561	* 0x6c 2
562	* 0x7c 2
563	* Turion 64: 0x68 2
564	*
565	*/
566	uint32_t u32Dummy;
567	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
568	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
569	u32BaseFamily= (u32Version >> 8) & 0xf;
570	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
571	u32Model = ((u32Version >> 4) & 0xf);
572	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
573	u32Stepping = u32Version & 0xf;
574	if ( u32Family == 0xf
575	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
576	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
577	{
578	LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
579	}
580
581	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
582	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
583	LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
584	LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.svm.u32MaxASID));
585	LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
586
587	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
588	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
589	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
590	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
591	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
592	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
593	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
594	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
595	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
596	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
597
598	/* Only try once. */
599	pVM->hwaccm.s.fInitialized = true;
600
601	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
602	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
603
604	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
605	AssertRC(rc);
606	if (rc == VINF_SUCCESS)
607	{
608	pVM->fHWACCMEnabled = true;
609	pVM->hwaccm.s.svm.fEnabled = true;
610
611	if (pVM->hwaccm.s.fNestedPaging)
612	LogRel(("HWACCM: Enabled nested paging\n"));
613
614	hwaccmr3DisableRawMode(pVM);
615	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
616	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
617	#ifdef VBOX_ENABLE_64_BITS_GUESTS
618	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
619	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
620	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
621	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
622	#endif
623	}
624	else
625	{
626	pVM->fHWACCMEnabled = false;
627	}
628	}
629	}
630	return VINF_SUCCESS;
631	}
632
633	/**
634	* Applies relocations to data and code managed by this
635	* component. This function will be called at init and
636	* whenever the VMM need to relocate it self inside the GC.
637	*
638	* @param pVM The VM.
639	*/
640	HWACCMR3DECL(void) HWACCMR3Relocate(PVM pVM)
641	{
642	Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
643	return;
644	}
645
646
647	/**
648	* Checks hardware accelerated raw mode is allowed.
649	*
650	* @returns boolean
651	* @param pVM The VM to operate on.
652	*/
653	HWACCMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
654	{
655	return pVM->hwaccm.s.fAllowed;
656	}
657
658
659	/**
660	* Notification callback which is called whenever there is a chance that a CR3
661	* value might have changed.
662	* This is called by PGM.
663	*
664	* @param pVM The VM to operate on.
665	* @param enmShadowMode New paging mode.
666	*/
667	HWACCMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode)
668	{
669	pVM->hwaccm.s.enmShadowMode = enmShadowMode;
670	}
671
672	/**
673	* Terminates the HWACCM.
674	*
675	* Termination means cleaning up and freeing all resources,
676	* the VM it self is at this point powered off or suspended.
677	*
678	* @returns VBox status code.
679	* @param pVM The VM to operate on.
680	*/
681	HWACCMR3DECL(int) HWACCMR3Term(PVM pVM)
682	{
683	if (pVM->hwaccm.s.pStatExitReason)
684	{
685	MMHyperFree(pVM, pVM->hwaccm.s.pStatExitReason);
686	pVM->hwaccm.s.pStatExitReason = 0;
687	}
688	return 0;
689	}
690
691
692	/**
693	* The VM is being reset.
694	*
695	* For the HWACCM component this means that any GDT/LDT/TSS monitors
696	* needs to be removed.
697	*
698	* @param pVM VM handle.
699	*/
700	HWACCMR3DECL(void) HWACCMR3Reset(PVM pVM)
701	{
702	LogFlow(("HWACCMR3Reset:\n"));
703
704	if (pVM->fHWACCMEnabled)
705	hwaccmr3DisableRawMode(pVM);
706
707	/* On first entry we'll sync everything. */
708	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
709
710	pVM->hwaccm.s.vmx.cr0_mask = 0;
711	pVM->hwaccm.s.vmx.cr4_mask = 0;
712
713	pVM->hwaccm.s.Event.fPending = false;
714	}
715
716	/**
717	* Checks if we can currently use hardware accelerated raw mode.
718	*
719	* @returns boolean
720	* @param pVM The VM to operate on.
721	* @param pCtx Partial VM execution context
722	*/
723	HWACCMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
724	{
725	Assert(pVM->fHWACCMEnabled);
726
727	/* AMD SVM supports real & protected mode with or without paging. */
728	if (pVM->hwaccm.s.svm.fEnabled)
729	{
730	pVM->hwaccm.s.fActive = true;
731	return true;
732	}
733
734	/* @todo we can support real-mode by using v86 with identity mapped pages.
735	* (but do we really care?)
736	*/
737
738	pVM->hwaccm.s.fActive = false;
739
740	/** @note The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
741
742	if (!CPUMIsGuestInLongModeEx(pCtx))
743	{
744	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
745	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
746	return false;
747
748	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
749	/* Windows XP; switch to protected mode; all selectors are marked not present in the
750	* hidden registers (possible recompiler bug; see load_seg_vm) */
751	if (pCtx->csHid.Attr.n.u1Present == 0)
752	return false;
753	if (pCtx->ssHid.Attr.n.u1Present == 0)
754	return false;
755	}
756
757	if (pVM->hwaccm.s.vmx.fEnabled)
758	{
759	uint32_t mask;
760
761	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
762	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
763	/* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
764	mask &= ~X86_CR0_NE;
765	#ifdef HWACCM_VMX_EMULATE_ALL
766	/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
767	mask &= ~(X86_CR0_PG\|X86_CR0_PE);
768	#endif
769	if ((pCtx->cr0 & mask) != mask)
770	return false;
771
772	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
773	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
774	if ((pCtx->cr0 & mask) != 0)
775	return false;
776
777	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
778	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
779	mask &= ~X86_CR4_VMXE;
780	if ((pCtx->cr4 & mask) != mask)
781	return false;
782
783	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
784	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
785	if ((pCtx->cr4 & mask) != 0)
786	return false;
787
788	pVM->hwaccm.s.fActive = true;
789	return true;
790	}
791
792	return false;
793	}
794
795	/**
796	* Checks if we are currently using hardware accelerated raw mode.
797	*
798	* @returns boolean
799	* @param pVM The VM to operate on.
800	*/
801	HWACCMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
802	{
803	return pVM->hwaccm.s.fActive;
804	}
805
806	/**
807	* Checks if we are currently using nested paging.
808	*
809	* @returns boolean
810	* @param pVM The VM to operate on.
811	*/
812	HWACCMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
813	{
814	return pVM->hwaccm.s.fNestedPaging;
815	}
816
817	/**
818	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
819	*
820	* @returns boolean
821	* @param pVM The VM to operate on.
822	*/
823	HWACCMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
824	{
825	return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
826	}
827
828	/**
829	* Execute state save operation.
830	*
831	* @returns VBox status code.
832	* @param pVM VM Handle.
833	* @param pSSM SSM operation handle.
834	*/
835	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
836	{
837	int rc;
838
839	Log(("hwaccmR3Save:\n"));
840
841	/*
842	* Save the basic bits - fortunately all the other things can be resynced on load.
843	*/
844	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
845	AssertRCReturn(rc, rc);
846	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
847	AssertRCReturn(rc, rc);
848	rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
849	AssertRCReturn(rc, rc);
850
851	return VINF_SUCCESS;
852	}
853
854
855	/**
856	* Execute state load operation.
857	*
858	* @returns VBox status code.
859	* @param pVM VM Handle.
860	* @param pSSM SSM operation handle.
861	* @param u32Version Data layout version.
862	*/
863	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
864	{
865	int rc;
866
867	Log(("hwaccmR3Load:\n"));
868
869	/*
870	* Validate version.
871	*/
872	if (u32Version != HWACCM_SSM_VERSION)
873	{
874	Log(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
875	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
876	}
877	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
878	AssertRCReturn(rc, rc);
879	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
880	AssertRCReturn(rc, rc);
881	rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
882	AssertRCReturn(rc, rc);
883
884	return VINF_SUCCESS;
885	}
886
887
888
889

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source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 11043

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