VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 12746

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1/* $Id: HWACCM.cpp 12746 2008-09-25 15:18:01Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/hwacc_vmx.h>
34#include <VBox/hwacc_svm.h>
35#include "HWACCMInternal.h"
36#include <VBox/vm.h>
37#include <VBox/err.h>
38#include <VBox/param.h>
39#include <VBox/patm.h>
40#include <VBox/csam.h>
41#include <VBox/selm.h>
42
43#include <iprt/assert.h>
44#include <VBox/log.h>
45#include <iprt/asm.h>
46#include <iprt/string.h>
47#include <iprt/thread.h>
48
49/*******************************************************************************
50* Internal Functions *
51*******************************************************************************/
52static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
53static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
54
55
56/**
57 * Initializes the HWACCM.
58 *
59 * @returns VBox status code.
60 * @param pVM The VM to operate on.
61 */
62HWACCMR3DECL(int) HWACCMR3Init(PVM pVM)
63{
64 LogFlow(("HWACCMR3Init\n"));
65
66 /*
67 * Assert alignment and sizes.
68 */
69 AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
70 AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
71
72 /* Some structure checks. */
73 AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
74 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
75 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
76 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
77
78 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
79 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
80 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
81 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
82 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
83 AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
84 AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
85
86
87 /*
88 * Register the saved state data unit.
89 */
90 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
91 NULL, hwaccmR3Save, NULL,
92 NULL, hwaccmR3Load, NULL);
93 if (VBOX_FAILURE(rc))
94 return rc;
95
96 /* Misc initialisation. */
97 pVM->hwaccm.s.vmx.fSupported = false;
98 pVM->hwaccm.s.svm.fSupported = false;
99 pVM->hwaccm.s.vmx.fEnabled = false;
100 pVM->hwaccm.s.svm.fEnabled = false;
101
102 pVM->hwaccm.s.fActive = false;
103 pVM->hwaccm.s.fNestedPaging = false;
104
105 /* On first entry we'll sync everything. */
106 pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
107
108 pVM->hwaccm.s.vmx.cr0_mask = 0;
109 pVM->hwaccm.s.vmx.cr4_mask = 0;
110
111 /*
112 * Statistics.
113 */
114 STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
115 STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
116 STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
117
118 STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
119 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
120 STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
121 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
122 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
123 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
124 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
125 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
126 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
127 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
128 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDB, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DB", STAMUNIT_OCCURENCES, "Nr of occurances");
129 STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
130 STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
131 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
132 STAM_REG(pVM, &pVM->hwaccm.s.StatExitRdtsc, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Rdtsc", STAMUNIT_OCCURENCES, "Nr of occurances");
133 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
134 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
135 STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
136 STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
137 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
138 STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
139 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
140 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
141 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/WriteString", STAMUNIT_OCCURENCES, "Nr of occurances");
142 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringRead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/ReadString", STAMUNIT_OCCURENCES, "Nr of occurances");
143 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
144 STAM_REG(pVM, &pVM->hwaccm.s.StatExitMaxResume, STAMTYPE_COUNTER, "/HWACCM/Exit/Safety/MaxResume", STAMUNIT_OCCURENCES, "Nr of occurances");
145
146 STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
147 STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
148
149 STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
150 STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
151 STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
152
153 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageManual, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Virt/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
154 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPhysPageManual, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Phys/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
155 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBManual, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
156 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBCRxChange, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/CRx", STAMUNIT_OCCURENCES, "Nr of occurances");
157 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageInvlpg, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
158 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Switch", STAMUNIT_OCCURENCES, "Nr of occurances");
159 STAM_REG(pVM, &pVM->hwaccm.s.StatNoFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Skipped", STAMUNIT_OCCURENCES, "Nr of occurances");
160 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushASID, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/ASID", STAMUNIT_OCCURENCES, "Nr of occurances");
161
162 STAM_REG(pVM, &pVM->hwaccm.s.StatTSCOffset, STAMTYPE_COUNTER, "/HWACCM/TSC/Offset", STAMUNIT_OCCURENCES, "Nr of occurances");
163 STAM_REG(pVM, &pVM->hwaccm.s.StatTSCIntercept, STAMTYPE_COUNTER, "/HWACCM/TSC/Intercept", STAMUNIT_OCCURENCES, "Nr of occurances");
164
165 STAM_REG(pVM, &pVM->hwaccm.s.StatDRxArmed, STAMTYPE_COUNTER, "/HWACCM/Debug/Armed", STAMUNIT_OCCURENCES, "Nr of occurances");
166 STAM_REG(pVM, &pVM->hwaccm.s.StatDRxContextSwitch, STAMTYPE_COUNTER, "/HWACCM/Debug/ContextSwitch", STAMUNIT_OCCURENCES, "Nr of occurances");
167 STAM_REG(pVM, &pVM->hwaccm.s.StatDRxIOCheck, STAMTYPE_COUNTER, "/HWACCM/Debug/IOCheck", STAMUNIT_OCCURENCES, "Nr of occurances");
168
169 pVM->hwaccm.s.paStatExitReason = NULL;
170
171#ifdef VBOX_WITH_STATISTICS
172 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVM->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.paStatExitReason);
173 AssertRC(rc);
174 if (VBOX_SUCCESS(rc))
175 {
176 for (int i=0;i<MAX_EXITREASON_STAT;i++)
177 {
178 int rc = STAMR3RegisterF(pVM, &pVM->hwaccm.s.paStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Exit reason",
179 "/HWACCM/Exit/Reason/%02x", i);
180 AssertRC(rc);
181 }
182 int rc = STAMR3Register(pVM, &pVM->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, "/HWACCM/Exit/Reason/#NPF", STAMUNIT_OCCURENCES, "Exit reason");
183 AssertRC(rc);
184 }
185 pVM->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVM->hwaccm.s.paStatExitReason);
186 Assert(pVM->hwaccm.s.paStatExitReasonR0);
187#endif
188
189 /* Disabled by default. */
190 pVM->fHWACCMEnabled = false;
191
192 /*
193 * Check CFGM options.
194 */
195 /* Nested paging: disabled by default. */
196 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
197 AssertRC(rc);
198
199 /* HWACCM support must be explicitely enabled in the configuration file. */
200 rc = CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed, false);
201 AssertRC(rc);
202
203 return VINF_SUCCESS;
204}
205
206/**
207 * Turns off normal raw mode features
208 *
209 * @param pVM The VM to operate on.
210 */
211static void hwaccmR3DisableRawMode(PVM pVM)
212{
213 /* Disable PATM & CSAM. */
214 PATMR3AllowPatching(pVM, false);
215 CSAMDisableScanning(pVM);
216
217 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
218 SELMR3DisableMonitoring(pVM);
219 TRPMR3DisableMonitoring(pVM);
220
221 /* The hidden selector registers are now valid. */
222 CPUMSetHiddenSelRegsValid(pVM, true);
223
224 /* Disable the switcher code (safety precaution). */
225 VMMR3DisableSwitcher(pVM);
226
227 /* Disable mapping of the hypervisor into the shadow page table. */
228 PGMR3ChangeShwPDMappings(pVM, false);
229
230 /* Disable the switcher */
231 VMMR3DisableSwitcher(pVM);
232
233 if (pVM->hwaccm.s.fNestedPaging)
234 {
235 /* Reinit the paging mode to force the new shadow mode. */
236 PGMR3ChangeMode(pVM, PGMMODE_REAL);
237 }
238}
239
240/**
241 * Initialize VT-x or AMD-V.
242 *
243 * @returns VBox status code.
244 * @param pVM The VM handle.
245 */
246HWACCMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
247{
248 int rc;
249
250 if ( !pVM->hwaccm.s.vmx.fSupported
251 && !pVM->hwaccm.s.svm.fSupported)
252 {
253 LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Vrc\n", pVM->hwaccm.s.lLastError));
254 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
255 return VINF_SUCCESS;
256 }
257
258 /*
259 * Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
260 * because it turns off paging, which is not allowed in VMX root mode.
261 *
262 * To simplify matters we'll just force all running VMs to either use raw or hwaccm mode. No mixing allowed.
263 *
264 */
265 /* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
266 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
267 if (VBOX_FAILURE(rc))
268 {
269 LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Vrc\n", rc));
270 LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
271 /* Invert the selection */
272 pVM->hwaccm.s.fAllowed ^= 1;
273 LogRel(("HWACCMR3InitFinalize: new HWACCM status = %s\n", pVM->hwaccm.s.fAllowed ? "enabled" : "disabled"));
274
275 if (pVM->hwaccm.s.fAllowed)
276 {
277 if (pVM->hwaccm.s.vmx.fSupported)
278 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses Intel VT-x hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using VT-x as well.\n");
279 else
280 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses AMD-V hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using AMD-V as well.\n");
281 }
282 else
283 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses software virtualization. It is not allowed to simultaneously use VT-x or AMD-V, therefore this VM will be run using software virtualization as well.\n");
284 }
285
286 if (pVM->hwaccm.s.fAllowed == false)
287 return VINF_SUCCESS; /* disabled */
288
289 Assert(!pVM->fHWACCMEnabled);
290
291 if (pVM->hwaccm.s.vmx.fSupported)
292 {
293 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
294
295 if ( pVM->hwaccm.s.fInitialized == false
296 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
297 {
298 uint64_t val;
299
300 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
301 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
302 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
303 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
304 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
305 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
306 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
307 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
308
309 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
310 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
311 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
312 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
313 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
314 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
315 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
316 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
317 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
318 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
319 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
320
321 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
322 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
323 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
324 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
325 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
326 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
327 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
328 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
329 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
330 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
331 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
332 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
333 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
334 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
335 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
336 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
337 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
338 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
339 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
340 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
341 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
342 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
343 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
344 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
345 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
346 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
347 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
348 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
349 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
350 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
351 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
352 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
353 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
354 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
355 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
356 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
357
358 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
359 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
360 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
361 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
362 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
363 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
364 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
365 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
366 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
367 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
368 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
369 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
370 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
371 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
372 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
373 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
374 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
375 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
376 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
377 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
378 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
379 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
380 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
381 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
382 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
383 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
384 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
385 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
386 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
387 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
388 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
389 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
390 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
391 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
392 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
393
394 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
395 {
396 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
397 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
398 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
399 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
400 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
401 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
402 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
403 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
404 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
405 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
406
407 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
408 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
409 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
410 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
411 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
412 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
413 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
414 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
415 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
416 }
417
418 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
419 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
420 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
421 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
422 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
423 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
424 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
425 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
426 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
427 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
428 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
429 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
430 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
431 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
432 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
433
434 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
435 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
436 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
437 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
438 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
439 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
440 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
441 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
442 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
443 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
444 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
445
446 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
447 {
448 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
449
450 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
451 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
452 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
453 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
454 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
455 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
456 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
457 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
458 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
459 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
460 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
461 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
462 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
463 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
464 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
465 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
466 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
467 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
468 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
469 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
470 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
471 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
472 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
473 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
474 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
475 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
476 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
477 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
478 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
479 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
480 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
481 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
482 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
483 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
484 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
485 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
486 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
487 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
488 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
489 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
490 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
491 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
492 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
493 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
494 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
495 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
496 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
497 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
498 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
499 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
500 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
501 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
502 }
503
504 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
505 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
506 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
507 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
508 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
509
510 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
511 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
512 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
513 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
514 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
515
516 LogRel(("HWACCM: VMCS physaddr = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
517 LogRel(("HWACCM: TPR shadow physaddr = %VHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
518 LogRel(("HWACCM: MSR bitmap physaddr = %VHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
519
520 /* Only try once. */
521 pVM->hwaccm.s.fInitialized = true;
522
523 /* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
524 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TSS_SIZE, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
525 AssertRC(rc);
526 if (RT_FAILURE(rc))
527 return rc;
528
529 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
530 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
531 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
532 /* Bit set to 0 means redirection enabled. */
533 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
534 /* Allow all port IO, so the VT-x IO intercepts do their job. */
535 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
536 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
537
538 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
539 AssertRC(rc);
540 if (rc == VINF_SUCCESS)
541 {
542 pVM->fHWACCMEnabled = true;
543 pVM->hwaccm.s.vmx.fEnabled = true;
544 hwaccmR3DisableRawMode(pVM);
545
546 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
547#ifdef VBOX_ENABLE_64_BITS_GUESTS
548 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
549 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
550 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
551 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
552 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
553#endif
554 LogRel(("HWACCM: VMX enabled!\n"));
555 }
556 else
557 {
558 LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
559 LogRel(("HWACCM: Last instruction error %x\n", pVM->hwaccm.s.vmx.ulLastInstrError));
560 pVM->fHWACCMEnabled = false;
561 }
562 }
563 }
564 else
565 if (pVM->hwaccm.s.svm.fSupported)
566 {
567 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
568
569 if (pVM->hwaccm.s.fInitialized == false)
570 {
571 /* Erratum 170 which requires a forced TLB flush for each world switch:
572 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
573 *
574 * All BH-G1/2 and DH-G1/2 models include a fix:
575 * Athlon X2: 0x6b 1/2
576 * 0x68 1/2
577 * Athlon 64: 0x7f 1
578 * 0x6f 2
579 * Sempron: 0x7f 1/2
580 * 0x6f 2
581 * 0x6c 2
582 * 0x7c 2
583 * Turion 64: 0x68 2
584 *
585 */
586 uint32_t u32Dummy;
587 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
588 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
589 u32BaseFamily= (u32Version >> 8) & 0xf;
590 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
591 u32Model = ((u32Version >> 4) & 0xf);
592 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
593 u32Stepping = u32Version & 0xf;
594 if ( u32Family == 0xf
595 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
596 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
597 {
598 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
599 }
600
601 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
602 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
603 LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
604 LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.svm.u32MaxASID));
605 LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
606
607 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
608 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
609 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
610 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
611 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
612 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
613 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
614 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
615 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
616 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
617
618 /* Only try once. */
619 pVM->hwaccm.s.fInitialized = true;
620
621 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
622 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
623
624 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
625 AssertRC(rc);
626 if (rc == VINF_SUCCESS)
627 {
628 pVM->fHWACCMEnabled = true;
629 pVM->hwaccm.s.svm.fEnabled = true;
630
631 if (pVM->hwaccm.s.fNestedPaging)
632 LogRel(("HWACCM: Enabled nested paging\n"));
633
634 hwaccmR3DisableRawMode(pVM);
635 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
636 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
637#ifdef VBOX_ENABLE_64_BITS_GUESTS
638 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
639 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
640 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
641 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
642#endif
643 }
644 else
645 {
646 pVM->fHWACCMEnabled = false;
647 }
648 }
649 }
650 return VINF_SUCCESS;
651}
652
653/**
654 * Applies relocations to data and code managed by this
655 * component. This function will be called at init and
656 * whenever the VMM need to relocate it self inside the GC.
657 *
658 * @param pVM The VM.
659 */
660HWACCMR3DECL(void) HWACCMR3Relocate(PVM pVM)
661{
662 Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
663 return;
664}
665
666/**
667 * Checks hardware accelerated raw mode is allowed.
668 *
669 * @returns boolean
670 * @param pVM The VM to operate on.
671 */
672HWACCMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
673{
674 return pVM->hwaccm.s.fAllowed;
675}
676
677/**
678 * Notification callback which is called whenever there is a chance that a CR3
679 * value might have changed.
680 *
681 * This is called by PGM.
682 *
683 * @param pVM The VM to operate on.
684 * @param enmShadowMode New paging mode.
685 */
686HWACCMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode)
687{
688 pVM->hwaccm.s.enmShadowMode = enmShadowMode;
689}
690
691/**
692 * Terminates the HWACCM.
693 *
694 * Termination means cleaning up and freeing all resources,
695 * the VM it self is at this point powered off or suspended.
696 *
697 * @returns VBox status code.
698 * @param pVM The VM to operate on.
699 */
700HWACCMR3DECL(int) HWACCMR3Term(PVM pVM)
701{
702 if (pVM->hwaccm.s.vmx.pRealModeTSS)
703 {
704 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
705 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
706 }
707
708 if (pVM->hwaccm.s.paStatExitReason)
709 {
710 MMHyperFree(pVM, pVM->hwaccm.s.paStatExitReason);
711 pVM->hwaccm.s.paStatExitReason = NULL;
712 }
713 return 0;
714}
715
716/**
717 * The VM is being reset.
718 *
719 * For the HWACCM component this means that any GDT/LDT/TSS monitors
720 * needs to be removed.
721 *
722 * @param pVM VM handle.
723 */
724HWACCMR3DECL(void) HWACCMR3Reset(PVM pVM)
725{
726 LogFlow(("HWACCMR3Reset:\n"));
727
728 if (pVM->fHWACCMEnabled)
729 hwaccmR3DisableRawMode(pVM);
730
731 /* On first entry we'll sync everything. */
732 pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
733
734 pVM->hwaccm.s.vmx.cr0_mask = 0;
735 pVM->hwaccm.s.vmx.cr4_mask = 0;
736
737 pVM->hwaccm.s.Event.fPending = false;
738}
739
740/**
741 * Checks if we can currently use hardware accelerated raw mode.
742 *
743 * @returns boolean
744 * @param pVM The VM to operate on.
745 * @param pCtx Partial VM execution context
746 */
747HWACCMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
748{
749 Assert(pVM->fHWACCMEnabled);
750
751 /* AMD SVM supports real & protected mode with or without paging. */
752 if (pVM->hwaccm.s.svm.fEnabled)
753 {
754 pVM->hwaccm.s.fActive = true;
755 return true;
756 }
757
758 /** @todo we can support real-mode by using v86 with identity mapped pages.
759 * (but do we really care?)
760 */
761
762 pVM->hwaccm.s.fActive = false;
763
764 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
765
766 if (!CPUMIsGuestInLongModeEx(pCtx))
767 {
768 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
769 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
770 return false;
771
772 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
773 /* Windows XP; switch to protected mode; all selectors are marked not present in the
774 * hidden registers (possible recompiler bug; see load_seg_vm) */
775 if (pCtx->csHid.Attr.n.u1Present == 0)
776 return false;
777 if (pCtx->ssHid.Attr.n.u1Present == 0)
778 return false;
779 }
780
781 if (pVM->hwaccm.s.vmx.fEnabled)
782 {
783 uint32_t mask;
784
785 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
786 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
787 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
788 mask &= ~X86_CR0_NE;
789 /* We support protected mode without paging using identity mapping. */
790 mask &= ~X86_CR0_PG;
791
792#ifdef HWACCM_VMX_EMULATE_ALL
793 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
794 mask &= ~(X86_CR0_PG|X86_CR0_PE);
795#endif
796 if ((pCtx->cr0 & mask) != mask)
797 return false;
798
799 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
800 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
801 if ((pCtx->cr0 & mask) != 0)
802 return false;
803
804 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
805 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
806 mask &= ~X86_CR4_VMXE;
807 if ((pCtx->cr4 & mask) != mask)
808 return false;
809
810 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
811 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
812 if ((pCtx->cr4 & mask) != 0)
813 return false;
814
815 pVM->hwaccm.s.fActive = true;
816 return true;
817 }
818
819 return false;
820}
821
822/**
823 * Checks if we are currently using hardware accelerated raw mode.
824 *
825 * @returns boolean
826 * @param pVM The VM to operate on.
827 */
828HWACCMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
829{
830 return pVM->hwaccm.s.fActive;
831}
832
833/**
834 * Checks if we are currently using nested paging.
835 *
836 * @returns boolean
837 * @param pVM The VM to operate on.
838 */
839HWACCMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
840{
841 return pVM->hwaccm.s.fNestedPaging;
842}
843
844/**
845 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
846 *
847 * @returns boolean
848 * @param pVM The VM to operate on.
849 */
850HWACCMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
851{
852 return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
853}
854
855/**
856 * Check fatal VT-x/AMD-V error and produce some meaningful
857 * log release message.
858 *
859 * @param pVM The VM to operate on.
860 * @param iStatusCode VBox status code
861 */
862HWACCMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
863{
864 switch(iStatusCode)
865 {
866 case VERR_VMX_INVALID_VMCS_FIELD:
867 break;
868
869 case VERR_VMX_INVALID_VMCS_PTR:
870 LogRel(("VERR_VMX_INVALID_VMCS_PTR: Current pointer %VGp vs %VGp\n", pVM->hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->hwaccm.s.vmx.pVMCSPhys));
871 LogRel(("VERR_VMX_INVALID_VMCS_PTR: Current VMCS version %x\n", pVM->hwaccm.s.vmx.lasterror.ulVMCSRevision));
872 break;
873
874 case VERR_VMX_INVALID_VMXON_PTR:
875 break;
876 }
877}
878
879/**
880 * Execute state save operation.
881 *
882 * @returns VBox status code.
883 * @param pVM VM Handle.
884 * @param pSSM SSM operation handle.
885 */
886static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
887{
888 int rc;
889
890 Log(("hwaccmR3Save:\n"));
891
892 /*
893 * Save the basic bits - fortunately all the other things can be resynced on load.
894 */
895 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
896 AssertRCReturn(rc, rc);
897 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
898 AssertRCReturn(rc, rc);
899 rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
900 AssertRCReturn(rc, rc);
901
902 return VINF_SUCCESS;
903}
904
905/**
906 * Execute state load operation.
907 *
908 * @returns VBox status code.
909 * @param pVM VM Handle.
910 * @param pSSM SSM operation handle.
911 * @param u32Version Data layout version.
912 */
913static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
914{
915 int rc;
916
917 Log(("hwaccmR3Load:\n"));
918
919 /*
920 * Validate version.
921 */
922 if (u32Version != HWACCM_SSM_VERSION)
923 {
924 AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
925 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
926 }
927 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
928 AssertRCReturn(rc, rc);
929 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
930 AssertRCReturn(rc, rc);
931 rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
932 AssertRCReturn(rc, rc);
933
934 return VINF_SUCCESS;
935}
936
937
938
939
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