HWACCM.cpp@ 13626

Last change on this file since 13626 was 13565, checked in by vboxsync, 16 years ago
#1865: REM (VMM bits) - moved EMFlushREMTBs to REMFlushTBs, deleted dead REMGC.cpp.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 58.1 KB

Line
1	/* $Id: HWACCM.cpp 13565 2008-10-24 17:48:59Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_HWACCM
26	#include <VBox/cpum.h>
27	#include <VBox/stam.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/trpm.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/patm.h>
34	#include <VBox/csam.h>
35	#include <VBox/selm.h>
36	#include <VBox/rem.h>
37	#include <VBox/hwacc_vmx.h>
38	#include <VBox/hwacc_svm.h>
39	#include "HWACCMInternal.h"
40	#include <VBox/vm.h>
41	#include <VBox/err.h>
42	#include <VBox/param.h>
43
44	#include <iprt/assert.h>
45	#include <VBox/log.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48	#include <iprt/thread.h>
49
50	/*******************************************************************************
51	* Internal Functions *
52	*******************************************************************************/
53	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
54	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
55
56
57	/**
58	* Initializes the HWACCM.
59	*
60	* @returns VBox status code.
61	* @param pVM The VM to operate on.
62	*/
63	VMMR3DECL(int) HWACCMR3Init(PVM pVM)
64	{
65	LogFlow(("HWACCMR3Init\n"));
66
67	/*
68	* Assert alignment and sizes.
69	*/
70	AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
71	AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
72
73	/* Some structure checks. */
74	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
75	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
76	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
77	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
78
79	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
80	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
81	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
82	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
83	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
84	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
85	AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
86
87
88	/*
89	* Register the saved state data unit.
90	*/
91	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
92	NULL, hwaccmR3Save, NULL,
93	NULL, hwaccmR3Load, NULL);
94	if (VBOX_FAILURE(rc))
95	return rc;
96
97	/* Misc initialisation. */
98	pVM->hwaccm.s.vmx.fSupported = false;
99	pVM->hwaccm.s.svm.fSupported = false;
100	pVM->hwaccm.s.vmx.fEnabled = false;
101	pVM->hwaccm.s.svm.fEnabled = false;
102
103	pVM->hwaccm.s.fActive = false;
104	pVM->hwaccm.s.fNestedPaging = false;
105
106	/* On first entry we'll sync everything. */
107	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
108
109	pVM->hwaccm.s.vmx.cr0_mask = 0;
110	pVM->hwaccm.s.vmx.cr4_mask = 0;
111
112	/*
113	* Statistics.
114	*/
115	STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
116	STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
117	STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
118
119	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
120	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
121	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
122	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
123	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
124	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
125	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
126	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
127	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
128	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
129	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDB, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DB", STAMUNIT_OCCURENCES, "Nr of occurances");
130	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
131	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
132	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
133	STAM_REG(pVM, &pVM->hwaccm.s.StatExitRdtsc, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Rdtsc", STAMUNIT_OCCURENCES, "Nr of occurances");
134	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
135	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
136	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
137	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
138	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
139	STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
140	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
141	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
142	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/WriteString", STAMUNIT_OCCURENCES, "Nr of occurances");
143	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringRead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/ReadString", STAMUNIT_OCCURENCES, "Nr of occurances");
144	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
145	STAM_REG(pVM, &pVM->hwaccm.s.StatExitMaxResume, STAMTYPE_COUNTER, "/HWACCM/Exit/Safety/MaxResume", STAMUNIT_OCCURENCES, "Nr of occurances");
146
147	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
148	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
149
150	STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
151	STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
152	STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
153
154	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageManual, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Virt/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
155	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPhysPageManual, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Phys/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
156	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBManual, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
157	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBCRxChange, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/CRx", STAMUNIT_OCCURENCES, "Nr of occurances");
158	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageInvlpg, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
159	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Switch", STAMUNIT_OCCURENCES, "Nr of occurances");
160	STAM_REG(pVM, &pVM->hwaccm.s.StatNoFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Skipped", STAMUNIT_OCCURENCES, "Nr of occurances");
161	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushASID, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/ASID", STAMUNIT_OCCURENCES, "Nr of occurances");
162	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBInvlpga, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/PhysInvlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
163
164	STAM_REG(pVM, &pVM->hwaccm.s.StatTSCOffset, STAMTYPE_COUNTER, "/HWACCM/TSC/Offset", STAMUNIT_OCCURENCES, "Nr of occurances");
165	STAM_REG(pVM, &pVM->hwaccm.s.StatTSCIntercept, STAMTYPE_COUNTER, "/HWACCM/TSC/Intercept", STAMUNIT_OCCURENCES, "Nr of occurances");
166
167	STAM_REG(pVM, &pVM->hwaccm.s.StatDRxArmed, STAMTYPE_COUNTER, "/HWACCM/Debug/Armed", STAMUNIT_OCCURENCES, "Nr of occurances");
168	STAM_REG(pVM, &pVM->hwaccm.s.StatDRxContextSwitch, STAMTYPE_COUNTER, "/HWACCM/Debug/ContextSwitch", STAMUNIT_OCCURENCES, "Nr of occurances");
169	STAM_REG(pVM, &pVM->hwaccm.s.StatDRxIOCheck, STAMTYPE_COUNTER, "/HWACCM/Debug/IOCheck", STAMUNIT_OCCURENCES, "Nr of occurances");
170
171	pVM->hwaccm.s.paStatExitReason = NULL;
172
173	#ifdef VBOX_WITH_STATISTICS
174	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVM->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.paStatExitReason);
175	AssertRC(rc);
176	if (VBOX_SUCCESS(rc))
177	{
178	for (int i=0;i<MAX_EXITREASON_STAT;i++)
179	{
180	int rc = STAMR3RegisterF(pVM, &pVM->hwaccm.s.paStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Exit reason",
181	"/HWACCM/Exit/Reason/%02x", i);
182	AssertRC(rc);
183	}
184	int rc = STAMR3Register(pVM, &pVM->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, "/HWACCM/Exit/Reason/#NPF", STAMUNIT_OCCURENCES, "Exit reason");
185	AssertRC(rc);
186	}
187	pVM->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVM->hwaccm.s.paStatExitReason);
188	Assert(pVM->hwaccm.s.paStatExitReasonR0);
189	#endif
190
191	/* Disabled by default. */
192	pVM->fHWACCMEnabled = false;
193
194	/*
195	* Check CFGM options.
196	*/
197	/* Nested paging: disabled by default. */
198	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
199	AssertRC(rc);
200
201	/* VT-x VPID: disabled by default. */
202	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableVPID", &pVM->hwaccm.s.fAllowVPID, false);
203	AssertRC(rc);
204
205	/* HWACCM support must be explicitely enabled in the configuration file. */
206	rc = CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed, false);
207	AssertRC(rc);
208
209	return VINF_SUCCESS;
210	}
211
212	/**
213	* Turns off normal raw mode features
214	*
215	* @param pVM The VM to operate on.
216	*/
217	static void hwaccmR3DisableRawMode(PVM pVM)
218	{
219	/* Disable PATM & CSAM. */
220	PATMR3AllowPatching(pVM, false);
221	CSAMDisableScanning(pVM);
222
223	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
224	SELMR3DisableMonitoring(pVM);
225	TRPMR3DisableMonitoring(pVM);
226
227	/* The hidden selector registers are now valid. */
228	CPUMSetHiddenSelRegsValid(pVM, true);
229
230	/* Disable the switcher code (safety precaution). */
231	VMMR3DisableSwitcher(pVM);
232
233	/* Disable mapping of the hypervisor into the shadow page table. */
234	PGMR3ChangeShwPDMappings(pVM, false);
235
236	/* Disable the switcher */
237	VMMR3DisableSwitcher(pVM);
238
239	if (pVM->hwaccm.s.fNestedPaging)
240	{
241	/* Reinit the paging mode to force the new shadow mode. */
242	PGMR3ChangeMode(pVM, PGMMODE_REAL);
243	}
244	}
245
246	/**
247	* Initialize VT-x or AMD-V.
248	*
249	* @returns VBox status code.
250	* @param pVM The VM handle.
251	*/
252	VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
253	{
254	int rc;
255
256	if ( !pVM->hwaccm.s.vmx.fSupported
257	&& !pVM->hwaccm.s.svm.fSupported)
258	{
259	LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Vrc\n", pVM->hwaccm.s.lLastError));
260	LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
261	return VINF_SUCCESS;
262	}
263
264	/*
265	* Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
266	* because it turns off paging, which is not allowed in VMX root mode.
267	*
268	* To simplify matters we'll just force all running VMs to either use raw or hwaccm mode. No mixing allowed.
269	*
270	*/
271	/* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
272	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
273	if (VBOX_FAILURE(rc))
274	{
275	LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Vrc\n", rc));
276	LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
277	/* Invert the selection */
278	pVM->hwaccm.s.fAllowed ^= 1;
279	LogRel(("HWACCMR3InitFinalize: new HWACCM status = %s\n", pVM->hwaccm.s.fAllowed ? "enabled" : "disabled"));
280
281	if (pVM->hwaccm.s.fAllowed)
282	{
283	if (pVM->hwaccm.s.vmx.fSupported)
284	VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses Intel VT-x hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using VT-x as well.\n");
285	else
286	VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses AMD-V hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using AMD-V as well.\n");
287	}
288	else
289	VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses software virtualization. It is not allowed to simultaneously use VT-x or AMD-V, therefore this VM will be run using software virtualization as well.\n");
290	}
291
292	if (pVM->hwaccm.s.fAllowed == false)
293	return VINF_SUCCESS; /* disabled */
294
295	Assert(!pVM->fHWACCMEnabled);
296
297	if (pVM->hwaccm.s.vmx.fSupported)
298	{
299	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
300
301	if ( pVM->hwaccm.s.fInitialized == false
302	&& pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
303	{
304	uint64_t val;
305	RTGCPHYS GCPhys = 0;
306
307	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
308	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
309	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
310	LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
311	LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
312	LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
313	LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
314	LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
315
316	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
317	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
318	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
319	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
320	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
321	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
322	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
323	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
324	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT must be set\n"));
325	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
326	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT must be set\n"));
327
328	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
329	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
330	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
331	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
332	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
333	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
334	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
335	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
336	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
337	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
338	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
339	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
340	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
341	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
342	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
343	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
344	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
345	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
346	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
347	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
348	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
349	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
350	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
351	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
352	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
353	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
354	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
355	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
356	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
357	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
358	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
359	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
360	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
361	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
362	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
363	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
364	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
365	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
366	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
367	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
368	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
369	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
370
371	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
372	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
373	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT must be set\n"));
374	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
375	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET must be set\n"));
376	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
377	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT must be set\n"));
378	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
379	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT must be set\n"));
380	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
381	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT must be set\n"));
382	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
383	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT must be set\n"));
384	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
385	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT must be set\n"));
386	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
387	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT must be set\n"));
388	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
389	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT must be set\n"));
390	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
391	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT must be set\n"));
392	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
393	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT must be set\n"));
394	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
395	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW must be set\n"));
396	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
397	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT must be set\n"));
398	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
399	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT must be set\n"));
400	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
401	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS must be set\n"));
402	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
403	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG must be set\n"));
404	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
405	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS must be set\n"));
406	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
407	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT must be set\n"));
408	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
409	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT must be set\n"));
410	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
411	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL must be set\n"));
412
413	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
414	{
415	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
416	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
417	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
418	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
419	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
420	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
421	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
422	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
423	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
424	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
425
426	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
427	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
428	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC must be set\n"));
429	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
430	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT must be set\n"));
431	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
432	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID must be set\n"));
433	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
434	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT must be set\n"));
435	}
436
437	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
438	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
439	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
440	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
441	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
442	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
443	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
444	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
445	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
446	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
447	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
448	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
449	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
450	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
451	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
452	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
453	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
454	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
455	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG must be set\n"));
456	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
457	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE must be set\n"));
458	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
459	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM must be set\n"));
460	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
461	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON must be set\n"));
462	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
463	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR must be set\n"));
464	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
465	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR must be set\n"));
466	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
467	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR must be set\n"));
468
469	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
470	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
471	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
472	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
473	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
474	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
475	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
476	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
477	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
478	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
479	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
480	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
481	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
482	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
483	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
484	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
485	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
486	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
487	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
488	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
489	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG must be set\n"));
490	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
491	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 must be set\n"));
492	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
493	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ must be set\n"));
494	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
495	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR must be set\n"));
496	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
497	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR must be set\n"));
498	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
499	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR must be set\n"));
500	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
501	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR must be set\n"));
502	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
503	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER must be set\n"));
504
505	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
506	{
507	LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
508
509	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
510	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
511	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
512	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
513	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
514	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
515	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
516	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
517	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
518	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
519	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
520	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
521	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
522	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
523	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
524	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
525	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
526	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
527	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
528	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
529	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
530	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
531	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
532	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
533	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
534	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
535	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
536	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
537	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
538	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
539	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
540	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
541	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
542	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
543	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
544	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
545	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
546	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
547	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
548	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
549	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
550	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
551	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
552	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
553	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
554	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
555	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
556	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
557	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
558	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
559	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
560	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
561	}
562
563	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
564	LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
565	LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
566	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
567	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
568
569	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
570	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
571	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
572	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
573	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
574
575	LogRel(("HWACCM: VMCS physaddr = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
576	LogRel(("HWACCM: TPR shadow physaddr = %VHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
577	LogRel(("HWACCM: MSR bitmap physaddr = %VHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
578
579	#ifdef HWACCM_VTX_WITH_EPT
580	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
581	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
582	#endif /* HWACCM_VTX_WITH_EPT */
583	#ifdef HWACCM_VTX_WITH_VPID
584	if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
585	&& !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
586	pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.fAllowVPID;
587	#endif /* HWACCM_VTX_WITH_VPID */
588
589	/* Only try once. */
590	pVM->hwaccm.s.fInitialized = true;
591
592	/* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
593	rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
594	AssertRC(rc);
595	if (RT_FAILURE(rc))
596	return rc;
597
598	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
599	ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
600	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
601	/* Bit set to 0 means redirection enabled. */
602	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
603	/* Allow all port IO, so the VT-x IO intercepts do their job. */
604	memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
605	((unsigned char )pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
606
607	/* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
608	* real and protected mode without paging with EPT.
609	*/
610	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
611	for (unsigned i=0;i<X86_PG_ENTRIES;i++)
612	{
613	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
614	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_G;
615	}
616
617	/* We convert it here every time as pci regions could be reconfigured. */
618	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
619	AssertRC(rc);
620	LogRel(("HWACCM: Real Mode TSS guest physaddr = %VGp\n", GCPhys));
621
622	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
623	AssertRC(rc);
624	LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %VGp\n", GCPhys));
625
626	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
627	AssertRC(rc);
628	if (rc == VINF_SUCCESS)
629	{
630	pVM->fHWACCMEnabled = true;
631	pVM->hwaccm.s.vmx.fEnabled = true;
632	hwaccmR3DisableRawMode(pVM);
633
634	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
635	#ifdef VBOX_ENABLE_64_BITS_GUESTS
636	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
637	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
638	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
639	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
640	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
641	#endif
642	LogRel(("HWACCM: VMX enabled!\n"));
643	if (pVM->hwaccm.s.fNestedPaging)
644	{
645	LogRel(("HWACCM: Enabled nested paging\n"));
646	LogRel(("HWACCM: EPT root page = %VHp\n", PGMGetEPTCR3(pVM)));
647	}
648	if (pVM->hwaccm.s.vmx.fVPID)
649	LogRel(("HWACCM: Enabled VPID\n"));
650
651	if ( pVM->hwaccm.s.fNestedPaging
652	\|\| pVM->hwaccm.s.vmx.fVPID)
653	{
654	LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
655	LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
656	}
657	}
658	else
659	{
660	LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
661	LogRel(("HWACCM: Last instruction error %x\n", pVM->hwaccm.s.vmx.ulLastInstrError));
662	pVM->fHWACCMEnabled = false;
663	}
664	}
665	}
666	else
667	if (pVM->hwaccm.s.svm.fSupported)
668	{
669	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
670
671	if (pVM->hwaccm.s.fInitialized == false)
672	{
673	/* Erratum 170 which requires a forced TLB flush for each world switch:
674	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
675	*
676	* All BH-G1/2 and DH-G1/2 models include a fix:
677	* Athlon X2: 0x6b 1/2
678	* 0x68 1/2
679	* Athlon 64: 0x7f 1
680	* 0x6f 2
681	* Sempron: 0x7f 1/2
682	* 0x6f 2
683	* 0x6c 2
684	* 0x7c 2
685	* Turion 64: 0x68 2
686	*
687	*/
688	uint32_t u32Dummy;
689	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
690	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
691	u32BaseFamily= (u32Version >> 8) & 0xf;
692	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
693	u32Model = ((u32Version >> 4) & 0xf);
694	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
695	u32Stepping = u32Version & 0xf;
696	if ( u32Family == 0xf
697	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
698	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
699	{
700	LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
701	}
702
703	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
704	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
705	LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
706	LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
707	LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
708
709	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
710	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
711	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
712	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
713	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
714	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
715	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
716	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
717	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
718	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
719
720	/* Only try once. */
721	pVM->hwaccm.s.fInitialized = true;
722
723	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
724	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
725
726	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
727	AssertRC(rc);
728	if (rc == VINF_SUCCESS)
729	{
730	pVM->fHWACCMEnabled = true;
731	pVM->hwaccm.s.svm.fEnabled = true;
732
733	if (pVM->hwaccm.s.fNestedPaging)
734	LogRel(("HWACCM: Enabled nested paging\n"));
735
736	hwaccmR3DisableRawMode(pVM);
737	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
738	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
739	#ifdef VBOX_ENABLE_64_BITS_GUESTS
740	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
741	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
742	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
743	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
744	#endif
745	}
746	else
747	{
748	pVM->fHWACCMEnabled = false;
749	}
750	}
751	}
752	return VINF_SUCCESS;
753	}
754
755	/**
756	* Applies relocations to data and code managed by this
757	* component. This function will be called at init and
758	* whenever the VMM need to relocate it self inside the GC.
759	*
760	* @param pVM The VM.
761	*/
762	VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
763	{
764	Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
765	return;
766	}
767
768	/**
769	* Checks hardware accelerated raw mode is allowed.
770	*
771	* @returns boolean
772	* @param pVM The VM to operate on.
773	*/
774	VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
775	{
776	return pVM->hwaccm.s.fAllowed;
777	}
778
779	/**
780	* Notification callback which is called whenever there is a chance that a CR3
781	* value might have changed.
782	*
783	* This is called by PGM.
784	*
785	* @param pVM The VM to operate on.
786	* @param enmShadowMode New shadow paging mode.
787	* @param enmGuestMode New guest paging mode.
788	*/
789	VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
790	{
791	pVM->hwaccm.s.enmShadowMode = enmShadowMode;
792	if ( pVM->hwaccm.s.vmx.fEnabled
793	&& pVM->fHWACCMEnabled)
794	{
795	if ( pVM->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
796	&& enmGuestMode >= PGMMODE_PROTECTED)
797	{
798	PCPUMCTX pCtx;
799
800	pCtx = CPUMQueryGuestCtxPtr(pVM);
801
802	/* After a real mode switch to protected mode we must force
803	* CPL to 0. Our real mode emulation had to set it to 3.
804	*/
805	pCtx->ssHid.Attr.n.u2Dpl = 0;
806	}
807	}
808	}
809
810	/**
811	* Terminates the HWACCM.
812	*
813	* Termination means cleaning up and freeing all resources,
814	* the VM it self is at this point powered off or suspended.
815	*
816	* @returns VBox status code.
817	* @param pVM The VM to operate on.
818	*/
819	VMMR3DECL(int) HWACCMR3Term(PVM pVM)
820	{
821	if (pVM->hwaccm.s.vmx.pRealModeTSS)
822	{
823	PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
824	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
825	}
826
827	if (pVM->hwaccm.s.paStatExitReason)
828	{
829	MMHyperFree(pVM, pVM->hwaccm.s.paStatExitReason);
830	pVM->hwaccm.s.paStatExitReason = NULL;
831	}
832	return 0;
833	}
834
835	/**
836	* The VM is being reset.
837	*
838	* For the HWACCM component this means that any GDT/LDT/TSS monitors
839	* needs to be removed.
840	*
841	* @param pVM VM handle.
842	*/
843	VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
844	{
845	LogFlow(("HWACCMR3Reset:\n"));
846
847	if (pVM->fHWACCMEnabled)
848	hwaccmR3DisableRawMode(pVM);
849
850	/* On first entry we'll sync everything. */
851	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
852
853	pVM->hwaccm.s.vmx.cr0_mask = 0;
854	pVM->hwaccm.s.vmx.cr4_mask = 0;
855
856	pVM->hwaccm.s.Event.fPending = false;
857
858	/* Reset state information for real-mode emulation in VT-x. */
859	pVM->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
860	}
861
862	/**
863	* Checks if we can currently use hardware accelerated raw mode.
864	*
865	* @returns boolean
866	* @param pVM The VM to operate on.
867	* @param pCtx Partial VM execution context
868	*/
869	VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
870	{
871	Assert(pVM->fHWACCMEnabled);
872
873	/* AMD SVM supports real & protected mode with or without paging. */
874	if (pVM->hwaccm.s.svm.fEnabled)
875	{
876	pVM->hwaccm.s.fActive = true;
877	return true;
878	}
879
880	pVM->hwaccm.s.fActive = false;
881
882	/* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
883	#ifdef HWACCM_VMX_EMULATE_REALMODE
884	if (CPUMIsGuestInRealModeEx(pCtx))
885	{
886	/* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
887	* The base must also be equal to (sel << 4).
888	*/
889	if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
890	&& pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
891	\|\| pCtx->ds != (pCtx->dsHid.u64Base >> 4)
892	\|\| pCtx->es != (pCtx->esHid.u64Base >> 4)
893	\|\| pCtx->fs != (pCtx->fsHid.u64Base >> 4)
894	\|\| pCtx->gs != (pCtx->gsHid.u64Base >> 4)
895	\|\| pCtx->ss != (pCtx->ssHid.u64Base >> 4))
896	return false;
897	}
898	else
899	{
900	PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
901	/* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
902	* from real to protected mode. (all sorts of RPL & DPL assumptions)
903	*/
904	if ( pVM->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
905	&& enmGuestMode >= PGMMODE_PROTECTED)
906	{
907	if ( (pCtx->cs & X86_SEL_RPL)
908	\|\| (pCtx->ds & X86_SEL_RPL)
909	\|\| (pCtx->es & X86_SEL_RPL)
910	\|\| (pCtx->fs & X86_SEL_RPL)
911	\|\| (pCtx->gs & X86_SEL_RPL)
912	\|\| (pCtx->ss & X86_SEL_RPL))
913	{
914	/* Flush the translation blocks as code pages may have been
915	* changed (Fedora4 boot image, reset, boot iso)
916	*/
917	REMFlushTBs(pVM);
918	return false;
919	}
920	}
921	}
922	#else
923	if (!CPUMIsGuestInLongModeEx(pCtx))
924	{
925	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
926	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
927	return false;
928
929	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
930	/* Windows XP; switch to protected mode; all selectors are marked not present in the
931	* hidden registers (possible recompiler bug; see load_seg_vm) */
932	if (pCtx->csHid.Attr.n.u1Present == 0)
933	return false;
934	if (pCtx->ssHid.Attr.n.u1Present == 0)
935	return false;
936	}
937	#endif
938
939	if (pVM->hwaccm.s.vmx.fEnabled)
940	{
941	uint32_t mask;
942
943	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
944	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
945	/* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
946	mask &= ~X86_CR0_NE;
947
948	#ifdef HWACCM_VMX_EMULATE_REALMODE
949	/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
950	mask &= ~(X86_CR0_PG\|X86_CR0_PE);
951	#else
952	/* We support protected mode without paging using identity mapping. */
953	mask &= ~X86_CR0_PG;
954	#endif
955	if ((pCtx->cr0 & mask) != mask)
956	return false;
957
958	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
959	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
960	if ((pCtx->cr0 & mask) != 0)
961	return false;
962
963	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
964	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
965	mask &= ~X86_CR4_VMXE;
966	if ((pCtx->cr4 & mask) != mask)
967	return false;
968
969	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
970	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
971	if ((pCtx->cr4 & mask) != 0)
972	return false;
973
974	pVM->hwaccm.s.fActive = true;
975	return true;
976	}
977
978	return false;
979	}
980
981	/**
982	* Checks if we are currently using hardware accelerated raw mode.
983	*
984	* @returns boolean
985	* @param pVM The VM to operate on.
986	*/
987	VMMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
988	{
989	return pVM->hwaccm.s.fActive;
990	}
991
992	/**
993	* Checks if we are currently using nested paging.
994	*
995	* @returns boolean
996	* @param pVM The VM to operate on.
997	*/
998	VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
999	{
1000	return pVM->hwaccm.s.fNestedPaging;
1001	}
1002
1003	/**
1004	* Checks if we are currently using VPID in VT-x mode.
1005	*
1006	* @returns boolean
1007	* @param pVM The VM to operate on.
1008	*/
1009	VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
1010	{
1011	return pVM->hwaccm.s.vmx.fVPID;
1012	}
1013
1014
1015	/**
1016	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
1017	*
1018	* @returns boolean
1019	* @param pVM The VM to operate on.
1020	*/
1021	VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
1022	{
1023	return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
1024	}
1025
1026	/**
1027	* Check fatal VT-x/AMD-V error and produce some meaningful
1028	* log release message.
1029	*
1030	* @param pVM The VM to operate on.
1031	* @param iStatusCode VBox status code
1032	*/
1033	VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
1034	{
1035	switch(iStatusCode)
1036	{
1037	case VERR_VMX_INVALID_VMCS_FIELD:
1038	break;
1039
1040	case VERR_VMX_INVALID_VMCS_PTR:
1041	LogRel(("VERR_VMX_INVALID_VMCS_PTR: Current pointer %VGp vs %VGp\n", pVM->hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->hwaccm.s.vmx.pVMCSPhys));
1042	LogRel(("VERR_VMX_INVALID_VMCS_PTR: Current VMCS version %x\n", pVM->hwaccm.s.vmx.lasterror.ulVMCSRevision));
1043	break;
1044
1045	case VERR_VMX_UNABLE_TO_START_VM:
1046	LogRel(("VERR_VMX_UNABLE_TO_START_VM: instruction error %x\n", pVM->hwaccm.s.vmx.lasterror.ulLastInstrError));
1047	LogRel(("VERR_VMX_UNABLE_TO_START_VM: exit reason %x\n", pVM->hwaccm.s.vmx.lasterror.ulLastExitReason));
1048	break;
1049
1050	case VERR_VMX_UNABLE_TO_RESUME_VM:
1051	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: instruction error %x\n", pVM->hwaccm.s.vmx.lasterror.ulLastInstrError));
1052	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: exit reason %x\n", pVM->hwaccm.s.vmx.lasterror.ulLastExitReason));
1053	break;
1054
1055	case VERR_VMX_INVALID_VMXON_PTR:
1056	break;
1057	}
1058	}
1059
1060	/**
1061	* Execute state save operation.
1062	*
1063	* @returns VBox status code.
1064	* @param pVM VM Handle.
1065	* @param pSSM SSM operation handle.
1066	*/
1067	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
1068	{
1069	int rc;
1070
1071	Log(("hwaccmR3Save:\n"));
1072
1073	/*
1074	* Save the basic bits - fortunately all the other things can be resynced on load.
1075	*/
1076	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
1077	AssertRCReturn(rc, rc);
1078	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
1079	AssertRCReturn(rc, rc);
1080	rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
1081	AssertRCReturn(rc, rc);
1082
1083	return VINF_SUCCESS;
1084	}
1085
1086	/**
1087	* Execute state load operation.
1088	*
1089	* @returns VBox status code.
1090	* @param pVM VM Handle.
1091	* @param pSSM SSM operation handle.
1092	* @param u32Version Data layout version.
1093	*/
1094	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1095	{
1096	int rc;
1097
1098	Log(("hwaccmR3Load:\n"));
1099
1100	/*
1101	* Validate version.
1102	*/
1103	if (u32Version != HWACCM_SSM_VERSION)
1104	{
1105	AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
1106	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1107	}
1108	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
1109	AssertRCReturn(rc, rc);
1110	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
1111	AssertRCReturn(rc, rc);
1112	rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
1113	AssertRCReturn(rc, rc);
1114
1115	return VINF_SUCCESS;
1116	}
1117
1118
1119
1120

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 13626

Download in other formats: