VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 14704

Last change on this file since 14704 was 14704, checked in by vboxsync, 16 years ago

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1/* $Id: HWACCM.cpp 14704 2008-11-27 13:49:48Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/csam.h>
35#include <VBox/selm.h>
36#include <VBox/rem.h>
37#include <VBox/hwacc_vmx.h>
38#include <VBox/hwacc_svm.h>
39#include "HWACCMInternal.h"
40#include <VBox/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/string.h>
48#include <iprt/thread.h>
49
50/*******************************************************************************
51* Internal Functions *
52*******************************************************************************/
53static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
54static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
55
56
57/**
58 * Initializes the HWACCM.
59 *
60 * @returns VBox status code.
61 * @param pVM The VM to operate on.
62 */
63VMMR3DECL(int) HWACCMR3Init(PVM pVM)
64{
65 LogFlow(("HWACCMR3Init\n"));
66
67 /*
68 * Assert alignment and sizes.
69 */
70 AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
71 AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
72
73 /* Some structure checks. */
74 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
75 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
76 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
77 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
78
79 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
80 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
81 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
82 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
83 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
84 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
85 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
86
87
88 /*
89 * Register the saved state data unit.
90 */
91 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
92 NULL, hwaccmR3Save, NULL,
93 NULL, hwaccmR3Load, NULL);
94 if (RT_FAILURE(rc))
95 return rc;
96
97 /* Misc initialisation. */
98 pVM->hwaccm.s.vmx.fSupported = false;
99 pVM->hwaccm.s.svm.fSupported = false;
100 pVM->hwaccm.s.vmx.fEnabled = false;
101 pVM->hwaccm.s.svm.fEnabled = false;
102
103 pVM->hwaccm.s.fActive = false;
104 pVM->hwaccm.s.fNestedPaging = false;
105
106 /* Disabled by default. */
107 pVM->fHWACCMEnabled = false;
108
109 /*
110 * Check CFGM options.
111 */
112 /* Nested paging: disabled by default. */
113 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
114 AssertRC(rc);
115
116 /* VT-x VPID: disabled by default. */
117 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
118 AssertRC(rc);
119
120 /* HWACCM support must be explicitely enabled in the configuration file. */
121 rc = CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed, false);
122 AssertRC(rc);
123
124 return VINF_SUCCESS;
125}
126
127/**
128 * Initializes the per-VCPU HWACCM.
129 *
130 * @returns VBox status code.
131 * @param pVM The VM to operate on.
132 */
133VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
134{
135 LogFlow(("HWACCMR3InitCPU\n"));
136
137#ifdef VBOX_WITH_STATISTICS
138 /*
139 * Statistics.
140 */
141 for (unsigned i=0;i<pVM->cCPUs;i++)
142 {
143 PVMCPU pVCpu = &pVM->aCpus[i];
144 int rc;
145
146 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
147 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
148 AssertRC(rc);
149 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit",
150 "/PROF/HWACCM/CPU%d/SwitchFromGC", i);
151 AssertRC(rc);
152 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
153 "/PROF/HWACCM/CPU%d/InGC", i);
154 AssertRC(rc);
155
156#define HWACCM_REG_COUNTER(a, b) \
157 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
158 AssertRC(rc);
159
160 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
161 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
162 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
163 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
164 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
165 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
166 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
167 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
168 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
169 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
170 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
171 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
172 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
173 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
174 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
175 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCRxWrite, "/HWACCM/CPU%d/Exit/Instr/CR/Write");
176 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCRxRead, "/HWACCM/CPU%d/Exit/Instr/CR/Read");
177 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
178 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
179 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
180 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
181 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
182 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
183 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
184 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
185 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
186 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
187
188 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
189 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
190
191 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
192 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
193 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
194
195 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
196 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
197 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
198 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
199 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
200 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
201 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
202 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
203 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
204
205 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
206 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
207
208 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
209 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
210 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
211
212#undef HWACCM_REG_COUNTER
213
214 pVCpu->hwaccm.s.paStatExitReason = NULL;
215
216 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
217 AssertRC(rc);
218 if (RT_SUCCESS(rc))
219 {
220 for (int j=0;j<MAX_EXITREASON_STAT;j++)
221 {
222 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Exit reason",
223 "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
224 AssertRC(rc);
225 }
226 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Exit reason", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
227 AssertRC(rc);
228 }
229 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
230 Assert(pVCpu->hwaccm.s.paStatExitReasonR0);
231 }
232#endif /* VBOX_WITH_STATISTICS */
233 return VINF_SUCCESS;
234}
235
236/**
237 * Turns off normal raw mode features
238 *
239 * @param pVM The VM to operate on.
240 */
241static void hwaccmR3DisableRawMode(PVM pVM)
242{
243 /* Disable PATM & CSAM. */
244 PATMR3AllowPatching(pVM, false);
245 CSAMDisableScanning(pVM);
246
247 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
248 SELMR3DisableMonitoring(pVM);
249 TRPMR3DisableMonitoring(pVM);
250
251 /* The hidden selector registers are now valid. */
252 CPUMSetHiddenSelRegsValid(pVM, true);
253
254 /* Disable the switcher code (safety precaution). */
255 VMMR3DisableSwitcher(pVM);
256
257 /* Disable mapping of the hypervisor into the shadow page table. */
258 PGMR3ChangeShwPDMappings(pVM, false);
259
260 /* Disable the switcher */
261 VMMR3DisableSwitcher(pVM);
262
263 if (pVM->hwaccm.s.fNestedPaging)
264 {
265 /* Reinit the paging mode to force the new shadow mode. */
266 PGMR3ChangeMode(pVM, PGMMODE_REAL);
267 }
268}
269
270/**
271 * Initialize VT-x or AMD-V.
272 *
273 * @returns VBox status code.
274 * @param pVM The VM handle.
275 */
276VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
277{
278 int rc;
279
280 if ( !pVM->hwaccm.s.vmx.fSupported
281 && !pVM->hwaccm.s.svm.fSupported)
282 {
283 LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
284 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
285 return VINF_SUCCESS;
286 }
287
288 /*
289 * Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
290 * because it turns off paging, which is not allowed in VMX root mode.
291 *
292 * To simplify matters we'll just force all running VMs to either use raw or VT-x mode. No mixing allowed in the VT-x case.
293 * There's no such problem with AMD-V. (@todo)
294 *
295 */
296 /* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
297 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
298 if (RT_FAILURE(rc))
299 {
300 LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
301 LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
302 /* Invert the selection */
303 pVM->hwaccm.s.fAllowed ^= 1;
304 LogRel(("HWACCMR3InitFinalize: new HWACCM status = %s\n", pVM->hwaccm.s.fAllowed ? "enabled" : "disabled"));
305
306 if (pVM->hwaccm.s.fAllowed)
307 {
308 if (pVM->hwaccm.s.vmx.fSupported)
309 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses Intel VT-x hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using VT-x as well.\n");
310 else
311 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses AMD-V hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using AMD-V as well.\n");
312 }
313 else
314 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses software virtualization. It is not allowed to simultaneously use VT-x or AMD-V, therefore this VM will be run using software virtualization as well.\n");
315 }
316
317 if (pVM->hwaccm.s.fAllowed == false)
318 return VINF_SUCCESS; /* disabled */
319
320 Assert(!pVM->fHWACCMEnabled);
321
322 if (pVM->hwaccm.s.vmx.fSupported)
323 {
324 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
325
326 if ( pVM->hwaccm.s.fInitialized == false
327 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
328 {
329 uint64_t val;
330 RTGCPHYS GCPhys = 0;
331
332 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
333 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
334 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
335 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
336 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
337 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
338 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
339 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
340
341 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
342 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
343 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
344 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
345 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
346 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
347 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
348 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
349 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
350 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
351 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
352
353 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
354 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
355 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
356 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
357 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
358 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
359 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
360 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
361 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
362 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
363 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
364 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
365 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
366 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
367 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
368 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
369 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
370 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
371 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
372 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
373 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
374 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
375 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
376 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
377 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
378 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
379 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
380 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
381 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
382 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
383 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
384 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
385 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
386 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
387 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
388 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
389 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
390 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
391 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
392 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
393 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
394 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
395
396 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
397 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
398 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
399 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
400 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
401 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
402 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
403 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
404 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
405 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
406 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
407 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
408 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
409 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
410 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
411 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
412 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
413 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
414 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
415 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
416 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
417 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
418 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
419 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
420 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
421 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
422 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
423 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
424 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
425 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
426 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
427 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
428 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
429 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
430 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
431 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
432 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
433 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
434 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
435 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
436 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
437
438 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
439 {
440 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
441 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
442 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
443 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
444 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
445 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
446 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
447 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
448 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
449 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
450
451 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
452 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
453 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
454 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
455 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
456 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
457 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
458 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
459 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
460 }
461
462 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
463 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
464 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
465 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
466 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
467 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
468 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
469 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
470 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
471 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
472 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
473 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
474 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
475 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
476 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
477 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
478 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
479 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
480 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
481 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
482 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
483 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
484 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
485 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
486 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
487 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
488 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
489 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
490 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
491 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
492 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
493
494 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
495 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
496 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
497 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
498 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
499 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
500 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
501 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
502 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
503 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
504 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
505 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
506 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
507 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
508 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
509 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
510 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
511 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
512 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
513 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
514 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
515 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
516 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
517 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
518 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
519 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
520 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
521 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
522 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
523 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
524 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
525 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
526 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
527 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
528 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
529
530 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
531 {
532 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
533
534 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
535 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
536 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
537 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
538 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
539 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
540 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
541 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
542 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
543 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
544 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
545 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
546 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
547 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
548 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
549 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
550 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
551 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
552 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
553 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
554 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
555 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
556 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
557 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
558 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
559 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
560 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
561 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
562 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
563 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
564 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
565 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
566 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
567 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
568 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
569 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
570 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
571 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
572 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
573 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
574 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
575 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
576 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
577 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
578 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
579 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
580 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
581 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
582 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
583 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
584 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
585 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
586 }
587
588 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
589 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
590 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
591 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
592 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
593
594 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
595 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
596 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
597 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
598 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
599
600 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
601 LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
602
603 for (unsigned i=0;i<pVM->cCPUs;i++)
604 LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
605
606#ifdef HWACCM_VTX_WITH_EPT
607 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
608 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
609#endif /* HWACCM_VTX_WITH_EPT */
610#ifdef HWACCM_VTX_WITH_VPID
611 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
612 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
613 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
614#endif /* HWACCM_VTX_WITH_VPID */
615
616 /* Only try once. */
617 pVM->hwaccm.s.fInitialized = true;
618
619 /* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
620 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
621 AssertRC(rc);
622 if (RT_FAILURE(rc))
623 return rc;
624
625 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
626 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
627 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
628 /* Bit set to 0 means redirection enabled. */
629 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
630 /* Allow all port IO, so the VT-x IO intercepts do their job. */
631 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
632 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
633
634 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
635 * real and protected mode without paging with EPT.
636 */
637 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
638 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
639 {
640 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
641 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
642 }
643
644 /* We convert it here every time as pci regions could be reconfigured. */
645 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
646 AssertRC(rc);
647 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
648
649 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
650 AssertRC(rc);
651 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
652
653 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
654 AssertRC(rc);
655 if (rc == VINF_SUCCESS)
656 {
657 pVM->fHWACCMEnabled = true;
658 pVM->hwaccm.s.vmx.fEnabled = true;
659 hwaccmR3DisableRawMode(pVM);
660
661 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
662#ifdef VBOX_ENABLE_64_BITS_GUESTS
663 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
664 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
665 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
666 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
667 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
668#endif
669 LogRel(("HWACCM: VMX enabled!\n"));
670 if (pVM->hwaccm.s.fNestedPaging)
671 {
672 LogRel(("HWACCM: Enabled nested paging\n"));
673 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetEPTCR3(pVM)));
674 }
675 if (pVM->hwaccm.s.vmx.fVPID)
676 LogRel(("HWACCM: Enabled VPID\n"));
677
678 if ( pVM->hwaccm.s.fNestedPaging
679 || pVM->hwaccm.s.vmx.fVPID)
680 {
681 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
682 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
683 }
684 }
685 else
686 {
687 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
688 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
689 pVM->fHWACCMEnabled = false;
690 }
691 }
692 }
693 else
694 if (pVM->hwaccm.s.svm.fSupported)
695 {
696 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
697
698 if (pVM->hwaccm.s.fInitialized == false)
699 {
700 /* Erratum 170 which requires a forced TLB flush for each world switch:
701 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
702 *
703 * All BH-G1/2 and DH-G1/2 models include a fix:
704 * Athlon X2: 0x6b 1/2
705 * 0x68 1/2
706 * Athlon 64: 0x7f 1
707 * 0x6f 2
708 * Sempron: 0x7f 1/2
709 * 0x6f 2
710 * 0x6c 2
711 * 0x7c 2
712 * Turion 64: 0x68 2
713 *
714 */
715 uint32_t u32Dummy;
716 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
717 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
718 u32BaseFamily= (u32Version >> 8) & 0xf;
719 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
720 u32Model = ((u32Version >> 4) & 0xf);
721 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
722 u32Stepping = u32Version & 0xf;
723 if ( u32Family == 0xf
724 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
725 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
726 {
727 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
728 }
729
730 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
731 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
732 LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
733 LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
734 LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
735
736 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
737 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
738 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
739 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
740 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
741 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
742 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
743 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
744 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
745 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
746
747 /* Only try once. */
748 pVM->hwaccm.s.fInitialized = true;
749
750 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
751 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
752
753 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
754 AssertRC(rc);
755 if (rc == VINF_SUCCESS)
756 {
757 pVM->fHWACCMEnabled = true;
758 pVM->hwaccm.s.svm.fEnabled = true;
759
760 if (pVM->hwaccm.s.fNestedPaging)
761 LogRel(("HWACCM: Enabled nested paging\n"));
762
763 hwaccmR3DisableRawMode(pVM);
764 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
765 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
766 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
767#ifdef VBOX_ENABLE_64_BITS_GUESTS
768 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
769 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
770 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
771 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
772#endif
773 }
774 else
775 {
776 pVM->fHWACCMEnabled = false;
777 }
778 }
779 }
780
781#if (HC_ARCH_BITS == 32) && defined(VBOX_ENABLE_64_BITS_GUESTS)
782 if ( pVM->fHWACCMEnabled
783 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE))
784 {
785 rc = VMMR3InitSwitcher3264(pVM);
786 if (VBOX_FAILURE(rc))
787 {
788 LogRel(("WARNING: Unable to map the VM structure into the intermediate page table; disabling long mode support\n"));
789 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
790 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
791 }
792 }
793#endif
794 return VINF_SUCCESS;
795}
796
797/**
798 * Applies relocations to data and code managed by this
799 * component. This function will be called at init and
800 * whenever the VMM need to relocate it self inside the GC.
801 *
802 * @param pVM The VM.
803 */
804VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
805{
806 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
807
808 /* Fetch the current paging mode during the relocate callback during state loading. */
809 if (VMR3GetState(pVM) == VMSTATE_LOADING)
810 {
811 for (unsigned i=0;i<pVM->cCPUs;i++)
812 {
813 PVMCPU pVCpu = &pVM->aCpus[i];
814 /* @todo SMP */
815 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVM);
816 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVM);
817 }
818 }
819
820 return;
821}
822
823/**
824 * Checks hardware accelerated raw mode is allowed.
825 *
826 * @returns boolean
827 * @param pVM The VM to operate on.
828 */
829VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
830{
831 return pVM->hwaccm.s.fAllowed;
832}
833
834/**
835 * Notification callback which is called whenever there is a chance that a CR3
836 * value might have changed.
837 *
838 * This is called by PGM.
839 *
840 * @param pVM The VM to operate on.
841 * @param enmShadowMode New shadow paging mode.
842 * @param enmGuestMode New guest paging mode.
843 */
844VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
845{
846 /* Ignore page mode changes during state loading. */
847 if (VMR3GetState(pVM) == VMSTATE_LOADING)
848 return;
849
850 PVMCPU pVCpu = VMMGetCpu(pVM);
851 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
852
853 if ( pVM->hwaccm.s.vmx.fEnabled
854 && pVM->fHWACCMEnabled)
855 {
856 if ( pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
857 && enmGuestMode >= PGMMODE_PROTECTED)
858 {
859 PCPUMCTX pCtx;
860
861 pCtx = CPUMQueryGuestCtxPtr(pVM);
862
863 /* After a real mode switch to protected mode we must force
864 * CPL to 0. Our real mode emulation had to set it to 3.
865 */
866 pCtx->ssHid.Attr.n.u2Dpl = 0;
867 }
868 }
869}
870
871/**
872 * Terminates the HWACCM.
873 *
874 * Termination means cleaning up and freeing all resources,
875 * the VM it self is at this point powered off or suspended.
876 *
877 * @returns VBox status code.
878 * @param pVM The VM to operate on.
879 */
880VMMR3DECL(int) HWACCMR3Term(PVM pVM)
881{
882 if (pVM->hwaccm.s.vmx.pRealModeTSS)
883 {
884 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
885 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
886 }
887 return 0;
888}
889
890/**
891 * Terminates the per-VCPU HWACCM.
892 *
893 * Termination means cleaning up and freeing all resources,
894 * the VM it self is at this point powered off or suspended.
895 *
896 * @returns VBox status code.
897 * @param pVM The VM to operate on.
898 */
899VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
900{
901 for (unsigned i=0;i<pVM->cCPUs;i++)
902 {
903 PVMCPU pVCpu = &pVM->aCpus[i];
904
905 if (pVCpu->hwaccm.s.paStatExitReason)
906 {
907 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
908 pVCpu->hwaccm.s.paStatExitReason = NULL;
909 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
910 }
911 }
912 return 0;
913}
914
915/**
916 * The VM is being reset.
917 *
918 * For the HWACCM component this means that any GDT/LDT/TSS monitors
919 * needs to be removed.
920 *
921 * @param pVM VM handle.
922 */
923VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
924{
925 LogFlow(("HWACCMR3Reset:\n"));
926
927 if (pVM->fHWACCMEnabled)
928 hwaccmR3DisableRawMode(pVM);
929
930 for (unsigned i=0;i<pVM->cCPUs;i++)
931 {
932 PVMCPU pVCpu = &pVM->aCpus[i];
933
934 /* On first entry we'll sync everything. */
935 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
936
937 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
938 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
939
940 pVCpu->hwaccm.s.Event.fPending = false;
941
942 /* Reset state information for real-mode emulation in VT-x. */
943 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
944 }
945}
946
947/**
948 * Checks if we can currently use hardware accelerated raw mode.
949 *
950 * @returns boolean
951 * @param pVM The VM to operate on.
952 * @param pCtx Partial VM execution context
953 */
954VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
955{
956 Assert(pVM->fHWACCMEnabled);
957
958 /* AMD SVM supports real & protected mode with or without paging. */
959 if (pVM->hwaccm.s.svm.fEnabled)
960 {
961 pVM->hwaccm.s.fActive = true;
962 return true;
963 }
964
965 pVM->hwaccm.s.fActive = false;
966
967 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
968#ifdef HWACCM_VMX_EMULATE_REALMODE
969 if (CPUMIsGuestInRealModeEx(pCtx))
970 {
971 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
972 * The base must also be equal to (sel << 4).
973 */
974 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
975 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
976 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
977 || pCtx->es != (pCtx->esHid.u64Base >> 4)
978 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
979 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
980 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
981 return false;
982 }
983 else
984 {
985 PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
986 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
987 * from real to protected mode. (all sorts of RPL & DPL assumptions)
988 */
989 PVMCPU pVCpu = VMMGetCpu(pVM);
990
991 if ( pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
992 && enmGuestMode >= PGMMODE_PROTECTED)
993 {
994 if ( (pCtx->cs & X86_SEL_RPL)
995 || (pCtx->ds & X86_SEL_RPL)
996 || (pCtx->es & X86_SEL_RPL)
997 || (pCtx->fs & X86_SEL_RPL)
998 || (pCtx->gs & X86_SEL_RPL)
999 || (pCtx->ss & X86_SEL_RPL))
1000 {
1001 return false;
1002 }
1003 }
1004 }
1005#else
1006 if (!CPUMIsGuestInLongModeEx(pCtx))
1007 {
1008 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
1009 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
1010 return false;
1011
1012 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
1013 /* Windows XP; switch to protected mode; all selectors are marked not present in the
1014 * hidden registers (possible recompiler bug; see load_seg_vm) */
1015 if (pCtx->csHid.Attr.n.u1Present == 0)
1016 return false;
1017 if (pCtx->ssHid.Attr.n.u1Present == 0)
1018 return false;
1019 }
1020#endif
1021
1022 if (pVM->hwaccm.s.vmx.fEnabled)
1023 {
1024 uint32_t mask;
1025
1026 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
1027 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
1028 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
1029 mask &= ~X86_CR0_NE;
1030
1031#ifdef HWACCM_VMX_EMULATE_REALMODE
1032 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
1033 mask &= ~(X86_CR0_PG|X86_CR0_PE);
1034#else
1035 /* We support protected mode without paging using identity mapping. */
1036 mask &= ~X86_CR0_PG;
1037#endif
1038 if ((pCtx->cr0 & mask) != mask)
1039 return false;
1040
1041 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
1042 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
1043 if ((pCtx->cr0 & mask) != 0)
1044 return false;
1045
1046 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
1047 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1048 mask &= ~X86_CR4_VMXE;
1049 if ((pCtx->cr4 & mask) != mask)
1050 return false;
1051
1052 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
1053 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
1054 if ((pCtx->cr4 & mask) != 0)
1055 return false;
1056
1057 pVM->hwaccm.s.fActive = true;
1058 return true;
1059 }
1060
1061 return false;
1062}
1063
1064/**
1065 * Checks if we are currently using hardware accelerated raw mode.
1066 *
1067 * @returns boolean
1068 * @param pVM The VM to operate on.
1069 */
1070VMMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
1071{
1072 return pVM->hwaccm.s.fActive;
1073}
1074
1075/**
1076 * Checks if we are currently using nested paging.
1077 *
1078 * @returns boolean
1079 * @param pVM The VM to operate on.
1080 */
1081VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
1082{
1083 return pVM->hwaccm.s.fNestedPaging;
1084}
1085
1086/**
1087 * Checks if we are currently using VPID in VT-x mode.
1088 *
1089 * @returns boolean
1090 * @param pVM The VM to operate on.
1091 */
1092VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
1093{
1094 return pVM->hwaccm.s.vmx.fVPID;
1095}
1096
1097
1098/**
1099 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
1100 *
1101 * @returns boolean
1102 * @param pVM The VM to operate on.
1103 */
1104VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
1105{
1106 /* @todo SMP */
1107 return HWACCMIsEnabled(pVM) && pVM->aCpus[0].hwaccm.s.Event.fPending;
1108}
1109
1110
1111/**
1112 * Inject an NMI into a running VM
1113 *
1114 * @returns boolean
1115 * @param pVM The VM to operate on.
1116 */
1117VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
1118{
1119 pVM->hwaccm.s.fInjectNMI = true;
1120 return VINF_SUCCESS;
1121}
1122
1123/**
1124 * Check fatal VT-x/AMD-V error and produce some meaningful
1125 * log release message.
1126 *
1127 * @param pVM The VM to operate on.
1128 * @param iStatusCode VBox status code
1129 */
1130VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
1131{
1132 for (unsigned i=0;i<pVM->cCPUs;i++)
1133 {
1134 switch(iStatusCode)
1135 {
1136 case VERR_VMX_INVALID_VMCS_FIELD:
1137 break;
1138
1139 case VERR_VMX_INVALID_VMCS_PTR:
1140 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1141 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
1142 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
1143 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
1144 break;
1145
1146 case VERR_VMX_UNABLE_TO_START_VM:
1147 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1148 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1149#if 0 /* @todo dump the current control fields to the release log */
1150 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
1151 {
1152
1153 }
1154#endif
1155 break;
1156
1157 case VERR_VMX_UNABLE_TO_RESUME_VM:
1158 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1159 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1160 break;
1161
1162 case VERR_VMX_INVALID_VMXON_PTR:
1163 break;
1164 }
1165 }
1166}
1167
1168/**
1169 * Execute state save operation.
1170 *
1171 * @returns VBox status code.
1172 * @param pVM VM Handle.
1173 * @param pSSM SSM operation handle.
1174 */
1175static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
1176{
1177 int rc;
1178
1179 Log(("hwaccmR3Save:\n"));
1180
1181 for (unsigned i=0;i<pVM->cCPUs;i++)
1182 {
1183 /*
1184 * Save the basic bits - fortunately all the other things can be resynced on load.
1185 */
1186 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
1187 AssertRCReturn(rc, rc);
1188 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
1189 AssertRCReturn(rc, rc);
1190 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
1191 AssertRCReturn(rc, rc);
1192 }
1193
1194 return VINF_SUCCESS;
1195}
1196
1197/**
1198 * Execute state load operation.
1199 *
1200 * @returns VBox status code.
1201 * @param pVM VM Handle.
1202 * @param pSSM SSM operation handle.
1203 * @param u32Version Data layout version.
1204 */
1205static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1206{
1207 int rc;
1208
1209 Log(("hwaccmR3Load:\n"));
1210
1211 /*
1212 * Validate version.
1213 */
1214 if (u32Version != HWACCM_SSM_VERSION)
1215 {
1216 AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
1217 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1218 }
1219 for (unsigned i=0;i<pVM->cCPUs;i++)
1220 {
1221 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
1222 AssertRCReturn(rc, rc);
1223 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
1224 AssertRCReturn(rc, rc);
1225 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
1226 AssertRCReturn(rc, rc);
1227 }
1228 return VINF_SUCCESS;
1229}
1230
1231
1232
1233
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