1 | /* $Id: HWACCM.cpp 14902 2008-12-02 14:24:03Z vboxsync $ */
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2 | /** @file
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3 | * HWACCM - Intel/AMD VM Hardware Support Manager
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2007 Sun Microsystems, Inc.
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | *
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17 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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18 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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19 | * additional information or have any questions.
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20 | */
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21 |
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22 | /*******************************************************************************
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23 | * Header Files *
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24 | *******************************************************************************/
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25 | #define LOG_GROUP LOG_GROUP_HWACCM
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26 | #include <VBox/cpum.h>
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27 | #include <VBox/stam.h>
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28 | #include <VBox/mm.h>
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29 | #include <VBox/pdm.h>
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30 | #include <VBox/pgm.h>
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31 | #include <VBox/trpm.h>
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32 | #include <VBox/dbgf.h>
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33 | #include <VBox/patm.h>
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34 | #include <VBox/csam.h>
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35 | #include <VBox/selm.h>
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36 | #include <VBox/rem.h>
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37 | #include <VBox/hwacc_vmx.h>
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38 | #include <VBox/hwacc_svm.h>
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39 | #include "HWACCMInternal.h"
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40 | #include <VBox/vm.h>
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41 | #include <VBox/err.h>
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42 | #include <VBox/param.h>
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43 |
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44 | #include <iprt/assert.h>
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45 | #include <VBox/log.h>
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46 | #include <iprt/asm.h>
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47 | #include <iprt/string.h>
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48 | #include <iprt/thread.h>
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49 |
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50 | /*******************************************************************************
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51 | * Internal Functions *
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52 | *******************************************************************************/
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53 | static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
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54 | static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
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55 |
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56 |
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57 | /**
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58 | * Initializes the HWACCM.
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59 | *
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60 | * @returns VBox status code.
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61 | * @param pVM The VM to operate on.
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62 | */
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63 | VMMR3DECL(int) HWACCMR3Init(PVM pVM)
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64 | {
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65 | LogFlow(("HWACCMR3Init\n"));
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66 |
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67 | /*
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68 | * Assert alignment and sizes.
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69 | */
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70 | AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
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71 | AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
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72 |
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73 | /* Some structure checks. */
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74 | AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
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75 | AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
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76 | AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
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77 | AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
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78 |
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79 | AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
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80 | AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
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81 | AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
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82 | AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
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83 | AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
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84 | AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
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85 | AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
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86 |
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87 |
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88 | /*
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89 | * Register the saved state data unit.
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90 | */
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91 | int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
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92 | NULL, hwaccmR3Save, NULL,
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93 | NULL, hwaccmR3Load, NULL);
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94 | if (RT_FAILURE(rc))
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95 | return rc;
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96 |
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97 | /* Misc initialisation. */
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98 | pVM->hwaccm.s.vmx.fSupported = false;
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99 | pVM->hwaccm.s.svm.fSupported = false;
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100 | pVM->hwaccm.s.vmx.fEnabled = false;
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101 | pVM->hwaccm.s.svm.fEnabled = false;
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102 |
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103 | pVM->hwaccm.s.fActive = false;
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104 | pVM->hwaccm.s.fNestedPaging = false;
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105 |
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106 | /* Disabled by default. */
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107 | pVM->fHWACCMEnabled = false;
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108 |
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109 | /*
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110 | * Check CFGM options.
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111 | */
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112 | /* Nested paging: disabled by default. */
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113 | rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
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114 | AssertRC(rc);
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115 |
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116 | /* VT-x VPID: disabled by default. */
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117 | rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
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118 | AssertRC(rc);
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119 |
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120 | /* HWACCM support must be explicitely enabled in the configuration file. */
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121 | rc = CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed, false);
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122 | AssertRC(rc);
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123 |
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124 | #ifdef RT_OS_DARWIN
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125 | if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
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126 | #else
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127 | if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
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128 | #endif
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129 | {
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130 | AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
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131 | VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
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132 | return VERR_HWACCM_CONFIG_MISMATCH;
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133 | }
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134 |
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135 | if (VMMIsHwVirtExtForced(pVM))
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136 | pVM->fHWACCMEnabled = true;
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137 |
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138 | return VINF_SUCCESS;
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139 | }
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140 |
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141 | /**
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142 | * Initializes the per-VCPU HWACCM.
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143 | *
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144 | * @returns VBox status code.
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145 | * @param pVM The VM to operate on.
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146 | */
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147 | VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
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148 | {
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149 | LogFlow(("HWACCMR3InitCPU\n"));
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150 |
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151 | #ifdef VBOX_WITH_STATISTICS
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152 | /*
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153 | * Statistics.
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154 | */
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155 | for (unsigned i=0;i<pVM->cCPUs;i++)
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156 | {
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157 | PVMCPU pVCpu = &pVM->aCpus[i];
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158 | int rc;
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159 |
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160 | rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
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161 | "/PROF/HWACCM/CPU%d/SwitchToGC", i);
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162 | AssertRC(rc);
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163 | rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit",
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164 | "/PROF/HWACCM/CPU%d/SwitchFromGC", i);
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165 | AssertRC(rc);
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166 | rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
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167 | "/PROF/HWACCM/CPU%d/InGC", i);
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168 | AssertRC(rc);
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169 |
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170 | #define HWACCM_REG_COUNTER(a, b) \
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171 | rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
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172 | AssertRC(rc);
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173 |
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174 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
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175 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
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176 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
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177 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
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178 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
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179 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
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180 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
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181 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
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182 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
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183 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
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184 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
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185 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
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186 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
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187 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
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188 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
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189 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCRxWrite, "/HWACCM/CPU%d/Exit/Instr/CR/Write");
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190 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCRxRead, "/HWACCM/CPU%d/Exit/Instr/CR/Read");
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191 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
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192 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
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193 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
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194 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
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195 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
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196 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
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197 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
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198 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
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199 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
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200 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
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201 |
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202 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
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203 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
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204 |
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205 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
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206 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
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207 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
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208 |
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209 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
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210 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
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211 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
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212 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
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213 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
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214 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
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215 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
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216 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
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217 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
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218 |
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219 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
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220 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
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221 |
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222 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
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223 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
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224 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
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225 |
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226 | #undef HWACCM_REG_COUNTER
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227 |
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228 | pVCpu->hwaccm.s.paStatExitReason = NULL;
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229 |
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230 | rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
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231 | AssertRC(rc);
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232 | if (RT_SUCCESS(rc))
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233 | {
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234 | for (int j=0;j<MAX_EXITREASON_STAT;j++)
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235 | {
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236 | rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Exit reason",
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237 | "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
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238 | AssertRC(rc);
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239 | }
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240 | rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Exit reason", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
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241 | AssertRC(rc);
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242 | }
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243 | pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
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244 | Assert(pVCpu->hwaccm.s.paStatExitReasonR0);
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245 | }
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246 | #endif /* VBOX_WITH_STATISTICS */
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247 | return VINF_SUCCESS;
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248 | }
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249 |
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250 | /**
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251 | * Turns off normal raw mode features
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252 | *
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253 | * @param pVM The VM to operate on.
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254 | */
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255 | static void hwaccmR3DisableRawMode(PVM pVM)
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256 | {
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257 | /* Disable PATM & CSAM. */
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258 | PATMR3AllowPatching(pVM, false);
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259 | CSAMDisableScanning(pVM);
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260 |
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261 | /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
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262 | SELMR3DisableMonitoring(pVM);
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263 | TRPMR3DisableMonitoring(pVM);
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264 |
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265 | /* The hidden selector registers are now valid. */
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266 | CPUMSetHiddenSelRegsValid(pVM, true);
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267 |
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268 | /* Disable the switcher code (safety precaution). */
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269 | VMMR3DisableSwitcher(pVM);
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270 |
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271 | /* Disable mapping of the hypervisor into the shadow page table. */
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272 | PGMR3ChangeShwPDMappings(pVM, false);
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273 |
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274 | /* Disable the switcher */
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275 | VMMR3DisableSwitcher(pVM);
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276 |
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277 | if (pVM->hwaccm.s.fNestedPaging)
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278 | {
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279 | /* Reinit the paging mode to force the new shadow mode. */
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280 | PGMR3ChangeMode(pVM, PGMMODE_REAL);
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281 | }
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282 | }
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283 |
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284 | /**
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285 | * Initialize VT-x or AMD-V.
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286 | *
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287 | * @returns VBox status code.
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288 | * @param pVM The VM handle.
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289 | */
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290 | VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
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291 | {
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292 | int rc;
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293 |
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294 | if ( !pVM->hwaccm.s.vmx.fSupported
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295 | && !pVM->hwaccm.s.svm.fSupported)
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296 | {
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297 | LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
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298 | LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
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299 | #ifdef RT_OS_DARWIN
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300 | if (VMMIsHwVirtExtForced(pVM))
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301 | return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
|
---|
302 | #endif
|
---|
303 | return VINF_SUCCESS;
|
---|
304 | }
|
---|
305 |
|
---|
306 | /*
|
---|
307 | * Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
|
---|
308 | * because it turns off paging, which is not allowed in VMX root mode.
|
---|
309 | *
|
---|
310 | * To simplify matters we'll just force all running VMs to either use raw or VT-x mode. No mixing allowed in the VT-x case.
|
---|
311 | * There's no such problem with AMD-V. (@todo)
|
---|
312 | *
|
---|
313 | */
|
---|
314 | /* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
|
---|
315 | rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
|
---|
316 | if (RT_FAILURE(rc))
|
---|
317 | {
|
---|
318 | LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
|
---|
319 | LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
|
---|
320 |
|
---|
321 | #ifdef RT_OS_DARWIN
|
---|
322 | /*
|
---|
323 | * This is 100% fatal if we didn't prepare for a HwVirtExt setup because of
|
---|
324 | * missing ring-0 allocations. For VMs that require HwVirtExt it doesn't normally
|
---|
325 | * make sense to try run them in software mode, so fail that too.
|
---|
326 | */
|
---|
327 | if (VMMIsHwVirtExtForced(pVM))
|
---|
328 | VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to "
|
---|
329 | "simultaneously use VT-x.");
|
---|
330 | else
|
---|
331 | VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not "
|
---|
332 | "allowed to simultaneously use software virtualization.");
|
---|
333 | return rc;
|
---|
334 |
|
---|
335 | #else /* !RT_OS_DARWIN */
|
---|
336 |
|
---|
337 | /* Invert the selection */
|
---|
338 | pVM->hwaccm.s.fAllowed ^= 1;
|
---|
339 | if (pVM->hwaccm.s.fAllowed)
|
---|
340 | {
|
---|
341 | if (pVM->hwaccm.s.vmx.fSupported)
|
---|
342 | VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not allowed "
|
---|
343 | "to simultaneously use software virtualization.\n");
|
---|
344 | else
|
---|
345 | VM_SET_ERROR(pVM, rc, "An active VM already uses AMD-V hardware acceleration. It is not allowed to "
|
---|
346 | "simultaneously use software virtualization.\n");
|
---|
347 | }
|
---|
348 | else
|
---|
349 | VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to simultaneously "
|
---|
350 | "use VT-x or AMD-V.\n");
|
---|
351 | return rc;
|
---|
352 | #endif /* !RT_OS_DARWIN */
|
---|
353 | }
|
---|
354 |
|
---|
355 | if (pVM->hwaccm.s.fAllowed == false)
|
---|
356 | return VINF_SUCCESS; /* disabled */
|
---|
357 |
|
---|
358 | Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
|
---|
359 |
|
---|
360 | if (pVM->hwaccm.s.vmx.fSupported)
|
---|
361 | {
|
---|
362 | Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
|
---|
363 |
|
---|
364 | if ( pVM->hwaccm.s.fInitialized == false
|
---|
365 | && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
|
---|
366 | {
|
---|
367 | uint64_t val;
|
---|
368 | RTGCPHYS GCPhys = 0;
|
---|
369 |
|
---|
370 | LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
|
---|
371 | LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
|
---|
372 | LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
|
---|
373 | LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
|
---|
374 | LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
|
---|
375 | LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
|
---|
376 | LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
|
---|
377 | LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
|
---|
378 |
|
---|
379 | LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
|
---|
380 | val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
|
---|
381 | if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
|
---|
382 | LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
|
---|
383 | if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
|
---|
384 | LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
|
---|
385 | val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
|
---|
386 | if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
|
---|
387 | LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
|
---|
388 | if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
|
---|
389 | LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
|
---|
390 |
|
---|
391 | LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
|
---|
392 | val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
|
---|
393 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
|
---|
394 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
|
---|
395 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
|
---|
396 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
|
---|
397 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
|
---|
398 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
|
---|
399 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
|
---|
400 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
|
---|
401 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
|
---|
402 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
|
---|
403 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
|
---|
404 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
|
---|
405 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
|
---|
406 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
|
---|
407 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
|
---|
408 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
|
---|
409 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
|
---|
410 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
|
---|
411 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
|
---|
412 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
|
---|
413 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
|
---|
414 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
|
---|
415 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
|
---|
416 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
|
---|
417 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
|
---|
418 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
|
---|
419 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
|
---|
420 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
|
---|
421 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
|
---|
422 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
|
---|
423 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
|
---|
424 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
|
---|
425 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
|
---|
426 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
|
---|
427 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
|
---|
428 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
|
---|
429 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
|
---|
430 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
|
---|
431 | if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
|
---|
432 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
|
---|
433 |
|
---|
434 | val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
|
---|
435 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
|
---|
436 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
|
---|
437 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
|
---|
438 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
|
---|
439 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
|
---|
440 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
|
---|
441 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
|
---|
442 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
|
---|
443 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
|
---|
444 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
|
---|
445 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
|
---|
446 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
|
---|
447 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
|
---|
448 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
|
---|
449 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
|
---|
450 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
|
---|
451 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
|
---|
452 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
|
---|
453 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
|
---|
454 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
|
---|
455 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
|
---|
456 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
|
---|
457 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
|
---|
458 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
|
---|
459 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
|
---|
460 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
|
---|
461 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
|
---|
462 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
|
---|
463 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
|
---|
464 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
|
---|
465 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
|
---|
466 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
|
---|
467 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
|
---|
468 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
|
---|
469 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
|
---|
470 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
|
---|
471 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
|
---|
472 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
|
---|
473 | if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
|
---|
474 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
|
---|
475 |
|
---|
476 | if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
|
---|
477 | {
|
---|
478 | LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
|
---|
479 | val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
|
---|
480 | if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
|
---|
481 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
|
---|
482 | if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
|
---|
483 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
|
---|
484 | if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
|
---|
485 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
|
---|
486 | if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
|
---|
487 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
|
---|
488 |
|
---|
489 | val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
|
---|
490 | if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
|
---|
491 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
|
---|
492 | if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
|
---|
493 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
|
---|
494 | if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
|
---|
495 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
|
---|
496 | if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
|
---|
497 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
|
---|
498 | }
|
---|
499 |
|
---|
500 | LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
|
---|
501 | val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
|
---|
502 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
|
---|
503 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
|
---|
504 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
|
---|
505 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
|
---|
506 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
|
---|
507 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
|
---|
508 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
|
---|
509 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
|
---|
510 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
|
---|
511 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
|
---|
512 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
|
---|
513 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
|
---|
514 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
|
---|
515 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
|
---|
516 | val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
|
---|
517 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
|
---|
518 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
|
---|
519 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
|
---|
520 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
|
---|
521 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
|
---|
522 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
|
---|
523 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
|
---|
524 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
|
---|
525 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
|
---|
526 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
|
---|
527 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
|
---|
528 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
|
---|
529 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
|
---|
530 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
|
---|
531 |
|
---|
532 | LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
|
---|
533 | val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
|
---|
534 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
|
---|
535 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
|
---|
536 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
|
---|
537 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
|
---|
538 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
|
---|
539 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
|
---|
540 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
|
---|
541 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
|
---|
542 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
|
---|
543 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
|
---|
544 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
|
---|
545 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
|
---|
546 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
|
---|
547 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
|
---|
548 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
|
---|
549 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
|
---|
550 | val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
|
---|
551 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
|
---|
552 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
|
---|
553 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
|
---|
554 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
|
---|
555 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
|
---|
556 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
|
---|
557 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
|
---|
558 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
|
---|
559 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
|
---|
560 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
|
---|
561 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
|
---|
562 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
|
---|
563 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
|
---|
564 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
|
---|
565 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
|
---|
566 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
|
---|
567 |
|
---|
568 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
|
---|
569 | {
|
---|
570 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
|
---|
571 |
|
---|
572 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
|
---|
573 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
|
---|
574 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
|
---|
575 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
|
---|
576 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
|
---|
577 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
|
---|
578 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
|
---|
579 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
|
---|
580 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
|
---|
581 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
|
---|
582 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
|
---|
583 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
|
---|
584 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
|
---|
585 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
|
---|
586 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
|
---|
587 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
|
---|
588 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
|
---|
589 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
|
---|
590 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
|
---|
591 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
|
---|
592 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
|
---|
593 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
|
---|
594 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
|
---|
595 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
|
---|
596 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
|
---|
597 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
|
---|
598 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
|
---|
599 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
|
---|
600 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
|
---|
601 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
|
---|
602 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
|
---|
603 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
|
---|
604 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
|
---|
605 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
|
---|
606 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
|
---|
607 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
|
---|
608 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
|
---|
609 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
|
---|
610 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
|
---|
611 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
|
---|
612 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
|
---|
613 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
|
---|
614 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
|
---|
615 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
|
---|
616 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
|
---|
617 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
|
---|
618 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
|
---|
619 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
|
---|
620 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
|
---|
621 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
|
---|
622 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
|
---|
623 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
|
---|
624 | }
|
---|
625 |
|
---|
626 | LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
|
---|
627 | LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
|
---|
628 | LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
|
---|
629 | LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
|
---|
630 | LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
|
---|
631 |
|
---|
632 | LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
|
---|
633 | LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
|
---|
634 | LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
|
---|
635 | LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
|
---|
636 | LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
|
---|
637 |
|
---|
638 | LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
|
---|
639 | LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
|
---|
640 |
|
---|
641 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
642 | LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
|
---|
643 |
|
---|
644 | #ifdef HWACCM_VTX_WITH_EPT
|
---|
645 | if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
|
---|
646 | pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
|
---|
647 | #endif /* HWACCM_VTX_WITH_EPT */
|
---|
648 | #ifdef HWACCM_VTX_WITH_VPID
|
---|
649 | if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
|
---|
650 | && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
|
---|
651 | pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
|
---|
652 | #endif /* HWACCM_VTX_WITH_VPID */
|
---|
653 |
|
---|
654 | /* Only try once. */
|
---|
655 | pVM->hwaccm.s.fInitialized = true;
|
---|
656 |
|
---|
657 | /* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
|
---|
658 | rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
|
---|
659 | AssertRC(rc);
|
---|
660 | if (RT_FAILURE(rc))
|
---|
661 | return rc;
|
---|
662 |
|
---|
663 | /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
|
---|
664 | ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
|
---|
665 | pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
|
---|
666 | /* Bit set to 0 means redirection enabled. */
|
---|
667 | memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
|
---|
668 | /* Allow all port IO, so the VT-x IO intercepts do their job. */
|
---|
669 | memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
|
---|
670 | *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
|
---|
671 |
|
---|
672 | /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
|
---|
673 | * real and protected mode without paging with EPT.
|
---|
674 | */
|
---|
675 | pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
|
---|
676 | for (unsigned i=0;i<X86_PG_ENTRIES;i++)
|
---|
677 | {
|
---|
678 | pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
|
---|
679 | pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
|
---|
680 | }
|
---|
681 |
|
---|
682 | /* We convert it here every time as pci regions could be reconfigured. */
|
---|
683 | rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
|
---|
684 | AssertRC(rc);
|
---|
685 | LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
|
---|
686 |
|
---|
687 | rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
|
---|
688 | AssertRC(rc);
|
---|
689 | LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
|
---|
690 |
|
---|
691 | rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
|
---|
692 | AssertRC(rc);
|
---|
693 | if (rc == VINF_SUCCESS)
|
---|
694 | {
|
---|
695 | pVM->fHWACCMEnabled = true;
|
---|
696 | pVM->hwaccm.s.vmx.fEnabled = true;
|
---|
697 | hwaccmR3DisableRawMode(pVM);
|
---|
698 |
|
---|
699 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
|
---|
700 | #ifdef VBOX_ENABLE_64_BITS_GUESTS
|
---|
701 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
|
---|
702 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
|
---|
703 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
|
---|
704 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
|
---|
705 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
|
---|
706 | #endif
|
---|
707 | LogRel(("HWACCM: VMX enabled!\n"));
|
---|
708 | if (pVM->hwaccm.s.fNestedPaging)
|
---|
709 | {
|
---|
710 | LogRel(("HWACCM: Enabled nested paging\n"));
|
---|
711 | LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetEPTCR3(pVM)));
|
---|
712 | }
|
---|
713 | if (pVM->hwaccm.s.vmx.fVPID)
|
---|
714 | LogRel(("HWACCM: Enabled VPID\n"));
|
---|
715 |
|
---|
716 | if ( pVM->hwaccm.s.fNestedPaging
|
---|
717 | || pVM->hwaccm.s.vmx.fVPID)
|
---|
718 | {
|
---|
719 | LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
|
---|
720 | LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
|
---|
721 | }
|
---|
722 | }
|
---|
723 | else
|
---|
724 | {
|
---|
725 | LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
|
---|
726 | LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
|
---|
727 | pVM->fHWACCMEnabled = false;
|
---|
728 | }
|
---|
729 | }
|
---|
730 | }
|
---|
731 | else
|
---|
732 | if (pVM->hwaccm.s.svm.fSupported)
|
---|
733 | {
|
---|
734 | Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
|
---|
735 |
|
---|
736 | if (pVM->hwaccm.s.fInitialized == false)
|
---|
737 | {
|
---|
738 | /* Erratum 170 which requires a forced TLB flush for each world switch:
|
---|
739 | * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
|
---|
740 | *
|
---|
741 | * All BH-G1/2 and DH-G1/2 models include a fix:
|
---|
742 | * Athlon X2: 0x6b 1/2
|
---|
743 | * 0x68 1/2
|
---|
744 | * Athlon 64: 0x7f 1
|
---|
745 | * 0x6f 2
|
---|
746 | * Sempron: 0x7f 1/2
|
---|
747 | * 0x6f 2
|
---|
748 | * 0x6c 2
|
---|
749 | * 0x7c 2
|
---|
750 | * Turion 64: 0x68 2
|
---|
751 | *
|
---|
752 | */
|
---|
753 | uint32_t u32Dummy;
|
---|
754 | uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
|
---|
755 | ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
|
---|
756 | u32BaseFamily= (u32Version >> 8) & 0xf;
|
---|
757 | u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
|
---|
758 | u32Model = ((u32Version >> 4) & 0xf);
|
---|
759 | u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
|
---|
760 | u32Stepping = u32Version & 0xf;
|
---|
761 | if ( u32Family == 0xf
|
---|
762 | && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
|
---|
763 | && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
|
---|
764 | {
|
---|
765 | LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
|
---|
766 | }
|
---|
767 |
|
---|
768 | LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
|
---|
769 | LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
|
---|
770 | LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
|
---|
771 | LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
|
---|
772 | LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
|
---|
773 |
|
---|
774 | if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
|
---|
775 | LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
|
---|
776 | if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
|
---|
777 | LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
|
---|
778 | if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
|
---|
779 | LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
|
---|
780 | if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
|
---|
781 | LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
|
---|
782 | if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
|
---|
783 | LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
|
---|
784 |
|
---|
785 | /* Only try once. */
|
---|
786 | pVM->hwaccm.s.fInitialized = true;
|
---|
787 |
|
---|
788 | if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
|
---|
789 | pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
|
---|
790 |
|
---|
791 | rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
|
---|
792 | AssertRC(rc);
|
---|
793 | if (rc == VINF_SUCCESS)
|
---|
794 | {
|
---|
795 | pVM->fHWACCMEnabled = true;
|
---|
796 | pVM->hwaccm.s.svm.fEnabled = true;
|
---|
797 |
|
---|
798 | if (pVM->hwaccm.s.fNestedPaging)
|
---|
799 | LogRel(("HWACCM: Enabled nested paging\n"));
|
---|
800 |
|
---|
801 | hwaccmR3DisableRawMode(pVM);
|
---|
802 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
|
---|
803 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
|
---|
804 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
|
---|
805 | #ifdef VBOX_ENABLE_64_BITS_GUESTS
|
---|
806 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
|
---|
807 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
|
---|
808 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
|
---|
809 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
|
---|
810 | #endif
|
---|
811 | }
|
---|
812 | else
|
---|
813 | {
|
---|
814 | pVM->fHWACCMEnabled = false;
|
---|
815 | }
|
---|
816 | }
|
---|
817 | }
|
---|
818 |
|
---|
819 | #if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
|
---|
820 | if (pVM->fHWACCMEnabled)
|
---|
821 | {
|
---|
822 | switch(PGMGetHostMode(pVM))
|
---|
823 | {
|
---|
824 | case PGMMODE_32_BIT:
|
---|
825 | pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
|
---|
826 | break;
|
---|
827 |
|
---|
828 | case PGMMODE_PAE:
|
---|
829 | case PGMMODE_PAE_NX:
|
---|
830 | pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
|
---|
831 | break;
|
---|
832 |
|
---|
833 | default:
|
---|
834 | AssertFailed();
|
---|
835 | break;
|
---|
836 | }
|
---|
837 |
|
---|
838 | rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
|
---|
839 | AssertMsgRCReturn(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc), rc);
|
---|
840 |
|
---|
841 | rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
|
---|
842 | AssertMsgRCReturn(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc), rc);
|
---|
843 |
|
---|
844 | rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
|
---|
845 | AssertMsgRCReturn(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc), rc);
|
---|
846 |
|
---|
847 | rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
|
---|
848 | AssertMsgRCReturn(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc), rc);
|
---|
849 |
|
---|
850 | #ifdef DEBUG
|
---|
851 | rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
|
---|
852 | AssertMsgRCReturn(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc), rc);
|
---|
853 | #endif
|
---|
854 | }
|
---|
855 | #endif
|
---|
856 | return VINF_SUCCESS;
|
---|
857 | }
|
---|
858 |
|
---|
859 | /**
|
---|
860 | * Applies relocations to data and code managed by this
|
---|
861 | * component. This function will be called at init and
|
---|
862 | * whenever the VMM need to relocate it self inside the GC.
|
---|
863 | *
|
---|
864 | * @param pVM The VM.
|
---|
865 | */
|
---|
866 | VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
|
---|
867 | {
|
---|
868 | Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
|
---|
869 |
|
---|
870 | /* Fetch the current paging mode during the relocate callback during state loading. */
|
---|
871 | if (VMR3GetState(pVM) == VMSTATE_LOADING)
|
---|
872 | {
|
---|
873 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
874 | {
|
---|
875 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
876 | /* @todo SMP */
|
---|
877 | pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVM);
|
---|
878 | pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVM);
|
---|
879 | }
|
---|
880 | }
|
---|
881 |
|
---|
882 | return;
|
---|
883 | }
|
---|
884 |
|
---|
885 | /**
|
---|
886 | * Checks hardware accelerated raw mode is allowed.
|
---|
887 | *
|
---|
888 | * @returns boolean
|
---|
889 | * @param pVM The VM to operate on.
|
---|
890 | */
|
---|
891 | VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
|
---|
892 | {
|
---|
893 | return pVM->hwaccm.s.fAllowed;
|
---|
894 | }
|
---|
895 |
|
---|
896 | /**
|
---|
897 | * Notification callback which is called whenever there is a chance that a CR3
|
---|
898 | * value might have changed.
|
---|
899 | *
|
---|
900 | * This is called by PGM.
|
---|
901 | *
|
---|
902 | * @param pVM The VM to operate on.
|
---|
903 | * @param enmShadowMode New shadow paging mode.
|
---|
904 | * @param enmGuestMode New guest paging mode.
|
---|
905 | */
|
---|
906 | VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
|
---|
907 | {
|
---|
908 | /* Ignore page mode changes during state loading. */
|
---|
909 | if (VMR3GetState(pVM) == VMSTATE_LOADING)
|
---|
910 | return;
|
---|
911 |
|
---|
912 | PVMCPU pVCpu = VMMGetCpu(pVM);
|
---|
913 | pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
|
---|
914 |
|
---|
915 | if ( pVM->hwaccm.s.vmx.fEnabled
|
---|
916 | && pVM->fHWACCMEnabled)
|
---|
917 | {
|
---|
918 | if ( pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
|
---|
919 | && enmGuestMode >= PGMMODE_PROTECTED)
|
---|
920 | {
|
---|
921 | PCPUMCTX pCtx;
|
---|
922 |
|
---|
923 | pCtx = CPUMQueryGuestCtxPtr(pVM);
|
---|
924 |
|
---|
925 | /* After a real mode switch to protected mode we must force
|
---|
926 | * CPL to 0. Our real mode emulation had to set it to 3.
|
---|
927 | */
|
---|
928 | pCtx->ssHid.Attr.n.u2Dpl = 0;
|
---|
929 | }
|
---|
930 | }
|
---|
931 | }
|
---|
932 |
|
---|
933 | /**
|
---|
934 | * Terminates the HWACCM.
|
---|
935 | *
|
---|
936 | * Termination means cleaning up and freeing all resources,
|
---|
937 | * the VM it self is at this point powered off or suspended.
|
---|
938 | *
|
---|
939 | * @returns VBox status code.
|
---|
940 | * @param pVM The VM to operate on.
|
---|
941 | */
|
---|
942 | VMMR3DECL(int) HWACCMR3Term(PVM pVM)
|
---|
943 | {
|
---|
944 | if (pVM->hwaccm.s.vmx.pRealModeTSS)
|
---|
945 | {
|
---|
946 | PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
|
---|
947 | pVM->hwaccm.s.vmx.pRealModeTSS = 0;
|
---|
948 | }
|
---|
949 | return 0;
|
---|
950 | }
|
---|
951 |
|
---|
952 | /**
|
---|
953 | * Terminates the per-VCPU HWACCM.
|
---|
954 | *
|
---|
955 | * Termination means cleaning up and freeing all resources,
|
---|
956 | * the VM it self is at this point powered off or suspended.
|
---|
957 | *
|
---|
958 | * @returns VBox status code.
|
---|
959 | * @param pVM The VM to operate on.
|
---|
960 | */
|
---|
961 | VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
|
---|
962 | {
|
---|
963 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
964 | {
|
---|
965 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
966 |
|
---|
967 | if (pVCpu->hwaccm.s.paStatExitReason)
|
---|
968 | {
|
---|
969 | MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
|
---|
970 | pVCpu->hwaccm.s.paStatExitReason = NULL;
|
---|
971 | pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
|
---|
972 | }
|
---|
973 | }
|
---|
974 | return 0;
|
---|
975 | }
|
---|
976 |
|
---|
977 | /**
|
---|
978 | * The VM is being reset.
|
---|
979 | *
|
---|
980 | * For the HWACCM component this means that any GDT/LDT/TSS monitors
|
---|
981 | * needs to be removed.
|
---|
982 | *
|
---|
983 | * @param pVM VM handle.
|
---|
984 | */
|
---|
985 | VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
|
---|
986 | {
|
---|
987 | LogFlow(("HWACCMR3Reset:\n"));
|
---|
988 |
|
---|
989 | if (pVM->fHWACCMEnabled)
|
---|
990 | hwaccmR3DisableRawMode(pVM);
|
---|
991 |
|
---|
992 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
993 | {
|
---|
994 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
995 |
|
---|
996 | /* On first entry we'll sync everything. */
|
---|
997 | pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
|
---|
998 |
|
---|
999 | pVCpu->hwaccm.s.vmx.cr0_mask = 0;
|
---|
1000 | pVCpu->hwaccm.s.vmx.cr4_mask = 0;
|
---|
1001 |
|
---|
1002 | pVCpu->hwaccm.s.Event.fPending = false;
|
---|
1003 |
|
---|
1004 | /* Reset state information for real-mode emulation in VT-x. */
|
---|
1005 | pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
|
---|
1006 | }
|
---|
1007 | }
|
---|
1008 |
|
---|
1009 | /**
|
---|
1010 | * Checks if we can currently use hardware accelerated raw mode.
|
---|
1011 | *
|
---|
1012 | * @returns boolean
|
---|
1013 | * @param pVM The VM to operate on.
|
---|
1014 | * @param pCtx Partial VM execution context
|
---|
1015 | */
|
---|
1016 | VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
|
---|
1017 | {
|
---|
1018 | Assert(pVM->fHWACCMEnabled);
|
---|
1019 |
|
---|
1020 | /* AMD SVM supports real & protected mode with or without paging. */
|
---|
1021 | if (pVM->hwaccm.s.svm.fEnabled)
|
---|
1022 | {
|
---|
1023 | pVM->hwaccm.s.fActive = true;
|
---|
1024 | return true;
|
---|
1025 | }
|
---|
1026 |
|
---|
1027 | pVM->hwaccm.s.fActive = false;
|
---|
1028 |
|
---|
1029 | /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
|
---|
1030 | #ifdef HWACCM_VMX_EMULATE_REALMODE
|
---|
1031 | if (CPUMIsGuestInRealModeEx(pCtx))
|
---|
1032 | {
|
---|
1033 | /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
|
---|
1034 | * The base must also be equal to (sel << 4).
|
---|
1035 | */
|
---|
1036 | if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
|
---|
1037 | && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
|
---|
1038 | || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
|
---|
1039 | || pCtx->es != (pCtx->esHid.u64Base >> 4)
|
---|
1040 | || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
|
---|
1041 | || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
|
---|
1042 | || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
|
---|
1043 | return false;
|
---|
1044 | }
|
---|
1045 | else
|
---|
1046 | {
|
---|
1047 | PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
|
---|
1048 | /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
|
---|
1049 | * from real to protected mode. (all sorts of RPL & DPL assumptions)
|
---|
1050 | */
|
---|
1051 | PVMCPU pVCpu = VMMGetCpu(pVM);
|
---|
1052 |
|
---|
1053 | if ( pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
|
---|
1054 | && enmGuestMode >= PGMMODE_PROTECTED)
|
---|
1055 | {
|
---|
1056 | if ( (pCtx->cs & X86_SEL_RPL)
|
---|
1057 | || (pCtx->ds & X86_SEL_RPL)
|
---|
1058 | || (pCtx->es & X86_SEL_RPL)
|
---|
1059 | || (pCtx->fs & X86_SEL_RPL)
|
---|
1060 | || (pCtx->gs & X86_SEL_RPL)
|
---|
1061 | || (pCtx->ss & X86_SEL_RPL))
|
---|
1062 | {
|
---|
1063 | return false;
|
---|
1064 | }
|
---|
1065 | }
|
---|
1066 | }
|
---|
1067 | #else
|
---|
1068 | if (!CPUMIsGuestInLongModeEx(pCtx))
|
---|
1069 | {
|
---|
1070 | /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
|
---|
1071 | if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
|
---|
1072 | return false;
|
---|
1073 |
|
---|
1074 | /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
|
---|
1075 | /* Windows XP; switch to protected mode; all selectors are marked not present in the
|
---|
1076 | * hidden registers (possible recompiler bug; see load_seg_vm) */
|
---|
1077 | if (pCtx->csHid.Attr.n.u1Present == 0)
|
---|
1078 | return false;
|
---|
1079 | if (pCtx->ssHid.Attr.n.u1Present == 0)
|
---|
1080 | return false;
|
---|
1081 | }
|
---|
1082 | #endif
|
---|
1083 |
|
---|
1084 | if (pVM->hwaccm.s.vmx.fEnabled)
|
---|
1085 | {
|
---|
1086 | uint32_t mask;
|
---|
1087 |
|
---|
1088 | /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
|
---|
1089 | mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
|
---|
1090 | /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
|
---|
1091 | mask &= ~X86_CR0_NE;
|
---|
1092 |
|
---|
1093 | #ifdef HWACCM_VMX_EMULATE_REALMODE
|
---|
1094 | /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
|
---|
1095 | mask &= ~(X86_CR0_PG|X86_CR0_PE);
|
---|
1096 | #else
|
---|
1097 | /* We support protected mode without paging using identity mapping. */
|
---|
1098 | mask &= ~X86_CR0_PG;
|
---|
1099 | #endif
|
---|
1100 | if ((pCtx->cr0 & mask) != mask)
|
---|
1101 | return false;
|
---|
1102 |
|
---|
1103 | /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
|
---|
1104 | mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
|
---|
1105 | if ((pCtx->cr0 & mask) != 0)
|
---|
1106 | return false;
|
---|
1107 |
|
---|
1108 | /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
|
---|
1109 | mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
|
---|
1110 | mask &= ~X86_CR4_VMXE;
|
---|
1111 | if ((pCtx->cr4 & mask) != mask)
|
---|
1112 | return false;
|
---|
1113 |
|
---|
1114 | /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
|
---|
1115 | mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
|
---|
1116 | if ((pCtx->cr4 & mask) != 0)
|
---|
1117 | return false;
|
---|
1118 |
|
---|
1119 | pVM->hwaccm.s.fActive = true;
|
---|
1120 | return true;
|
---|
1121 | }
|
---|
1122 |
|
---|
1123 | return false;
|
---|
1124 | }
|
---|
1125 |
|
---|
1126 | /**
|
---|
1127 | * Checks if we are currently using hardware accelerated raw mode.
|
---|
1128 | *
|
---|
1129 | * @returns boolean
|
---|
1130 | * @param pVM The VM to operate on.
|
---|
1131 | */
|
---|
1132 | VMMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
|
---|
1133 | {
|
---|
1134 | return pVM->hwaccm.s.fActive;
|
---|
1135 | }
|
---|
1136 |
|
---|
1137 | /**
|
---|
1138 | * Checks if we are currently using nested paging.
|
---|
1139 | *
|
---|
1140 | * @returns boolean
|
---|
1141 | * @param pVM The VM to operate on.
|
---|
1142 | */
|
---|
1143 | VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
|
---|
1144 | {
|
---|
1145 | return pVM->hwaccm.s.fNestedPaging;
|
---|
1146 | }
|
---|
1147 |
|
---|
1148 | /**
|
---|
1149 | * Checks if we are currently using VPID in VT-x mode.
|
---|
1150 | *
|
---|
1151 | * @returns boolean
|
---|
1152 | * @param pVM The VM to operate on.
|
---|
1153 | */
|
---|
1154 | VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
|
---|
1155 | {
|
---|
1156 | return pVM->hwaccm.s.vmx.fVPID;
|
---|
1157 | }
|
---|
1158 |
|
---|
1159 |
|
---|
1160 | /**
|
---|
1161 | * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
|
---|
1162 | *
|
---|
1163 | * @returns boolean
|
---|
1164 | * @param pVM The VM to operate on.
|
---|
1165 | */
|
---|
1166 | VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
|
---|
1167 | {
|
---|
1168 | /* @todo SMP */
|
---|
1169 | return HWACCMIsEnabled(pVM) && pVM->aCpus[0].hwaccm.s.Event.fPending;
|
---|
1170 | }
|
---|
1171 |
|
---|
1172 |
|
---|
1173 | /**
|
---|
1174 | * Inject an NMI into a running VM
|
---|
1175 | *
|
---|
1176 | * @returns boolean
|
---|
1177 | * @param pVM The VM to operate on.
|
---|
1178 | */
|
---|
1179 | VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
|
---|
1180 | {
|
---|
1181 | pVM->hwaccm.s.fInjectNMI = true;
|
---|
1182 | return VINF_SUCCESS;
|
---|
1183 | }
|
---|
1184 |
|
---|
1185 | /**
|
---|
1186 | * Check fatal VT-x/AMD-V error and produce some meaningful
|
---|
1187 | * log release message.
|
---|
1188 | *
|
---|
1189 | * @param pVM The VM to operate on.
|
---|
1190 | * @param iStatusCode VBox status code
|
---|
1191 | */
|
---|
1192 | VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
|
---|
1193 | {
|
---|
1194 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
1195 | {
|
---|
1196 | switch(iStatusCode)
|
---|
1197 | {
|
---|
1198 | case VERR_VMX_INVALID_VMCS_FIELD:
|
---|
1199 | break;
|
---|
1200 |
|
---|
1201 | case VERR_VMX_INVALID_VMCS_PTR:
|
---|
1202 | LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
|
---|
1203 | LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
|
---|
1204 | LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
|
---|
1205 | LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
|
---|
1206 | break;
|
---|
1207 |
|
---|
1208 | case VERR_VMX_UNABLE_TO_START_VM:
|
---|
1209 | LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
|
---|
1210 | LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
|
---|
1211 | #if 0 /* @todo dump the current control fields to the release log */
|
---|
1212 | if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
|
---|
1213 | {
|
---|
1214 |
|
---|
1215 | }
|
---|
1216 | #endif
|
---|
1217 | break;
|
---|
1218 |
|
---|
1219 | case VERR_VMX_UNABLE_TO_RESUME_VM:
|
---|
1220 | LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
|
---|
1221 | LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
|
---|
1222 | break;
|
---|
1223 |
|
---|
1224 | case VERR_VMX_INVALID_VMXON_PTR:
|
---|
1225 | break;
|
---|
1226 | }
|
---|
1227 | }
|
---|
1228 | }
|
---|
1229 |
|
---|
1230 | /**
|
---|
1231 | * Execute state save operation.
|
---|
1232 | *
|
---|
1233 | * @returns VBox status code.
|
---|
1234 | * @param pVM VM Handle.
|
---|
1235 | * @param pSSM SSM operation handle.
|
---|
1236 | */
|
---|
1237 | static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
|
---|
1238 | {
|
---|
1239 | int rc;
|
---|
1240 |
|
---|
1241 | Log(("hwaccmR3Save:\n"));
|
---|
1242 |
|
---|
1243 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
1244 | {
|
---|
1245 | /*
|
---|
1246 | * Save the basic bits - fortunately all the other things can be resynced on load.
|
---|
1247 | */
|
---|
1248 | rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
|
---|
1249 | AssertRCReturn(rc, rc);
|
---|
1250 | rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
|
---|
1251 | AssertRCReturn(rc, rc);
|
---|
1252 | rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
|
---|
1253 | AssertRCReturn(rc, rc);
|
---|
1254 | }
|
---|
1255 |
|
---|
1256 | return VINF_SUCCESS;
|
---|
1257 | }
|
---|
1258 |
|
---|
1259 | /**
|
---|
1260 | * Execute state load operation.
|
---|
1261 | *
|
---|
1262 | * @returns VBox status code.
|
---|
1263 | * @param pVM VM Handle.
|
---|
1264 | * @param pSSM SSM operation handle.
|
---|
1265 | * @param u32Version Data layout version.
|
---|
1266 | */
|
---|
1267 | static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
|
---|
1268 | {
|
---|
1269 | int rc;
|
---|
1270 |
|
---|
1271 | Log(("hwaccmR3Load:\n"));
|
---|
1272 |
|
---|
1273 | /*
|
---|
1274 | * Validate version.
|
---|
1275 | */
|
---|
1276 | if (u32Version != HWACCM_SSM_VERSION)
|
---|
1277 | {
|
---|
1278 | AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
|
---|
1279 | return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
|
---|
1280 | }
|
---|
1281 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
1282 | {
|
---|
1283 | rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
|
---|
1284 | AssertRCReturn(rc, rc);
|
---|
1285 | rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
|
---|
1286 | AssertRCReturn(rc, rc);
|
---|
1287 | rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
|
---|
1288 | AssertRCReturn(rc, rc);
|
---|
1289 | }
|
---|
1290 | return VINF_SUCCESS;
|
---|
1291 | }
|
---|
1292 |
|
---|
1293 |
|
---|
1294 |
|
---|
1295 |
|
---|