VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 15017

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1/* $Id: HWACCM.cpp 15017 2008-12-05 08:58:38Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/csam.h>
35#include <VBox/selm.h>
36#include <VBox/rem.h>
37#include <VBox/hwacc_vmx.h>
38#include <VBox/hwacc_svm.h>
39#include "HWACCMInternal.h"
40#include <VBox/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/string.h>
48#include <iprt/thread.h>
49
50/*******************************************************************************
51* Internal Functions *
52*******************************************************************************/
53static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
54static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
55
56
57/**
58 * Initializes the HWACCM.
59 *
60 * @returns VBox status code.
61 * @param pVM The VM to operate on.
62 */
63VMMR3DECL(int) HWACCMR3Init(PVM pVM)
64{
65 LogFlow(("HWACCMR3Init\n"));
66
67 /*
68 * Assert alignment and sizes.
69 */
70 AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
71 AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
72
73 /* Some structure checks. */
74 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
75 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
76 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
77 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
78
79 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
80 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
81 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
82 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
83 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
84 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
85 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
86
87
88 /*
89 * Register the saved state data unit.
90 */
91 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
92 NULL, hwaccmR3Save, NULL,
93 NULL, hwaccmR3Load, NULL);
94 if (RT_FAILURE(rc))
95 return rc;
96
97 /* Misc initialisation. */
98 pVM->hwaccm.s.vmx.fSupported = false;
99 pVM->hwaccm.s.svm.fSupported = false;
100 pVM->hwaccm.s.vmx.fEnabled = false;
101 pVM->hwaccm.s.svm.fEnabled = false;
102
103 pVM->hwaccm.s.fActive = false;
104 pVM->hwaccm.s.fNestedPaging = false;
105
106 /* Disabled by default. */
107 pVM->fHWACCMEnabled = false;
108
109 /*
110 * Check CFGM options.
111 */
112 /* Nested paging: disabled by default. */
113 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
114 AssertRC(rc);
115
116 /* VT-x VPID: disabled by default. */
117 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
118 AssertRC(rc);
119
120 /* HWACCM support must be explicitely enabled in the configuration file. */
121 rc = CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed, false);
122 AssertRC(rc);
123
124#ifdef RT_OS_DARWIN
125 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
126#else
127 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
128#endif
129 {
130 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
131 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
132 return VERR_HWACCM_CONFIG_MISMATCH;
133 }
134
135 if (VMMIsHwVirtExtForced(pVM))
136 pVM->fHWACCMEnabled = true;
137
138 return VINF_SUCCESS;
139}
140
141/**
142 * Initializes the per-VCPU HWACCM.
143 *
144 * @returns VBox status code.
145 * @param pVM The VM to operate on.
146 */
147VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
148{
149 LogFlow(("HWACCMR3InitCPU\n"));
150
151#ifdef VBOX_WITH_STATISTICS
152 /*
153 * Statistics.
154 */
155 for (unsigned i=0;i<pVM->cCPUs;i++)
156 {
157 PVMCPU pVCpu = &pVM->aCpus[i];
158 int rc;
159
160 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
161 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
162 AssertRC(rc);
163 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit",
164 "/PROF/HWACCM/CPU%d/SwitchFromGC", i);
165 AssertRC(rc);
166 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
167 "/PROF/HWACCM/CPU%d/InGC", i);
168 AssertRC(rc);
169
170#define HWACCM_REG_COUNTER(a, b) \
171 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
172 AssertRC(rc);
173
174 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
175 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
176 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
177 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
178 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
179 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
180 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
181 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
182 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
183 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
184 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
185 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
186 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
187 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
188 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
189 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
190 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
191 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
192 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
193 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
194 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
195 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
196 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
197 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
198 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
199
200 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
201 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
202
203 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
204 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
205 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
206
207 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
208 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
209 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
210 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
211 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
212 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
213 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
214 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
215 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
216
217 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
218 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
219
220 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
221 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
222 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
223
224 for (int j=0;i<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
225 {
226 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of CRx writes",
227 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%", j);
228 AssertRC(rc);
229 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of CRx reads",
230 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%", j);
231 AssertRC(rc);
232 }
233
234#undef HWACCM_REG_COUNTER
235
236 pVCpu->hwaccm.s.paStatExitReason = NULL;
237
238 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
239 AssertRC(rc);
240 if (RT_SUCCESS(rc))
241 {
242 for (int j=0;j<MAX_EXITREASON_STAT;j++)
243 {
244 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Exit reason",
245 "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
246 AssertRC(rc);
247 }
248 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Exit reason", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
249 AssertRC(rc);
250 }
251 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
252 Assert(pVCpu->hwaccm.s.paStatExitReasonR0);
253 }
254#endif /* VBOX_WITH_STATISTICS */
255 return VINF_SUCCESS;
256}
257
258/**
259 * Turns off normal raw mode features
260 *
261 * @param pVM The VM to operate on.
262 */
263static void hwaccmR3DisableRawMode(PVM pVM)
264{
265 /* Disable PATM & CSAM. */
266 PATMR3AllowPatching(pVM, false);
267 CSAMDisableScanning(pVM);
268
269 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
270 SELMR3DisableMonitoring(pVM);
271 TRPMR3DisableMonitoring(pVM);
272
273 /* The hidden selector registers are now valid. */
274 CPUMSetHiddenSelRegsValid(pVM, true);
275
276 /* Disable the switcher code (safety precaution). */
277 VMMR3DisableSwitcher(pVM);
278
279 /* Disable mapping of the hypervisor into the shadow page table. */
280 PGMR3ChangeShwPDMappings(pVM, false);
281
282 /* Disable the switcher */
283 VMMR3DisableSwitcher(pVM);
284
285 if (pVM->hwaccm.s.fNestedPaging)
286 {
287 /* Reinit the paging mode to force the new shadow mode. */
288 PGMR3ChangeMode(pVM, PGMMODE_REAL);
289 }
290}
291
292/**
293 * Initialize VT-x or AMD-V.
294 *
295 * @returns VBox status code.
296 * @param pVM The VM handle.
297 */
298VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
299{
300 int rc;
301
302 if ( !pVM->hwaccm.s.vmx.fSupported
303 && !pVM->hwaccm.s.svm.fSupported)
304 {
305 LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
306 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
307#ifdef RT_OS_DARWIN
308 if (VMMIsHwVirtExtForced(pVM))
309 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
310#endif
311 return VINF_SUCCESS;
312 }
313
314 /*
315 * Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
316 * because it turns off paging, which is not allowed in VMX root mode.
317 *
318 * To simplify matters we'll just force all running VMs to either use raw or VT-x mode. No mixing allowed in the VT-x case.
319 * There's no such problem with AMD-V. (@todo)
320 *
321 */
322 /* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
323 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
324 if (RT_FAILURE(rc))
325 {
326 LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
327 LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
328
329#ifdef RT_OS_DARWIN
330 /*
331 * This is 100% fatal if we didn't prepare for a HwVirtExt setup because of
332 * missing ring-0 allocations. For VMs that require HwVirtExt it doesn't normally
333 * make sense to try run them in software mode, so fail that too.
334 */
335 if (VMMIsHwVirtExtForced(pVM))
336 VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to "
337 "simultaneously use VT-x.");
338 else
339 VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not "
340 "allowed to simultaneously use software virtualization.");
341 return rc;
342
343#else /* !RT_OS_DARWIN */
344
345 /* Invert the selection */
346 pVM->hwaccm.s.fAllowed ^= 1;
347 if (pVM->hwaccm.s.fAllowed)
348 {
349 if (pVM->hwaccm.s.vmx.fSupported)
350 VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not allowed "
351 "to simultaneously use software virtualization.\n");
352 else
353 VM_SET_ERROR(pVM, rc, "An active VM already uses AMD-V hardware acceleration. It is not allowed to "
354 "simultaneously use software virtualization.\n");
355 }
356 else
357 VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to simultaneously "
358 "use VT-x or AMD-V.\n");
359 return rc;
360#endif /* !RT_OS_DARWIN */
361 }
362
363 if (pVM->hwaccm.s.fAllowed == false)
364 return VINF_SUCCESS; /* disabled */
365
366 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
367
368 if (pVM->hwaccm.s.vmx.fSupported)
369 {
370 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
371
372 if ( pVM->hwaccm.s.fInitialized == false
373 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
374 {
375 uint64_t val;
376 RTGCPHYS GCPhys = 0;
377
378 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
379 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
380 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
381 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
382 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
383 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
384 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
385 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
386
387 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
388 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
389 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
390 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
391 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
392 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
393 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
394 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
395 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
396 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
397 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
398
399 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
400 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
401 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
402 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
403 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
404 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
405 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
406 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
407 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
408 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
409 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
410 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
411 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
412 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
413 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
414 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
415 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
416 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
417 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
418 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
419 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
420 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
421 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
422 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
423 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
424 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
425 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
426 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
427 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
428 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
429 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
430 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
431 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
432 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
433 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
434 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
435 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
436 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
437 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
438 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
439 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
440 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
441
442 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
443 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
444 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
445 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
446 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
447 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
448 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
449 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
450 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
451 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
452 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
453 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
454 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
455 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
456 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
457 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
458 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
459 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
460 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
461 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
462 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
463 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
464 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
465 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
466 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
467 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
468 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
469 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
470 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
471 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
472 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
473 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
474 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
475 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
476 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
477 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
478 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
479 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
480 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
481 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
482 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
483
484 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
485 {
486 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
487 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
488 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
489 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
490 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
491 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
492 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
493 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
494 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
495 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
496
497 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
498 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
499 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
500 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
501 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
502 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
503 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
504 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
505 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
506 }
507
508 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
509 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
510 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
511 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
512 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
513 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
514 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
515 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
516 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
517 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
518 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
519 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
520 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
521 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
522 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
523 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
524 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
525 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
526 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
527 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
528 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
529 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
530 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
531 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
532 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
533 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
534 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
535 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
536 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
537 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
538 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
539
540 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
541 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
542 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
543 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
544 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
545 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
546 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
547 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
548 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
549 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
550 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
551 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
552 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
553 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
554 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
555 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
556 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
557 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
558 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
559 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
560 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
561 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
562 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
563 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
564 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
565 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
566 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
567 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
568 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
569 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
570 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
571 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
572 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
573 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
574 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
575
576 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
577 {
578 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
579
580 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
581 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
582 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
583 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
584 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
585 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
586 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
587 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
588 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
589 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
590 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
591 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
592 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
593 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
594 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
595 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
596 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
597 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
598 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
599 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
600 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
601 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
602 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
603 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
604 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
605 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
606 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
607 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
608 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
609 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
610 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
611 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
612 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
613 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
614 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
615 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
616 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
617 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
618 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
619 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
620 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
621 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
622 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
623 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
624 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
625 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
626 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
627 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
628 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
629 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
630 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
631 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
632 }
633
634 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
635 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
636 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
637 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
638 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
639
640 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
641 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
642 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
643 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
644 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
645
646 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
647 LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
648
649 for (unsigned i=0;i<pVM->cCPUs;i++)
650 LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
651
652#ifdef HWACCM_VTX_WITH_EPT
653 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
654 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
655#endif /* HWACCM_VTX_WITH_EPT */
656#ifdef HWACCM_VTX_WITH_VPID
657 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
658 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
659 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
660#endif /* HWACCM_VTX_WITH_VPID */
661
662 /* Only try once. */
663 pVM->hwaccm.s.fInitialized = true;
664
665 /* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
666 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
667 AssertRC(rc);
668 if (RT_FAILURE(rc))
669 return rc;
670
671 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
672 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
673 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
674 /* Bit set to 0 means redirection enabled. */
675 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
676 /* Allow all port IO, so the VT-x IO intercepts do their job. */
677 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
678 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
679
680 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
681 * real and protected mode without paging with EPT.
682 */
683 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
684 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
685 {
686 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
687 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
688 }
689
690 /* We convert it here every time as pci regions could be reconfigured. */
691 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
692 AssertRC(rc);
693 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
694
695 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
696 AssertRC(rc);
697 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
698
699 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
700 AssertRC(rc);
701 if (rc == VINF_SUCCESS)
702 {
703 pVM->fHWACCMEnabled = true;
704 pVM->hwaccm.s.vmx.fEnabled = true;
705 hwaccmR3DisableRawMode(pVM);
706
707 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
708#ifdef VBOX_ENABLE_64_BITS_GUESTS
709 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
710 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
711 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
712 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
713 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
714#endif
715 LogRel(("HWACCM: VMX enabled!\n"));
716 if (pVM->hwaccm.s.fNestedPaging)
717 {
718 LogRel(("HWACCM: Enabled nested paging\n"));
719 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetEPTCR3(pVM)));
720 }
721 if (pVM->hwaccm.s.vmx.fVPID)
722 LogRel(("HWACCM: Enabled VPID\n"));
723
724 if ( pVM->hwaccm.s.fNestedPaging
725 || pVM->hwaccm.s.vmx.fVPID)
726 {
727 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
728 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
729 }
730 }
731 else
732 {
733 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
734 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
735 pVM->fHWACCMEnabled = false;
736 }
737 }
738 }
739 else
740 if (pVM->hwaccm.s.svm.fSupported)
741 {
742 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
743
744 if (pVM->hwaccm.s.fInitialized == false)
745 {
746 /* Erratum 170 which requires a forced TLB flush for each world switch:
747 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
748 *
749 * All BH-G1/2 and DH-G1/2 models include a fix:
750 * Athlon X2: 0x6b 1/2
751 * 0x68 1/2
752 * Athlon 64: 0x7f 1
753 * 0x6f 2
754 * Sempron: 0x7f 1/2
755 * 0x6f 2
756 * 0x6c 2
757 * 0x7c 2
758 * Turion 64: 0x68 2
759 *
760 */
761 uint32_t u32Dummy;
762 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
763 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
764 u32BaseFamily= (u32Version >> 8) & 0xf;
765 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
766 u32Model = ((u32Version >> 4) & 0xf);
767 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
768 u32Stepping = u32Version & 0xf;
769 if ( u32Family == 0xf
770 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
771 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
772 {
773 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
774 }
775
776 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
777 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
778 LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
779 LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
780 LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
781
782 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
783 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
784 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
785 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
786 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
787 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
788 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
789 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
790 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
791 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
792
793 /* Only try once. */
794 pVM->hwaccm.s.fInitialized = true;
795
796 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
797 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
798
799 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
800 AssertRC(rc);
801 if (rc == VINF_SUCCESS)
802 {
803 pVM->fHWACCMEnabled = true;
804 pVM->hwaccm.s.svm.fEnabled = true;
805
806 if (pVM->hwaccm.s.fNestedPaging)
807 LogRel(("HWACCM: Enabled nested paging\n"));
808
809 hwaccmR3DisableRawMode(pVM);
810 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
811 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
812 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
813#ifdef VBOX_ENABLE_64_BITS_GUESTS
814 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
815 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
816 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
817 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
818#endif
819 }
820 else
821 {
822 pVM->fHWACCMEnabled = false;
823 }
824 }
825 }
826
827#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
828 if (pVM->fHWACCMEnabled)
829 {
830 switch(PGMGetHostMode(pVM))
831 {
832 case PGMMODE_32_BIT:
833 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
834 break;
835
836 case PGMMODE_PAE:
837 case PGMMODE_PAE_NX:
838 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
839 break;
840
841 default:
842 AssertFailed();
843 break;
844 }
845
846 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
847 AssertMsgRCReturn(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc), rc);
848
849 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
850 AssertMsgRCReturn(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc), rc);
851
852 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
853 AssertMsgRCReturn(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc), rc);
854
855 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
856 AssertMsgRCReturn(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc), rc);
857
858# ifdef DEBUG
859 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
860 AssertMsgRCReturn(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc), rc);
861# endif
862 }
863#endif
864 return VINF_SUCCESS;
865}
866
867/**
868 * Applies relocations to data and code managed by this
869 * component. This function will be called at init and
870 * whenever the VMM need to relocate it self inside the GC.
871 *
872 * @param pVM The VM.
873 */
874VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
875{
876 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
877
878 /* Fetch the current paging mode during the relocate callback during state loading. */
879 if (VMR3GetState(pVM) == VMSTATE_LOADING)
880 {
881 for (unsigned i=0;i<pVM->cCPUs;i++)
882 {
883 PVMCPU pVCpu = &pVM->aCpus[i];
884 /* @todo SMP */
885 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVM);
886 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVM);
887 }
888 }
889
890 return;
891}
892
893/**
894 * Checks hardware accelerated raw mode is allowed.
895 *
896 * @returns boolean
897 * @param pVM The VM to operate on.
898 */
899VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
900{
901 return pVM->hwaccm.s.fAllowed;
902}
903
904/**
905 * Notification callback which is called whenever there is a chance that a CR3
906 * value might have changed.
907 *
908 * This is called by PGM.
909 *
910 * @param pVM The VM to operate on.
911 * @param enmShadowMode New shadow paging mode.
912 * @param enmGuestMode New guest paging mode.
913 */
914VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
915{
916 /* Ignore page mode changes during state loading. */
917 if (VMR3GetState(pVM) == VMSTATE_LOADING)
918 return;
919
920 PVMCPU pVCpu = VMMGetCpu(pVM);
921 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
922
923 if ( pVM->hwaccm.s.vmx.fEnabled
924 && pVM->fHWACCMEnabled)
925 {
926 if ( pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
927 && enmGuestMode >= PGMMODE_PROTECTED)
928 {
929 PCPUMCTX pCtx;
930
931 pCtx = CPUMQueryGuestCtxPtr(pVM);
932
933 /* After a real mode switch to protected mode we must force
934 * CPL to 0. Our real mode emulation had to set it to 3.
935 */
936 pCtx->ssHid.Attr.n.u2Dpl = 0;
937 }
938 }
939}
940
941/**
942 * Terminates the HWACCM.
943 *
944 * Termination means cleaning up and freeing all resources,
945 * the VM it self is at this point powered off or suspended.
946 *
947 * @returns VBox status code.
948 * @param pVM The VM to operate on.
949 */
950VMMR3DECL(int) HWACCMR3Term(PVM pVM)
951{
952 if (pVM->hwaccm.s.vmx.pRealModeTSS)
953 {
954 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
955 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
956 }
957 return 0;
958}
959
960/**
961 * Terminates the per-VCPU HWACCM.
962 *
963 * Termination means cleaning up and freeing all resources,
964 * the VM it self is at this point powered off or suspended.
965 *
966 * @returns VBox status code.
967 * @param pVM The VM to operate on.
968 */
969VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
970{
971 for (unsigned i=0;i<pVM->cCPUs;i++)
972 {
973 PVMCPU pVCpu = &pVM->aCpus[i];
974
975 if (pVCpu->hwaccm.s.paStatExitReason)
976 {
977 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
978 pVCpu->hwaccm.s.paStatExitReason = NULL;
979 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
980 }
981 }
982 return 0;
983}
984
985/**
986 * The VM is being reset.
987 *
988 * For the HWACCM component this means that any GDT/LDT/TSS monitors
989 * needs to be removed.
990 *
991 * @param pVM VM handle.
992 */
993VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
994{
995 LogFlow(("HWACCMR3Reset:\n"));
996
997 if (pVM->fHWACCMEnabled)
998 hwaccmR3DisableRawMode(pVM);
999
1000 for (unsigned i=0;i<pVM->cCPUs;i++)
1001 {
1002 PVMCPU pVCpu = &pVM->aCpus[i];
1003
1004 /* On first entry we'll sync everything. */
1005 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1006
1007 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1008 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1009
1010 pVCpu->hwaccm.s.Event.fPending = false;
1011
1012 /* Reset state information for real-mode emulation in VT-x. */
1013 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1014 }
1015}
1016
1017/**
1018 * Checks if we can currently use hardware accelerated raw mode.
1019 *
1020 * @returns boolean
1021 * @param pVM The VM to operate on.
1022 * @param pCtx Partial VM execution context
1023 */
1024VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
1025{
1026 Assert(pVM->fHWACCMEnabled);
1027
1028 /* AMD SVM supports real & protected mode with or without paging. */
1029 if (pVM->hwaccm.s.svm.fEnabled)
1030 {
1031 pVM->hwaccm.s.fActive = true;
1032 return true;
1033 }
1034
1035 pVM->hwaccm.s.fActive = false;
1036
1037 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
1038#ifdef HWACCM_VMX_EMULATE_REALMODE
1039 if (CPUMIsGuestInRealModeEx(pCtx))
1040 {
1041 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
1042 * The base must also be equal to (sel << 4).
1043 */
1044 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
1045 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
1046 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
1047 || pCtx->es != (pCtx->esHid.u64Base >> 4)
1048 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
1049 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
1050 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
1051 return false;
1052 }
1053 else
1054 {
1055 PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
1056 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
1057 * from real to protected mode. (all sorts of RPL & DPL assumptions)
1058 */
1059 PVMCPU pVCpu = VMMGetCpu(pVM);
1060
1061 if ( pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
1062 && enmGuestMode >= PGMMODE_PROTECTED)
1063 {
1064 if ( (pCtx->cs & X86_SEL_RPL)
1065 || (pCtx->ds & X86_SEL_RPL)
1066 || (pCtx->es & X86_SEL_RPL)
1067 || (pCtx->fs & X86_SEL_RPL)
1068 || (pCtx->gs & X86_SEL_RPL)
1069 || (pCtx->ss & X86_SEL_RPL))
1070 {
1071 return false;
1072 }
1073 }
1074 }
1075#else
1076 if (!CPUMIsGuestInLongModeEx(pCtx))
1077 {
1078 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
1079 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
1080 return false;
1081
1082 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
1083 /* Windows XP; switch to protected mode; all selectors are marked not present in the
1084 * hidden registers (possible recompiler bug; see load_seg_vm) */
1085 if (pCtx->csHid.Attr.n.u1Present == 0)
1086 return false;
1087 if (pCtx->ssHid.Attr.n.u1Present == 0)
1088 return false;
1089 }
1090#endif
1091
1092 if (pVM->hwaccm.s.vmx.fEnabled)
1093 {
1094 uint32_t mask;
1095
1096 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
1097 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
1098 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
1099 mask &= ~X86_CR0_NE;
1100
1101#ifdef HWACCM_VMX_EMULATE_REALMODE
1102 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
1103 mask &= ~(X86_CR0_PG|X86_CR0_PE);
1104#else
1105 /* We support protected mode without paging using identity mapping. */
1106 mask &= ~X86_CR0_PG;
1107#endif
1108 if ((pCtx->cr0 & mask) != mask)
1109 return false;
1110
1111 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
1112 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
1113 if ((pCtx->cr0 & mask) != 0)
1114 return false;
1115
1116 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
1117 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1118 mask &= ~X86_CR4_VMXE;
1119 if ((pCtx->cr4 & mask) != mask)
1120 return false;
1121
1122 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
1123 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
1124 if ((pCtx->cr4 & mask) != 0)
1125 return false;
1126
1127 pVM->hwaccm.s.fActive = true;
1128 return true;
1129 }
1130
1131 return false;
1132}
1133
1134/**
1135 * Checks if we are currently using hardware accelerated raw mode.
1136 *
1137 * @returns boolean
1138 * @param pVM The VM to operate on.
1139 */
1140VMMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
1141{
1142 return pVM->hwaccm.s.fActive;
1143}
1144
1145/**
1146 * Checks if we are currently using nested paging.
1147 *
1148 * @returns boolean
1149 * @param pVM The VM to operate on.
1150 */
1151VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
1152{
1153 return pVM->hwaccm.s.fNestedPaging;
1154}
1155
1156/**
1157 * Checks if we are currently using VPID in VT-x mode.
1158 *
1159 * @returns boolean
1160 * @param pVM The VM to operate on.
1161 */
1162VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
1163{
1164 return pVM->hwaccm.s.vmx.fVPID;
1165}
1166
1167
1168/**
1169 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
1170 *
1171 * @returns boolean
1172 * @param pVM The VM to operate on.
1173 */
1174VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
1175{
1176 /* @todo SMP */
1177 return HWACCMIsEnabled(pVM) && pVM->aCpus[0].hwaccm.s.Event.fPending;
1178}
1179
1180
1181/**
1182 * Inject an NMI into a running VM
1183 *
1184 * @returns boolean
1185 * @param pVM The VM to operate on.
1186 */
1187VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
1188{
1189 pVM->hwaccm.s.fInjectNMI = true;
1190 return VINF_SUCCESS;
1191}
1192
1193/**
1194 * Check fatal VT-x/AMD-V error and produce some meaningful
1195 * log release message.
1196 *
1197 * @param pVM The VM to operate on.
1198 * @param iStatusCode VBox status code
1199 */
1200VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
1201{
1202 for (unsigned i=0;i<pVM->cCPUs;i++)
1203 {
1204 switch(iStatusCode)
1205 {
1206 case VERR_VMX_INVALID_VMCS_FIELD:
1207 break;
1208
1209 case VERR_VMX_INVALID_VMCS_PTR:
1210 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1211 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
1212 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
1213 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
1214 break;
1215
1216 case VERR_VMX_UNABLE_TO_START_VM:
1217 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1218 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1219#if 0 /* @todo dump the current control fields to the release log */
1220 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
1221 {
1222
1223 }
1224#endif
1225 break;
1226
1227 case VERR_VMX_UNABLE_TO_RESUME_VM:
1228 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1229 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1230 break;
1231
1232 case VERR_VMX_INVALID_VMXON_PTR:
1233 break;
1234 }
1235 }
1236}
1237
1238/**
1239 * Execute state save operation.
1240 *
1241 * @returns VBox status code.
1242 * @param pVM VM Handle.
1243 * @param pSSM SSM operation handle.
1244 */
1245static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
1246{
1247 int rc;
1248
1249 Log(("hwaccmR3Save:\n"));
1250
1251 for (unsigned i=0;i<pVM->cCPUs;i++)
1252 {
1253 /*
1254 * Save the basic bits - fortunately all the other things can be resynced on load.
1255 */
1256 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
1257 AssertRCReturn(rc, rc);
1258 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
1259 AssertRCReturn(rc, rc);
1260 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
1261 AssertRCReturn(rc, rc);
1262 }
1263
1264 return VINF_SUCCESS;
1265}
1266
1267/**
1268 * Execute state load operation.
1269 *
1270 * @returns VBox status code.
1271 * @param pVM VM Handle.
1272 * @param pSSM SSM operation handle.
1273 * @param u32Version Data layout version.
1274 */
1275static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1276{
1277 int rc;
1278
1279 Log(("hwaccmR3Load:\n"));
1280
1281 /*
1282 * Validate version.
1283 */
1284 if (u32Version != HWACCM_SSM_VERSION)
1285 {
1286 AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
1287 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1288 }
1289 for (unsigned i=0;i<pVM->cCPUs;i++)
1290 {
1291 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
1292 AssertRCReturn(rc, rc);
1293 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
1294 AssertRCReturn(rc, rc);
1295 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
1296 AssertRCReturn(rc, rc);
1297 }
1298 return VINF_SUCCESS;
1299}
1300
1301
1302
1303
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