VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 15184

Last change on this file since 15184 was 15174, checked in by vboxsync, 16 years ago

#1865: don't ever return invalid ring-0 address on 2x4G systems, simply return NIL_RTR0PTR.
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1/* $Id: HWACCM.cpp 15174 2008-12-09 14:11:35Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/csam.h>
35#include <VBox/selm.h>
36#include <VBox/rem.h>
37#include <VBox/hwacc_vmx.h>
38#include <VBox/hwacc_svm.h>
39#include "HWACCMInternal.h"
40#include <VBox/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/string.h>
48#include <iprt/thread.h>
49
50/*******************************************************************************
51* Internal Functions *
52*******************************************************************************/
53static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
54static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
55
56
57/**
58 * Initializes the HWACCM.
59 *
60 * @returns VBox status code.
61 * @param pVM The VM to operate on.
62 */
63VMMR3DECL(int) HWACCMR3Init(PVM pVM)
64{
65 LogFlow(("HWACCMR3Init\n"));
66
67 /*
68 * Assert alignment and sizes.
69 */
70 AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
71 AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
72
73 /* Some structure checks. */
74 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
75 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
76 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
77 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
78
79 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
80 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
81 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
82 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
83 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
84 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
85 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
86
87
88 /*
89 * Register the saved state data unit.
90 */
91 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
92 NULL, hwaccmR3Save, NULL,
93 NULL, hwaccmR3Load, NULL);
94 if (RT_FAILURE(rc))
95 return rc;
96
97 /* Misc initialisation. */
98 pVM->hwaccm.s.vmx.fSupported = false;
99 pVM->hwaccm.s.svm.fSupported = false;
100 pVM->hwaccm.s.vmx.fEnabled = false;
101 pVM->hwaccm.s.svm.fEnabled = false;
102
103 pVM->hwaccm.s.fActive = false;
104 pVM->hwaccm.s.fNestedPaging = false;
105
106 /* Disabled by default. */
107 pVM->fHWACCMEnabled = false;
108
109 /*
110 * Check CFGM options.
111 */
112 /* Nested paging: disabled by default. */
113 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
114 AssertRC(rc);
115
116 /* VT-x VPID: disabled by default. */
117 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
118 AssertRC(rc);
119
120 /* HWACCM support must be explicitely enabled in the configuration file. */
121 rc = CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed, false);
122 AssertRC(rc);
123
124#ifdef RT_OS_DARWIN
125 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
126#else
127 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
128#endif
129 {
130 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
131 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
132 return VERR_HWACCM_CONFIG_MISMATCH;
133 }
134
135 if (VMMIsHwVirtExtForced(pVM))
136 pVM->fHWACCMEnabled = true;
137
138 return VINF_SUCCESS;
139}
140
141/**
142 * Initializes the per-VCPU HWACCM.
143 *
144 * @returns VBox status code.
145 * @param pVM The VM to operate on.
146 */
147VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
148{
149 LogFlow(("HWACCMR3InitCPU\n"));
150
151#ifdef VBOX_WITH_STATISTICS
152 /*
153 * Statistics.
154 */
155 for (unsigned i=0;i<pVM->cCPUs;i++)
156 {
157 PVMCPU pVCpu = &pVM->aCpus[i];
158 int rc;
159
160 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
161 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
162 AssertRC(rc);
163 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit",
164 "/PROF/HWACCM/CPU%d/SwitchFromGC", i);
165 AssertRC(rc);
166 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
167 "/PROF/HWACCM/CPU%d/InGC", i);
168 AssertRC(rc);
169
170#define HWACCM_REG_COUNTER(a, b) \
171 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
172 AssertRC(rc);
173
174 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
175 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
176 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
177 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
178 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
179 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
180 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
181 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
182 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
183 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
184 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
185 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
186 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
187 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
188 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
189 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
190 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
191 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
192 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
193 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
194 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
195 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
196 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
197 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
198 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
199
200 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
201 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
202
203 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
204 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
205 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
206
207 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
208 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
209 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
210 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
211 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
212 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
213 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
214 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
215 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
216
217 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
218 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
219
220 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
221 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
222 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
223
224 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
225 {
226 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
227 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
228 AssertRC(rc);
229 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
230 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
231 AssertRC(rc);
232 }
233
234#undef HWACCM_REG_COUNTER
235
236 pVCpu->hwaccm.s.paStatExitReason = NULL;
237
238 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
239 AssertRC(rc);
240 if (RT_SUCCESS(rc))
241 {
242 for (int j=0;j<MAX_EXITREASON_STAT;j++)
243 {
244 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Exit reason",
245 "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
246 AssertRC(rc);
247 }
248 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Exit reason", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
249 AssertRC(rc);
250 }
251 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
252# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
253 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
254# else
255 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
256# endif
257 }
258#endif /* VBOX_WITH_STATISTICS */
259 return VINF_SUCCESS;
260}
261
262/**
263 * Turns off normal raw mode features
264 *
265 * @param pVM The VM to operate on.
266 */
267static void hwaccmR3DisableRawMode(PVM pVM)
268{
269 /* Disable PATM & CSAM. */
270 PATMR3AllowPatching(pVM, false);
271 CSAMDisableScanning(pVM);
272
273 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
274 SELMR3DisableMonitoring(pVM);
275 TRPMR3DisableMonitoring(pVM);
276
277 /* The hidden selector registers are now valid. */
278 CPUMSetHiddenSelRegsValid(pVM, true);
279
280 /* Disable the switcher code (safety precaution). */
281 VMMR3DisableSwitcher(pVM);
282
283 /* Disable mapping of the hypervisor into the shadow page table. */
284 PGMR3ChangeShwPDMappings(pVM, false);
285
286 /* Disable the switcher */
287 VMMR3DisableSwitcher(pVM);
288
289 if (pVM->hwaccm.s.fNestedPaging)
290 {
291 /* Reinit the paging mode to force the new shadow mode. */
292 PGMR3ChangeMode(pVM, PGMMODE_REAL);
293 }
294}
295
296/**
297 * Initialize VT-x or AMD-V.
298 *
299 * @returns VBox status code.
300 * @param pVM The VM handle.
301 */
302VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
303{
304 int rc;
305
306 if ( !pVM->hwaccm.s.vmx.fSupported
307 && !pVM->hwaccm.s.svm.fSupported)
308 {
309 LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
310 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
311#ifdef RT_OS_DARWIN
312 if (VMMIsHwVirtExtForced(pVM))
313 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
314#endif
315 return VINF_SUCCESS;
316 }
317
318 /*
319 * Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
320 * because it turns off paging, which is not allowed in VMX root mode.
321 *
322 * To simplify matters we'll just force all running VMs to either use raw or VT-x mode. No mixing allowed in the VT-x case.
323 * There's no such problem with AMD-V. (@todo)
324 *
325 */
326 /* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
327 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
328 if (RT_FAILURE(rc))
329 {
330 LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
331 LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
332
333#ifdef RT_OS_DARWIN
334 /*
335 * This is 100% fatal if we didn't prepare for a HwVirtExt setup because of
336 * missing ring-0 allocations. For VMs that require HwVirtExt it doesn't normally
337 * make sense to try run them in software mode, so fail that too.
338 */
339 if (VMMIsHwVirtExtForced(pVM))
340 VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to "
341 "simultaneously use VT-x.");
342 else
343 VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not "
344 "allowed to simultaneously use software virtualization.");
345 return rc;
346
347#else /* !RT_OS_DARWIN */
348
349 /* Invert the selection */
350 pVM->hwaccm.s.fAllowed ^= 1;
351 if (pVM->hwaccm.s.fAllowed)
352 {
353 if (pVM->hwaccm.s.vmx.fSupported)
354 VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not allowed "
355 "to simultaneously use software virtualization.\n");
356 else
357 VM_SET_ERROR(pVM, rc, "An active VM already uses AMD-V hardware acceleration. It is not allowed to "
358 "simultaneously use software virtualization.\n");
359 }
360 else
361 VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to simultaneously "
362 "use VT-x or AMD-V.\n");
363 return rc;
364#endif /* !RT_OS_DARWIN */
365 }
366
367 if (pVM->hwaccm.s.fAllowed == false)
368 return VINF_SUCCESS; /* disabled */
369
370 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
371
372 if (pVM->hwaccm.s.vmx.fSupported)
373 {
374 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
375
376 if ( pVM->hwaccm.s.fInitialized == false
377 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
378 {
379 uint64_t val;
380 RTGCPHYS GCPhys = 0;
381
382 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
383 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
384 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
385 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
386 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
387 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
388 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
389 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
390
391 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
392 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
393 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
394 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
395 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
396 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
397 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
398 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
399 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
400 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
401 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
402
403 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
404 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
405 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
406 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
407 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
408 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
409 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
410 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
411 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
412 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
413 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
414 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
415 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
416 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
417 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
418 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
419 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
420 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
421 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
422 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
423 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
424 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
425 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
426 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
427 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
428 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
429 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
430 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
431 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
432 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
433 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
434 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
435 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
436 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
437 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
438 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
439 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
440 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
441 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
442 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
443 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
444 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
445
446 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
447 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
448 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
449 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
450 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
451 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
452 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
453 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
454 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
455 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
456 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
457 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
458 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
459 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
460 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
461 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
462 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
463 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
464 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
465 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
466 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
467 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
468 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
469 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
470 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
471 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
472 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
473 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
474 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
475 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
476 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
477 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
478 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
479 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
480 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
481 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
482 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
483 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
484 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
485 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
486 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
487
488 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
489 {
490 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
491 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
492 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
493 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
494 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
495 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
496 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
497 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
498 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
499 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
500
501 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
502 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
503 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
504 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
505 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
506 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
507 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
508 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
509 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
510 }
511
512 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
513 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
514 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
515 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
516 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
517 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
518 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
519 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
520 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
521 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
522 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
523 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
524 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
525 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
526 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
527 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
528 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
529 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
530 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
531 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
532 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
533 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
534 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
535 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
536 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
537 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
538 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
539 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
540 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
541 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
542 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
543
544 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
545 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
546 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
547 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
548 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
549 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
550 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
551 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
552 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
553 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
554 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
555 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
556 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
557 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
558 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
559 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
560 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
561 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
562 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
563 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
564 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
565 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
566 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
567 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
568 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
569 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
570 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
571 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
572 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
573 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
574 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
575 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
576 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
577 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
578 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
579
580 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
581 {
582 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
583
584 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
585 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
586 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
587 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
588 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
589 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
590 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
591 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
592 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
593 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
594 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
595 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
596 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
597 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
598 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
599 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
600 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
601 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
602 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
603 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
604 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
605 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
606 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
607 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
608 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
609 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
610 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
611 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
612 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
613 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
614 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
615 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
616 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
617 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
618 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
619 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
620 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
621 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
622 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
623 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
624 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
625 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
626 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
627 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
628 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
629 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
630 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
631 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
632 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
633 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
634 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
635 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
636 }
637
638 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
639 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
640 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
641 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
642 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
643
644 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
645 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
646 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
647 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
648 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
649
650 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
651 LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
652
653 for (unsigned i=0;i<pVM->cCPUs;i++)
654 LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
655
656#ifdef HWACCM_VTX_WITH_EPT
657 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
658 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
659#endif /* HWACCM_VTX_WITH_EPT */
660#ifdef HWACCM_VTX_WITH_VPID
661 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
662 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
663 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
664#endif /* HWACCM_VTX_WITH_VPID */
665
666 /* Only try once. */
667 pVM->hwaccm.s.fInitialized = true;
668
669 /* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
670 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
671 AssertRC(rc);
672 if (RT_FAILURE(rc))
673 return rc;
674
675 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
676 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
677 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
678 /* Bit set to 0 means redirection enabled. */
679 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
680 /* Allow all port IO, so the VT-x IO intercepts do their job. */
681 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
682 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
683
684 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
685 * real and protected mode without paging with EPT.
686 */
687 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
688 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
689 {
690 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
691 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
692 }
693
694 /* We convert it here every time as pci regions could be reconfigured. */
695 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
696 AssertRC(rc);
697 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
698
699 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
700 AssertRC(rc);
701 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
702
703 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
704 AssertRC(rc);
705 if (rc == VINF_SUCCESS)
706 {
707 pVM->fHWACCMEnabled = true;
708 pVM->hwaccm.s.vmx.fEnabled = true;
709 hwaccmR3DisableRawMode(pVM);
710
711 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
712#ifdef VBOX_ENABLE_64_BITS_GUESTS
713 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
714 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
715 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
716 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
717 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
718#endif
719 LogRel(("HWACCM: VMX enabled!\n"));
720 if (pVM->hwaccm.s.fNestedPaging)
721 {
722 LogRel(("HWACCM: Enabled nested paging\n"));
723 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetEPTCR3(pVM)));
724 }
725 if (pVM->hwaccm.s.vmx.fVPID)
726 LogRel(("HWACCM: Enabled VPID\n"));
727
728 if ( pVM->hwaccm.s.fNestedPaging
729 || pVM->hwaccm.s.vmx.fVPID)
730 {
731 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
732 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
733 }
734 }
735 else
736 {
737 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
738 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
739 pVM->fHWACCMEnabled = false;
740 }
741 }
742 }
743 else
744 if (pVM->hwaccm.s.svm.fSupported)
745 {
746 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
747
748 if (pVM->hwaccm.s.fInitialized == false)
749 {
750 /* Erratum 170 which requires a forced TLB flush for each world switch:
751 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
752 *
753 * All BH-G1/2 and DH-G1/2 models include a fix:
754 * Athlon X2: 0x6b 1/2
755 * 0x68 1/2
756 * Athlon 64: 0x7f 1
757 * 0x6f 2
758 * Sempron: 0x7f 1/2
759 * 0x6f 2
760 * 0x6c 2
761 * 0x7c 2
762 * Turion 64: 0x68 2
763 *
764 */
765 uint32_t u32Dummy;
766 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
767 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
768 u32BaseFamily= (u32Version >> 8) & 0xf;
769 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
770 u32Model = ((u32Version >> 4) & 0xf);
771 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
772 u32Stepping = u32Version & 0xf;
773 if ( u32Family == 0xf
774 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
775 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
776 {
777 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
778 }
779
780 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
781 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
782 LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
783 LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
784 LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
785
786 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
787 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
788 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
789 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
790 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
791 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
792 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
793 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
794 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
795 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
796
797 /* Only try once. */
798 pVM->hwaccm.s.fInitialized = true;
799
800 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
801 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
802
803 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
804 AssertRC(rc);
805 if (rc == VINF_SUCCESS)
806 {
807 pVM->fHWACCMEnabled = true;
808 pVM->hwaccm.s.svm.fEnabled = true;
809
810 if (pVM->hwaccm.s.fNestedPaging)
811 LogRel(("HWACCM: Enabled nested paging\n"));
812
813 hwaccmR3DisableRawMode(pVM);
814 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
815 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
816 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
817#ifdef VBOX_ENABLE_64_BITS_GUESTS
818 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
819 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
820 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
821 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
822#endif
823 }
824 else
825 {
826 pVM->fHWACCMEnabled = false;
827 }
828 }
829 }
830
831#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
832 if (pVM->fHWACCMEnabled)
833 {
834 switch(PGMGetHostMode(pVM))
835 {
836 case PGMMODE_32_BIT:
837 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
838 break;
839
840 case PGMMODE_PAE:
841 case PGMMODE_PAE_NX:
842 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
843 break;
844
845 default:
846 AssertFailed();
847 break;
848 }
849
850 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
851 AssertMsgRCReturn(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc), rc);
852
853 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
854 AssertMsgRCReturn(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc), rc);
855
856 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
857 AssertMsgRCReturn(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc), rc);
858
859 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
860 AssertMsgRCReturn(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc), rc);
861
862# ifdef DEBUG
863 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
864 AssertMsgRCReturn(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc), rc);
865# endif
866 }
867#endif
868 return VINF_SUCCESS;
869}
870
871/**
872 * Applies relocations to data and code managed by this
873 * component. This function will be called at init and
874 * whenever the VMM need to relocate it self inside the GC.
875 *
876 * @param pVM The VM.
877 */
878VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
879{
880 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
881
882 /* Fetch the current paging mode during the relocate callback during state loading. */
883 if (VMR3GetState(pVM) == VMSTATE_LOADING)
884 {
885 for (unsigned i=0;i<pVM->cCPUs;i++)
886 {
887 PVMCPU pVCpu = &pVM->aCpus[i];
888 /* @todo SMP */
889 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVM);
890 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVM);
891 }
892 }
893
894 return;
895}
896
897/**
898 * Checks hardware accelerated raw mode is allowed.
899 *
900 * @returns boolean
901 * @param pVM The VM to operate on.
902 */
903VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
904{
905 return pVM->hwaccm.s.fAllowed;
906}
907
908/**
909 * Notification callback which is called whenever there is a chance that a CR3
910 * value might have changed.
911 *
912 * This is called by PGM.
913 *
914 * @param pVM The VM to operate on.
915 * @param enmShadowMode New shadow paging mode.
916 * @param enmGuestMode New guest paging mode.
917 */
918VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
919{
920 /* Ignore page mode changes during state loading. */
921 if (VMR3GetState(pVM) == VMSTATE_LOADING)
922 return;
923
924 PVMCPU pVCpu = VMMGetCpu(pVM);
925 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
926
927 if ( pVM->hwaccm.s.vmx.fEnabled
928 && pVM->fHWACCMEnabled)
929 {
930 if ( pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
931 && enmGuestMode >= PGMMODE_PROTECTED)
932 {
933 PCPUMCTX pCtx;
934
935 pCtx = CPUMQueryGuestCtxPtr(pVM);
936
937 /* After a real mode switch to protected mode we must force
938 * CPL to 0. Our real mode emulation had to set it to 3.
939 */
940 pCtx->ssHid.Attr.n.u2Dpl = 0;
941 }
942 }
943}
944
945/**
946 * Terminates the HWACCM.
947 *
948 * Termination means cleaning up and freeing all resources,
949 * the VM it self is at this point powered off or suspended.
950 *
951 * @returns VBox status code.
952 * @param pVM The VM to operate on.
953 */
954VMMR3DECL(int) HWACCMR3Term(PVM pVM)
955{
956 if (pVM->hwaccm.s.vmx.pRealModeTSS)
957 {
958 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
959 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
960 }
961 return 0;
962}
963
964/**
965 * Terminates the per-VCPU HWACCM.
966 *
967 * Termination means cleaning up and freeing all resources,
968 * the VM it self is at this point powered off or suspended.
969 *
970 * @returns VBox status code.
971 * @param pVM The VM to operate on.
972 */
973VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
974{
975 for (unsigned i=0;i<pVM->cCPUs;i++)
976 {
977 PVMCPU pVCpu = &pVM->aCpus[i];
978
979 if (pVCpu->hwaccm.s.paStatExitReason)
980 {
981 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
982 pVCpu->hwaccm.s.paStatExitReason = NULL;
983 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
984 }
985 }
986 return 0;
987}
988
989/**
990 * The VM is being reset.
991 *
992 * For the HWACCM component this means that any GDT/LDT/TSS monitors
993 * needs to be removed.
994 *
995 * @param pVM VM handle.
996 */
997VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
998{
999 LogFlow(("HWACCMR3Reset:\n"));
1000
1001 if (pVM->fHWACCMEnabled)
1002 hwaccmR3DisableRawMode(pVM);
1003
1004 for (unsigned i=0;i<pVM->cCPUs;i++)
1005 {
1006 PVMCPU pVCpu = &pVM->aCpus[i];
1007
1008 /* On first entry we'll sync everything. */
1009 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1010
1011 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1012 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1013
1014 pVCpu->hwaccm.s.Event.fPending = false;
1015
1016 /* Reset state information for real-mode emulation in VT-x. */
1017 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1018 }
1019}
1020
1021/**
1022 * Checks if we can currently use hardware accelerated raw mode.
1023 *
1024 * @returns boolean
1025 * @param pVM The VM to operate on.
1026 * @param pCtx Partial VM execution context
1027 */
1028VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
1029{
1030 Assert(pVM->fHWACCMEnabled);
1031
1032 /* AMD SVM supports real & protected mode with or without paging. */
1033 if (pVM->hwaccm.s.svm.fEnabled)
1034 {
1035 pVM->hwaccm.s.fActive = true;
1036 return true;
1037 }
1038
1039 pVM->hwaccm.s.fActive = false;
1040
1041 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
1042#ifdef HWACCM_VMX_EMULATE_REALMODE
1043 if (CPUMIsGuestInRealModeEx(pCtx))
1044 {
1045 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
1046 * The base must also be equal to (sel << 4).
1047 */
1048 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
1049 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
1050 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
1051 || pCtx->es != (pCtx->esHid.u64Base >> 4)
1052 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
1053 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
1054 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
1055 return false;
1056 }
1057 else
1058 {
1059 PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
1060 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
1061 * from real to protected mode. (all sorts of RPL & DPL assumptions)
1062 */
1063 PVMCPU pVCpu = VMMGetCpu(pVM);
1064
1065 if ( pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
1066 && enmGuestMode >= PGMMODE_PROTECTED)
1067 {
1068 if ( (pCtx->cs & X86_SEL_RPL)
1069 || (pCtx->ds & X86_SEL_RPL)
1070 || (pCtx->es & X86_SEL_RPL)
1071 || (pCtx->fs & X86_SEL_RPL)
1072 || (pCtx->gs & X86_SEL_RPL)
1073 || (pCtx->ss & X86_SEL_RPL))
1074 {
1075 return false;
1076 }
1077 }
1078 }
1079#else
1080 if (!CPUMIsGuestInLongModeEx(pCtx))
1081 {
1082 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
1083 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
1084 return false;
1085
1086 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
1087 /* Windows XP; switch to protected mode; all selectors are marked not present in the
1088 * hidden registers (possible recompiler bug; see load_seg_vm) */
1089 if (pCtx->csHid.Attr.n.u1Present == 0)
1090 return false;
1091 if (pCtx->ssHid.Attr.n.u1Present == 0)
1092 return false;
1093 }
1094#endif
1095
1096 if (pVM->hwaccm.s.vmx.fEnabled)
1097 {
1098 uint32_t mask;
1099
1100 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
1101 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
1102 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
1103 mask &= ~X86_CR0_NE;
1104
1105#ifdef HWACCM_VMX_EMULATE_REALMODE
1106 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
1107 mask &= ~(X86_CR0_PG|X86_CR0_PE);
1108#else
1109 /* We support protected mode without paging using identity mapping. */
1110 mask &= ~X86_CR0_PG;
1111#endif
1112 if ((pCtx->cr0 & mask) != mask)
1113 return false;
1114
1115 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
1116 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
1117 if ((pCtx->cr0 & mask) != 0)
1118 return false;
1119
1120 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
1121 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1122 mask &= ~X86_CR4_VMXE;
1123 if ((pCtx->cr4 & mask) != mask)
1124 return false;
1125
1126 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
1127 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
1128 if ((pCtx->cr4 & mask) != 0)
1129 return false;
1130
1131 pVM->hwaccm.s.fActive = true;
1132 return true;
1133 }
1134
1135 return false;
1136}
1137
1138/**
1139 * Checks if we are currently using hardware accelerated raw mode.
1140 *
1141 * @returns boolean
1142 * @param pVM The VM to operate on.
1143 */
1144VMMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
1145{
1146 return pVM->hwaccm.s.fActive;
1147}
1148
1149/**
1150 * Checks if we are currently using nested paging.
1151 *
1152 * @returns boolean
1153 * @param pVM The VM to operate on.
1154 */
1155VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
1156{
1157 return pVM->hwaccm.s.fNestedPaging;
1158}
1159
1160/**
1161 * Checks if we are currently using VPID in VT-x mode.
1162 *
1163 * @returns boolean
1164 * @param pVM The VM to operate on.
1165 */
1166VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
1167{
1168 return pVM->hwaccm.s.vmx.fVPID;
1169}
1170
1171
1172/**
1173 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
1174 *
1175 * @returns boolean
1176 * @param pVM The VM to operate on.
1177 */
1178VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
1179{
1180 /* @todo SMP */
1181 return HWACCMIsEnabled(pVM) && pVM->aCpus[0].hwaccm.s.Event.fPending;
1182}
1183
1184
1185/**
1186 * Inject an NMI into a running VM
1187 *
1188 * @returns boolean
1189 * @param pVM The VM to operate on.
1190 */
1191VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
1192{
1193 pVM->hwaccm.s.fInjectNMI = true;
1194 return VINF_SUCCESS;
1195}
1196
1197/**
1198 * Check fatal VT-x/AMD-V error and produce some meaningful
1199 * log release message.
1200 *
1201 * @param pVM The VM to operate on.
1202 * @param iStatusCode VBox status code
1203 */
1204VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
1205{
1206 for (unsigned i=0;i<pVM->cCPUs;i++)
1207 {
1208 switch(iStatusCode)
1209 {
1210 case VERR_VMX_INVALID_VMCS_FIELD:
1211 break;
1212
1213 case VERR_VMX_INVALID_VMCS_PTR:
1214 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1215 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
1216 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
1217 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
1218 break;
1219
1220 case VERR_VMX_UNABLE_TO_START_VM:
1221 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1222 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1223#if 0 /* @todo dump the current control fields to the release log */
1224 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
1225 {
1226
1227 }
1228#endif
1229 break;
1230
1231 case VERR_VMX_UNABLE_TO_RESUME_VM:
1232 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1233 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1234 break;
1235
1236 case VERR_VMX_INVALID_VMXON_PTR:
1237 break;
1238 }
1239 }
1240}
1241
1242/**
1243 * Execute state save operation.
1244 *
1245 * @returns VBox status code.
1246 * @param pVM VM Handle.
1247 * @param pSSM SSM operation handle.
1248 */
1249static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
1250{
1251 int rc;
1252
1253 Log(("hwaccmR3Save:\n"));
1254
1255 for (unsigned i=0;i<pVM->cCPUs;i++)
1256 {
1257 /*
1258 * Save the basic bits - fortunately all the other things can be resynced on load.
1259 */
1260 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
1261 AssertRCReturn(rc, rc);
1262 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
1263 AssertRCReturn(rc, rc);
1264 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
1265 AssertRCReturn(rc, rc);
1266 }
1267
1268 return VINF_SUCCESS;
1269}
1270
1271/**
1272 * Execute state load operation.
1273 *
1274 * @returns VBox status code.
1275 * @param pVM VM Handle.
1276 * @param pSSM SSM operation handle.
1277 * @param u32Version Data layout version.
1278 */
1279static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1280{
1281 int rc;
1282
1283 Log(("hwaccmR3Load:\n"));
1284
1285 /*
1286 * Validate version.
1287 */
1288 if (u32Version != HWACCM_SSM_VERSION)
1289 {
1290 AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
1291 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1292 }
1293 for (unsigned i=0;i<pVM->cCPUs;i++)
1294 {
1295 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
1296 AssertRCReturn(rc, rc);
1297 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
1298 AssertRCReturn(rc, rc);
1299 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
1300 AssertRCReturn(rc, rc);
1301 }
1302 return VINF_SUCCESS;
1303}
1304
1305
1306
1307
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