HWACCM.cpp@ 15203

Last change on this file since 15203 was 15197, checked in by vboxsync, 16 years ago
HWACCM: split up the SwitchFromGC (aka StatExit) stats into two parts to get a better idea about what's slow on darwin.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 62.7 KB

Line
1	/* $Id: HWACCM.cpp 15197 2008-12-09 17:35:39Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_HWACCM
26	#include <VBox/cpum.h>
27	#include <VBox/stam.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/trpm.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/patm.h>
34	#include <VBox/csam.h>
35	#include <VBox/selm.h>
36	#include <VBox/rem.h>
37	#include <VBox/hwacc_vmx.h>
38	#include <VBox/hwacc_svm.h>
39	#include "HWACCMInternal.h"
40	#include <VBox/vm.h>
41	#include <VBox/err.h>
42	#include <VBox/param.h>
43
44	#include <iprt/assert.h>
45	#include <VBox/log.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48	#include <iprt/thread.h>
49
50	/*******************************************************************************
51	* Internal Functions *
52	*******************************************************************************/
53	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
54	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
55
56
57	/**
58	* Initializes the HWACCM.
59	*
60	* @returns VBox status code.
61	* @param pVM The VM to operate on.
62	*/
63	VMMR3DECL(int) HWACCMR3Init(PVM pVM)
64	{
65	LogFlow(("HWACCMR3Init\n"));
66
67	/*
68	* Assert alignment and sizes.
69	*/
70	AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
71	AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
72
73	/* Some structure checks. */
74	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
75	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
76	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
77	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
78
79	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
80	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
81	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
82	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
83	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
84	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
85	AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
86
87
88	/*
89	* Register the saved state data unit.
90	*/
91	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
92	NULL, hwaccmR3Save, NULL,
93	NULL, hwaccmR3Load, NULL);
94	if (RT_FAILURE(rc))
95	return rc;
96
97	/* Misc initialisation. */
98	pVM->hwaccm.s.vmx.fSupported = false;
99	pVM->hwaccm.s.svm.fSupported = false;
100	pVM->hwaccm.s.vmx.fEnabled = false;
101	pVM->hwaccm.s.svm.fEnabled = false;
102
103	pVM->hwaccm.s.fActive = false;
104	pVM->hwaccm.s.fNestedPaging = false;
105
106	/* Disabled by default. */
107	pVM->fHWACCMEnabled = false;
108
109	/*
110	* Check CFGM options.
111	*/
112	/* Nested paging: disabled by default. */
113	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
114	AssertRC(rc);
115
116	/* VT-x VPID: disabled by default. */
117	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
118	AssertRC(rc);
119
120	/* HWACCM support must be explicitely enabled in the configuration file. */
121	rc = CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed, false);
122	AssertRC(rc);
123
124	#ifdef RT_OS_DARWIN
125	if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
126	#else
127	if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
128	#endif
129	{
130	AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
131	VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
132	return VERR_HWACCM_CONFIG_MISMATCH;
133	}
134
135	if (VMMIsHwVirtExtForced(pVM))
136	pVM->fHWACCMEnabled = true;
137
138	return VINF_SUCCESS;
139	}
140
141	/**
142	* Initializes the per-VCPU HWACCM.
143	*
144	* @returns VBox status code.
145	* @param pVM The VM to operate on.
146	*/
147	VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
148	{
149	LogFlow(("HWACCMR3InitCPU\n"));
150
151	#ifdef VBOX_WITH_STATISTICS
152	/*
153	* Statistics.
154	*/
155	for (unsigned i=0;i<pVM->cCPUs;i++)
156	{
157	PVMCPU pVCpu = &pVM->aCpus[i];
158	int rc;
159
160	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
161	"/PROF/HWACCM/CPU%d/SwitchToGC", i);
162	AssertRC(rc);
163	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
164	"/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
165	AssertRC(rc);
166	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
167	"/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
168	AssertRC(rc);
169	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
170	"/PROF/HWACCM/CPU%d/InGC", i);
171	AssertRC(rc);
172
173	#define HWACCM_REG_COUNTER(a, b) \
174	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
175	AssertRC(rc);
176
177	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
178	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
179	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
180	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
181	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
182	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
183	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
184	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
185	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
186	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
187	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
188	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
189	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
190	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
191	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
192	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
193	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
194	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
195	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
196	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
197	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
198	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
199	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
200	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
201	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
202
203	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
204	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
205
206	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
207	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
208	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
209
210	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
211	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
212	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
213	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
214	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
215	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
216	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
217	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
218	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
219
220	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
221	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
222
223	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
224	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
225	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
226
227	for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
228	{
229	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
230	"/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
231	AssertRC(rc);
232	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
233	"/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
234	AssertRC(rc);
235	}
236
237	#undef HWACCM_REG_COUNTER
238
239	pVCpu->hwaccm.s.paStatExitReason = NULL;
240
241	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
242	AssertRC(rc);
243	if (RT_SUCCESS(rc))
244	{
245	for (int j=0;j<MAX_EXITREASON_STAT;j++)
246	{
247	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Exit reason",
248	"/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
249	AssertRC(rc);
250	}
251	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Exit reason", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
252	AssertRC(rc);
253	}
254	pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
255	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
256	Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
257	# else
258	Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
259	# endif
260	}
261	#endif /* VBOX_WITH_STATISTICS */
262	return VINF_SUCCESS;
263	}
264
265	/**
266	* Turns off normal raw mode features
267	*
268	* @param pVM The VM to operate on.
269	*/
270	static void hwaccmR3DisableRawMode(PVM pVM)
271	{
272	/* Disable PATM & CSAM. */
273	PATMR3AllowPatching(pVM, false);
274	CSAMDisableScanning(pVM);
275
276	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
277	SELMR3DisableMonitoring(pVM);
278	TRPMR3DisableMonitoring(pVM);
279
280	/* The hidden selector registers are now valid. */
281	CPUMSetHiddenSelRegsValid(pVM, true);
282
283	/* Disable the switcher code (safety precaution). */
284	VMMR3DisableSwitcher(pVM);
285
286	/* Disable mapping of the hypervisor into the shadow page table. */
287	PGMR3ChangeShwPDMappings(pVM, false);
288
289	/* Disable the switcher */
290	VMMR3DisableSwitcher(pVM);
291
292	if (pVM->hwaccm.s.fNestedPaging)
293	{
294	/* Reinit the paging mode to force the new shadow mode. */
295	PGMR3ChangeMode(pVM, PGMMODE_REAL);
296	}
297	}
298
299	/**
300	* Initialize VT-x or AMD-V.
301	*
302	* @returns VBox status code.
303	* @param pVM The VM handle.
304	*/
305	VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
306	{
307	int rc;
308
309	if ( !pVM->hwaccm.s.vmx.fSupported
310	&& !pVM->hwaccm.s.svm.fSupported)
311	{
312	LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
313	LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
314	#ifdef RT_OS_DARWIN
315	if (VMMIsHwVirtExtForced(pVM))
316	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
317	#endif
318	return VINF_SUCCESS;
319	}
320
321	/*
322	* Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
323	* because it turns off paging, which is not allowed in VMX root mode.
324	*
325	* To simplify matters we'll just force all running VMs to either use raw or VT-x mode. No mixing allowed in the VT-x case.
326	* There's no such problem with AMD-V. (@todo)
327	*
328	*/
329	/* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
330	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
331	if (RT_FAILURE(rc))
332	{
333	LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
334	LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
335
336	#ifdef RT_OS_DARWIN
337	/*
338	* This is 100% fatal if we didn't prepare for a HwVirtExt setup because of
339	* missing ring-0 allocations. For VMs that require HwVirtExt it doesn't normally
340	* make sense to try run them in software mode, so fail that too.
341	*/
342	if (VMMIsHwVirtExtForced(pVM))
343	VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to "
344	"simultaneously use VT-x.");
345	else
346	VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not "
347	"allowed to simultaneously use software virtualization.");
348	return rc;
349
350	#else /* !RT_OS_DARWIN */
351
352	/* Invert the selection */
353	pVM->hwaccm.s.fAllowed ^= 1;
354	if (pVM->hwaccm.s.fAllowed)
355	{
356	if (pVM->hwaccm.s.vmx.fSupported)
357	VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not allowed "
358	"to simultaneously use software virtualization.\n");
359	else
360	VM_SET_ERROR(pVM, rc, "An active VM already uses AMD-V hardware acceleration. It is not allowed to "
361	"simultaneously use software virtualization.\n");
362	}
363	else
364	VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to simultaneously "
365	"use VT-x or AMD-V.\n");
366	return rc;
367	#endif /* !RT_OS_DARWIN */
368	}
369
370	if (pVM->hwaccm.s.fAllowed == false)
371	return VINF_SUCCESS; /* disabled */
372
373	Assert(!pVM->fHWACCMEnabled \|\| VMMIsHwVirtExtForced(pVM));
374
375	if (pVM->hwaccm.s.vmx.fSupported)
376	{
377	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
378
379	if ( pVM->hwaccm.s.fInitialized == false
380	&& pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
381	{
382	uint64_t val;
383	RTGCPHYS GCPhys = 0;
384
385	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
386	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
387	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
388	LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
389	LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
390	LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
391	LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
392	LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
393
394	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
395	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
396	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
397	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
398	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
399	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
400	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
401	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
402	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT must be set\n"));
403	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
404	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT must be set\n"));
405
406	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
407	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
408	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
409	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
410	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
411	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
412	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
413	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
414	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
415	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
416	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
417	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
418	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
419	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
420	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
421	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
422	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
423	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
424	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
425	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
426	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
427	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
428	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
429	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
430	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
431	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
432	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
433	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
434	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
435	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
436	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
437	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
438	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
439	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
440	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
441	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
442	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
443	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
444	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
445	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
446	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
447	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
448
449	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
450	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
451	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT must be set\n"));
452	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
453	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET must be set\n"));
454	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
455	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT must be set\n"));
456	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
457	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT must be set\n"));
458	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
459	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT must be set\n"));
460	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
461	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT must be set\n"));
462	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
463	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT must be set\n"));
464	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
465	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT must be set\n"));
466	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
467	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT must be set\n"));
468	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
469	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT must be set\n"));
470	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
471	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT must be set\n"));
472	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
473	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW must be set\n"));
474	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
475	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT must be set\n"));
476	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
477	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT must be set\n"));
478	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
479	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS must be set\n"));
480	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
481	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG must be set\n"));
482	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
483	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS must be set\n"));
484	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
485	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT must be set\n"));
486	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
487	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT must be set\n"));
488	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
489	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL must be set\n"));
490
491	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
492	{
493	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
494	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
495	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
496	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
497	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
498	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
499	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
500	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
501	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
502	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
503
504	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
505	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
506	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC must be set\n"));
507	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
508	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT must be set\n"));
509	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
510	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID must be set\n"));
511	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
512	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT must be set\n"));
513	}
514
515	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
516	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
517	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
518	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
519	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
520	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
521	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
522	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
523	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
524	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
525	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
526	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
527	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
528	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
529	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
530	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
531	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
532	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
533	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG must be set\n"));
534	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
535	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE must be set\n"));
536	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
537	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM must be set\n"));
538	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
539	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON must be set\n"));
540	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
541	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR must be set\n"));
542	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
543	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR must be set\n"));
544	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
545	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR must be set\n"));
546
547	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
548	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
549	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
550	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
551	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
552	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
553	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
554	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
555	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
556	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
557	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
558	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
559	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
560	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
561	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
562	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
563	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
564	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
565	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
566	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
567	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG must be set\n"));
568	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
569	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 must be set\n"));
570	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
571	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ must be set\n"));
572	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
573	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR must be set\n"));
574	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
575	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR must be set\n"));
576	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
577	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR must be set\n"));
578	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
579	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR must be set\n"));
580	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
581	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER must be set\n"));
582
583	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
584	{
585	LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
586
587	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
588	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
589	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
590	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
591	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
592	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
593	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
594	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
595	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
596	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
597	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
598	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
599	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
600	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
601	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
602	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
603	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
604	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
605	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
606	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
607	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
608	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
609	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
610	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
611	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
612	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
613	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
614	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
615	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
616	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
617	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
618	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
619	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
620	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
621	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
622	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
623	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
624	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
625	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
626	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
627	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
628	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
629	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
630	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
631	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
632	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
633	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
634	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
635	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
636	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
637	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
638	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
639	}
640
641	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
642	LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
643	LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
644	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
645	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
646
647	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
648	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
649	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
650	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
651	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
652
653	LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
654	LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
655
656	for (unsigned i=0;i<pVM->cCPUs;i++)
657	LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
658
659	#ifdef HWACCM_VTX_WITH_EPT
660	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
661	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
662	#endif /* HWACCM_VTX_WITH_EPT */
663	#ifdef HWACCM_VTX_WITH_VPID
664	if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
665	&& !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
666	pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
667	#endif /* HWACCM_VTX_WITH_VPID */
668
669	/* Only try once. */
670	pVM->hwaccm.s.fInitialized = true;
671
672	/* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
673	rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
674	AssertRC(rc);
675	if (RT_FAILURE(rc))
676	return rc;
677
678	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
679	ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
680	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
681	/* Bit set to 0 means redirection enabled. */
682	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
683	/* Allow all port IO, so the VT-x IO intercepts do their job. */
684	memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
685	((unsigned char )pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
686
687	/* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
688	* real and protected mode without paging with EPT.
689	*/
690	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
691	for (unsigned i=0;i<X86_PG_ENTRIES;i++)
692	{
693	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
694	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_G;
695	}
696
697	/* We convert it here every time as pci regions could be reconfigured. */
698	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
699	AssertRC(rc);
700	LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
701
702	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
703	AssertRC(rc);
704	LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
705
706	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
707	AssertRC(rc);
708	if (rc == VINF_SUCCESS)
709	{
710	pVM->fHWACCMEnabled = true;
711	pVM->hwaccm.s.vmx.fEnabled = true;
712	hwaccmR3DisableRawMode(pVM);
713
714	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
715	#ifdef VBOX_ENABLE_64_BITS_GUESTS
716	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
717	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
718	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
719	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
720	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
721	#endif
722	LogRel(("HWACCM: VMX enabled!\n"));
723	if (pVM->hwaccm.s.fNestedPaging)
724	{
725	LogRel(("HWACCM: Enabled nested paging\n"));
726	LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetEPTCR3(pVM)));
727	}
728	if (pVM->hwaccm.s.vmx.fVPID)
729	LogRel(("HWACCM: Enabled VPID\n"));
730
731	if ( pVM->hwaccm.s.fNestedPaging
732	\|\| pVM->hwaccm.s.vmx.fVPID)
733	{
734	LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
735	LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
736	}
737	}
738	else
739	{
740	LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
741	LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
742	pVM->fHWACCMEnabled = false;
743	}
744	}
745	}
746	else
747	if (pVM->hwaccm.s.svm.fSupported)
748	{
749	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
750
751	if (pVM->hwaccm.s.fInitialized == false)
752	{
753	/* Erratum 170 which requires a forced TLB flush for each world switch:
754	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
755	*
756	* All BH-G1/2 and DH-G1/2 models include a fix:
757	* Athlon X2: 0x6b 1/2
758	* 0x68 1/2
759	* Athlon 64: 0x7f 1
760	* 0x6f 2
761	* Sempron: 0x7f 1/2
762	* 0x6f 2
763	* 0x6c 2
764	* 0x7c 2
765	* Turion 64: 0x68 2
766	*
767	*/
768	uint32_t u32Dummy;
769	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
770	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
771	u32BaseFamily= (u32Version >> 8) & 0xf;
772	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
773	u32Model = ((u32Version >> 4) & 0xf);
774	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
775	u32Stepping = u32Version & 0xf;
776	if ( u32Family == 0xf
777	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
778	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
779	{
780	LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
781	}
782
783	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
784	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
785	LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
786	LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
787	LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
788
789	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
790	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
791	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
792	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
793	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
794	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
795	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
796	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
797	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
798	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
799
800	/* Only try once. */
801	pVM->hwaccm.s.fInitialized = true;
802
803	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
804	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
805
806	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
807	AssertRC(rc);
808	if (rc == VINF_SUCCESS)
809	{
810	pVM->fHWACCMEnabled = true;
811	pVM->hwaccm.s.svm.fEnabled = true;
812
813	if (pVM->hwaccm.s.fNestedPaging)
814	LogRel(("HWACCM: Enabled nested paging\n"));
815
816	hwaccmR3DisableRawMode(pVM);
817	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
818	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
819	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
820	#ifdef VBOX_ENABLE_64_BITS_GUESTS
821	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
822	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
823	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
824	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
825	#endif
826	}
827	else
828	{
829	pVM->fHWACCMEnabled = false;
830	}
831	}
832	}
833
834	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
835	if (pVM->fHWACCMEnabled)
836	{
837	switch(PGMGetHostMode(pVM))
838	{
839	case PGMMODE_32_BIT:
840	pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
841	break;
842
843	case PGMMODE_PAE:
844	case PGMMODE_PAE_NX:
845	pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
846	break;
847
848	default:
849	AssertFailed();
850	break;
851	}
852
853	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
854	AssertMsgRCReturn(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc), rc);
855
856	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
857	AssertMsgRCReturn(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc), rc);
858
859	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
860	AssertMsgRCReturn(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc), rc);
861
862	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
863	AssertMsgRCReturn(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc), rc);
864
865	# ifdef DEBUG
866	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
867	AssertMsgRCReturn(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc), rc);
868	# endif
869	}
870	#endif
871	return VINF_SUCCESS;
872	}
873
874	/**
875	* Applies relocations to data and code managed by this
876	* component. This function will be called at init and
877	* whenever the VMM need to relocate it self inside the GC.
878	*
879	* @param pVM The VM.
880	*/
881	VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
882	{
883	Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
884
885	/* Fetch the current paging mode during the relocate callback during state loading. */
886	if (VMR3GetState(pVM) == VMSTATE_LOADING)
887	{
888	for (unsigned i=0;i<pVM->cCPUs;i++)
889	{
890	PVMCPU pVCpu = &pVM->aCpus[i];
891	/* @todo SMP */
892	pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVM);
893	pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVM);
894	}
895	}
896
897	return;
898	}
899
900	/**
901	* Checks hardware accelerated raw mode is allowed.
902	*
903	* @returns boolean
904	* @param pVM The VM to operate on.
905	*/
906	VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
907	{
908	return pVM->hwaccm.s.fAllowed;
909	}
910
911	/**
912	* Notification callback which is called whenever there is a chance that a CR3
913	* value might have changed.
914	*
915	* This is called by PGM.
916	*
917	* @param pVM The VM to operate on.
918	* @param enmShadowMode New shadow paging mode.
919	* @param enmGuestMode New guest paging mode.
920	*/
921	VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
922	{
923	/* Ignore page mode changes during state loading. */
924	if (VMR3GetState(pVM) == VMSTATE_LOADING)
925	return;
926
927	PVMCPU pVCpu = VMMGetCpu(pVM);
928	pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
929
930	if ( pVM->hwaccm.s.vmx.fEnabled
931	&& pVM->fHWACCMEnabled)
932	{
933	if ( pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
934	&& enmGuestMode >= PGMMODE_PROTECTED)
935	{
936	PCPUMCTX pCtx;
937
938	pCtx = CPUMQueryGuestCtxPtr(pVM);
939
940	/* After a real mode switch to protected mode we must force
941	* CPL to 0. Our real mode emulation had to set it to 3.
942	*/
943	pCtx->ssHid.Attr.n.u2Dpl = 0;
944	}
945	}
946	}
947
948	/**
949	* Terminates the HWACCM.
950	*
951	* Termination means cleaning up and freeing all resources,
952	* the VM it self is at this point powered off or suspended.
953	*
954	* @returns VBox status code.
955	* @param pVM The VM to operate on.
956	*/
957	VMMR3DECL(int) HWACCMR3Term(PVM pVM)
958	{
959	if (pVM->hwaccm.s.vmx.pRealModeTSS)
960	{
961	PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
962	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
963	}
964	return 0;
965	}
966
967	/**
968	* Terminates the per-VCPU HWACCM.
969	*
970	* Termination means cleaning up and freeing all resources,
971	* the VM it self is at this point powered off or suspended.
972	*
973	* @returns VBox status code.
974	* @param pVM The VM to operate on.
975	*/
976	VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
977	{
978	for (unsigned i=0;i<pVM->cCPUs;i++)
979	{
980	PVMCPU pVCpu = &pVM->aCpus[i];
981
982	if (pVCpu->hwaccm.s.paStatExitReason)
983	{
984	MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
985	pVCpu->hwaccm.s.paStatExitReason = NULL;
986	pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
987	}
988	}
989	return 0;
990	}
991
992	/**
993	* The VM is being reset.
994	*
995	* For the HWACCM component this means that any GDT/LDT/TSS monitors
996	* needs to be removed.
997	*
998	* @param pVM VM handle.
999	*/
1000	VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1001	{
1002	LogFlow(("HWACCMR3Reset:\n"));
1003
1004	if (pVM->fHWACCMEnabled)
1005	hwaccmR3DisableRawMode(pVM);
1006
1007	for (unsigned i=0;i<pVM->cCPUs;i++)
1008	{
1009	PVMCPU pVCpu = &pVM->aCpus[i];
1010
1011	/* On first entry we'll sync everything. */
1012	pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1013
1014	pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1015	pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1016
1017	pVCpu->hwaccm.s.Event.fPending = false;
1018
1019	/* Reset state information for real-mode emulation in VT-x. */
1020	pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1021	}
1022	}
1023
1024	/**
1025	* Checks if we can currently use hardware accelerated raw mode.
1026	*
1027	* @returns boolean
1028	* @param pVM The VM to operate on.
1029	* @param pCtx Partial VM execution context
1030	*/
1031	VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
1032	{
1033	Assert(pVM->fHWACCMEnabled);
1034
1035	/* AMD SVM supports real & protected mode with or without paging. */
1036	if (pVM->hwaccm.s.svm.fEnabled)
1037	{
1038	pVM->hwaccm.s.fActive = true;
1039	return true;
1040	}
1041
1042	pVM->hwaccm.s.fActive = false;
1043
1044	/* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
1045	#ifdef HWACCM_VMX_EMULATE_REALMODE
1046	if (CPUMIsGuestInRealModeEx(pCtx))
1047	{
1048	/* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
1049	* The base must also be equal to (sel << 4).
1050	*/
1051	if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
1052	&& pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
1053	\|\| pCtx->ds != (pCtx->dsHid.u64Base >> 4)
1054	\|\| pCtx->es != (pCtx->esHid.u64Base >> 4)
1055	\|\| pCtx->fs != (pCtx->fsHid.u64Base >> 4)
1056	\|\| pCtx->gs != (pCtx->gsHid.u64Base >> 4)
1057	\|\| pCtx->ss != (pCtx->ssHid.u64Base >> 4))
1058	return false;
1059	}
1060	else
1061	{
1062	PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
1063	/* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
1064	* from real to protected mode. (all sorts of RPL & DPL assumptions)
1065	*/
1066	PVMCPU pVCpu = VMMGetCpu(pVM);
1067
1068	if ( pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
1069	&& enmGuestMode >= PGMMODE_PROTECTED)
1070	{
1071	if ( (pCtx->cs & X86_SEL_RPL)
1072	\|\| (pCtx->ds & X86_SEL_RPL)
1073	\|\| (pCtx->es & X86_SEL_RPL)
1074	\|\| (pCtx->fs & X86_SEL_RPL)
1075	\|\| (pCtx->gs & X86_SEL_RPL)
1076	\|\| (pCtx->ss & X86_SEL_RPL))
1077	{
1078	return false;
1079	}
1080	}
1081	}
1082	#else
1083	if (!CPUMIsGuestInLongModeEx(pCtx))
1084	{
1085	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
1086	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
1087	return false;
1088
1089	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
1090	/* Windows XP; switch to protected mode; all selectors are marked not present in the
1091	* hidden registers (possible recompiler bug; see load_seg_vm) */
1092	if (pCtx->csHid.Attr.n.u1Present == 0)
1093	return false;
1094	if (pCtx->ssHid.Attr.n.u1Present == 0)
1095	return false;
1096	}
1097	#endif
1098
1099	if (pVM->hwaccm.s.vmx.fEnabled)
1100	{
1101	uint32_t mask;
1102
1103	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
1104	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
1105	/* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
1106	mask &= ~X86_CR0_NE;
1107
1108	#ifdef HWACCM_VMX_EMULATE_REALMODE
1109	/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
1110	mask &= ~(X86_CR0_PG\|X86_CR0_PE);
1111	#else
1112	/* We support protected mode without paging using identity mapping. */
1113	mask &= ~X86_CR0_PG;
1114	#endif
1115	if ((pCtx->cr0 & mask) != mask)
1116	return false;
1117
1118	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
1119	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
1120	if ((pCtx->cr0 & mask) != 0)
1121	return false;
1122
1123	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
1124	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1125	mask &= ~X86_CR4_VMXE;
1126	if ((pCtx->cr4 & mask) != mask)
1127	return false;
1128
1129	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
1130	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
1131	if ((pCtx->cr4 & mask) != 0)
1132	return false;
1133
1134	pVM->hwaccm.s.fActive = true;
1135	return true;
1136	}
1137
1138	return false;
1139	}
1140
1141	/**
1142	* Checks if we are currently using hardware accelerated raw mode.
1143	*
1144	* @returns boolean
1145	* @param pVM The VM to operate on.
1146	*/
1147	VMMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
1148	{
1149	return pVM->hwaccm.s.fActive;
1150	}
1151
1152	/**
1153	* Checks if we are currently using nested paging.
1154	*
1155	* @returns boolean
1156	* @param pVM The VM to operate on.
1157	*/
1158	VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
1159	{
1160	return pVM->hwaccm.s.fNestedPaging;
1161	}
1162
1163	/**
1164	* Checks if we are currently using VPID in VT-x mode.
1165	*
1166	* @returns boolean
1167	* @param pVM The VM to operate on.
1168	*/
1169	VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
1170	{
1171	return pVM->hwaccm.s.vmx.fVPID;
1172	}
1173
1174
1175	/**
1176	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
1177	*
1178	* @returns boolean
1179	* @param pVM The VM to operate on.
1180	*/
1181	VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
1182	{
1183	/* @todo SMP */
1184	return HWACCMIsEnabled(pVM) && pVM->aCpus[0].hwaccm.s.Event.fPending;
1185	}
1186
1187
1188	/**
1189	* Inject an NMI into a running VM
1190	*
1191	* @returns boolean
1192	* @param pVM The VM to operate on.
1193	*/
1194	VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
1195	{
1196	pVM->hwaccm.s.fInjectNMI = true;
1197	return VINF_SUCCESS;
1198	}
1199
1200	/**
1201	* Check fatal VT-x/AMD-V error and produce some meaningful
1202	* log release message.
1203	*
1204	* @param pVM The VM to operate on.
1205	* @param iStatusCode VBox status code
1206	*/
1207	VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
1208	{
1209	for (unsigned i=0;i<pVM->cCPUs;i++)
1210	{
1211	switch(iStatusCode)
1212	{
1213	case VERR_VMX_INVALID_VMCS_FIELD:
1214	break;
1215
1216	case VERR_VMX_INVALID_VMCS_PTR:
1217	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1218	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
1219	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
1220	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
1221	break;
1222
1223	case VERR_VMX_UNABLE_TO_START_VM:
1224	LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1225	LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1226	#if 0 /* @todo dump the current control fields to the release log */
1227	if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
1228	{
1229
1230	}
1231	#endif
1232	break;
1233
1234	case VERR_VMX_UNABLE_TO_RESUME_VM:
1235	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1236	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1237	break;
1238
1239	case VERR_VMX_INVALID_VMXON_PTR:
1240	break;
1241	}
1242	}
1243	}
1244
1245	/**
1246	* Execute state save operation.
1247	*
1248	* @returns VBox status code.
1249	* @param pVM VM Handle.
1250	* @param pSSM SSM operation handle.
1251	*/
1252	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
1253	{
1254	int rc;
1255
1256	Log(("hwaccmR3Save:\n"));
1257
1258	for (unsigned i=0;i<pVM->cCPUs;i++)
1259	{
1260	/*
1261	* Save the basic bits - fortunately all the other things can be resynced on load.
1262	*/
1263	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
1264	AssertRCReturn(rc, rc);
1265	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
1266	AssertRCReturn(rc, rc);
1267	rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
1268	AssertRCReturn(rc, rc);
1269	}
1270
1271	return VINF_SUCCESS;
1272	}
1273
1274	/**
1275	* Execute state load operation.
1276	*
1277	* @returns VBox status code.
1278	* @param pVM VM Handle.
1279	* @param pSSM SSM operation handle.
1280	* @param u32Version Data layout version.
1281	*/
1282	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1283	{
1284	int rc;
1285
1286	Log(("hwaccmR3Load:\n"));
1287
1288	/*
1289	* Validate version.
1290	*/
1291	if (u32Version != HWACCM_SSM_VERSION)
1292	{
1293	AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
1294	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1295	}
1296	for (unsigned i=0;i<pVM->cCPUs;i++)
1297	{
1298	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
1299	AssertRCReturn(rc, rc);
1300	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
1301	AssertRCReturn(rc, rc);
1302	rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
1303	AssertRCReturn(rc, rc);
1304	}
1305	return VINF_SUCCESS;
1306	}
1307
1308
1309
1310

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 15203

Download in other formats: