1 | /* $Id: HWACCM.cpp 15611 2008-12-16 22:28:15Z vboxsync $ */
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2 | /** @file
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3 | * HWACCM - Intel/AMD VM Hardware Support Manager
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2007 Sun Microsystems, Inc.
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | *
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17 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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18 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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19 | * additional information or have any questions.
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20 | */
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21 |
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22 | /*******************************************************************************
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23 | * Header Files *
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24 | *******************************************************************************/
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25 | #define LOG_GROUP LOG_GROUP_HWACCM
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26 | #include <VBox/cpum.h>
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27 | #include <VBox/stam.h>
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28 | #include <VBox/mm.h>
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29 | #include <VBox/pdm.h>
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30 | #include <VBox/pgm.h>
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31 | #include <VBox/trpm.h>
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32 | #include <VBox/dbgf.h>
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33 | #include <VBox/patm.h>
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34 | #include <VBox/csam.h>
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35 | #include <VBox/selm.h>
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36 | #include <VBox/rem.h>
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37 | #include <VBox/hwacc_vmx.h>
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38 | #include <VBox/hwacc_svm.h>
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39 | #include "HWACCMInternal.h"
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40 | #include <VBox/vm.h>
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41 | #include <VBox/err.h>
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42 | #include <VBox/param.h>
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43 |
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44 | #include <iprt/assert.h>
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45 | #include <VBox/log.h>
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46 | #include <iprt/asm.h>
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47 | #include <iprt/string.h>
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48 | #include <iprt/thread.h>
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49 |
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50 | /*******************************************************************************
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51 | * Global Variables *
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52 | *******************************************************************************/
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53 | #ifdef VBOX_WITH_STATISTICS
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54 | # define EXIT_REASON(def, val, str) #def " - " #val " - " str
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55 | # define EXIT_REASON_NIL() NULL
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56 | /** Exit reason descriptions for VT-x, used to describe statistics. */
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57 | static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
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58 | {
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59 | EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
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60 | EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
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61 | EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
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62 | EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
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63 | EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
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64 | EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
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65 | EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
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66 | EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
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67 | EXIT_REASON_NIL(),
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68 | EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
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69 | EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
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70 | EXIT_REASON_NIL(),
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71 | EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
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72 | EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
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73 | EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
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74 | EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
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75 | EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
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76 | EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
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77 | EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
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78 | EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
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79 | EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
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80 | EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
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81 | EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
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82 | EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
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83 | EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
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84 | EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
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85 | EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
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86 | EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
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87 | EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
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88 | EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
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89 | EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
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90 | EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
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91 | EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
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92 | EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
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93 | EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
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94 | EXIT_REASON_NIL(),
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95 | EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
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96 | EXIT_REASON_NIL(),
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97 | EXIT_REASON_NIL(),
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98 | EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
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99 | EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
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100 | EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
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101 | EXIT_REASON_NIL(),
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102 | EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
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103 | EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
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104 | EXIT_REASON_NIL(),
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105 | EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
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106 | EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
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107 | EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
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108 | EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
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109 | EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
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110 | EXIT_REASON_NIL(),
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111 | EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
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112 | EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
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113 | EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
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114 | EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
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115 | EXIT_REASON_NIL()
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116 | };
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117 | /** Exit reason descriptions for AMD-V, used to describe statistics. */
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118 | static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
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119 | {
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120 | /** @todo fill in these. */
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121 | EXIT_REASON_NIL()
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122 | };
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123 | # undef EXIT_REASON
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124 | # undef EXIT_REASON_NIL
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125 | #endif /* VBOX_WITH_STATISTICS */
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126 |
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127 | /*******************************************************************************
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128 | * Internal Functions *
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129 | *******************************************************************************/
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130 | static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
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131 | static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
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132 |
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133 |
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134 | /**
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135 | * Initializes the HWACCM.
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136 | *
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137 | * @returns VBox status code.
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138 | * @param pVM The VM to operate on.
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139 | */
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140 | VMMR3DECL(int) HWACCMR3Init(PVM pVM)
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141 | {
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142 | LogFlow(("HWACCMR3Init\n"));
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143 |
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144 | /*
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145 | * Assert alignment and sizes.
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146 | */
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147 | AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
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148 | AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
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149 |
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150 | /* Some structure checks. */
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151 | AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
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152 | AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
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153 | AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
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154 | AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
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155 |
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156 | AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
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157 | AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
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158 | AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
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159 | AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
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160 | AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
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161 | AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
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162 | AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
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163 |
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164 |
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165 | /*
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166 | * Register the saved state data unit.
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167 | */
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168 | int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
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169 | NULL, hwaccmR3Save, NULL,
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170 | NULL, hwaccmR3Load, NULL);
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171 | if (RT_FAILURE(rc))
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172 | return rc;
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173 |
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174 | /* Misc initialisation. */
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175 | pVM->hwaccm.s.vmx.fSupported = false;
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176 | pVM->hwaccm.s.svm.fSupported = false;
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177 | pVM->hwaccm.s.vmx.fEnabled = false;
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178 | pVM->hwaccm.s.svm.fEnabled = false;
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179 |
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180 | pVM->hwaccm.s.fActive = false;
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181 | pVM->hwaccm.s.fNestedPaging = false;
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182 |
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183 | /* Disabled by default. */
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184 | pVM->fHWACCMEnabled = false;
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185 |
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186 | /*
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187 | * Check CFGM options.
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188 | */
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189 | PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
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190 | PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
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191 | /* Nested paging: disabled by default. */
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192 | rc = CFGMR3QueryBoolDef(pRoot, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
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193 | AssertRC(rc);
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194 |
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195 | /* VT-x VPID: disabled by default. */
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196 | rc = CFGMR3QueryBoolDef(pRoot, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
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197 | AssertRC(rc);
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198 |
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199 | /* HWACCM support must be explicitely enabled in the configuration file. */
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200 | rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
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201 | AssertRC(rc);
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202 |
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203 | #ifdef RT_OS_DARWIN
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204 | if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
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205 | #else
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206 | if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
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207 | #endif
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208 | {
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209 | AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
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210 | VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
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211 | return VERR_HWACCM_CONFIG_MISMATCH;
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212 | }
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213 |
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214 | if (VMMIsHwVirtExtForced(pVM))
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215 | pVM->fHWACCMEnabled = true;
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216 |
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217 | #if HC_ARCH_BITS == 32
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218 | /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
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219 | * (To use the default, don't set 64bitEnabled in CFGM.) */
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220 | rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
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221 | AssertLogRelRCReturn(rc, rc);
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222 | if (pVM->hwaccm.s.fAllow64BitGuests)
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223 | {
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224 | # ifdef RT_OS_DARWIN
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225 | if (!VMMIsHwVirtExtForced(pVM))
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226 | # else
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227 | if (!pVM->hwaccm.s.fAllowed)
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228 | # endif
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229 | return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling VT-x.");
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230 | }
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231 | #else
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232 | /* We always allow 64 bits guests on 64 bits hosts. */
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233 | pVM->hwaccm.s.fAllow64BitGuests = true;
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234 | #endif
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235 |
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236 | return VINF_SUCCESS;
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237 | }
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238 |
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239 | /**
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240 | * Initializes the per-VCPU HWACCM.
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241 | *
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242 | * @returns VBox status code.
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243 | * @param pVM The VM to operate on.
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244 | */
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245 | VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
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246 | {
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247 | LogFlow(("HWACCMR3InitCPU\n"));
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248 |
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249 | #ifdef VBOX_WITH_STATISTICS
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250 | /*
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251 | * Statistics.
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252 | */
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253 | for (unsigned i=0;i<pVM->cCPUs;i++)
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254 | {
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255 | PVMCPU pVCpu = &pVM->aCpus[i];
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256 | int rc;
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257 |
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258 | rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
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259 | "/PROF/HWACCM/CPU%d/SwitchToGC", i);
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260 | AssertRC(rc);
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261 | rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
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262 | "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
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263 | AssertRC(rc);
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264 | rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
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265 | "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
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266 | AssertRC(rc);
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267 | # if 1 /* temporary for tracking down darwin holdup. */
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268 | rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
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269 | "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
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270 | AssertRC(rc);
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271 | rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
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272 | "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
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273 | AssertRC(rc);
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274 | rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
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275 | "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
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276 | AssertRC(rc);
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277 | # endif
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278 | rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
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279 | "/PROF/HWACCM/CPU%d/InGC", i);
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280 | AssertRC(rc);
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281 |
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282 | # define HWACCM_REG_COUNTER(a, b) \
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283 | rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
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284 | AssertRC(rc);
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285 |
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286 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
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287 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
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288 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
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289 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
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290 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
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291 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
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292 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
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293 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
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294 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
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295 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
|
---|
296 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
|
---|
297 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
|
---|
298 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
|
---|
299 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
|
---|
300 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
|
---|
301 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
|
---|
302 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
|
---|
303 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
|
---|
304 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
|
---|
305 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
|
---|
306 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
|
---|
307 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
|
---|
308 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
|
---|
309 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
|
---|
310 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
|
---|
311 |
|
---|
312 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
|
---|
313 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
|
---|
314 |
|
---|
315 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
|
---|
316 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
|
---|
317 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
|
---|
318 |
|
---|
319 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
|
---|
320 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
|
---|
321 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
|
---|
322 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
|
---|
323 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
|
---|
324 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
|
---|
325 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
|
---|
326 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
|
---|
327 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
|
---|
328 |
|
---|
329 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
|
---|
330 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
|
---|
331 |
|
---|
332 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
|
---|
333 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
|
---|
334 | HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
|
---|
335 |
|
---|
336 | for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
|
---|
337 | {
|
---|
338 | rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
|
---|
339 | "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
|
---|
340 | AssertRC(rc);
|
---|
341 | rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
|
---|
342 | "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
|
---|
343 | AssertRC(rc);
|
---|
344 | }
|
---|
345 |
|
---|
346 | #undef HWACCM_REG_COUNTER
|
---|
347 |
|
---|
348 | pVCpu->hwaccm.s.paStatExitReason = NULL;
|
---|
349 |
|
---|
350 | rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
|
---|
351 | AssertRC(rc);
|
---|
352 | if (RT_SUCCESS(rc))
|
---|
353 | {
|
---|
354 | const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
|
---|
355 | for (int j=0;j<MAX_EXITREASON_STAT;j++)
|
---|
356 | {
|
---|
357 | rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
|
---|
358 | papszDesc[j] ? papszDesc[j] : "Exit reason",
|
---|
359 | "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
|
---|
360 | AssertRC(rc);
|
---|
361 | }
|
---|
362 | rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
|
---|
363 | AssertRC(rc);
|
---|
364 | }
|
---|
365 | pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
|
---|
366 | # ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
|
---|
367 | Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
|
---|
368 | # else
|
---|
369 | Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
|
---|
370 | # endif
|
---|
371 | }
|
---|
372 | #endif /* VBOX_WITH_STATISTICS */
|
---|
373 | return VINF_SUCCESS;
|
---|
374 | }
|
---|
375 |
|
---|
376 | /**
|
---|
377 | * Turns off normal raw mode features
|
---|
378 | *
|
---|
379 | * @param pVM The VM to operate on.
|
---|
380 | */
|
---|
381 | static void hwaccmR3DisableRawMode(PVM pVM)
|
---|
382 | {
|
---|
383 | /* Disable PATM & CSAM. */
|
---|
384 | PATMR3AllowPatching(pVM, false);
|
---|
385 | CSAMDisableScanning(pVM);
|
---|
386 |
|
---|
387 | /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
|
---|
388 | SELMR3DisableMonitoring(pVM);
|
---|
389 | TRPMR3DisableMonitoring(pVM);
|
---|
390 |
|
---|
391 | /* The hidden selector registers are now valid. */
|
---|
392 | CPUMSetHiddenSelRegsValid(pVM, true);
|
---|
393 |
|
---|
394 | /* Disable the switcher code (safety precaution). */
|
---|
395 | VMMR3DisableSwitcher(pVM);
|
---|
396 |
|
---|
397 | /* Disable mapping of the hypervisor into the shadow page table. */
|
---|
398 | PGMR3ChangeShwPDMappings(pVM, false);
|
---|
399 |
|
---|
400 | /* Disable the switcher */
|
---|
401 | VMMR3DisableSwitcher(pVM);
|
---|
402 |
|
---|
403 | if (pVM->hwaccm.s.fNestedPaging)
|
---|
404 | {
|
---|
405 | /* Reinit the paging mode to force the new shadow mode. */
|
---|
406 | PGMR3ChangeMode(pVM, PGMMODE_REAL);
|
---|
407 | }
|
---|
408 | }
|
---|
409 |
|
---|
410 | /**
|
---|
411 | * Initialize VT-x or AMD-V.
|
---|
412 | *
|
---|
413 | * @returns VBox status code.
|
---|
414 | * @param pVM The VM handle.
|
---|
415 | */
|
---|
416 | VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
|
---|
417 | {
|
---|
418 | int rc;
|
---|
419 |
|
---|
420 | if ( !pVM->hwaccm.s.vmx.fSupported
|
---|
421 | && !pVM->hwaccm.s.svm.fSupported)
|
---|
422 | {
|
---|
423 | LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
|
---|
424 | LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
|
---|
425 | #ifdef RT_OS_DARWIN
|
---|
426 | if (VMMIsHwVirtExtForced(pVM))
|
---|
427 | return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
|
---|
428 | #endif
|
---|
429 | return VINF_SUCCESS;
|
---|
430 | }
|
---|
431 |
|
---|
432 | /*
|
---|
433 | * Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
|
---|
434 | * because it turns off paging, which is not allowed in VMX root mode.
|
---|
435 | *
|
---|
436 | * To simplify matters we'll just force all running VMs to either use raw or VT-x mode. No mixing allowed in the VT-x case.
|
---|
437 | * There's no such problem with AMD-V. (@todo)
|
---|
438 | *
|
---|
439 | */
|
---|
440 | /* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
|
---|
441 | rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
|
---|
442 | if (RT_FAILURE(rc))
|
---|
443 | {
|
---|
444 | LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
|
---|
445 | LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
|
---|
446 |
|
---|
447 | #ifdef RT_OS_DARWIN
|
---|
448 | /*
|
---|
449 | * This is 100% fatal if we didn't prepare for a HwVirtExt setup because of
|
---|
450 | * missing ring-0 allocations. For VMs that require HwVirtExt it doesn't normally
|
---|
451 | * make sense to try run them in software mode, so fail that too.
|
---|
452 | */
|
---|
453 | if (VMMIsHwVirtExtForced(pVM))
|
---|
454 | VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to "
|
---|
455 | "simultaneously use VT-x.");
|
---|
456 | else
|
---|
457 | VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not "
|
---|
458 | "allowed to simultaneously use software virtualization.");
|
---|
459 | return rc;
|
---|
460 |
|
---|
461 | #else /* !RT_OS_DARWIN */
|
---|
462 |
|
---|
463 | /* Invert the selection */
|
---|
464 | pVM->hwaccm.s.fAllowed ^= 1;
|
---|
465 | if (pVM->hwaccm.s.fAllowed)
|
---|
466 | {
|
---|
467 | if (pVM->hwaccm.s.vmx.fSupported)
|
---|
468 | VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not allowed "
|
---|
469 | "to simultaneously use software virtualization.\n");
|
---|
470 | else
|
---|
471 | VM_SET_ERROR(pVM, rc, "An active VM already uses AMD-V hardware acceleration. It is not allowed to "
|
---|
472 | "simultaneously use software virtualization.\n");
|
---|
473 | }
|
---|
474 | else
|
---|
475 | VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to simultaneously "
|
---|
476 | "use VT-x or AMD-V.\n");
|
---|
477 | return rc;
|
---|
478 | #endif /* !RT_OS_DARWIN */
|
---|
479 | }
|
---|
480 |
|
---|
481 | if (pVM->hwaccm.s.fAllowed == false)
|
---|
482 | return VINF_SUCCESS; /* disabled */
|
---|
483 |
|
---|
484 | Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
|
---|
485 |
|
---|
486 | if (pVM->hwaccm.s.vmx.fSupported)
|
---|
487 | {
|
---|
488 | Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
|
---|
489 |
|
---|
490 | if ( pVM->hwaccm.s.fInitialized == false
|
---|
491 | && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
|
---|
492 | {
|
---|
493 | uint64_t val;
|
---|
494 | RTGCPHYS GCPhys = 0;
|
---|
495 |
|
---|
496 | LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
|
---|
497 | LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
|
---|
498 | LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
|
---|
499 | LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
|
---|
500 | LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
|
---|
501 | LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
|
---|
502 | LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
|
---|
503 | LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
|
---|
504 |
|
---|
505 | LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
|
---|
506 | val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
|
---|
507 | if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
|
---|
508 | LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
|
---|
509 | if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
|
---|
510 | LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
|
---|
511 | val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
|
---|
512 | if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
|
---|
513 | LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
|
---|
514 | if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
|
---|
515 | LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
|
---|
516 |
|
---|
517 | LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
|
---|
518 | val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
|
---|
519 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
|
---|
520 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
|
---|
521 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
|
---|
522 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
|
---|
523 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
|
---|
524 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
|
---|
525 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
|
---|
526 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
|
---|
527 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
|
---|
528 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
|
---|
529 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
|
---|
530 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
|
---|
531 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
|
---|
532 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
|
---|
533 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
|
---|
534 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
|
---|
535 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
|
---|
536 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
|
---|
537 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
|
---|
538 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
|
---|
539 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
|
---|
540 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
|
---|
541 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
|
---|
542 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
|
---|
543 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
|
---|
544 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
|
---|
545 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
|
---|
546 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
|
---|
547 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
|
---|
548 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
|
---|
549 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
|
---|
550 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
|
---|
551 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
|
---|
552 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
|
---|
553 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
|
---|
554 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
|
---|
555 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
|
---|
556 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
|
---|
557 | if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
|
---|
558 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
|
---|
559 |
|
---|
560 | val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
|
---|
561 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
|
---|
562 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
|
---|
563 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
|
---|
564 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
|
---|
565 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
|
---|
566 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
|
---|
567 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
|
---|
568 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
|
---|
569 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
|
---|
570 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
|
---|
571 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
|
---|
572 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
|
---|
573 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
|
---|
574 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
|
---|
575 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
|
---|
576 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
|
---|
577 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
|
---|
578 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
|
---|
579 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
|
---|
580 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
|
---|
581 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
|
---|
582 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
|
---|
583 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
|
---|
584 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
|
---|
585 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
|
---|
586 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
|
---|
587 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
|
---|
588 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
|
---|
589 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
|
---|
590 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
|
---|
591 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
|
---|
592 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
|
---|
593 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
|
---|
594 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
|
---|
595 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
|
---|
596 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
|
---|
597 | if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
|
---|
598 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
|
---|
599 | if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
|
---|
600 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
|
---|
601 |
|
---|
602 | if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
|
---|
603 | {
|
---|
604 | LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
|
---|
605 | val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
|
---|
606 | if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
|
---|
607 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
|
---|
608 | if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
|
---|
609 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
|
---|
610 | if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
|
---|
611 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
|
---|
612 | if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
|
---|
613 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
|
---|
614 |
|
---|
615 | val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
|
---|
616 | if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
|
---|
617 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
|
---|
618 | if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
|
---|
619 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
|
---|
620 | if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
|
---|
621 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
|
---|
622 | if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
|
---|
623 | LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
|
---|
624 | }
|
---|
625 |
|
---|
626 | LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
|
---|
627 | val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
|
---|
628 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
|
---|
629 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
|
---|
630 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
|
---|
631 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
|
---|
632 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
|
---|
633 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
|
---|
634 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
|
---|
635 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
|
---|
636 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
|
---|
637 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
|
---|
638 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
|
---|
639 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
|
---|
640 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
|
---|
641 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
|
---|
642 | val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
|
---|
643 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
|
---|
644 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
|
---|
645 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
|
---|
646 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
|
---|
647 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
|
---|
648 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
|
---|
649 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
|
---|
650 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
|
---|
651 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
|
---|
652 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
|
---|
653 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
|
---|
654 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
|
---|
655 | if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
|
---|
656 | LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
|
---|
657 |
|
---|
658 | LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
|
---|
659 | val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
|
---|
660 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
|
---|
661 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
|
---|
662 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
|
---|
663 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
|
---|
664 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
|
---|
665 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
|
---|
666 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
|
---|
667 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
|
---|
668 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
|
---|
669 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
|
---|
670 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
|
---|
671 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
|
---|
672 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
|
---|
673 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
|
---|
674 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
|
---|
675 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
|
---|
676 | val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
|
---|
677 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
|
---|
678 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
|
---|
679 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
|
---|
680 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
|
---|
681 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
|
---|
682 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
|
---|
683 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
|
---|
684 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
|
---|
685 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
|
---|
686 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
|
---|
687 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
|
---|
688 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
|
---|
689 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
|
---|
690 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
|
---|
691 | if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
|
---|
692 | LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
|
---|
693 |
|
---|
694 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
|
---|
695 | {
|
---|
696 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
|
---|
697 |
|
---|
698 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
|
---|
699 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
|
---|
700 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
|
---|
701 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
|
---|
702 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
|
---|
703 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
|
---|
704 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
|
---|
705 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
|
---|
706 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
|
---|
707 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
|
---|
708 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
|
---|
709 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
|
---|
710 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
|
---|
711 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
|
---|
712 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
|
---|
713 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
|
---|
714 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
|
---|
715 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
|
---|
716 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
|
---|
717 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
|
---|
718 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
|
---|
719 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
|
---|
720 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
|
---|
721 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
|
---|
722 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
|
---|
723 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
|
---|
724 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
|
---|
725 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
|
---|
726 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
|
---|
727 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
|
---|
728 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
|
---|
729 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
|
---|
730 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
|
---|
731 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
|
---|
732 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
|
---|
733 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
|
---|
734 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
|
---|
735 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
|
---|
736 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
|
---|
737 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
|
---|
738 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
|
---|
739 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
|
---|
740 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
|
---|
741 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
|
---|
742 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
|
---|
743 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
|
---|
744 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
|
---|
745 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
|
---|
746 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
|
---|
747 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
|
---|
748 | if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
|
---|
749 | LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
|
---|
750 | }
|
---|
751 |
|
---|
752 | LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
|
---|
753 | LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
|
---|
754 | LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
|
---|
755 | LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
|
---|
756 | LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
|
---|
757 |
|
---|
758 | LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
|
---|
759 | LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
|
---|
760 | LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
|
---|
761 | LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
|
---|
762 | LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
|
---|
763 |
|
---|
764 | LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
|
---|
765 | LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
|
---|
766 |
|
---|
767 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
768 | LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
|
---|
769 |
|
---|
770 | #ifdef HWACCM_VTX_WITH_EPT
|
---|
771 | if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
|
---|
772 | pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
|
---|
773 | #endif /* HWACCM_VTX_WITH_EPT */
|
---|
774 | #ifdef HWACCM_VTX_WITH_VPID
|
---|
775 | if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
|
---|
776 | && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
|
---|
777 | pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
|
---|
778 | #endif /* HWACCM_VTX_WITH_VPID */
|
---|
779 |
|
---|
780 | /* Only try once. */
|
---|
781 | pVM->hwaccm.s.fInitialized = true;
|
---|
782 |
|
---|
783 | /* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
|
---|
784 | #if 1
|
---|
785 | rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
|
---|
786 | #else
|
---|
787 | rc = VERR_NO_MEMORY; /* simulation of no VMMDev Heap. */
|
---|
788 | #endif
|
---|
789 | if (RT_SUCCESS(rc))
|
---|
790 | {
|
---|
791 | /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
|
---|
792 | ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
|
---|
793 | pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
|
---|
794 | /* Bit set to 0 means redirection enabled. */
|
---|
795 | memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
|
---|
796 | /* Allow all port IO, so the VT-x IO intercepts do their job. */
|
---|
797 | memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
|
---|
798 | *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
|
---|
799 |
|
---|
800 | /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
|
---|
801 | * real and protected mode without paging with EPT.
|
---|
802 | */
|
---|
803 | pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
|
---|
804 | for (unsigned i=0;i<X86_PG_ENTRIES;i++)
|
---|
805 | {
|
---|
806 | pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
|
---|
807 | pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
|
---|
808 | }
|
---|
809 |
|
---|
810 | /* We convert it here every time as pci regions could be reconfigured. */
|
---|
811 | rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
|
---|
812 | AssertRC(rc);
|
---|
813 | LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
|
---|
814 |
|
---|
815 | rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
|
---|
816 | AssertRC(rc);
|
---|
817 | LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
|
---|
818 | }
|
---|
819 | else
|
---|
820 | {
|
---|
821 | LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
|
---|
822 | pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
|
---|
823 | pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
|
---|
824 | }
|
---|
825 |
|
---|
826 | rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
|
---|
827 | AssertRC(rc);
|
---|
828 | if (rc == VINF_SUCCESS)
|
---|
829 | {
|
---|
830 | pVM->fHWACCMEnabled = true;
|
---|
831 | pVM->hwaccm.s.vmx.fEnabled = true;
|
---|
832 | hwaccmR3DisableRawMode(pVM);
|
---|
833 |
|
---|
834 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
|
---|
835 | #ifdef VBOX_ENABLE_64_BITS_GUESTS
|
---|
836 | if (pVM->hwaccm.s.fAllow64BitGuests)
|
---|
837 | {
|
---|
838 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
|
---|
839 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
|
---|
840 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
|
---|
841 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
|
---|
842 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
|
---|
843 | }
|
---|
844 | #endif
|
---|
845 | LogRel(("HWACCM: VMX enabled!\n"));
|
---|
846 | LogRel((pVM->hwaccm.s.fAllow64BitGuests
|
---|
847 | ? "HWACCM: 32-bit and 64-bit guest supported.\n"
|
---|
848 | : "HWACCM: 32-bit guest supported.\n"));
|
---|
849 | if (pVM->hwaccm.s.fNestedPaging)
|
---|
850 | {
|
---|
851 | LogRel(("HWACCM: Enabled nested paging\n"));
|
---|
852 | LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetEPTCR3(pVM)));
|
---|
853 | }
|
---|
854 | if (pVM->hwaccm.s.vmx.fVPID)
|
---|
855 | LogRel(("HWACCM: Enabled VPID\n"));
|
---|
856 |
|
---|
857 | if ( pVM->hwaccm.s.fNestedPaging
|
---|
858 | || pVM->hwaccm.s.vmx.fVPID)
|
---|
859 | {
|
---|
860 | LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
|
---|
861 | LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
|
---|
862 | }
|
---|
863 | }
|
---|
864 | else
|
---|
865 | {
|
---|
866 | LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
|
---|
867 | LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
|
---|
868 | pVM->fHWACCMEnabled = false;
|
---|
869 | }
|
---|
870 | }
|
---|
871 | }
|
---|
872 | else
|
---|
873 | if (pVM->hwaccm.s.svm.fSupported)
|
---|
874 | {
|
---|
875 | Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
|
---|
876 |
|
---|
877 | if (pVM->hwaccm.s.fInitialized == false)
|
---|
878 | {
|
---|
879 | /* Erratum 170 which requires a forced TLB flush for each world switch:
|
---|
880 | * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
|
---|
881 | *
|
---|
882 | * All BH-G1/2 and DH-G1/2 models include a fix:
|
---|
883 | * Athlon X2: 0x6b 1/2
|
---|
884 | * 0x68 1/2
|
---|
885 | * Athlon 64: 0x7f 1
|
---|
886 | * 0x6f 2
|
---|
887 | * Sempron: 0x7f 1/2
|
---|
888 | * 0x6f 2
|
---|
889 | * 0x6c 2
|
---|
890 | * 0x7c 2
|
---|
891 | * Turion 64: 0x68 2
|
---|
892 | *
|
---|
893 | */
|
---|
894 | uint32_t u32Dummy;
|
---|
895 | uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
|
---|
896 | ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
|
---|
897 | u32BaseFamily= (u32Version >> 8) & 0xf;
|
---|
898 | u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
|
---|
899 | u32Model = ((u32Version >> 4) & 0xf);
|
---|
900 | u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
|
---|
901 | u32Stepping = u32Version & 0xf;
|
---|
902 | if ( u32Family == 0xf
|
---|
903 | && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
|
---|
904 | && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
|
---|
905 | {
|
---|
906 | LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
|
---|
907 | }
|
---|
908 |
|
---|
909 | LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
|
---|
910 | LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
|
---|
911 | LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
|
---|
912 | LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
|
---|
913 | LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
|
---|
914 |
|
---|
915 | if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
|
---|
916 | LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
|
---|
917 | if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
|
---|
918 | LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
|
---|
919 | if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
|
---|
920 | LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
|
---|
921 | if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
|
---|
922 | LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
|
---|
923 | if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
|
---|
924 | LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
|
---|
925 |
|
---|
926 | /* Only try once. */
|
---|
927 | pVM->hwaccm.s.fInitialized = true;
|
---|
928 |
|
---|
929 | if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
|
---|
930 | pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
|
---|
931 |
|
---|
932 | rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
|
---|
933 | AssertRC(rc);
|
---|
934 | if (rc == VINF_SUCCESS)
|
---|
935 | {
|
---|
936 | pVM->fHWACCMEnabled = true;
|
---|
937 | pVM->hwaccm.s.svm.fEnabled = true;
|
---|
938 |
|
---|
939 | if (pVM->hwaccm.s.fNestedPaging)
|
---|
940 | LogRel(("HWACCM: Enabled nested paging\n"));
|
---|
941 |
|
---|
942 | hwaccmR3DisableRawMode(pVM);
|
---|
943 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
|
---|
944 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
|
---|
945 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
|
---|
946 | #ifdef VBOX_ENABLE_64_BITS_GUESTS
|
---|
947 | if (pVM->hwaccm.s.fAllow64BitGuests)
|
---|
948 | {
|
---|
949 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
|
---|
950 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
|
---|
951 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
|
---|
952 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
|
---|
953 | }
|
---|
954 | #endif
|
---|
955 | LogRel((pVM->hwaccm.s.fAllow64BitGuests
|
---|
956 | ? "HWACCM: 32-bit and 64-bit guest supported.\n"
|
---|
957 | : "HWACCM: 32-bit guest supported.\n"));
|
---|
958 | }
|
---|
959 | else
|
---|
960 | {
|
---|
961 | pVM->fHWACCMEnabled = false;
|
---|
962 | }
|
---|
963 | }
|
---|
964 | }
|
---|
965 | return VINF_SUCCESS;
|
---|
966 | }
|
---|
967 |
|
---|
968 | /**
|
---|
969 | * Applies relocations to data and code managed by this
|
---|
970 | * component. This function will be called at init and
|
---|
971 | * whenever the VMM need to relocate it self inside the GC.
|
---|
972 | *
|
---|
973 | * @param pVM The VM.
|
---|
974 | */
|
---|
975 | VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
|
---|
976 | {
|
---|
977 | Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
|
---|
978 |
|
---|
979 | /* Fetch the current paging mode during the relocate callback during state loading. */
|
---|
980 | if (VMR3GetState(pVM) == VMSTATE_LOADING)
|
---|
981 | {
|
---|
982 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
983 | {
|
---|
984 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
985 | /* @todo SMP */
|
---|
986 | pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVM);
|
---|
987 | pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMGetGuestMode(pVM);
|
---|
988 | }
|
---|
989 | }
|
---|
990 | #if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
|
---|
991 | if (pVM->fHWACCMEnabled)
|
---|
992 | {
|
---|
993 | int rc;
|
---|
994 |
|
---|
995 | switch(PGMGetHostMode(pVM))
|
---|
996 | {
|
---|
997 | case PGMMODE_32_BIT:
|
---|
998 | pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
|
---|
999 | break;
|
---|
1000 |
|
---|
1001 | case PGMMODE_PAE:
|
---|
1002 | case PGMMODE_PAE_NX:
|
---|
1003 | pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
|
---|
1004 | break;
|
---|
1005 |
|
---|
1006 | default:
|
---|
1007 | AssertFailed();
|
---|
1008 | break;
|
---|
1009 | }
|
---|
1010 | rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
|
---|
1011 | AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
|
---|
1012 |
|
---|
1013 | rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
|
---|
1014 | AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
|
---|
1015 |
|
---|
1016 | rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
|
---|
1017 | AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
|
---|
1018 |
|
---|
1019 | rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
|
---|
1020 | AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
|
---|
1021 |
|
---|
1022 | # ifdef DEBUG
|
---|
1023 | rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
|
---|
1024 | AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
|
---|
1025 | # endif
|
---|
1026 | }
|
---|
1027 | #endif
|
---|
1028 | return;
|
---|
1029 | }
|
---|
1030 |
|
---|
1031 | /**
|
---|
1032 | * Checks hardware accelerated raw mode is allowed.
|
---|
1033 | *
|
---|
1034 | * @returns boolean
|
---|
1035 | * @param pVM The VM to operate on.
|
---|
1036 | */
|
---|
1037 | VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
|
---|
1038 | {
|
---|
1039 | return pVM->hwaccm.s.fAllowed;
|
---|
1040 | }
|
---|
1041 |
|
---|
1042 | /**
|
---|
1043 | * Notification callback which is called whenever there is a chance that a CR3
|
---|
1044 | * value might have changed.
|
---|
1045 | *
|
---|
1046 | * This is called by PGM.
|
---|
1047 | *
|
---|
1048 | * @param pVM The VM to operate on.
|
---|
1049 | * @param enmShadowMode New shadow paging mode.
|
---|
1050 | * @param enmGuestMode New guest paging mode.
|
---|
1051 | */
|
---|
1052 | VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
|
---|
1053 | {
|
---|
1054 | /* Ignore page mode changes during state loading. */
|
---|
1055 | if (VMR3GetState(pVM) == VMSTATE_LOADING)
|
---|
1056 | return;
|
---|
1057 |
|
---|
1058 | PVMCPU pVCpu = VMMGetCpu(pVM);
|
---|
1059 | pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
|
---|
1060 |
|
---|
1061 | if ( pVM->hwaccm.s.vmx.fEnabled
|
---|
1062 | && pVM->fHWACCMEnabled)
|
---|
1063 | {
|
---|
1064 | if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
|
---|
1065 | && enmGuestMode >= PGMMODE_PROTECTED)
|
---|
1066 | {
|
---|
1067 | PCPUMCTX pCtx;
|
---|
1068 |
|
---|
1069 | pCtx = CPUMQueryGuestCtxPtr(pVM);
|
---|
1070 |
|
---|
1071 | /* After a real mode switch to protected mode we must force
|
---|
1072 | * CPL to 0. Our real mode emulation had to set it to 3.
|
---|
1073 | */
|
---|
1074 | pCtx->ssHid.Attr.n.u2Dpl = 0;
|
---|
1075 | }
|
---|
1076 | }
|
---|
1077 |
|
---|
1078 | if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
|
---|
1079 | {
|
---|
1080 | /* Keep track of paging mode changes. */
|
---|
1081 | pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
|
---|
1082 | pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
|
---|
1083 |
|
---|
1084 | /* Did we miss a change, because all code was executed in the recompiler? */
|
---|
1085 | if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
|
---|
1086 | {
|
---|
1087 | Log(("HWACCMR3PagingModeChanged missed %s->%s transition (last seen %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
|
---|
1088 | pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
|
---|
1089 | }
|
---|
1090 | }
|
---|
1091 |
|
---|
1092 | /* Reset the contents of the read cache. */
|
---|
1093 | PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
|
---|
1094 | for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
|
---|
1095 | pCache->Read.aFieldVal[j] = 0;
|
---|
1096 | }
|
---|
1097 |
|
---|
1098 | /**
|
---|
1099 | * Terminates the HWACCM.
|
---|
1100 | *
|
---|
1101 | * Termination means cleaning up and freeing all resources,
|
---|
1102 | * the VM it self is at this point powered off or suspended.
|
---|
1103 | *
|
---|
1104 | * @returns VBox status code.
|
---|
1105 | * @param pVM The VM to operate on.
|
---|
1106 | */
|
---|
1107 | VMMR3DECL(int) HWACCMR3Term(PVM pVM)
|
---|
1108 | {
|
---|
1109 | if (pVM->hwaccm.s.vmx.pRealModeTSS)
|
---|
1110 | {
|
---|
1111 | PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
|
---|
1112 | pVM->hwaccm.s.vmx.pRealModeTSS = 0;
|
---|
1113 | }
|
---|
1114 | return 0;
|
---|
1115 | }
|
---|
1116 |
|
---|
1117 | /**
|
---|
1118 | * Terminates the per-VCPU HWACCM.
|
---|
1119 | *
|
---|
1120 | * Termination means cleaning up and freeing all resources,
|
---|
1121 | * the VM it self is at this point powered off or suspended.
|
---|
1122 | *
|
---|
1123 | * @returns VBox status code.
|
---|
1124 | * @param pVM The VM to operate on.
|
---|
1125 | */
|
---|
1126 | VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
|
---|
1127 | {
|
---|
1128 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
1129 | {
|
---|
1130 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
1131 |
|
---|
1132 | if (pVCpu->hwaccm.s.paStatExitReason)
|
---|
1133 | {
|
---|
1134 | MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
|
---|
1135 | pVCpu->hwaccm.s.paStatExitReason = NULL;
|
---|
1136 | pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
|
---|
1137 | }
|
---|
1138 | }
|
---|
1139 | return 0;
|
---|
1140 | }
|
---|
1141 |
|
---|
1142 | /**
|
---|
1143 | * The VM is being reset.
|
---|
1144 | *
|
---|
1145 | * For the HWACCM component this means that any GDT/LDT/TSS monitors
|
---|
1146 | * needs to be removed.
|
---|
1147 | *
|
---|
1148 | * @param pVM VM handle.
|
---|
1149 | */
|
---|
1150 | VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
|
---|
1151 | {
|
---|
1152 | LogFlow(("HWACCMR3Reset:\n"));
|
---|
1153 |
|
---|
1154 | if (pVM->fHWACCMEnabled)
|
---|
1155 | hwaccmR3DisableRawMode(pVM);
|
---|
1156 |
|
---|
1157 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
1158 | {
|
---|
1159 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
1160 |
|
---|
1161 | /* On first entry we'll sync everything. */
|
---|
1162 | pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
|
---|
1163 |
|
---|
1164 | pVCpu->hwaccm.s.vmx.cr0_mask = 0;
|
---|
1165 | pVCpu->hwaccm.s.vmx.cr4_mask = 0;
|
---|
1166 |
|
---|
1167 | pVCpu->hwaccm.s.Event.fPending = false;
|
---|
1168 |
|
---|
1169 | /* Reset state information for real-mode emulation in VT-x. */
|
---|
1170 | pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
|
---|
1171 | pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
|
---|
1172 | pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
|
---|
1173 |
|
---|
1174 | /* Reset the contents of the read cache. */
|
---|
1175 | PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
|
---|
1176 | for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
|
---|
1177 | pCache->Read.aFieldVal[j] = 0;
|
---|
1178 |
|
---|
1179 | /* Magic marker for searching in crash dumps. */
|
---|
1180 | strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
|
---|
1181 |
|
---|
1182 | }
|
---|
1183 | }
|
---|
1184 |
|
---|
1185 | /**
|
---|
1186 | * Checks if we can currently use hardware accelerated raw mode.
|
---|
1187 | *
|
---|
1188 | * @returns boolean
|
---|
1189 | * @param pVM The VM to operate on.
|
---|
1190 | * @param pCtx Partial VM execution context
|
---|
1191 | */
|
---|
1192 | VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
|
---|
1193 | {
|
---|
1194 | Assert(pVM->fHWACCMEnabled);
|
---|
1195 |
|
---|
1196 | /* AMD SVM supports real & protected mode with or without paging. */
|
---|
1197 | if (pVM->hwaccm.s.svm.fEnabled)
|
---|
1198 | {
|
---|
1199 | pVM->hwaccm.s.fActive = true;
|
---|
1200 | return true;
|
---|
1201 | }
|
---|
1202 |
|
---|
1203 | pVM->hwaccm.s.fActive = false;
|
---|
1204 |
|
---|
1205 | /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
|
---|
1206 | #ifdef HWACCM_VMX_EMULATE_REALMODE
|
---|
1207 | if (pVM->hwaccm.s.vmx.pRealModeTSS)
|
---|
1208 | {
|
---|
1209 | if (CPUMIsGuestInRealModeEx(pCtx))
|
---|
1210 | {
|
---|
1211 | /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
|
---|
1212 | * The base must also be equal to (sel << 4).
|
---|
1213 | */
|
---|
1214 | if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
|
---|
1215 | && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
|
---|
1216 | || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
|
---|
1217 | || pCtx->es != (pCtx->esHid.u64Base >> 4)
|
---|
1218 | || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
|
---|
1219 | || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
|
---|
1220 | || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
|
---|
1221 | {
|
---|
1222 | return false;
|
---|
1223 | }
|
---|
1224 | }
|
---|
1225 | else
|
---|
1226 | {
|
---|
1227 | PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
|
---|
1228 | /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
|
---|
1229 | * from real to protected mode. (all sorts of RPL & DPL assumptions)
|
---|
1230 | */
|
---|
1231 | PVMCPU pVCpu = VMMGetCpu(pVM);
|
---|
1232 |
|
---|
1233 | if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
|
---|
1234 | && enmGuestMode >= PGMMODE_PROTECTED)
|
---|
1235 | {
|
---|
1236 | if ( (pCtx->cs & X86_SEL_RPL)
|
---|
1237 | || (pCtx->ds & X86_SEL_RPL)
|
---|
1238 | || (pCtx->es & X86_SEL_RPL)
|
---|
1239 | || (pCtx->fs & X86_SEL_RPL)
|
---|
1240 | || (pCtx->gs & X86_SEL_RPL)
|
---|
1241 | || (pCtx->ss & X86_SEL_RPL))
|
---|
1242 | {
|
---|
1243 | return false;
|
---|
1244 | }
|
---|
1245 | }
|
---|
1246 | }
|
---|
1247 | }
|
---|
1248 | else
|
---|
1249 | #endif /* HWACCM_VMX_EMULATE_REALMODE */
|
---|
1250 | {
|
---|
1251 | if (!CPUMIsGuestInLongModeEx(pCtx))
|
---|
1252 | {
|
---|
1253 | /** @todo This should (probably) be set on every excursion to the REM,
|
---|
1254 | * however it's too risky right now. So, only apply it when we go
|
---|
1255 | * back to REM for real mode execution. (The XP hack below doesn't
|
---|
1256 | * work reliably without this.)
|
---|
1257 | * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
|
---|
1258 | pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
|
---|
1259 |
|
---|
1260 | /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
|
---|
1261 | if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
|
---|
1262 | return false;
|
---|
1263 |
|
---|
1264 | /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
|
---|
1265 | /* Windows XP; switch to protected mode; all selectors are marked not present in the
|
---|
1266 | * hidden registers (possible recompiler bug; see load_seg_vm) */
|
---|
1267 | if (pCtx->csHid.Attr.n.u1Present == 0)
|
---|
1268 | return false;
|
---|
1269 | if (pCtx->ssHid.Attr.n.u1Present == 0)
|
---|
1270 | return false;
|
---|
1271 |
|
---|
1272 | /* Windows XP: possible same as above, but new recompiler requires new heuristics?
|
---|
1273 | VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
|
---|
1274 | if (pCtx->rsp >= pCtx->ssHid.u32Limit)
|
---|
1275 | return false;
|
---|
1276 | #if 0
|
---|
1277 | if ( pCtx->cs >= pCtx->gdtr.cbGdt
|
---|
1278 | || pCtx->ss >= pCtx->gdtr.cbGdt
|
---|
1279 | || pCtx->ds >= pCtx->gdtr.cbGdt
|
---|
1280 | || pCtx->es >= pCtx->gdtr.cbGdt
|
---|
1281 | || pCtx->fs >= pCtx->gdtr.cbGdt
|
---|
1282 | || pCtx->gs >= pCtx->gdtr.cbGdt)
|
---|
1283 | return false;
|
---|
1284 | #endif
|
---|
1285 | }
|
---|
1286 | }
|
---|
1287 |
|
---|
1288 | if (pVM->hwaccm.s.vmx.fEnabled)
|
---|
1289 | {
|
---|
1290 | uint32_t mask;
|
---|
1291 |
|
---|
1292 | /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
|
---|
1293 | mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
|
---|
1294 | /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
|
---|
1295 | mask &= ~X86_CR0_NE;
|
---|
1296 |
|
---|
1297 | #ifdef HWACCM_VMX_EMULATE_REALMODE
|
---|
1298 | if (pVM->hwaccm.s.vmx.pRealModeTSS)
|
---|
1299 | {
|
---|
1300 | /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
|
---|
1301 | mask &= ~(X86_CR0_PG|X86_CR0_PE);
|
---|
1302 | }
|
---|
1303 | else
|
---|
1304 | #endif
|
---|
1305 | {
|
---|
1306 | /* We support protected mode without paging using identity mapping. */
|
---|
1307 | mask &= ~X86_CR0_PG;
|
---|
1308 | }
|
---|
1309 | if ((pCtx->cr0 & mask) != mask)
|
---|
1310 | return false;
|
---|
1311 |
|
---|
1312 | /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
|
---|
1313 | mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
|
---|
1314 | if ((pCtx->cr0 & mask) != 0)
|
---|
1315 | return false;
|
---|
1316 |
|
---|
1317 | /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
|
---|
1318 | mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
|
---|
1319 | mask &= ~X86_CR4_VMXE;
|
---|
1320 | if ((pCtx->cr4 & mask) != mask)
|
---|
1321 | return false;
|
---|
1322 |
|
---|
1323 | /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
|
---|
1324 | mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
|
---|
1325 | if ((pCtx->cr4 & mask) != 0)
|
---|
1326 | return false;
|
---|
1327 |
|
---|
1328 | pVM->hwaccm.s.fActive = true;
|
---|
1329 | return true;
|
---|
1330 | }
|
---|
1331 |
|
---|
1332 | return false;
|
---|
1333 | }
|
---|
1334 |
|
---|
1335 | /**
|
---|
1336 | * Notifcation from EM about a rescheduling into hardware assisted execution
|
---|
1337 | * mode.
|
---|
1338 | *
|
---|
1339 | * @param pVCpu Pointer to the current virtual cpu structure.
|
---|
1340 | */
|
---|
1341 | VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
|
---|
1342 | {
|
---|
1343 | pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
|
---|
1344 | }
|
---|
1345 |
|
---|
1346 | /**
|
---|
1347 | * Notifcation from EM about returning from instruction emulation (REM / EM).
|
---|
1348 | *
|
---|
1349 | * @param pVCpu Pointer to the current virtual cpu structure.
|
---|
1350 | */
|
---|
1351 | VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
|
---|
1352 | {
|
---|
1353 | pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
|
---|
1354 | }
|
---|
1355 |
|
---|
1356 | /**
|
---|
1357 | * Checks if we are currently using hardware accelerated raw mode.
|
---|
1358 | *
|
---|
1359 | * @returns boolean
|
---|
1360 | * @param pVM The VM to operate on.
|
---|
1361 | */
|
---|
1362 | VMMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
|
---|
1363 | {
|
---|
1364 | return pVM->hwaccm.s.fActive;
|
---|
1365 | }
|
---|
1366 |
|
---|
1367 | /**
|
---|
1368 | * Checks if we are currently using nested paging.
|
---|
1369 | *
|
---|
1370 | * @returns boolean
|
---|
1371 | * @param pVM The VM to operate on.
|
---|
1372 | */
|
---|
1373 | VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
|
---|
1374 | {
|
---|
1375 | return pVM->hwaccm.s.fNestedPaging;
|
---|
1376 | }
|
---|
1377 |
|
---|
1378 | /**
|
---|
1379 | * Checks if we are currently using VPID in VT-x mode.
|
---|
1380 | *
|
---|
1381 | * @returns boolean
|
---|
1382 | * @param pVM The VM to operate on.
|
---|
1383 | */
|
---|
1384 | VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
|
---|
1385 | {
|
---|
1386 | return pVM->hwaccm.s.vmx.fVPID;
|
---|
1387 | }
|
---|
1388 |
|
---|
1389 |
|
---|
1390 | /**
|
---|
1391 | * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
|
---|
1392 | *
|
---|
1393 | * @returns boolean
|
---|
1394 | * @param pVM The VM to operate on.
|
---|
1395 | */
|
---|
1396 | VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
|
---|
1397 | {
|
---|
1398 | /* @todo SMP */
|
---|
1399 | return HWACCMIsEnabled(pVM) && pVM->aCpus[0].hwaccm.s.Event.fPending;
|
---|
1400 | }
|
---|
1401 |
|
---|
1402 |
|
---|
1403 | /**
|
---|
1404 | * Inject an NMI into a running VM
|
---|
1405 | *
|
---|
1406 | * @returns boolean
|
---|
1407 | * @param pVM The VM to operate on.
|
---|
1408 | */
|
---|
1409 | VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
|
---|
1410 | {
|
---|
1411 | pVM->hwaccm.s.fInjectNMI = true;
|
---|
1412 | return VINF_SUCCESS;
|
---|
1413 | }
|
---|
1414 |
|
---|
1415 | /**
|
---|
1416 | * Check fatal VT-x/AMD-V error and produce some meaningful
|
---|
1417 | * log release message.
|
---|
1418 | *
|
---|
1419 | * @param pVM The VM to operate on.
|
---|
1420 | * @param iStatusCode VBox status code
|
---|
1421 | */
|
---|
1422 | VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
|
---|
1423 | {
|
---|
1424 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
1425 | {
|
---|
1426 | switch(iStatusCode)
|
---|
1427 | {
|
---|
1428 | case VERR_VMX_INVALID_VMCS_FIELD:
|
---|
1429 | break;
|
---|
1430 |
|
---|
1431 | case VERR_VMX_INVALID_VMCS_PTR:
|
---|
1432 | LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
|
---|
1433 | LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
|
---|
1434 | LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
|
---|
1435 | LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
|
---|
1436 | break;
|
---|
1437 |
|
---|
1438 | case VERR_VMX_UNABLE_TO_START_VM:
|
---|
1439 | LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
|
---|
1440 | LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
|
---|
1441 | #if 0 /* @todo dump the current control fields to the release log */
|
---|
1442 | if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
|
---|
1443 | {
|
---|
1444 |
|
---|
1445 | }
|
---|
1446 | #endif
|
---|
1447 | break;
|
---|
1448 |
|
---|
1449 | case VERR_VMX_UNABLE_TO_RESUME_VM:
|
---|
1450 | LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
|
---|
1451 | LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
|
---|
1452 | break;
|
---|
1453 |
|
---|
1454 | case VERR_VMX_INVALID_VMXON_PTR:
|
---|
1455 | break;
|
---|
1456 | }
|
---|
1457 | }
|
---|
1458 | }
|
---|
1459 |
|
---|
1460 | /**
|
---|
1461 | * Execute state save operation.
|
---|
1462 | *
|
---|
1463 | * @returns VBox status code.
|
---|
1464 | * @param pVM VM Handle.
|
---|
1465 | * @param pSSM SSM operation handle.
|
---|
1466 | */
|
---|
1467 | static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
|
---|
1468 | {
|
---|
1469 | int rc;
|
---|
1470 |
|
---|
1471 | Log(("hwaccmR3Save:\n"));
|
---|
1472 |
|
---|
1473 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
1474 | {
|
---|
1475 | /*
|
---|
1476 | * Save the basic bits - fortunately all the other things can be resynced on load.
|
---|
1477 | */
|
---|
1478 | rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
|
---|
1479 | AssertRCReturn(rc, rc);
|
---|
1480 | rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
|
---|
1481 | AssertRCReturn(rc, rc);
|
---|
1482 | rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
|
---|
1483 | AssertRCReturn(rc, rc);
|
---|
1484 |
|
---|
1485 | rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
|
---|
1486 | AssertRCReturn(rc, rc);
|
---|
1487 | rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
|
---|
1488 | AssertRCReturn(rc, rc);
|
---|
1489 | rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
|
---|
1490 | AssertRCReturn(rc, rc);
|
---|
1491 | }
|
---|
1492 |
|
---|
1493 | return VINF_SUCCESS;
|
---|
1494 | }
|
---|
1495 |
|
---|
1496 | /**
|
---|
1497 | * Execute state load operation.
|
---|
1498 | *
|
---|
1499 | * @returns VBox status code.
|
---|
1500 | * @param pVM VM Handle.
|
---|
1501 | * @param pSSM SSM operation handle.
|
---|
1502 | * @param u32Version Data layout version.
|
---|
1503 | */
|
---|
1504 | static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
|
---|
1505 | {
|
---|
1506 | int rc;
|
---|
1507 |
|
---|
1508 | Log(("hwaccmR3Load:\n"));
|
---|
1509 |
|
---|
1510 | /*
|
---|
1511 | * Validate version.
|
---|
1512 | */
|
---|
1513 | if ( u32Version != HWACCM_SSM_VERSION
|
---|
1514 | && u32Version != HWACCM_SSM_VERSION_2_0_X)
|
---|
1515 | {
|
---|
1516 | AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
|
---|
1517 | return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
|
---|
1518 | }
|
---|
1519 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
1520 | {
|
---|
1521 | rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
|
---|
1522 | AssertRCReturn(rc, rc);
|
---|
1523 | rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
|
---|
1524 | AssertRCReturn(rc, rc);
|
---|
1525 | rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
|
---|
1526 | AssertRCReturn(rc, rc);
|
---|
1527 |
|
---|
1528 | if (u32Version >= HWACCM_SSM_VERSION)
|
---|
1529 | {
|
---|
1530 | uint32_t val;
|
---|
1531 |
|
---|
1532 | rc = SSMR3GetU32(pSSM, &val);
|
---|
1533 | AssertRCReturn(rc, rc);
|
---|
1534 | pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
|
---|
1535 |
|
---|
1536 | rc = SSMR3GetU32(pSSM, &val);
|
---|
1537 | AssertRCReturn(rc, rc);
|
---|
1538 | pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
|
---|
1539 |
|
---|
1540 | rc = SSMR3GetU32(pSSM, &val);
|
---|
1541 | AssertRCReturn(rc, rc);
|
---|
1542 | pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
|
---|
1543 | }
|
---|
1544 | }
|
---|
1545 | return VINF_SUCCESS;
|
---|
1546 | }
|
---|
1547 |
|
---|