HWACCM.cpp@ 15803

Last change on this file since 15803 was 15803, checked in by vboxsync, 16 years ago
Insert the magic marker during init
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 78.2 KB

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1	/* $Id: HWACCM.cpp 15803 2009-01-05 13:27:11Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_HWACCM
26	#include <VBox/cpum.h>
27	#include <VBox/stam.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/trpm.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/patm.h>
34	#include <VBox/csam.h>
35	#include <VBox/selm.h>
36	#include <VBox/rem.h>
37	#include <VBox/hwacc_vmx.h>
38	#include <VBox/hwacc_svm.h>
39	#include "HWACCMInternal.h"
40	#include <VBox/vm.h>
41	#include <VBox/err.h>
42	#include <VBox/param.h>
43
44	#include <iprt/assert.h>
45	#include <VBox/log.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48	#include <iprt/thread.h>
49
50	/*******************************************************************************
51	* Global Variables *
52	*******************************************************************************/
53	#ifdef VBOX_WITH_STATISTICS
54	# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55	# define EXIT_REASON_NIL() NULL
56	/** Exit reason descriptions for VT-x, used to describe statistics. */
57	static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58	{
59	EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60	EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61	EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62	EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63	EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64	EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65	EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66	EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67	EXIT_REASON_NIL(),
68	EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69	EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70	EXIT_REASON_NIL(),
71	EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72	EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73	EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74	EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75	EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76	EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77	EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78	EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79	EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80	EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81	EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82	EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83	EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84	EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85	EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86	EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87	EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88	EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89	EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90	EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91	EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92	EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93	EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94	EXIT_REASON_NIL(),
95	EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96	EXIT_REASON_NIL(),
97	EXIT_REASON_NIL(),
98	EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99	EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100	EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101	EXIT_REASON_NIL(),
102	EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103	EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104	EXIT_REASON_NIL(),
105	EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106	EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107	EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108	EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109	EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110	EXIT_REASON_NIL(),
111	EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112	EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113	EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114	EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115	EXIT_REASON_NIL()
116	};
117	/** Exit reason descriptions for AMD-V, used to describe statistics. */
118	static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119	{
120	/** @todo fill in these. */
121	EXIT_REASON_NIL()
122	};
123	# undef EXIT_REASON
124	# undef EXIT_REASON_NIL
125	#endif /* VBOX_WITH_STATISTICS */
126
127	/*******************************************************************************
128	* Internal Functions *
129	*******************************************************************************/
130	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
131	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
132
133
134	/**
135	* Initializes the HWACCM.
136	*
137	* @returns VBox status code.
138	* @param pVM The VM to operate on.
139	*/
140	VMMR3DECL(int) HWACCMR3Init(PVM pVM)
141	{
142	LogFlow(("HWACCMR3Init\n"));
143
144	/*
145	* Assert alignment and sizes.
146	*/
147	AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
148	AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
149
150	/* Some structure checks. */
151	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
152	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
153	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
154	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
155
156	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
157	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
158	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
159	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
160	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
161	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
162	AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
163
164
165	/*
166	* Register the saved state data unit.
167	*/
168	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
169	NULL, hwaccmR3Save, NULL,
170	NULL, hwaccmR3Load, NULL);
171	if (RT_FAILURE(rc))
172	return rc;
173
174	/* Misc initialisation. */
175	pVM->hwaccm.s.vmx.fSupported = false;
176	pVM->hwaccm.s.svm.fSupported = false;
177	pVM->hwaccm.s.vmx.fEnabled = false;
178	pVM->hwaccm.s.svm.fEnabled = false;
179
180	pVM->hwaccm.s.fActive = false;
181	pVM->hwaccm.s.fNestedPaging = false;
182
183	/* Disabled by default. */
184	pVM->fHWACCMEnabled = false;
185
186	/*
187	* Check CFGM options.
188	*/
189	PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
190	PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
191	/* Nested paging: disabled by default. */
192	rc = CFGMR3QueryBoolDef(pRoot, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
193	AssertRC(rc);
194
195	/* VT-x VPID: disabled by default. */
196	rc = CFGMR3QueryBoolDef(pRoot, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
197	AssertRC(rc);
198
199	/* HWACCM support must be explicitely enabled in the configuration file. */
200	rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
201	AssertRC(rc);
202
203	#ifdef RT_OS_DARWIN
204	if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
205	#else
206	if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
207	#endif
208	{
209	AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
210	VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
211	return VERR_HWACCM_CONFIG_MISMATCH;
212	}
213
214	if (VMMIsHwVirtExtForced(pVM))
215	pVM->fHWACCMEnabled = true;
216
217	#if HC_ARCH_BITS == 32
218	/* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
219	* (To use the default, don't set 64bitEnabled in CFGM.) */
220	rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
221	AssertLogRelRCReturn(rc, rc);
222	if (pVM->hwaccm.s.fAllow64BitGuests)
223	{
224	# ifdef RT_OS_DARWIN
225	if (!VMMIsHwVirtExtForced(pVM))
226	# else
227	if (!pVM->hwaccm.s.fAllowed)
228	# endif
229	return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling VT-x.");
230	}
231	#else
232	/* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
233	* via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
234	rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
235	AssertLogRelRCReturn(rc, rc);
236	#endif
237
238	return VINF_SUCCESS;
239	}
240
241	/**
242	* Initializes the per-VCPU HWACCM.
243	*
244	* @returns VBox status code.
245	* @param pVM The VM to operate on.
246	*/
247	VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
248	{
249	LogFlow(("HWACCMR3InitCPU\n"));
250
251	#ifdef VBOX_WITH_STATISTICS
252	/*
253	* Statistics.
254	*/
255	for (unsigned i=0;i<pVM->cCPUs;i++)
256	{
257	PVMCPU pVCpu = &pVM->aCpus[i];
258	int rc;
259
260	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
261	"/PROF/HWACCM/CPU%d/SwitchToGC", i);
262	AssertRC(rc);
263	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
264	"/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
265	AssertRC(rc);
266	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
267	"/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
268	AssertRC(rc);
269	# if 1 /* temporary for tracking down darwin holdup. */
270	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
271	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
272	AssertRC(rc);
273	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
274	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
275	AssertRC(rc);
276	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
277	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
278	AssertRC(rc);
279	# endif
280	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
281	"/PROF/HWACCM/CPU%d/InGC", i);
282	AssertRC(rc);
283
284	# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
285	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
286	"/PROF/HWACCM/CPU%d/Switcher3264", i);
287	AssertRC(rc);
288	# endif
289
290	# define HWACCM_REG_COUNTER(a, b) \
291	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
292	AssertRC(rc);
293
294	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
295	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
296	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
297	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
298	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
299	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
300	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
301	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
302	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
303	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
304	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
305	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
306	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
307	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
308	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
309	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
310	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
311	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
312	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
313	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
314	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
315	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
316	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
317	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
318	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
319
320	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
321	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
322
323	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
324	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
325	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
326
327	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
328	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
329	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
330	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
331	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
332	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
333	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
334	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
335	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
336
337	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
338	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
339
340	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
341	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
342	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
343
344	for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
345	{
346	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
347	"/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
348	AssertRC(rc);
349	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
350	"/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
351	AssertRC(rc);
352	}
353
354	#undef HWACCM_REG_COUNTER
355
356	pVCpu->hwaccm.s.paStatExitReason = NULL;
357
358	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
359	AssertRC(rc);
360	if (RT_SUCCESS(rc))
361	{
362	const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
363	for (int j=0;j<MAX_EXITREASON_STAT;j++)
364	{
365	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
366	papszDesc[j] ? papszDesc[j] : "Exit reason",
367	"/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
368	AssertRC(rc);
369	}
370	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
371	AssertRC(rc);
372	}
373	pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
374	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
375	Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
376	# else
377	Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
378	# endif
379
380	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
381	/* Magic marker for searching in crash dumps. */
382	strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
383	}
384	#endif /* VBOX_WITH_STATISTICS */
385	return VINF_SUCCESS;
386	}
387
388	/**
389	* Turns off normal raw mode features
390	*
391	* @param pVM The VM to operate on.
392	*/
393	static void hwaccmR3DisableRawMode(PVM pVM)
394	{
395	/* Disable PATM & CSAM. */
396	PATMR3AllowPatching(pVM, false);
397	CSAMDisableScanning(pVM);
398
399	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
400	SELMR3DisableMonitoring(pVM);
401	TRPMR3DisableMonitoring(pVM);
402
403	/* The hidden selector registers are now valid. */
404	CPUMSetHiddenSelRegsValid(pVM, true);
405
406	/* Disable the switcher code (safety precaution). */
407	VMMR3DisableSwitcher(pVM);
408
409	/* Disable mapping of the hypervisor into the shadow page table. */
410	PGMR3ChangeShwPDMappings(pVM, false);
411
412	/* Disable the switcher */
413	VMMR3DisableSwitcher(pVM);
414
415	if (pVM->hwaccm.s.fNestedPaging)
416	{
417	/* Reinit the paging mode to force the new shadow mode. */
418	PGMR3ChangeMode(pVM, PGMMODE_REAL);
419	}
420	}
421
422	/**
423	* Initialize VT-x or AMD-V.
424	*
425	* @returns VBox status code.
426	* @param pVM The VM handle.
427	*/
428	VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
429	{
430	int rc;
431
432	if ( !pVM->hwaccm.s.vmx.fSupported
433	&& !pVM->hwaccm.s.svm.fSupported)
434	{
435	LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
436	LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
437	#ifdef RT_OS_DARWIN
438	if (VMMIsHwVirtExtForced(pVM))
439	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
440	#endif
441	return VINF_SUCCESS;
442	}
443
444	/*
445	* Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
446	* because it turns off paging, which is not allowed in VMX root mode.
447	*
448	* To simplify matters we'll just force all running VMs to either use raw or VT-x mode. No mixing allowed in the VT-x case.
449	* There's no such problem with AMD-V. (@todo)
450	*
451	*/
452	/* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
453	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
454	if (RT_FAILURE(rc))
455	{
456	LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
457	LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
458
459	#ifdef RT_OS_DARWIN
460	/*
461	* This is 100% fatal if we didn't prepare for a HwVirtExt setup because of
462	* missing ring-0 allocations. For VMs that require HwVirtExt it doesn't normally
463	* make sense to try run them in software mode, so fail that too.
464	*/
465	if (VMMIsHwVirtExtForced(pVM))
466	VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to "
467	"simultaneously use VT-x.");
468	else
469	VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not "
470	"allowed to simultaneously use software virtualization.");
471	return rc;
472
473	#else /* !RT_OS_DARWIN */
474
475	/* Invert the selection */
476	pVM->hwaccm.s.fAllowed ^= 1;
477	if (pVM->hwaccm.s.fAllowed)
478	{
479	if (pVM->hwaccm.s.vmx.fSupported)
480	VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not allowed "
481	"to simultaneously use software virtualization.\n");
482	else
483	VM_SET_ERROR(pVM, rc, "An active VM already uses AMD-V hardware acceleration. It is not allowed to "
484	"simultaneously use software virtualization.\n");
485	}
486	else
487	VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to simultaneously "
488	"use VT-x or AMD-V.\n");
489	return rc;
490	#endif /* !RT_OS_DARWIN */
491	}
492
493	if (pVM->hwaccm.s.fAllowed == false)
494	return VINF_SUCCESS; /* disabled */
495
496	Assert(!pVM->fHWACCMEnabled \|\| VMMIsHwVirtExtForced(pVM));
497
498	if (pVM->hwaccm.s.vmx.fSupported)
499	{
500	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
501
502	if ( pVM->hwaccm.s.fInitialized == false
503	&& pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
504	{
505	uint64_t val;
506	RTGCPHYS GCPhys = 0;
507
508	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
509	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
510	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
511	LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
512	LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
513	LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
514	LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
515	LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
516
517	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
518	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
519	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
520	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
521	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
522	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
523	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
524	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
525	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
526	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
527	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
528	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
529	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT must be set\n"));
530	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
531	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT must be set\n"));
532	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
533	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI must be set\n"));
534	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
535	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER must be set\n"));
536
537	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
538	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
539	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
540	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
541	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
542	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
543	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
544	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
545	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
546	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
547	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
548	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
549	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
550	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
551	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
552	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
553	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
554	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
555	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
556	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
557	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
558	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
559	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
560	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
561	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
562	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
563	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
564	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
565	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
566	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
567	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
568	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
569	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
570	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
571	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
572	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
573	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
574	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
575	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
576	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
577	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
578	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
579	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
580	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
581
582	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
583	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
584	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT must be set\n"));
585	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
586	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET must be set\n"));
587	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
588	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT must be set\n"));
589	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
590	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT must be set\n"));
591	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
592	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT must be set\n"));
593	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
594	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT must be set\n"));
595	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
596	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT must be set\n"));
597	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
598	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT must be set\n"));
599	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
600	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT must be set\n"));
601	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
602	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT must be set\n"));
603	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
604	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT must be set\n"));
605	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
606	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW must be set\n"));
607	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
608	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT must be set\n"));
609	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
610	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT must be set\n"));
611	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
612	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT must be set\n"));
613	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
614	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS must be set\n"));
615	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
616	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG must be set\n"));
617	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
618	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS must be set\n"));
619	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
620	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT must be set\n"));
621	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
622	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT must be set\n"));
623	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
624	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL must be set\n"));
625
626	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
627	{
628	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
629	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
630	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
631	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
632	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
633	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
634	if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
635	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
636	if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
637	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
638	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
639	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
640	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
641	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
642
643	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
644	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
645	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC must be set\n"));
646	if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
647	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT must be set\n"));
648	if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
649	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC must be set\n"));
650	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
651	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT must be set\n"));
652	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
653	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID must be set\n"));
654	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
655	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT must be set\n"));
656	}
657
658	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
659	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
660	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
661	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
662	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
663	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
664	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
665	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
666	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
667	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
668	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
669	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
670	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
671	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
672	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
673	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
674	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
675	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
676	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG must be set\n"));
677	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
678	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE must be set\n"));
679	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
680	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM must be set\n"));
681	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
682	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON must be set\n"));
683	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
684	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR must be set\n"));
685	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
686	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR must be set\n"));
687	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
688	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR must be set\n"));
689
690	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
691	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
692	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
693	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
694	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
695	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
696	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
697	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
698	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
699	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
700	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
701	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
702	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
703	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
704	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
705	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
706	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
707	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
708	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
709	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
710	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG must be set\n"));
711	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
712	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 must be set\n"));
713	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
714	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ must be set\n"));
715	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
716	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR must be set\n"));
717	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
718	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR must be set\n"));
719	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
720	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR must be set\n"));
721	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
722	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR must be set\n"));
723	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
724	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER must be set\n"));
725
726	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
727	{
728	LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
729
730	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
731	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
732	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
733	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
734	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
735	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
736	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
737	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
738	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
739	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
740	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
741	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
742	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
743	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
744	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
745	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
746	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
747	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
748	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
749	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
750	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
751	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
752	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
753	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
754	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
755	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
756	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
757	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
758	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
759	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
760	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
761	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
762	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
763	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
764	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
765	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
766	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
767	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
768	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
769	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
770	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
771	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
772	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
773	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
774	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
775	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
776	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
777	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
778	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
779	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
780	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
781	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
782	}
783
784	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
785	LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
786	LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
787	LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
788	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
789	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
790
791	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
792	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
793	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
794	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
795	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
796
797	LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
798	LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
799
800	for (unsigned i=0;i<pVM->cCPUs;i++)
801	LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
802
803	#ifdef HWACCM_VTX_WITH_EPT
804	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
805	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
806	#endif /* HWACCM_VTX_WITH_EPT */
807	#ifdef HWACCM_VTX_WITH_VPID
808	if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
809	&& !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
810	pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
811	#endif /* HWACCM_VTX_WITH_VPID */
812
813	/* Only try once. */
814	pVM->hwaccm.s.fInitialized = true;
815
816	/* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
817	#if 1
818	rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
819	#else
820	rc = VERR_NO_MEMORY; /* simulation of no VMMDev Heap. */
821	#endif
822	if (RT_SUCCESS(rc))
823	{
824	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
825	ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
826	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
827	/* Bit set to 0 means redirection enabled. */
828	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
829	/* Allow all port IO, so the VT-x IO intercepts do their job. */
830	memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
831	((unsigned char )pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
832
833	/* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
834	* real and protected mode without paging with EPT.
835	*/
836	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
837	for (unsigned i=0;i<X86_PG_ENTRIES;i++)
838	{
839	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
840	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_G;
841	}
842
843	/* We convert it here every time as pci regions could be reconfigured. */
844	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
845	AssertRC(rc);
846	LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
847
848	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
849	AssertRC(rc);
850	LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
851	}
852	else
853	{
854	LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
855	pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
856	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
857	}
858
859	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
860	AssertRC(rc);
861	if (rc == VINF_SUCCESS)
862	{
863	pVM->fHWACCMEnabled = true;
864	pVM->hwaccm.s.vmx.fEnabled = true;
865	hwaccmR3DisableRawMode(pVM);
866
867	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
868	#ifdef VBOX_ENABLE_64_BITS_GUESTS
869	if (pVM->hwaccm.s.fAllow64BitGuests)
870	{
871	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
872	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
873	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
874	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
875	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
876	}
877	LogRel((pVM->hwaccm.s.fAllow64BitGuests
878	? "HWACCM: 32-bit and 64-bit guest supported.\n"
879	: "HWACCM: 32-bit guest supported.\n"));
880	#else
881	LogRel(("HWACCM: 32-bit guest supported.\n"));
882	#endif
883	LogRel(("HWACCM: VMX enabled!\n"));
884	if (pVM->hwaccm.s.fNestedPaging)
885	{
886	LogRel(("HWACCM: Enabled nested paging\n"));
887	LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetEPTCR3(pVM)));
888	}
889	if (pVM->hwaccm.s.vmx.fVPID)
890	LogRel(("HWACCM: Enabled VPID\n"));
891
892	if ( pVM->hwaccm.s.fNestedPaging
893	\|\| pVM->hwaccm.s.vmx.fVPID)
894	{
895	LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
896	LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
897	}
898	}
899	else
900	{
901	LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
902	LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
903	pVM->fHWACCMEnabled = false;
904	}
905	}
906	}
907	else
908	if (pVM->hwaccm.s.svm.fSupported)
909	{
910	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
911
912	if (pVM->hwaccm.s.fInitialized == false)
913	{
914	/* Erratum 170 which requires a forced TLB flush for each world switch:
915	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
916	*
917	* All BH-G1/2 and DH-G1/2 models include a fix:
918	* Athlon X2: 0x6b 1/2
919	* 0x68 1/2
920	* Athlon 64: 0x7f 1
921	* 0x6f 2
922	* Sempron: 0x7f 1/2
923	* 0x6f 2
924	* 0x6c 2
925	* 0x7c 2
926	* Turion 64: 0x68 2
927	*
928	*/
929	uint32_t u32Dummy;
930	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
931	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
932	u32BaseFamily= (u32Version >> 8) & 0xf;
933	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
934	u32Model = ((u32Version >> 4) & 0xf);
935	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
936	u32Stepping = u32Version & 0xf;
937	if ( u32Family == 0xf
938	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
939	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
940	{
941	LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
942	}
943
944	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
945	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
946	LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
947	LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
948	LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
949
950	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
951	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
952	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
953	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
954	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
955	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
956	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
957	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
958	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
959	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
960
961	/* Only try once. */
962	pVM->hwaccm.s.fInitialized = true;
963
964	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
965	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
966
967	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
968	AssertRC(rc);
969	if (rc == VINF_SUCCESS)
970	{
971	pVM->fHWACCMEnabled = true;
972	pVM->hwaccm.s.svm.fEnabled = true;
973
974	if (pVM->hwaccm.s.fNestedPaging)
975	LogRel(("HWACCM: Enabled nested paging\n"));
976
977	hwaccmR3DisableRawMode(pVM);
978	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
979	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
980	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
981	#ifdef VBOX_ENABLE_64_BITS_GUESTS
982	if (pVM->hwaccm.s.fAllow64BitGuests)
983	{
984	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
985	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
986	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
987	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
988	}
989	#endif
990	LogRel((pVM->hwaccm.s.fAllow64BitGuests
991	? "HWACCM: 32-bit and 64-bit guest supported.\n"
992	: "HWACCM: 32-bit guest supported.\n"));
993	}
994	else
995	{
996	pVM->fHWACCMEnabled = false;
997	}
998	}
999	}
1000	return VINF_SUCCESS;
1001	}
1002
1003	/**
1004	* Applies relocations to data and code managed by this
1005	* component. This function will be called at init and
1006	* whenever the VMM need to relocate it self inside the GC.
1007	*
1008	* @param pVM The VM.
1009	*/
1010	VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1011	{
1012	Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1013
1014	/* Fetch the current paging mode during the relocate callback during state loading. */
1015	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1016	{
1017	for (unsigned i=0;i<pVM->cCPUs;i++)
1018	{
1019	PVMCPU pVCpu = &pVM->aCpus[i];
1020	/* @todo SMP */
1021	pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVM);
1022	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMGetGuestMode(pVM);
1023	}
1024	}
1025	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1026	if (pVM->fHWACCMEnabled)
1027	{
1028	int rc;
1029
1030	switch(PGMGetHostMode(pVM))
1031	{
1032	case PGMMODE_32_BIT:
1033	pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1034	break;
1035
1036	case PGMMODE_PAE:
1037	case PGMMODE_PAE_NX:
1038	pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1039	break;
1040
1041	default:
1042	AssertFailed();
1043	break;
1044	}
1045	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1046	AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1047
1048	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1049	AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1050
1051	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1052	AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1053
1054	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1055	AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1056
1057	# ifdef DEBUG
1058	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1059	AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1060	# endif
1061	}
1062	#endif
1063	return;
1064	}
1065
1066	/**
1067	* Checks hardware accelerated raw mode is allowed.
1068	*
1069	* @returns boolean
1070	* @param pVM The VM to operate on.
1071	*/
1072	VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1073	{
1074	return pVM->hwaccm.s.fAllowed;
1075	}
1076
1077	/**
1078	* Notification callback which is called whenever there is a chance that a CR3
1079	* value might have changed.
1080	*
1081	* This is called by PGM.
1082	*
1083	* @param pVM The VM to operate on.
1084	* @param enmShadowMode New shadow paging mode.
1085	* @param enmGuestMode New guest paging mode.
1086	*/
1087	VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1088	{
1089	/* Ignore page mode changes during state loading. */
1090	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1091	return;
1092
1093	PVMCPU pVCpu = VMMGetCpu(pVM);
1094	pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1095
1096	if ( pVM->hwaccm.s.vmx.fEnabled
1097	&& pVM->fHWACCMEnabled)
1098	{
1099	if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1100	&& enmGuestMode >= PGMMODE_PROTECTED)
1101	{
1102	PCPUMCTX pCtx;
1103
1104	pCtx = CPUMQueryGuestCtxPtr(pVM);
1105
1106	/* After a real mode switch to protected mode we must force
1107	* CPL to 0. Our real mode emulation had to set it to 3.
1108	*/
1109	pCtx->ssHid.Attr.n.u2Dpl = 0;
1110	}
1111	}
1112
1113	if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1114	{
1115	/* Keep track of paging mode changes. */
1116	pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1117	pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1118
1119	/* Did we miss a change, because all code was executed in the recompiler? */
1120	if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1121	{
1122	Log(("HWACCMR3PagingModeChanged missed %s->%s transition (last seen %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1123	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1124	}
1125	}
1126
1127	/* Reset the contents of the read cache. */
1128	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1129	for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1130	pCache->Read.aFieldVal[j] = 0;
1131	}
1132
1133	/**
1134	* Terminates the HWACCM.
1135	*
1136	* Termination means cleaning up and freeing all resources,
1137	* the VM it self is at this point powered off or suspended.
1138	*
1139	* @returns VBox status code.
1140	* @param pVM The VM to operate on.
1141	*/
1142	VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1143	{
1144	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1145	{
1146	PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1147	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1148	}
1149	return 0;
1150	}
1151
1152	/**
1153	* Terminates the per-VCPU HWACCM.
1154	*
1155	* Termination means cleaning up and freeing all resources,
1156	* the VM it self is at this point powered off or suspended.
1157	*
1158	* @returns VBox status code.
1159	* @param pVM The VM to operate on.
1160	*/
1161	VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1162	{
1163	for (unsigned i=0;i<pVM->cCPUs;i++)
1164	{
1165	PVMCPU pVCpu = &pVM->aCpus[i];
1166
1167	if (pVCpu->hwaccm.s.paStatExitReason)
1168	{
1169	MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1170	pVCpu->hwaccm.s.paStatExitReason = NULL;
1171	pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1172	}
1173	}
1174	return 0;
1175	}
1176
1177	/**
1178	* The VM is being reset.
1179	*
1180	* For the HWACCM component this means that any GDT/LDT/TSS monitors
1181	* needs to be removed.
1182	*
1183	* @param pVM VM handle.
1184	*/
1185	VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1186	{
1187	LogFlow(("HWACCMR3Reset:\n"));
1188
1189	if (pVM->fHWACCMEnabled)
1190	hwaccmR3DisableRawMode(pVM);
1191
1192	for (unsigned i=0;i<pVM->cCPUs;i++)
1193	{
1194	PVMCPU pVCpu = &pVM->aCpus[i];
1195
1196	/* On first entry we'll sync everything. */
1197	pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1198
1199	pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1200	pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1201
1202	pVCpu->hwaccm.s.Event.fPending = false;
1203
1204	/* Reset state information for real-mode emulation in VT-x. */
1205	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1206	pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1207	pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1208
1209	/* Reset the contents of the read cache. */
1210	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1211	for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1212	pCache->Read.aFieldVal[j] = 0;
1213
1214	/* Magic marker for searching in crash dumps. */
1215	strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1216	}
1217	}
1218
1219	/**
1220	* Checks if we can currently use hardware accelerated raw mode.
1221	*
1222	* @returns boolean
1223	* @param pVM The VM to operate on.
1224	* @param pCtx Partial VM execution context
1225	*/
1226	VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
1227	{
1228	Assert(pVM->fHWACCMEnabled);
1229
1230	/* AMD SVM supports real & protected mode with or without paging. */
1231	if (pVM->hwaccm.s.svm.fEnabled)
1232	{
1233	pVM->hwaccm.s.fActive = true;
1234	return true;
1235	}
1236
1237	pVM->hwaccm.s.fActive = false;
1238
1239	/* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
1240	#ifdef HWACCM_VMX_EMULATE_REALMODE
1241	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1242	{
1243	if (CPUMIsGuestInRealModeEx(pCtx))
1244	{
1245	/* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
1246	* The base must also be equal to (sel << 4).
1247	*/
1248	if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
1249	&& pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
1250	\|\| pCtx->ds != (pCtx->dsHid.u64Base >> 4)
1251	\|\| pCtx->es != (pCtx->esHid.u64Base >> 4)
1252	\|\| pCtx->fs != (pCtx->fsHid.u64Base >> 4)
1253	\|\| pCtx->gs != (pCtx->gsHid.u64Base >> 4)
1254	\|\| pCtx->ss != (pCtx->ssHid.u64Base >> 4))
1255	{
1256	return false;
1257	}
1258	}
1259	else
1260	{
1261	PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
1262	/* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
1263	* from real to protected mode. (all sorts of RPL & DPL assumptions)
1264	*/
1265	PVMCPU pVCpu = VMMGetCpu(pVM);
1266
1267	if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1268	&& enmGuestMode >= PGMMODE_PROTECTED)
1269	{
1270	if ( (pCtx->cs & X86_SEL_RPL)
1271	\|\| (pCtx->ds & X86_SEL_RPL)
1272	\|\| (pCtx->es & X86_SEL_RPL)
1273	\|\| (pCtx->fs & X86_SEL_RPL)
1274	\|\| (pCtx->gs & X86_SEL_RPL)
1275	\|\| (pCtx->ss & X86_SEL_RPL))
1276	{
1277	return false;
1278	}
1279	}
1280	}
1281	}
1282	else
1283	#endif /* HWACCM_VMX_EMULATE_REALMODE */
1284	{
1285	if (!CPUMIsGuestInLongModeEx(pCtx))
1286	{
1287	/** @todo This should (probably) be set on every excursion to the REM,
1288	* however it's too risky right now. So, only apply it when we go
1289	* back to REM for real mode execution. (The XP hack below doesn't
1290	* work reliably without this.)
1291	* Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
1292	pVM->aCpus[0].hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1293
1294	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
1295	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
1296	return false;
1297
1298	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
1299	/* Windows XP; switch to protected mode; all selectors are marked not present in the
1300	* hidden registers (possible recompiler bug; see load_seg_vm) */
1301	if (pCtx->csHid.Attr.n.u1Present == 0)
1302	return false;
1303	if (pCtx->ssHid.Attr.n.u1Present == 0)
1304	return false;
1305
1306	/* Windows XP: possible same as above, but new recompiler requires new heuristics?
1307	VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
1308	/** @todo This check is actually wrong, it doesn't take the direction of the
1309	* stack segment into account. But, it does the job for now. */
1310	if (pCtx->rsp >= pCtx->ssHid.u32Limit)
1311	return false;
1312	#if 0
1313	if ( pCtx->cs >= pCtx->gdtr.cbGdt
1314	\|\| pCtx->ss >= pCtx->gdtr.cbGdt
1315	\|\| pCtx->ds >= pCtx->gdtr.cbGdt
1316	\|\| pCtx->es >= pCtx->gdtr.cbGdt
1317	\|\| pCtx->fs >= pCtx->gdtr.cbGdt
1318	\|\| pCtx->gs >= pCtx->gdtr.cbGdt)
1319	return false;
1320	#endif
1321	}
1322	}
1323
1324	if (pVM->hwaccm.s.vmx.fEnabled)
1325	{
1326	uint32_t mask;
1327
1328	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
1329	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
1330	/* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
1331	mask &= ~X86_CR0_NE;
1332
1333	#ifdef HWACCM_VMX_EMULATE_REALMODE
1334	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1335	{
1336	/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
1337	mask &= ~(X86_CR0_PG\|X86_CR0_PE);
1338	}
1339	else
1340	#endif
1341	{
1342	/* We support protected mode without paging using identity mapping. */
1343	mask &= ~X86_CR0_PG;
1344	}
1345	if ((pCtx->cr0 & mask) != mask)
1346	return false;
1347
1348	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
1349	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
1350	if ((pCtx->cr0 & mask) != 0)
1351	return false;
1352
1353	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
1354	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1355	mask &= ~X86_CR4_VMXE;
1356	if ((pCtx->cr4 & mask) != mask)
1357	return false;
1358
1359	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
1360	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
1361	if ((pCtx->cr4 & mask) != 0)
1362	return false;
1363
1364	pVM->hwaccm.s.fActive = true;
1365	return true;
1366	}
1367
1368	return false;
1369	}
1370
1371	/**
1372	* Notifcation from EM about a rescheduling into hardware assisted execution
1373	* mode.
1374	*
1375	* @param pVCpu Pointer to the current virtual cpu structure.
1376	*/
1377	VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
1378	{
1379	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1380	}
1381
1382	/**
1383	* Notifcation from EM about returning from instruction emulation (REM / EM).
1384	*
1385	* @param pVCpu Pointer to the current virtual cpu structure.
1386	*/
1387	VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
1388	{
1389	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1390	}
1391
1392	/**
1393	* Checks if we are currently using hardware accelerated raw mode.
1394	*
1395	* @returns boolean
1396	* @param pVM The VM to operate on.
1397	*/
1398	VMMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
1399	{
1400	return pVM->hwaccm.s.fActive;
1401	}
1402
1403	/**
1404	* Checks if we are currently using nested paging.
1405	*
1406	* @returns boolean
1407	* @param pVM The VM to operate on.
1408	*/
1409	VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
1410	{
1411	return pVM->hwaccm.s.fNestedPaging;
1412	}
1413
1414	/**
1415	* Checks if we are currently using VPID in VT-x mode.
1416	*
1417	* @returns boolean
1418	* @param pVM The VM to operate on.
1419	*/
1420	VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
1421	{
1422	return pVM->hwaccm.s.vmx.fVPID;
1423	}
1424
1425
1426	/**
1427	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
1428	*
1429	* @returns boolean
1430	* @param pVM The VM to operate on.
1431	*/
1432	VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
1433	{
1434	/* @todo SMP */
1435	return HWACCMIsEnabled(pVM) && pVM->aCpus[0].hwaccm.s.Event.fPending;
1436	}
1437
1438
1439	/**
1440	* Inject an NMI into a running VM
1441	*
1442	* @returns boolean
1443	* @param pVM The VM to operate on.
1444	*/
1445	VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
1446	{
1447	pVM->hwaccm.s.fInjectNMI = true;
1448	return VINF_SUCCESS;
1449	}
1450
1451	/**
1452	* Check fatal VT-x/AMD-V error and produce some meaningful
1453	* log release message.
1454	*
1455	* @param pVM The VM to operate on.
1456	* @param iStatusCode VBox status code
1457	*/
1458	VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
1459	{
1460	for (unsigned i=0;i<pVM->cCPUs;i++)
1461	{
1462	switch(iStatusCode)
1463	{
1464	case VERR_VMX_INVALID_VMCS_FIELD:
1465	break;
1466
1467	case VERR_VMX_INVALID_VMCS_PTR:
1468	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1469	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
1470	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
1471	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
1472	break;
1473
1474	case VERR_VMX_UNABLE_TO_START_VM:
1475	LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1476	LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1477	#if 0 /* @todo dump the current control fields to the release log */
1478	if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
1479	{
1480
1481	}
1482	#endif
1483	break;
1484
1485	case VERR_VMX_UNABLE_TO_RESUME_VM:
1486	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1487	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1488	break;
1489
1490	case VERR_VMX_INVALID_VMXON_PTR:
1491	break;
1492	}
1493	}
1494	}
1495
1496	/**
1497	* Execute state save operation.
1498	*
1499	* @returns VBox status code.
1500	* @param pVM VM Handle.
1501	* @param pSSM SSM operation handle.
1502	*/
1503	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
1504	{
1505	int rc;
1506
1507	Log(("hwaccmR3Save:\n"));
1508
1509	for (unsigned i=0;i<pVM->cCPUs;i++)
1510	{
1511	/*
1512	* Save the basic bits - fortunately all the other things can be resynced on load.
1513	*/
1514	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
1515	AssertRCReturn(rc, rc);
1516	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
1517	AssertRCReturn(rc, rc);
1518	rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
1519	AssertRCReturn(rc, rc);
1520
1521	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
1522	AssertRCReturn(rc, rc);
1523	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
1524	AssertRCReturn(rc, rc);
1525	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
1526	AssertRCReturn(rc, rc);
1527	}
1528
1529	return VINF_SUCCESS;
1530	}
1531
1532	/**
1533	* Execute state load operation.
1534	*
1535	* @returns VBox status code.
1536	* @param pVM VM Handle.
1537	* @param pSSM SSM operation handle.
1538	* @param u32Version Data layout version.
1539	*/
1540	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1541	{
1542	int rc;
1543
1544	Log(("hwaccmR3Load:\n"));
1545
1546	/*
1547	* Validate version.
1548	*/
1549	if ( u32Version != HWACCM_SSM_VERSION
1550	&& u32Version != HWACCM_SSM_VERSION_2_0_X)
1551	{
1552	AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
1553	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1554	}
1555	for (unsigned i=0;i<pVM->cCPUs;i++)
1556	{
1557	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
1558	AssertRCReturn(rc, rc);
1559	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
1560	AssertRCReturn(rc, rc);
1561	rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
1562	AssertRCReturn(rc, rc);
1563
1564	if (u32Version >= HWACCM_SSM_VERSION)
1565	{
1566	uint32_t val;
1567
1568	rc = SSMR3GetU32(pSSM, &val);
1569	AssertRCReturn(rc, rc);
1570	pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
1571
1572	rc = SSMR3GetU32(pSSM, &val);
1573	AssertRCReturn(rc, rc);
1574	pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
1575
1576	rc = SSMR3GetU32(pSSM, &val);
1577	AssertRCReturn(rc, rc);
1578	pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
1579	}
1580	}
1581	return VINF_SUCCESS;
1582	}
1583

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source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 15803

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