HWACCM.cpp@ 15934

Last change on this file since 15934 was 15934, checked in by vboxsync, 16 years ago
hwaccm: added a runtime warning if the user tries to execute a VM with VT-x/AMD-V enabled but this extension is not available
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File size: 78.8 KB

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1	/* $Id: HWACCM.cpp 15934 2009-01-14 10:39:06Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_HWACCM
26	#include <VBox/cpum.h>
27	#include <VBox/stam.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/trpm.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/patm.h>
34	#include <VBox/csam.h>
35	#include <VBox/selm.h>
36	#include <VBox/rem.h>
37	#include <VBox/hwacc_vmx.h>
38	#include <VBox/hwacc_svm.h>
39	#include "HWACCMInternal.h"
40	#include <VBox/vm.h>
41	#include <VBox/err.h>
42	#include <VBox/param.h>
43
44	#include <iprt/assert.h>
45	#include <VBox/log.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48	#include <iprt/thread.h>
49
50	/*******************************************************************************
51	* Global Variables *
52	*******************************************************************************/
53	#ifdef VBOX_WITH_STATISTICS
54	# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55	# define EXIT_REASON_NIL() NULL
56	/** Exit reason descriptions for VT-x, used to describe statistics. */
57	static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58	{
59	EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60	EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61	EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62	EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63	EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64	EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65	EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66	EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67	EXIT_REASON_NIL(),
68	EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69	EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70	EXIT_REASON_NIL(),
71	EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72	EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73	EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74	EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75	EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76	EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77	EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78	EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79	EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80	EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81	EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82	EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83	EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84	EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85	EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86	EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87	EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88	EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89	EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90	EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91	EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92	EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93	EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94	EXIT_REASON_NIL(),
95	EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96	EXIT_REASON_NIL(),
97	EXIT_REASON_NIL(),
98	EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99	EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100	EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101	EXIT_REASON_NIL(),
102	EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103	EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104	EXIT_REASON_NIL(),
105	EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106	EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107	EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108	EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109	EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110	EXIT_REASON_NIL(),
111	EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112	EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113	EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114	EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115	EXIT_REASON_NIL()
116	};
117	/** Exit reason descriptions for AMD-V, used to describe statistics. */
118	static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119	{
120	/** @todo fill in these. */
121	EXIT_REASON_NIL()
122	};
123	# undef EXIT_REASON
124	# undef EXIT_REASON_NIL
125	#endif /* VBOX_WITH_STATISTICS */
126
127	/*******************************************************************************
128	* Internal Functions *
129	*******************************************************************************/
130	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
131	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
132
133
134	/**
135	* Initializes the HWACCM.
136	*
137	* @returns VBox status code.
138	* @param pVM The VM to operate on.
139	*/
140	VMMR3DECL(int) HWACCMR3Init(PVM pVM)
141	{
142	LogFlow(("HWACCMR3Init\n"));
143
144	/*
145	* Assert alignment and sizes.
146	*/
147	AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
148	AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
149
150	/* Some structure checks. */
151	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
152	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
153	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
154	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
155
156	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
157	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
158	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
159	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
160	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
161	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
162	AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
163
164
165	/*
166	* Register the saved state data unit.
167	*/
168	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
169	NULL, hwaccmR3Save, NULL,
170	NULL, hwaccmR3Load, NULL);
171	if (RT_FAILURE(rc))
172	return rc;
173
174	/* Misc initialisation. */
175	pVM->hwaccm.s.vmx.fSupported = false;
176	pVM->hwaccm.s.svm.fSupported = false;
177	pVM->hwaccm.s.vmx.fEnabled = false;
178	pVM->hwaccm.s.svm.fEnabled = false;
179
180	pVM->hwaccm.s.fActive = false;
181	pVM->hwaccm.s.fNestedPaging = false;
182
183	/* Disabled by default. */
184	pVM->fHWACCMEnabled = false;
185
186	/*
187	* Check CFGM options.
188	*/
189	PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
190	PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
191	/* Nested paging: disabled by default. */
192	rc = CFGMR3QueryBoolDef(pRoot, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
193	AssertRC(rc);
194
195	/* VT-x VPID: disabled by default. */
196	rc = CFGMR3QueryBoolDef(pRoot, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
197	AssertRC(rc);
198
199	/* HWACCM support must be explicitely enabled in the configuration file. */
200	rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
201	AssertRC(rc);
202
203	#ifdef RT_OS_DARWIN
204	if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
205	#else
206	if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
207	#endif
208	{
209	AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
210	VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
211	return VERR_HWACCM_CONFIG_MISMATCH;
212	}
213
214	if (VMMIsHwVirtExtForced(pVM))
215	pVM->fHWACCMEnabled = true;
216
217	#if HC_ARCH_BITS == 32
218	/* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
219	* (To use the default, don't set 64bitEnabled in CFGM.) */
220	rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
221	AssertLogRelRCReturn(rc, rc);
222	if (pVM->hwaccm.s.fAllow64BitGuests)
223	{
224	# ifdef RT_OS_DARWIN
225	if (!VMMIsHwVirtExtForced(pVM))
226	# else
227	if (!pVM->hwaccm.s.fAllowed)
228	# endif
229	return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling VT-x.");
230	}
231	#else
232	/* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
233	* via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
234	rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
235	AssertLogRelRCReturn(rc, rc);
236	#endif
237
238	return VINF_SUCCESS;
239	}
240
241	/**
242	* Initializes the per-VCPU HWACCM.
243	*
244	* @returns VBox status code.
245	* @param pVM The VM to operate on.
246	*/
247	VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
248	{
249	LogFlow(("HWACCMR3InitCPU\n"));
250
251	#ifdef VBOX_WITH_STATISTICS
252	/*
253	* Statistics.
254	*/
255	for (unsigned i=0;i<pVM->cCPUs;i++)
256	{
257	PVMCPU pVCpu = &pVM->aCpus[i];
258	int rc;
259
260	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
261	"/PROF/HWACCM/CPU%d/SwitchToGC", i);
262	AssertRC(rc);
263	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
264	"/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
265	AssertRC(rc);
266	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
267	"/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
268	AssertRC(rc);
269	# if 1 /* temporary for tracking down darwin holdup. */
270	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
271	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
272	AssertRC(rc);
273	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
274	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
275	AssertRC(rc);
276	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
277	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
278	AssertRC(rc);
279	# endif
280	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
281	"/PROF/HWACCM/CPU%d/InGC", i);
282	AssertRC(rc);
283
284	# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
285	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
286	"/PROF/HWACCM/CPU%d/Switcher3264", i);
287	AssertRC(rc);
288	# endif
289
290	# define HWACCM_REG_COUNTER(a, b) \
291	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
292	AssertRC(rc);
293
294	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
295	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
296	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
297	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
298	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
299	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
300	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
301	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
302	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
303	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
304	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
305	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
306	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
307	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
308	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
309	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
310	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
311	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
312	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
313	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
314	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
315	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
316	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
317	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
318	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
319
320	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
321	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
322
323	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
324	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
325	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
326
327	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
328	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
329	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
330	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
331	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
332	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
333	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
334	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
335	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
336
337	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
338	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
339
340	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
341	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
342	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
343
344	for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
345	{
346	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
347	"/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
348	AssertRC(rc);
349	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
350	"/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
351	AssertRC(rc);
352	}
353
354	#undef HWACCM_REG_COUNTER
355
356	pVCpu->hwaccm.s.paStatExitReason = NULL;
357
358	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
359	AssertRC(rc);
360	if (RT_SUCCESS(rc))
361	{
362	const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
363	for (int j=0;j<MAX_EXITREASON_STAT;j++)
364	{
365	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
366	papszDesc[j] ? papszDesc[j] : "Exit reason",
367	"/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
368	AssertRC(rc);
369	}
370	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
371	AssertRC(rc);
372	}
373	pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
374	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
375	Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
376	# else
377	Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
378	# endif
379
380	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
381	/* Magic marker for searching in crash dumps. */
382	strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
383	pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
384	}
385	#endif /* VBOX_WITH_STATISTICS */
386	return VINF_SUCCESS;
387	}
388
389	/**
390	* Turns off normal raw mode features
391	*
392	* @param pVM The VM to operate on.
393	*/
394	static void hwaccmR3DisableRawMode(PVM pVM)
395	{
396	/* Disable PATM & CSAM. */
397	PATMR3AllowPatching(pVM, false);
398	CSAMDisableScanning(pVM);
399
400	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
401	SELMR3DisableMonitoring(pVM);
402	TRPMR3DisableMonitoring(pVM);
403
404	/* The hidden selector registers are now valid. */
405	CPUMSetHiddenSelRegsValid(pVM, true);
406
407	/* Disable the switcher code (safety precaution). */
408	VMMR3DisableSwitcher(pVM);
409
410	/* Disable mapping of the hypervisor into the shadow page table. */
411	PGMR3ChangeShwPDMappings(pVM, false);
412
413	/* Disable the switcher */
414	VMMR3DisableSwitcher(pVM);
415
416	if (pVM->hwaccm.s.fNestedPaging)
417	{
418	/* Reinit the paging mode to force the new shadow mode. */
419	PGMR3ChangeMode(pVM, PGMMODE_REAL);
420	}
421	}
422
423	/**
424	* Initialize VT-x or AMD-V.
425	*
426	* @returns VBox status code.
427	* @param pVM The VM handle.
428	*/
429	VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
430	{
431	int rc;
432
433	if ( !pVM->hwaccm.s.vmx.fSupported
434	&& !pVM->hwaccm.s.svm.fSupported)
435	{
436	LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
437	LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
438	VMSetRuntimeError(pVM, false, "HwaccmDisabled",
439	N_("You are trying to execute this VM with VT-x/AMD-V enabled but this hardware "
440	"extension is either not available or it is disabled in the BIOS. You might "
441	"check the BIOS settings and/or update the BIOS. The VM will be executed "
442	"without using this hardware extension"));
443	#ifdef RT_OS_DARWIN
444	if (VMMIsHwVirtExtForced(pVM))
445	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
446	#endif
447	return VINF_SUCCESS;
448	}
449
450	/*
451	* Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
452	* because it turns off paging, which is not allowed in VMX root mode.
453	*
454	* To simplify matters we'll just force all running VMs to either use raw or VT-x mode. No mixing allowed in the VT-x case.
455	* There's no such problem with AMD-V. (@todo)
456	*
457	*/
458	/* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
459	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
460	if (RT_FAILURE(rc))
461	{
462	LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
463	LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
464
465	#ifdef RT_OS_DARWIN
466	/*
467	* This is 100% fatal if we didn't prepare for a HwVirtExt setup because of
468	* missing ring-0 allocations. For VMs that require HwVirtExt it doesn't normally
469	* make sense to try run them in software mode, so fail that too.
470	*/
471	if (VMMIsHwVirtExtForced(pVM))
472	VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to "
473	"simultaneously use VT-x.");
474	else
475	VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not "
476	"allowed to simultaneously use software virtualization.");
477	return rc;
478
479	#else /* !RT_OS_DARWIN */
480
481	/* Invert the selection */
482	pVM->hwaccm.s.fAllowed ^= 1;
483	if (pVM->hwaccm.s.fAllowed)
484	{
485	if (pVM->hwaccm.s.vmx.fSupported)
486	VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not allowed "
487	"to simultaneously use software virtualization.\n");
488	else
489	VM_SET_ERROR(pVM, rc, "An active VM already uses AMD-V hardware acceleration. It is not allowed to "
490	"simultaneously use software virtualization.\n");
491	}
492	else
493	VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to simultaneously "
494	"use VT-x or AMD-V.\n");
495	return rc;
496	#endif /* !RT_OS_DARWIN */
497	}
498
499	if (pVM->hwaccm.s.fAllowed == false)
500	return VINF_SUCCESS; /* disabled */
501
502	Assert(!pVM->fHWACCMEnabled \|\| VMMIsHwVirtExtForced(pVM));
503
504	if (pVM->hwaccm.s.vmx.fSupported)
505	{
506	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
507
508	if ( pVM->hwaccm.s.fInitialized == false
509	&& pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
510	{
511	uint64_t val;
512	RTGCPHYS GCPhys = 0;
513
514	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
515	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
516	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
517	LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
518	LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
519	LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
520	LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
521	LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
522
523	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
524	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
525	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
526	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
527	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
528	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
529	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
530	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
531	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
532	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
533	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
534	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
535	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT must be set\n"));
536	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
537	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT must be set\n"));
538	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
539	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI must be set\n"));
540	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
541	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER must be set\n"));
542
543	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
544	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
545	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
546	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
547	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
548	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
549	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
550	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
551	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
552	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
553	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
554	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
555	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
556	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
557	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
558	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
559	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
560	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
561	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
562	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
563	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
564	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
565	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
566	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
567	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
568	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
569	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
570	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
571	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
572	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
573	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
574	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
575	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
576	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
577	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
578	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
579	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
580	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
581	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
582	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
583	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
584	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
585	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
586	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
587
588	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
589	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
590	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT must be set\n"));
591	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
592	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET must be set\n"));
593	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
594	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT must be set\n"));
595	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
596	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT must be set\n"));
597	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
598	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT must be set\n"));
599	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
600	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT must be set\n"));
601	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
602	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT must be set\n"));
603	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
604	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT must be set\n"));
605	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
606	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT must be set\n"));
607	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
608	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT must be set\n"));
609	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
610	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT must be set\n"));
611	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
612	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW must be set\n"));
613	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
614	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT must be set\n"));
615	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
616	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT must be set\n"));
617	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
618	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT must be set\n"));
619	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
620	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS must be set\n"));
621	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
622	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG must be set\n"));
623	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
624	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS must be set\n"));
625	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
626	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT must be set\n"));
627	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
628	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT must be set\n"));
629	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
630	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL must be set\n"));
631
632	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
633	{
634	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
635	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
636	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
637	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
638	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
639	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
640	if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
641	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
642	if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
643	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
644	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
645	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
646	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
647	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
648
649	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
650	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
651	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC must be set\n"));
652	if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
653	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT must be set\n"));
654	if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
655	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC must be set\n"));
656	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
657	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT must be set\n"));
658	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
659	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID must be set\n"));
660	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
661	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT must be set\n"));
662	}
663
664	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
665	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
666	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
667	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
668	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
669	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
670	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
671	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
672	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
673	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
674	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
675	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
676	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
677	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
678	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
679	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
680	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
681	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
682	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG must be set\n"));
683	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
684	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE must be set\n"));
685	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
686	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM must be set\n"));
687	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
688	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON must be set\n"));
689	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
690	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR must be set\n"));
691	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
692	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR must be set\n"));
693	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
694	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR must be set\n"));
695
696	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
697	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
698	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
699	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
700	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
701	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
702	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
703	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
704	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
705	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
706	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
707	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
708	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
709	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
710	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
711	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
712	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
713	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
714	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
715	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
716	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG must be set\n"));
717	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
718	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 must be set\n"));
719	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
720	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ must be set\n"));
721	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
722	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR must be set\n"));
723	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
724	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR must be set\n"));
725	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
726	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR must be set\n"));
727	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
728	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR must be set\n"));
729	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
730	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER must be set\n"));
731
732	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
733	{
734	LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
735
736	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
737	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
738	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
739	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
740	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
741	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
742	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
743	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
744	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
745	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
746	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
747	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
748	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
749	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
750	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
751	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
752	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
753	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
754	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
755	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
756	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
757	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
758	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
759	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
760	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
761	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
762	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
763	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
764	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
765	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
766	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
767	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
768	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
769	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
770	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
771	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
772	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
773	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
774	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
775	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
776	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
777	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
778	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
779	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
780	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
781	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
782	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
783	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
784	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
785	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
786	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
787	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
788	}
789
790	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
791	LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
792	LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
793	LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
794	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
795	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
796
797	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
798	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
799	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
800	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
801	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
802
803	LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
804	LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
805
806	for (unsigned i=0;i<pVM->cCPUs;i++)
807	LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
808
809	#ifdef HWACCM_VTX_WITH_EPT
810	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
811	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
812	#endif /* HWACCM_VTX_WITH_EPT */
813	#ifdef HWACCM_VTX_WITH_VPID
814	if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
815	&& !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
816	pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
817	#endif /* HWACCM_VTX_WITH_VPID */
818
819	/* Only try once. */
820	pVM->hwaccm.s.fInitialized = true;
821
822	/* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
823	#if 1
824	rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
825	#else
826	rc = VERR_NO_MEMORY; /* simulation of no VMMDev Heap. */
827	#endif
828	if (RT_SUCCESS(rc))
829	{
830	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
831	ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
832	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
833	/* Bit set to 0 means redirection enabled. */
834	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
835	/* Allow all port IO, so the VT-x IO intercepts do their job. */
836	memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
837	((unsigned char )pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
838
839	/* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
840	* real and protected mode without paging with EPT.
841	*/
842	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
843	for (unsigned i=0;i<X86_PG_ENTRIES;i++)
844	{
845	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
846	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_G;
847	}
848
849	/* We convert it here every time as pci regions could be reconfigured. */
850	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
851	AssertRC(rc);
852	LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
853
854	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
855	AssertRC(rc);
856	LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
857	}
858	else
859	{
860	LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
861	pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
862	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
863	}
864
865	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
866	AssertRC(rc);
867	if (rc == VINF_SUCCESS)
868	{
869	pVM->fHWACCMEnabled = true;
870	pVM->hwaccm.s.vmx.fEnabled = true;
871	hwaccmR3DisableRawMode(pVM);
872
873	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
874	#ifdef VBOX_ENABLE_64_BITS_GUESTS
875	if (pVM->hwaccm.s.fAllow64BitGuests)
876	{
877	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
878	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
879	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
880	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
881	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
882	}
883	LogRel((pVM->hwaccm.s.fAllow64BitGuests
884	? "HWACCM: 32-bit and 64-bit guest supported.\n"
885	: "HWACCM: 32-bit guest supported.\n"));
886	#else
887	LogRel(("HWACCM: 32-bit guest supported.\n"));
888	#endif
889	LogRel(("HWACCM: VMX enabled!\n"));
890	if (pVM->hwaccm.s.fNestedPaging)
891	{
892	LogRel(("HWACCM: Enabled nested paging\n"));
893	LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetEPTCR3(pVM)));
894	}
895	if (pVM->hwaccm.s.vmx.fVPID)
896	LogRel(("HWACCM: Enabled VPID\n"));
897
898	if ( pVM->hwaccm.s.fNestedPaging
899	\|\| pVM->hwaccm.s.vmx.fVPID)
900	{
901	LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
902	LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
903	}
904	}
905	else
906	{
907	LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
908	LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
909	pVM->fHWACCMEnabled = false;
910	}
911	}
912	}
913	else
914	if (pVM->hwaccm.s.svm.fSupported)
915	{
916	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
917
918	if (pVM->hwaccm.s.fInitialized == false)
919	{
920	/* Erratum 170 which requires a forced TLB flush for each world switch:
921	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
922	*
923	* All BH-G1/2 and DH-G1/2 models include a fix:
924	* Athlon X2: 0x6b 1/2
925	* 0x68 1/2
926	* Athlon 64: 0x7f 1
927	* 0x6f 2
928	* Sempron: 0x7f 1/2
929	* 0x6f 2
930	* 0x6c 2
931	* 0x7c 2
932	* Turion 64: 0x68 2
933	*
934	*/
935	uint32_t u32Dummy;
936	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
937	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
938	u32BaseFamily= (u32Version >> 8) & 0xf;
939	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
940	u32Model = ((u32Version >> 4) & 0xf);
941	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
942	u32Stepping = u32Version & 0xf;
943	if ( u32Family == 0xf
944	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
945	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
946	{
947	LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
948	}
949
950	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
951	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
952	LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
953	LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
954	LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
955
956	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
957	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
958	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
959	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
960	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
961	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
962	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
963	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
964	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
965	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
966
967	/* Only try once. */
968	pVM->hwaccm.s.fInitialized = true;
969
970	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
971	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
972
973	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
974	AssertRC(rc);
975	if (rc == VINF_SUCCESS)
976	{
977	pVM->fHWACCMEnabled = true;
978	pVM->hwaccm.s.svm.fEnabled = true;
979
980	if (pVM->hwaccm.s.fNestedPaging)
981	LogRel(("HWACCM: Enabled nested paging\n"));
982
983	hwaccmR3DisableRawMode(pVM);
984	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
985	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
986	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
987	#ifdef VBOX_ENABLE_64_BITS_GUESTS
988	if (pVM->hwaccm.s.fAllow64BitGuests)
989	{
990	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
991	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
992	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
993	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
994	}
995	#endif
996	LogRel((pVM->hwaccm.s.fAllow64BitGuests
997	? "HWACCM: 32-bit and 64-bit guest supported.\n"
998	: "HWACCM: 32-bit guest supported.\n"));
999	}
1000	else
1001	{
1002	pVM->fHWACCMEnabled = false;
1003	}
1004	}
1005	}
1006	return VINF_SUCCESS;
1007	}
1008
1009	/**
1010	* Applies relocations to data and code managed by this
1011	* component. This function will be called at init and
1012	* whenever the VMM need to relocate it self inside the GC.
1013	*
1014	* @param pVM The VM.
1015	*/
1016	VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1017	{
1018	Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1019
1020	/* Fetch the current paging mode during the relocate callback during state loading. */
1021	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1022	{
1023	for (unsigned i=0;i<pVM->cCPUs;i++)
1024	{
1025	PVMCPU pVCpu = &pVM->aCpus[i];
1026	/* @todo SMP */
1027	pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVM);
1028	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMGetGuestMode(pVM);
1029	}
1030	}
1031	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1032	if (pVM->fHWACCMEnabled)
1033	{
1034	int rc;
1035
1036	switch(PGMGetHostMode(pVM))
1037	{
1038	case PGMMODE_32_BIT:
1039	pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1040	break;
1041
1042	case PGMMODE_PAE:
1043	case PGMMODE_PAE_NX:
1044	pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1045	break;
1046
1047	default:
1048	AssertFailed();
1049	break;
1050	}
1051	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1052	AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1053
1054	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1055	AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1056
1057	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1058	AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1059
1060	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1061	AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1062
1063	# ifdef DEBUG
1064	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1065	AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1066	# endif
1067	}
1068	#endif
1069	return;
1070	}
1071
1072	/**
1073	* Checks hardware accelerated raw mode is allowed.
1074	*
1075	* @returns boolean
1076	* @param pVM The VM to operate on.
1077	*/
1078	VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1079	{
1080	return pVM->hwaccm.s.fAllowed;
1081	}
1082
1083	/**
1084	* Notification callback which is called whenever there is a chance that a CR3
1085	* value might have changed.
1086	*
1087	* This is called by PGM.
1088	*
1089	* @param pVM The VM to operate on.
1090	* @param enmShadowMode New shadow paging mode.
1091	* @param enmGuestMode New guest paging mode.
1092	*/
1093	VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1094	{
1095	/* Ignore page mode changes during state loading. */
1096	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1097	return;
1098
1099	PVMCPU pVCpu = VMMGetCpu(pVM);
1100	pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1101
1102	if ( pVM->hwaccm.s.vmx.fEnabled
1103	&& pVM->fHWACCMEnabled)
1104	{
1105	if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1106	&& enmGuestMode >= PGMMODE_PROTECTED)
1107	{
1108	PCPUMCTX pCtx;
1109
1110	pCtx = CPUMQueryGuestCtxPtr(pVM);
1111
1112	/* After a real mode switch to protected mode we must force
1113	* CPL to 0. Our real mode emulation had to set it to 3.
1114	*/
1115	pCtx->ssHid.Attr.n.u2Dpl = 0;
1116	}
1117	}
1118
1119	if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1120	{
1121	/* Keep track of paging mode changes. */
1122	pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1123	pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1124
1125	/* Did we miss a change, because all code was executed in the recompiler? */
1126	if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1127	{
1128	Log(("HWACCMR3PagingModeChanged missed %s->%s transition (last seen %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1129	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1130	}
1131	}
1132
1133	/* Reset the contents of the read cache. */
1134	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1135	for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1136	pCache->Read.aFieldVal[j] = 0;
1137	}
1138
1139	/**
1140	* Terminates the HWACCM.
1141	*
1142	* Termination means cleaning up and freeing all resources,
1143	* the VM it self is at this point powered off or suspended.
1144	*
1145	* @returns VBox status code.
1146	* @param pVM The VM to operate on.
1147	*/
1148	VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1149	{
1150	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1151	{
1152	PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1153	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1154	}
1155	return 0;
1156	}
1157
1158	/**
1159	* Terminates the per-VCPU HWACCM.
1160	*
1161	* Termination means cleaning up and freeing all resources,
1162	* the VM it self is at this point powered off or suspended.
1163	*
1164	* @returns VBox status code.
1165	* @param pVM The VM to operate on.
1166	*/
1167	VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1168	{
1169	for (unsigned i=0;i<pVM->cCPUs;i++)
1170	{
1171	PVMCPU pVCpu = &pVM->aCpus[i];
1172
1173	if (pVCpu->hwaccm.s.paStatExitReason)
1174	{
1175	MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1176	pVCpu->hwaccm.s.paStatExitReason = NULL;
1177	pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1178	}
1179	pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1180	}
1181	return 0;
1182	}
1183
1184	/**
1185	* The VM is being reset.
1186	*
1187	* For the HWACCM component this means that any GDT/LDT/TSS monitors
1188	* needs to be removed.
1189	*
1190	* @param pVM VM handle.
1191	*/
1192	VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1193	{
1194	LogFlow(("HWACCMR3Reset:\n"));
1195
1196	if (pVM->fHWACCMEnabled)
1197	hwaccmR3DisableRawMode(pVM);
1198
1199	for (unsigned i=0;i<pVM->cCPUs;i++)
1200	{
1201	PVMCPU pVCpu = &pVM->aCpus[i];
1202
1203	/* On first entry we'll sync everything. */
1204	pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1205
1206	pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1207	pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1208
1209	pVCpu->hwaccm.s.Event.fPending = false;
1210
1211	/* Reset state information for real-mode emulation in VT-x. */
1212	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1213	pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1214	pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1215
1216	/* Reset the contents of the read cache. */
1217	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1218	for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1219	pCache->Read.aFieldVal[j] = 0;
1220
1221	/* Magic marker for searching in crash dumps. */
1222	strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1223	pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1224	}
1225	}
1226
1227	/**
1228	* Checks if we can currently use hardware accelerated raw mode.
1229	*
1230	* @returns boolean
1231	* @param pVM The VM to operate on.
1232	* @param pCtx Partial VM execution context
1233	*/
1234	VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
1235	{
1236	Assert(pVM->fHWACCMEnabled);
1237
1238	/* AMD SVM supports real & protected mode with or without paging. */
1239	if (pVM->hwaccm.s.svm.fEnabled)
1240	{
1241	pVM->hwaccm.s.fActive = true;
1242	return true;
1243	}
1244
1245	pVM->hwaccm.s.fActive = false;
1246
1247	/* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
1248	#ifdef HWACCM_VMX_EMULATE_REALMODE
1249	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1250	{
1251	if (CPUMIsGuestInRealModeEx(pCtx))
1252	{
1253	/* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
1254	* The base must also be equal to (sel << 4).
1255	*/
1256	if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
1257	&& pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
1258	\|\| pCtx->ds != (pCtx->dsHid.u64Base >> 4)
1259	\|\| pCtx->es != (pCtx->esHid.u64Base >> 4)
1260	\|\| pCtx->fs != (pCtx->fsHid.u64Base >> 4)
1261	\|\| pCtx->gs != (pCtx->gsHid.u64Base >> 4)
1262	\|\| pCtx->ss != (pCtx->ssHid.u64Base >> 4))
1263	{
1264	return false;
1265	}
1266	}
1267	else
1268	{
1269	PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
1270	/* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
1271	* from real to protected mode. (all sorts of RPL & DPL assumptions)
1272	*/
1273	PVMCPU pVCpu = VMMGetCpu(pVM);
1274
1275	if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1276	&& enmGuestMode >= PGMMODE_PROTECTED)
1277	{
1278	if ( (pCtx->cs & X86_SEL_RPL)
1279	\|\| (pCtx->ds & X86_SEL_RPL)
1280	\|\| (pCtx->es & X86_SEL_RPL)
1281	\|\| (pCtx->fs & X86_SEL_RPL)
1282	\|\| (pCtx->gs & X86_SEL_RPL)
1283	\|\| (pCtx->ss & X86_SEL_RPL))
1284	{
1285	return false;
1286	}
1287	}
1288	}
1289	}
1290	else
1291	#endif /* HWACCM_VMX_EMULATE_REALMODE */
1292	{
1293	if (!CPUMIsGuestInLongModeEx(pCtx))
1294	{
1295	/** @todo This should (probably) be set on every excursion to the REM,
1296	* however it's too risky right now. So, only apply it when we go
1297	* back to REM for real mode execution. (The XP hack below doesn't
1298	* work reliably without this.)
1299	* Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
1300	pVM->aCpus[0].hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1301
1302	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
1303	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
1304	return false;
1305
1306	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
1307	/* Windows XP; switch to protected mode; all selectors are marked not present in the
1308	* hidden registers (possible recompiler bug; see load_seg_vm) */
1309	if (pCtx->csHid.Attr.n.u1Present == 0)
1310	return false;
1311	if (pCtx->ssHid.Attr.n.u1Present == 0)
1312	return false;
1313
1314	/* Windows XP: possible same as above, but new recompiler requires new heuristics?
1315	VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
1316	/** @todo This check is actually wrong, it doesn't take the direction of the
1317	* stack segment into account. But, it does the job for now. */
1318	if (pCtx->rsp >= pCtx->ssHid.u32Limit)
1319	return false;
1320	#if 0
1321	if ( pCtx->cs >= pCtx->gdtr.cbGdt
1322	\|\| pCtx->ss >= pCtx->gdtr.cbGdt
1323	\|\| pCtx->ds >= pCtx->gdtr.cbGdt
1324	\|\| pCtx->es >= pCtx->gdtr.cbGdt
1325	\|\| pCtx->fs >= pCtx->gdtr.cbGdt
1326	\|\| pCtx->gs >= pCtx->gdtr.cbGdt)
1327	return false;
1328	#endif
1329	}
1330	}
1331
1332	if (pVM->hwaccm.s.vmx.fEnabled)
1333	{
1334	uint32_t mask;
1335
1336	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
1337	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
1338	/* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
1339	mask &= ~X86_CR0_NE;
1340
1341	#ifdef HWACCM_VMX_EMULATE_REALMODE
1342	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1343	{
1344	/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
1345	mask &= ~(X86_CR0_PG\|X86_CR0_PE);
1346	}
1347	else
1348	#endif
1349	{
1350	/* We support protected mode without paging using identity mapping. */
1351	mask &= ~X86_CR0_PG;
1352	}
1353	if ((pCtx->cr0 & mask) != mask)
1354	return false;
1355
1356	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
1357	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
1358	if ((pCtx->cr0 & mask) != 0)
1359	return false;
1360
1361	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
1362	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1363	mask &= ~X86_CR4_VMXE;
1364	if ((pCtx->cr4 & mask) != mask)
1365	return false;
1366
1367	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
1368	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
1369	if ((pCtx->cr4 & mask) != 0)
1370	return false;
1371
1372	pVM->hwaccm.s.fActive = true;
1373	return true;
1374	}
1375
1376	return false;
1377	}
1378
1379	/**
1380	* Notifcation from EM about a rescheduling into hardware assisted execution
1381	* mode.
1382	*
1383	* @param pVCpu Pointer to the current virtual cpu structure.
1384	*/
1385	VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
1386	{
1387	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1388	}
1389
1390	/**
1391	* Notifcation from EM about returning from instruction emulation (REM / EM).
1392	*
1393	* @param pVCpu Pointer to the current virtual cpu structure.
1394	*/
1395	VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
1396	{
1397	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1398	}
1399
1400	/**
1401	* Checks if we are currently using hardware accelerated raw mode.
1402	*
1403	* @returns boolean
1404	* @param pVM The VM to operate on.
1405	*/
1406	VMMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
1407	{
1408	return pVM->hwaccm.s.fActive;
1409	}
1410
1411	/**
1412	* Checks if we are currently using nested paging.
1413	*
1414	* @returns boolean
1415	* @param pVM The VM to operate on.
1416	*/
1417	VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
1418	{
1419	return pVM->hwaccm.s.fNestedPaging;
1420	}
1421
1422	/**
1423	* Checks if we are currently using VPID in VT-x mode.
1424	*
1425	* @returns boolean
1426	* @param pVM The VM to operate on.
1427	*/
1428	VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
1429	{
1430	return pVM->hwaccm.s.vmx.fVPID;
1431	}
1432
1433
1434	/**
1435	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
1436	*
1437	* @returns boolean
1438	* @param pVM The VM to operate on.
1439	*/
1440	VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
1441	{
1442	/* @todo SMP */
1443	return HWACCMIsEnabled(pVM) && pVM->aCpus[0].hwaccm.s.Event.fPending;
1444	}
1445
1446
1447	/**
1448	* Inject an NMI into a running VM
1449	*
1450	* @returns boolean
1451	* @param pVM The VM to operate on.
1452	*/
1453	VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
1454	{
1455	pVM->hwaccm.s.fInjectNMI = true;
1456	return VINF_SUCCESS;
1457	}
1458
1459	/**
1460	* Check fatal VT-x/AMD-V error and produce some meaningful
1461	* log release message.
1462	*
1463	* @param pVM The VM to operate on.
1464	* @param iStatusCode VBox status code
1465	*/
1466	VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
1467	{
1468	for (unsigned i=0;i<pVM->cCPUs;i++)
1469	{
1470	switch(iStatusCode)
1471	{
1472	case VERR_VMX_INVALID_VMCS_FIELD:
1473	break;
1474
1475	case VERR_VMX_INVALID_VMCS_PTR:
1476	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1477	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
1478	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
1479	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
1480	break;
1481
1482	case VERR_VMX_UNABLE_TO_START_VM:
1483	LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1484	LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1485	#if 0 /* @todo dump the current control fields to the release log */
1486	if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
1487	{
1488
1489	}
1490	#endif
1491	break;
1492
1493	case VERR_VMX_UNABLE_TO_RESUME_VM:
1494	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1495	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1496	break;
1497
1498	case VERR_VMX_INVALID_VMXON_PTR:
1499	break;
1500	}
1501	}
1502	}
1503
1504	/**
1505	* Execute state save operation.
1506	*
1507	* @returns VBox status code.
1508	* @param pVM VM Handle.
1509	* @param pSSM SSM operation handle.
1510	*/
1511	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
1512	{
1513	int rc;
1514
1515	Log(("hwaccmR3Save:\n"));
1516
1517	for (unsigned i=0;i<pVM->cCPUs;i++)
1518	{
1519	/*
1520	* Save the basic bits - fortunately all the other things can be resynced on load.
1521	*/
1522	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
1523	AssertRCReturn(rc, rc);
1524	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
1525	AssertRCReturn(rc, rc);
1526	rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
1527	AssertRCReturn(rc, rc);
1528
1529	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
1530	AssertRCReturn(rc, rc);
1531	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
1532	AssertRCReturn(rc, rc);
1533	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
1534	AssertRCReturn(rc, rc);
1535	}
1536
1537	return VINF_SUCCESS;
1538	}
1539
1540	/**
1541	* Execute state load operation.
1542	*
1543	* @returns VBox status code.
1544	* @param pVM VM Handle.
1545	* @param pSSM SSM operation handle.
1546	* @param u32Version Data layout version.
1547	*/
1548	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1549	{
1550	int rc;
1551
1552	Log(("hwaccmR3Load:\n"));
1553
1554	/*
1555	* Validate version.
1556	*/
1557	if ( u32Version != HWACCM_SSM_VERSION
1558	&& u32Version != HWACCM_SSM_VERSION_2_0_X)
1559	{
1560	AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
1561	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1562	}
1563	for (unsigned i=0;i<pVM->cCPUs;i++)
1564	{
1565	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
1566	AssertRCReturn(rc, rc);
1567	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
1568	AssertRCReturn(rc, rc);
1569	rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
1570	AssertRCReturn(rc, rc);
1571
1572	if (u32Version >= HWACCM_SSM_VERSION)
1573	{
1574	uint32_t val;
1575
1576	rc = SSMR3GetU32(pSSM, &val);
1577	AssertRCReturn(rc, rc);
1578	pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
1579
1580	rc = SSMR3GetU32(pSSM, &val);
1581	AssertRCReturn(rc, rc);
1582	pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
1583
1584	rc = SSMR3GetU32(pSSM, &val);
1585	AssertRCReturn(rc, rc);
1586	pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
1587	}
1588	}
1589	return VINF_SUCCESS;
1590	}
1591

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source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 15934

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