HWACCM.cpp@ 16482

Last change on this file since 16482 was 16422, checked in by vboxsync, 16 years ago
Just reinit real mode during hwaccm init
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File size: 78.6 KB

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1	/* $Id: HWACCM.cpp 16422 2009-01-30 15:21:17Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_HWACCM
26	#include <VBox/cpum.h>
27	#include <VBox/stam.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/trpm.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/patm.h>
34	#include <VBox/csam.h>
35	#include <VBox/selm.h>
36	#include <VBox/rem.h>
37	#include <VBox/hwacc_vmx.h>
38	#include <VBox/hwacc_svm.h>
39	#include "HWACCMInternal.h"
40	#include <VBox/vm.h>
41	#include <VBox/err.h>
42	#include <VBox/param.h>
43
44	#include <iprt/assert.h>
45	#include <VBox/log.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48	#include <iprt/thread.h>
49
50	/*******************************************************************************
51	* Global Variables *
52	*******************************************************************************/
53	#ifdef VBOX_WITH_STATISTICS
54	# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55	# define EXIT_REASON_NIL() NULL
56	/** Exit reason descriptions for VT-x, used to describe statistics. */
57	static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58	{
59	EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60	EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61	EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62	EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63	EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64	EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65	EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66	EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67	EXIT_REASON_NIL(),
68	EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69	EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70	EXIT_REASON_NIL(),
71	EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72	EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73	EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74	EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75	EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76	EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77	EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78	EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79	EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80	EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81	EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82	EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83	EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84	EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85	EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86	EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87	EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88	EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89	EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90	EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91	EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92	EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93	EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94	EXIT_REASON_NIL(),
95	EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96	EXIT_REASON_NIL(),
97	EXIT_REASON_NIL(),
98	EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99	EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100	EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101	EXIT_REASON_NIL(),
102	EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103	EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104	EXIT_REASON_NIL(),
105	EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106	EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107	EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108	EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109	EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110	EXIT_REASON_NIL(),
111	EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112	EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113	EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114	EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115	EXIT_REASON_NIL()
116	};
117	/** Exit reason descriptions for AMD-V, used to describe statistics. */
118	static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119	{
120	/** @todo fill in these. */
121	EXIT_REASON_NIL()
122	};
123	# undef EXIT_REASON
124	# undef EXIT_REASON_NIL
125	#endif /* VBOX_WITH_STATISTICS */
126
127	/*******************************************************************************
128	* Internal Functions *
129	*******************************************************************************/
130	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
131	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
132
133
134	/**
135	* Initializes the HWACCM.
136	*
137	* @returns VBox status code.
138	* @param pVM The VM to operate on.
139	*/
140	VMMR3DECL(int) HWACCMR3Init(PVM pVM)
141	{
142	LogFlow(("HWACCMR3Init\n"));
143
144	/*
145	* Assert alignment and sizes.
146	*/
147	AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
148	AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
149
150	/* Some structure checks. */
151	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
152	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
153	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
154	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
155
156	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
157	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
158	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
159	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
160	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
161	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
162	AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
163
164
165	/*
166	* Register the saved state data unit.
167	*/
168	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
169	NULL, hwaccmR3Save, NULL,
170	NULL, hwaccmR3Load, NULL);
171	if (RT_FAILURE(rc))
172	return rc;
173
174	/* Misc initialisation. */
175	pVM->hwaccm.s.vmx.fSupported = false;
176	pVM->hwaccm.s.svm.fSupported = false;
177	pVM->hwaccm.s.vmx.fEnabled = false;
178	pVM->hwaccm.s.svm.fEnabled = false;
179
180	pVM->hwaccm.s.fActive = false;
181	pVM->hwaccm.s.fNestedPaging = false;
182
183	/* Disabled by default. */
184	pVM->fHWACCMEnabled = false;
185
186	/*
187	* Check CFGM options.
188	*/
189	PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
190	PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
191	/* Nested paging: disabled by default. */
192	rc = CFGMR3QueryBoolDef(pRoot, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
193	AssertRC(rc);
194
195	/* VT-x VPID: disabled by default. */
196	rc = CFGMR3QueryBoolDef(pRoot, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
197	AssertRC(rc);
198
199	/* HWACCM support must be explicitely enabled in the configuration file. */
200	rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
201	AssertRC(rc);
202
203	#ifdef RT_OS_DARWIN
204	if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
205	#else
206	if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
207	#endif
208	{
209	AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
210	VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
211	return VERR_HWACCM_CONFIG_MISMATCH;
212	}
213
214	if (VMMIsHwVirtExtForced(pVM))
215	pVM->fHWACCMEnabled = true;
216
217	#if HC_ARCH_BITS == 32
218	/* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
219	* (To use the default, don't set 64bitEnabled in CFGM.) */
220	rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
221	AssertLogRelRCReturn(rc, rc);
222	if (pVM->hwaccm.s.fAllow64BitGuests)
223	{
224	# ifdef RT_OS_DARWIN
225	if (!VMMIsHwVirtExtForced(pVM))
226	# else
227	if (!pVM->hwaccm.s.fAllowed)
228	# endif
229	return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling VT-x.");
230	}
231	#else
232	/* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
233	* via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
234	rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
235	AssertLogRelRCReturn(rc, rc);
236	#endif
237
238	return VINF_SUCCESS;
239	}
240
241	/**
242	* Initializes the per-VCPU HWACCM.
243	*
244	* @returns VBox status code.
245	* @param pVM The VM to operate on.
246	*/
247	VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
248	{
249	LogFlow(("HWACCMR3InitCPU\n"));
250
251	#ifdef VBOX_WITH_STATISTICS
252	/*
253	* Statistics.
254	*/
255	for (unsigned i=0;i<pVM->cCPUs;i++)
256	{
257	PVMCPU pVCpu = &pVM->aCpus[i];
258	int rc;
259
260	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
261	"/PROF/HWACCM/CPU%d/SwitchToGC", i);
262	AssertRC(rc);
263	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
264	"/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
265	AssertRC(rc);
266	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
267	"/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
268	AssertRC(rc);
269	# if 1 /* temporary for tracking down darwin holdup. */
270	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
271	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
272	AssertRC(rc);
273	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
274	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
275	AssertRC(rc);
276	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
277	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
278	AssertRC(rc);
279	# endif
280	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
281	"/PROF/HWACCM/CPU%d/InGC", i);
282	AssertRC(rc);
283
284	# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
285	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
286	"/PROF/HWACCM/CPU%d/Switcher3264", i);
287	AssertRC(rc);
288	# endif
289
290	# define HWACCM_REG_COUNTER(a, b) \
291	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
292	AssertRC(rc);
293
294	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
295	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
296	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
297	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
298	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
299	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
300	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
301	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
302	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
303	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
304	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
305	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
306	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
307	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
308	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
309	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
310	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
311	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
312	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
313	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
314	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
315	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
316	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
317	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
318	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
319
320	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
321	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
322
323	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
324	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
325	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
326
327	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
328	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
329	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
330	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
331	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
332	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
333	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
334	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
335	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
336
337	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
338	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
339
340	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
341	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
342	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
343
344	for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
345	{
346	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
347	"/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
348	AssertRC(rc);
349	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
350	"/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
351	AssertRC(rc);
352	}
353
354	#undef HWACCM_REG_COUNTER
355
356	pVCpu->hwaccm.s.paStatExitReason = NULL;
357
358	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
359	AssertRC(rc);
360	if (RT_SUCCESS(rc))
361	{
362	const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
363	for (int j=0;j<MAX_EXITREASON_STAT;j++)
364	{
365	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
366	papszDesc[j] ? papszDesc[j] : "Exit reason",
367	"/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
368	AssertRC(rc);
369	}
370	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
371	AssertRC(rc);
372	}
373	pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
374	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
375	Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
376	# else
377	Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
378	# endif
379	}
380	#endif /* VBOX_WITH_STATISTICS */
381
382	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
383	/* Magic marker for searching in crash dumps. */
384	for (unsigned i=0;i<pVM->cCPUs;i++)
385	{
386	PVMCPU pVCpu = &pVM->aCpus[i];
387
388	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
389	strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
390	pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
391	}
392	#endif
393	return VINF_SUCCESS;
394	}
395
396	/**
397	* Turns off normal raw mode features
398	*
399	* @param pVM The VM to operate on.
400	*/
401	static void hwaccmR3DisableRawMode(PVM pVM)
402	{
403	/* Disable PATM & CSAM. */
404	PATMR3AllowPatching(pVM, false);
405	CSAMDisableScanning(pVM);
406
407	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
408	SELMR3DisableMonitoring(pVM);
409	TRPMR3DisableMonitoring(pVM);
410
411	/* The hidden selector registers are now valid. */
412	CPUMSetHiddenSelRegsValid(pVM, true);
413
414	/* Disable the switcher code (safety precaution). */
415	VMMR3DisableSwitcher(pVM);
416
417	/* Disable mapping of the hypervisor into the shadow page table. */
418	PGMR3MappingsDisable(pVM);
419
420	/* Disable the switcher */
421	VMMR3DisableSwitcher(pVM);
422
423	/* Reinit the paging mode to force the new shadow mode. */
424	PGMR3ChangeMode(pVM, PGMMODE_REAL);
425	}
426
427	/**
428	* Initialize VT-x or AMD-V.
429	*
430	* @returns VBox status code.
431	* @param pVM The VM handle.
432	*/
433	VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
434	{
435	int rc;
436
437	if ( !pVM->hwaccm.s.vmx.fSupported
438	&& !pVM->hwaccm.s.svm.fSupported)
439	{
440	LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
441	LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
442	#ifdef RT_OS_DARWIN
443	if (VMMIsHwVirtExtForced(pVM))
444	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
445	#endif
446	return VINF_SUCCESS;
447	}
448
449	/*
450	* Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
451	* because it turns off paging, which is not allowed in VMX root mode.
452	*
453	* To simplify matters we'll just force all running VMs to either use raw or VT-x mode. No mixing allowed in the VT-x case.
454	* There's no such problem with AMD-V. (@todo)
455	*
456	*/
457	/* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
458	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
459	if (RT_FAILURE(rc))
460	{
461	LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
462	LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
463
464	#ifdef RT_OS_DARWIN
465	/*
466	* This is 100% fatal if we didn't prepare for a HwVirtExt setup because of
467	* missing ring-0 allocations. For VMs that require HwVirtExt it doesn't normally
468	* make sense to try run them in software mode, so fail that too.
469	*/
470	if (VMMIsHwVirtExtForced(pVM))
471	VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to "
472	"simultaneously use VT-x.");
473	else
474	VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not "
475	"allowed to simultaneously use software virtualization.");
476	return rc;
477
478	#else /* !RT_OS_DARWIN */
479
480	/* Invert the selection */
481	pVM->hwaccm.s.fAllowed ^= 1;
482	if (pVM->hwaccm.s.fAllowed)
483	{
484	if (pVM->hwaccm.s.vmx.fSupported)
485	VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not allowed "
486	"to simultaneously use software virtualization.\n");
487	else
488	VM_SET_ERROR(pVM, rc, "An active VM already uses AMD-V hardware acceleration. It is not allowed to "
489	"simultaneously use software virtualization.\n");
490	}
491	else
492	VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to simultaneously "
493	"use VT-x or AMD-V.\n");
494	return rc;
495	#endif /* !RT_OS_DARWIN */
496	}
497
498	if (pVM->hwaccm.s.fAllowed == false)
499	return VINF_SUCCESS; /* disabled */
500
501	Assert(!pVM->fHWACCMEnabled \|\| VMMIsHwVirtExtForced(pVM));
502
503	if (pVM->hwaccm.s.vmx.fSupported)
504	{
505	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
506
507	if ( pVM->hwaccm.s.fInitialized == false
508	&& pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
509	{
510	uint64_t val;
511	RTGCPHYS GCPhys = 0;
512
513	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
514	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
515	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
516	LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
517	LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
518	LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
519	LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
520	LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
521
522	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
523	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
524	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
525	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
526	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
527	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
528	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
529	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
530	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
531	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
532	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
533	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
534	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT must be set\n"));
535	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
536	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT must be set\n"));
537	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
538	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI must be set\n"));
539	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
540	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER must be set\n"));
541
542	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
543	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
544	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
545	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
546	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
547	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
548	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
549	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
550	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
551	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
552	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
553	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
554	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
555	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
556	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
557	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
558	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
559	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
560	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
561	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
562	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
563	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
564	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
565	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
566	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
567	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
568	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
569	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
570	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
571	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
572	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
573	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
574	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
575	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
576	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
577	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
578	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
579	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
580	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
581	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
582	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
583	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
584	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
585	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
586
587	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
588	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
589	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT must be set\n"));
590	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
591	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET must be set\n"));
592	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
593	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT must be set\n"));
594	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
595	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT must be set\n"));
596	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
597	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT must be set\n"));
598	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
599	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT must be set\n"));
600	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
601	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT must be set\n"));
602	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
603	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT must be set\n"));
604	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
605	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT must be set\n"));
606	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
607	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT must be set\n"));
608	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
609	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT must be set\n"));
610	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
611	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW must be set\n"));
612	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
613	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT must be set\n"));
614	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
615	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT must be set\n"));
616	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
617	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT must be set\n"));
618	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
619	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS must be set\n"));
620	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
621	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG must be set\n"));
622	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
623	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS must be set\n"));
624	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
625	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT must be set\n"));
626	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
627	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT must be set\n"));
628	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
629	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL must be set\n"));
630
631	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
632	{
633	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
634	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
635	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
636	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
637	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
638	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
639	if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
640	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
641	if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
642	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
643	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
644	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
645	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
646	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
647
648	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
649	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
650	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC must be set\n"));
651	if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
652	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT must be set\n"));
653	if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
654	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC must be set\n"));
655	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
656	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT must be set\n"));
657	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
658	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID must be set\n"));
659	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
660	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT must be set\n"));
661	}
662
663	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
664	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
665	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
666	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
667	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
668	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
669	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
670	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
671	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
672	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
673	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
674	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
675	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
676	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
677	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
678	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
679	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
680	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
681	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG must be set\n"));
682	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
683	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE must be set\n"));
684	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
685	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM must be set\n"));
686	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
687	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON must be set\n"));
688	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
689	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR must be set\n"));
690	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
691	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR must be set\n"));
692	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
693	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR must be set\n"));
694
695	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
696	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
697	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
698	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
699	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
700	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
701	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
702	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
703	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
704	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
705	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
706	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
707	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
708	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
709	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
710	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
711	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
712	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
713	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
714	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
715	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG must be set\n"));
716	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
717	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 must be set\n"));
718	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
719	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ must be set\n"));
720	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
721	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR must be set\n"));
722	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
723	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR must be set\n"));
724	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
725	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR must be set\n"));
726	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
727	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR must be set\n"));
728	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
729	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER must be set\n"));
730
731	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
732	{
733	LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
734
735	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
736	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
737	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
738	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
739	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
740	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
741	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
742	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
743	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
744	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
745	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
746	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
747	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
748	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
749	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
750	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
751	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
752	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
753	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
754	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
755	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
756	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
757	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
758	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
759	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
760	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
761	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
762	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
763	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
764	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
765	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
766	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
767	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
768	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
769	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
770	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
771	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
772	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
773	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
774	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
775	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
776	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
777	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
778	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
779	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
780	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
781	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
782	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
783	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
784	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
785	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
786	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
787	}
788
789	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
790	LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
791	LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
792	LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
793	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
794	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
795
796	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
797	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
798	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
799	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
800	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
801
802	LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
803	LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
804
805	for (unsigned i=0;i<pVM->cCPUs;i++)
806	LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
807
808	#ifdef HWACCM_VTX_WITH_EPT
809	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
810	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
811	#endif /* HWACCM_VTX_WITH_EPT */
812	#ifdef HWACCM_VTX_WITH_VPID
813	if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
814	&& !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
815	pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
816	#endif /* HWACCM_VTX_WITH_VPID */
817
818	/* Only try once. */
819	pVM->hwaccm.s.fInitialized = true;
820
821	/* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
822	#if 1
823	rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
824	#else
825	rc = VERR_NO_MEMORY; /* simulation of no VMMDev Heap. */
826	#endif
827	if (RT_SUCCESS(rc))
828	{
829	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
830	ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
831	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
832	/* Bit set to 0 means redirection enabled. */
833	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
834	/* Allow all port IO, so the VT-x IO intercepts do their job. */
835	memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
836	((unsigned char )pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
837
838	/* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
839	* real and protected mode without paging with EPT.
840	*/
841	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
842	for (unsigned i=0;i<X86_PG_ENTRIES;i++)
843	{
844	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
845	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_G;
846	}
847
848	/* We convert it here every time as pci regions could be reconfigured. */
849	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
850	AssertRC(rc);
851	LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
852
853	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
854	AssertRC(rc);
855	LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
856	}
857	else
858	{
859	LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
860	pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
861	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
862	}
863
864	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
865	AssertRC(rc);
866	if (rc == VINF_SUCCESS)
867	{
868	pVM->fHWACCMEnabled = true;
869	pVM->hwaccm.s.vmx.fEnabled = true;
870	hwaccmR3DisableRawMode(pVM);
871
872	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
873	#ifdef VBOX_ENABLE_64_BITS_GUESTS
874	if (pVM->hwaccm.s.fAllow64BitGuests)
875	{
876	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
877	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
878	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
879	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
880	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
881	}
882	LogRel((pVM->hwaccm.s.fAllow64BitGuests
883	? "HWACCM: 32-bit and 64-bit guest supported.\n"
884	: "HWACCM: 32-bit guest supported.\n"));
885	#else
886	LogRel(("HWACCM: 32-bit guest supported.\n"));
887	#endif
888	LogRel(("HWACCM: VMX enabled!\n"));
889	if (pVM->hwaccm.s.fNestedPaging)
890	{
891	LogRel(("HWACCM: Enabled nested paging\n"));
892	LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetEPTCR3(pVM)));
893	}
894	if (pVM->hwaccm.s.vmx.fVPID)
895	LogRel(("HWACCM: Enabled VPID\n"));
896
897	if ( pVM->hwaccm.s.fNestedPaging
898	\|\| pVM->hwaccm.s.vmx.fVPID)
899	{
900	LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
901	LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
902	}
903	}
904	else
905	{
906	LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
907	LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
908	pVM->fHWACCMEnabled = false;
909	}
910	}
911	}
912	else
913	if (pVM->hwaccm.s.svm.fSupported)
914	{
915	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
916
917	if (pVM->hwaccm.s.fInitialized == false)
918	{
919	/* Erratum 170 which requires a forced TLB flush for each world switch:
920	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
921	*
922	* All BH-G1/2 and DH-G1/2 models include a fix:
923	* Athlon X2: 0x6b 1/2
924	* 0x68 1/2
925	* Athlon 64: 0x7f 1
926	* 0x6f 2
927	* Sempron: 0x7f 1/2
928	* 0x6f 2
929	* 0x6c 2
930	* 0x7c 2
931	* Turion 64: 0x68 2
932	*
933	*/
934	uint32_t u32Dummy;
935	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
936	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
937	u32BaseFamily= (u32Version >> 8) & 0xf;
938	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
939	u32Model = ((u32Version >> 4) & 0xf);
940	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
941	u32Stepping = u32Version & 0xf;
942	if ( u32Family == 0xf
943	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
944	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
945	{
946	LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
947	}
948
949	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
950	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
951	LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
952	LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
953	LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
954
955	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
956	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
957	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
958	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
959	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
960	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
961	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
962	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
963	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
964	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
965
966	/* Only try once. */
967	pVM->hwaccm.s.fInitialized = true;
968
969	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
970	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
971
972	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
973	AssertRC(rc);
974	if (rc == VINF_SUCCESS)
975	{
976	pVM->fHWACCMEnabled = true;
977	pVM->hwaccm.s.svm.fEnabled = true;
978
979	if (pVM->hwaccm.s.fNestedPaging)
980	LogRel(("HWACCM: Enabled nested paging\n"));
981
982	hwaccmR3DisableRawMode(pVM);
983	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
984	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
985	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
986	#ifdef VBOX_ENABLE_64_BITS_GUESTS
987	if (pVM->hwaccm.s.fAllow64BitGuests)
988	{
989	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
990	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
991	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
992	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
993	}
994	#endif
995	LogRel((pVM->hwaccm.s.fAllow64BitGuests
996	? "HWACCM: 32-bit and 64-bit guest supported.\n"
997	: "HWACCM: 32-bit guest supported.\n"));
998	}
999	else
1000	{
1001	pVM->fHWACCMEnabled = false;
1002	}
1003	}
1004	}
1005	return VINF_SUCCESS;
1006	}
1007
1008	/**
1009	* Applies relocations to data and code managed by this
1010	* component. This function will be called at init and
1011	* whenever the VMM need to relocate it self inside the GC.
1012	*
1013	* @param pVM The VM.
1014	*/
1015	VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1016	{
1017	Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1018
1019	/* Fetch the current paging mode during the relocate callback during state loading. */
1020	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1021	{
1022	for (unsigned i=0;i<pVM->cCPUs;i++)
1023	{
1024	PVMCPU pVCpu = &pVM->aCpus[i];
1025	/* @todo SMP */
1026	pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVM);
1027	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMGetGuestMode(pVM);
1028	}
1029	}
1030	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1031	if (pVM->fHWACCMEnabled)
1032	{
1033	int rc;
1034
1035	switch(PGMGetHostMode(pVM))
1036	{
1037	case PGMMODE_32_BIT:
1038	pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1039	break;
1040
1041	case PGMMODE_PAE:
1042	case PGMMODE_PAE_NX:
1043	pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1044	break;
1045
1046	default:
1047	AssertFailed();
1048	break;
1049	}
1050	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1051	AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1052
1053	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1054	AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1055
1056	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1057	AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1058
1059	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1060	AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1061
1062	# ifdef DEBUG
1063	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1064	AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1065	# endif
1066	}
1067	#endif
1068	return;
1069	}
1070
1071	/**
1072	* Checks hardware accelerated raw mode is allowed.
1073	*
1074	* @returns boolean
1075	* @param pVM The VM to operate on.
1076	*/
1077	VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1078	{
1079	return pVM->hwaccm.s.fAllowed;
1080	}
1081
1082	/**
1083	* Notification callback which is called whenever there is a chance that a CR3
1084	* value might have changed.
1085	*
1086	* This is called by PGM.
1087	*
1088	* @param pVM The VM to operate on.
1089	* @param enmShadowMode New shadow paging mode.
1090	* @param enmGuestMode New guest paging mode.
1091	*/
1092	VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1093	{
1094	/* Ignore page mode changes during state loading. */
1095	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1096	return;
1097
1098	PVMCPU pVCpu = VMMGetCpu(pVM);
1099	pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1100
1101	if ( pVM->hwaccm.s.vmx.fEnabled
1102	&& pVM->fHWACCMEnabled)
1103	{
1104	if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1105	&& enmGuestMode >= PGMMODE_PROTECTED)
1106	{
1107	PCPUMCTX pCtx;
1108
1109	pCtx = CPUMQueryGuestCtxPtr(pVM);
1110
1111	/* After a real mode switch to protected mode we must force
1112	* CPL to 0. Our real mode emulation had to set it to 3.
1113	*/
1114	pCtx->ssHid.Attr.n.u2Dpl = 0;
1115	}
1116	}
1117
1118	if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1119	{
1120	/* Keep track of paging mode changes. */
1121	pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1122	pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1123
1124	/* Did we miss a change, because all code was executed in the recompiler? */
1125	if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1126	{
1127	Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1128	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1129	}
1130	}
1131
1132	/* Reset the contents of the read cache. */
1133	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1134	for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1135	pCache->Read.aFieldVal[j] = 0;
1136	}
1137
1138	/**
1139	* Terminates the HWACCM.
1140	*
1141	* Termination means cleaning up and freeing all resources,
1142	* the VM it self is at this point powered off or suspended.
1143	*
1144	* @returns VBox status code.
1145	* @param pVM The VM to operate on.
1146	*/
1147	VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1148	{
1149	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1150	{
1151	PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1152	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1153	}
1154	HWACCMR3TermCPU(pVM);
1155	return 0;
1156	}
1157
1158	/**
1159	* Terminates the per-VCPU HWACCM.
1160	*
1161	* Termination means cleaning up and freeing all resources,
1162	* the VM it self is at this point powered off or suspended.
1163	*
1164	* @returns VBox status code.
1165	* @param pVM The VM to operate on.
1166	*/
1167	VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1168	{
1169	for (unsigned i=0;i<pVM->cCPUs;i++)
1170	{
1171	PVMCPU pVCpu = &pVM->aCpus[i];
1172
1173	if (pVCpu->hwaccm.s.paStatExitReason)
1174	{
1175	MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1176	pVCpu->hwaccm.s.paStatExitReason = NULL;
1177	pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1178	}
1179	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1180	memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1181	pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1182	pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1183	#endif
1184	}
1185	return 0;
1186	}
1187
1188	/**
1189	* The VM is being reset.
1190	*
1191	* For the HWACCM component this means that any GDT/LDT/TSS monitors
1192	* needs to be removed.
1193	*
1194	* @param pVM VM handle.
1195	*/
1196	VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1197	{
1198	LogFlow(("HWACCMR3Reset:\n"));
1199
1200	if (pVM->fHWACCMEnabled)
1201	hwaccmR3DisableRawMode(pVM);
1202
1203	for (unsigned i=0;i<pVM->cCPUs;i++)
1204	{
1205	PVMCPU pVCpu = &pVM->aCpus[i];
1206
1207	/* On first entry we'll sync everything. */
1208	pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1209
1210	pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1211	pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1212
1213	pVCpu->hwaccm.s.Event.fPending = false;
1214
1215	/* Reset state information for real-mode emulation in VT-x. */
1216	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1217	pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1218	pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1219
1220	/* Reset the contents of the read cache. */
1221	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1222	for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1223	pCache->Read.aFieldVal[j] = 0;
1224
1225	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1226	/* Magic marker for searching in crash dumps. */
1227	strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1228	pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1229	#endif
1230	}
1231	}
1232
1233	/**
1234	* Checks if we can currently use hardware accelerated raw mode.
1235	*
1236	* @returns boolean
1237	* @param pVM The VM to operate on.
1238	* @param pCtx Partial VM execution context
1239	*/
1240	VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
1241	{
1242	Assert(pVM->fHWACCMEnabled);
1243
1244	/* AMD SVM supports real & protected mode with or without paging. */
1245	if (pVM->hwaccm.s.svm.fEnabled)
1246	{
1247	pVM->hwaccm.s.fActive = true;
1248	return true;
1249	}
1250
1251	pVM->hwaccm.s.fActive = false;
1252
1253	/* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
1254	#ifdef HWACCM_VMX_EMULATE_REALMODE
1255	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1256	{
1257	if (CPUMIsGuestInRealModeEx(pCtx))
1258	{
1259	/* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
1260	* The base must also be equal to (sel << 4).
1261	*/
1262	if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
1263	&& pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
1264	\|\| pCtx->ds != (pCtx->dsHid.u64Base >> 4)
1265	\|\| pCtx->es != (pCtx->esHid.u64Base >> 4)
1266	\|\| pCtx->fs != (pCtx->fsHid.u64Base >> 4)
1267	\|\| pCtx->gs != (pCtx->gsHid.u64Base >> 4)
1268	\|\| pCtx->ss != (pCtx->ssHid.u64Base >> 4))
1269	{
1270	return false;
1271	}
1272	}
1273	else
1274	{
1275	PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
1276	/* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
1277	* from real to protected mode. (all sorts of RPL & DPL assumptions)
1278	*/
1279	PVMCPU pVCpu = VMMGetCpu(pVM);
1280
1281	if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1282	&& enmGuestMode >= PGMMODE_PROTECTED)
1283	{
1284	if ( (pCtx->cs & X86_SEL_RPL)
1285	\|\| (pCtx->ds & X86_SEL_RPL)
1286	\|\| (pCtx->es & X86_SEL_RPL)
1287	\|\| (pCtx->fs & X86_SEL_RPL)
1288	\|\| (pCtx->gs & X86_SEL_RPL)
1289	\|\| (pCtx->ss & X86_SEL_RPL))
1290	{
1291	return false;
1292	}
1293	}
1294	}
1295	}
1296	else
1297	#endif /* HWACCM_VMX_EMULATE_REALMODE */
1298	{
1299	if (!CPUMIsGuestInLongModeEx(pCtx))
1300	{
1301	/** @todo This should (probably) be set on every excursion to the REM,
1302	* however it's too risky right now. So, only apply it when we go
1303	* back to REM for real mode execution. (The XP hack below doesn't
1304	* work reliably without this.)
1305	* Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
1306	pVM->aCpus[0].hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1307
1308	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
1309	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
1310	return false;
1311
1312	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
1313	/* Windows XP; switch to protected mode; all selectors are marked not present in the
1314	* hidden registers (possible recompiler bug; see load_seg_vm) */
1315	if (pCtx->csHid.Attr.n.u1Present == 0)
1316	return false;
1317	if (pCtx->ssHid.Attr.n.u1Present == 0)
1318	return false;
1319
1320	/* Windows XP: possible same as above, but new recompiler requires new heuristics?
1321	VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
1322	/** @todo This check is actually wrong, it doesn't take the direction of the
1323	* stack segment into account. But, it does the job for now. */
1324	if (pCtx->rsp >= pCtx->ssHid.u32Limit)
1325	return false;
1326	#if 0
1327	if ( pCtx->cs >= pCtx->gdtr.cbGdt
1328	\|\| pCtx->ss >= pCtx->gdtr.cbGdt
1329	\|\| pCtx->ds >= pCtx->gdtr.cbGdt
1330	\|\| pCtx->es >= pCtx->gdtr.cbGdt
1331	\|\| pCtx->fs >= pCtx->gdtr.cbGdt
1332	\|\| pCtx->gs >= pCtx->gdtr.cbGdt)
1333	return false;
1334	#endif
1335	}
1336	}
1337
1338	if (pVM->hwaccm.s.vmx.fEnabled)
1339	{
1340	uint32_t mask;
1341
1342	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
1343	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
1344	/* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
1345	mask &= ~X86_CR0_NE;
1346
1347	#ifdef HWACCM_VMX_EMULATE_REALMODE
1348	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1349	{
1350	/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
1351	mask &= ~(X86_CR0_PG\|X86_CR0_PE);
1352	}
1353	else
1354	#endif
1355	{
1356	/* We support protected mode without paging using identity mapping. */
1357	mask &= ~X86_CR0_PG;
1358	}
1359	if ((pCtx->cr0 & mask) != mask)
1360	return false;
1361
1362	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
1363	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
1364	if ((pCtx->cr0 & mask) != 0)
1365	return false;
1366
1367	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
1368	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1369	mask &= ~X86_CR4_VMXE;
1370	if ((pCtx->cr4 & mask) != mask)
1371	return false;
1372
1373	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
1374	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
1375	if ((pCtx->cr4 & mask) != 0)
1376	return false;
1377
1378	pVM->hwaccm.s.fActive = true;
1379	return true;
1380	}
1381
1382	return false;
1383	}
1384
1385	/**
1386	* Notifcation from EM about a rescheduling into hardware assisted execution
1387	* mode.
1388	*
1389	* @param pVCpu Pointer to the current virtual cpu structure.
1390	*/
1391	VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
1392	{
1393	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1394	}
1395
1396	/**
1397	* Notifcation from EM about returning from instruction emulation (REM / EM).
1398	*
1399	* @param pVCpu Pointer to the current virtual cpu structure.
1400	*/
1401	VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
1402	{
1403	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1404	}
1405
1406	/**
1407	* Checks if we are currently using hardware accelerated raw mode.
1408	*
1409	* @returns boolean
1410	* @param pVM The VM to operate on.
1411	*/
1412	VMMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
1413	{
1414	return pVM->hwaccm.s.fActive;
1415	}
1416
1417	/**
1418	* Checks if we are currently using nested paging.
1419	*
1420	* @returns boolean
1421	* @param pVM The VM to operate on.
1422	*/
1423	VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
1424	{
1425	return pVM->hwaccm.s.fNestedPaging;
1426	}
1427
1428	/**
1429	* Checks if we are currently using VPID in VT-x mode.
1430	*
1431	* @returns boolean
1432	* @param pVM The VM to operate on.
1433	*/
1434	VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
1435	{
1436	return pVM->hwaccm.s.vmx.fVPID;
1437	}
1438
1439
1440	/**
1441	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
1442	*
1443	* @returns boolean
1444	* @param pVM The VM to operate on.
1445	*/
1446	VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
1447	{
1448	/* @todo SMP */
1449	return HWACCMIsEnabled(pVM) && pVM->aCpus[0].hwaccm.s.Event.fPending;
1450	}
1451
1452
1453	/**
1454	* Inject an NMI into a running VM
1455	*
1456	* @returns boolean
1457	* @param pVM The VM to operate on.
1458	*/
1459	VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
1460	{
1461	pVM->hwaccm.s.fInjectNMI = true;
1462	return VINF_SUCCESS;
1463	}
1464
1465	/**
1466	* Check fatal VT-x/AMD-V error and produce some meaningful
1467	* log release message.
1468	*
1469	* @param pVM The VM to operate on.
1470	* @param iStatusCode VBox status code
1471	*/
1472	VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
1473	{
1474	for (unsigned i=0;i<pVM->cCPUs;i++)
1475	{
1476	switch(iStatusCode)
1477	{
1478	case VERR_VMX_INVALID_VMCS_FIELD:
1479	break;
1480
1481	case VERR_VMX_INVALID_VMCS_PTR:
1482	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1483	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
1484	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
1485	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
1486	break;
1487
1488	case VERR_VMX_UNABLE_TO_START_VM:
1489	LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1490	LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1491	#if 0 /* @todo dump the current control fields to the release log */
1492	if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
1493	{
1494
1495	}
1496	#endif
1497	break;
1498
1499	case VERR_VMX_UNABLE_TO_RESUME_VM:
1500	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1501	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1502	break;
1503
1504	case VERR_VMX_INVALID_VMXON_PTR:
1505	break;
1506	}
1507	}
1508	}
1509
1510	/**
1511	* Execute state save operation.
1512	*
1513	* @returns VBox status code.
1514	* @param pVM VM Handle.
1515	* @param pSSM SSM operation handle.
1516	*/
1517	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
1518	{
1519	int rc;
1520
1521	Log(("hwaccmR3Save:\n"));
1522
1523	for (unsigned i=0;i<pVM->cCPUs;i++)
1524	{
1525	/*
1526	* Save the basic bits - fortunately all the other things can be resynced on load.
1527	*/
1528	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
1529	AssertRCReturn(rc, rc);
1530	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
1531	AssertRCReturn(rc, rc);
1532	rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
1533	AssertRCReturn(rc, rc);
1534
1535	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
1536	AssertRCReturn(rc, rc);
1537	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
1538	AssertRCReturn(rc, rc);
1539	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
1540	AssertRCReturn(rc, rc);
1541	}
1542
1543	return VINF_SUCCESS;
1544	}
1545
1546	/**
1547	* Execute state load operation.
1548	*
1549	* @returns VBox status code.
1550	* @param pVM VM Handle.
1551	* @param pSSM SSM operation handle.
1552	* @param u32Version Data layout version.
1553	*/
1554	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1555	{
1556	int rc;
1557
1558	Log(("hwaccmR3Load:\n"));
1559
1560	/*
1561	* Validate version.
1562	*/
1563	if ( u32Version != HWACCM_SSM_VERSION
1564	&& u32Version != HWACCM_SSM_VERSION_2_0_X)
1565	{
1566	AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
1567	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1568	}
1569	for (unsigned i=0;i<pVM->cCPUs;i++)
1570	{
1571	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
1572	AssertRCReturn(rc, rc);
1573	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
1574	AssertRCReturn(rc, rc);
1575	rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
1576	AssertRCReturn(rc, rc);
1577
1578	if (u32Version >= HWACCM_SSM_VERSION)
1579	{
1580	uint32_t val;
1581
1582	rc = SSMR3GetU32(pSSM, &val);
1583	AssertRCReturn(rc, rc);
1584	pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
1585
1586	rc = SSMR3GetU32(pSSM, &val);
1587	AssertRCReturn(rc, rc);
1588	pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
1589
1590	rc = SSMR3GetU32(pSSM, &val);
1591	AssertRCReturn(rc, rc);
1592	pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
1593	}
1594	}
1595	return VINF_SUCCESS;
1596	}
1597

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source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 16482

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