HWACCM.cpp@ 17522

Last change on this file since 17522 was 17489, checked in by vboxsync, 16 years ago
Don't use a special root for nested paging anymore.
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1	/* $Id: HWACCM.cpp 17489 2009-03-06 16:35:33Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_HWACCM
26	#include <VBox/cpum.h>
27	#include <VBox/stam.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/trpm.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/patm.h>
34	#include <VBox/csam.h>
35	#include <VBox/selm.h>
36	#include <VBox/rem.h>
37	#include <VBox/hwacc_vmx.h>
38	#include <VBox/hwacc_svm.h>
39	#include "HWACCMInternal.h"
40	#include <VBox/vm.h>
41	#include <VBox/err.h>
42	#include <VBox/param.h>
43
44	#include <iprt/assert.h>
45	#include <VBox/log.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48	#include <iprt/thread.h>
49
50	/*******************************************************************************
51	* Global Variables *
52	*******************************************************************************/
53	#ifdef VBOX_WITH_STATISTICS
54	# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55	# define EXIT_REASON_NIL() NULL
56	/** Exit reason descriptions for VT-x, used to describe statistics. */
57	static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58	{
59	EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60	EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61	EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62	EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63	EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64	EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65	EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66	EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67	EXIT_REASON_NIL(),
68	EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69	EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70	EXIT_REASON_NIL(),
71	EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72	EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73	EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74	EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75	EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76	EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77	EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78	EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79	EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80	EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81	EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82	EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83	EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84	EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85	EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86	EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87	EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88	EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89	EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90	EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91	EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92	EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93	EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94	EXIT_REASON_NIL(),
95	EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96	EXIT_REASON_NIL(),
97	EXIT_REASON_NIL(),
98	EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99	EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100	EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101	EXIT_REASON_NIL(),
102	EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103	EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104	EXIT_REASON_NIL(),
105	EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106	EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107	EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108	EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109	EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110	EXIT_REASON_NIL(),
111	EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112	EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113	EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114	EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115	EXIT_REASON_NIL()
116	};
117	/** Exit reason descriptions for AMD-V, used to describe statistics. */
118	static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119	{
120	/** @todo fill in these. */
121	EXIT_REASON_NIL()
122	};
123	# undef EXIT_REASON
124	# undef EXIT_REASON_NIL
125	#endif /* VBOX_WITH_STATISTICS */
126
127	/*******************************************************************************
128	* Internal Functions *
129	*******************************************************************************/
130	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
131	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
132
133
134	/**
135	* Initializes the HWACCM.
136	*
137	* @returns VBox status code.
138	* @param pVM The VM to operate on.
139	*/
140	VMMR3DECL(int) HWACCMR3Init(PVM pVM)
141	{
142	LogFlow(("HWACCMR3Init\n"));
143
144	/*
145	* Assert alignment and sizes.
146	*/
147	AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
148	AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
149
150	/* Some structure checks. */
151	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
152	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
153	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
154	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
155
156	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
157	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
158	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
159	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
160	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
161	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
162	AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
163
164
165	/*
166	* Register the saved state data unit.
167	*/
168	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
169	NULL, hwaccmR3Save, NULL,
170	NULL, hwaccmR3Load, NULL);
171	if (RT_FAILURE(rc))
172	return rc;
173
174	/* Misc initialisation. */
175	pVM->hwaccm.s.vmx.fSupported = false;
176	pVM->hwaccm.s.svm.fSupported = false;
177	pVM->hwaccm.s.vmx.fEnabled = false;
178	pVM->hwaccm.s.svm.fEnabled = false;
179
180	pVM->hwaccm.s.fActive = false;
181	pVM->hwaccm.s.fNestedPaging = false;
182
183	/* Disabled by default. */
184	pVM->fHWACCMEnabled = false;
185
186	/*
187	* Check CFGM options.
188	*/
189	PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
190	PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
191	/* Nested paging: disabled by default. */
192	rc = CFGMR3QueryBoolDef(pRoot, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
193	AssertRC(rc);
194
195	/* VT-x VPID: disabled by default. */
196	rc = CFGMR3QueryBoolDef(pRoot, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
197	AssertRC(rc);
198
199	/* HWACCM support must be explicitely enabled in the configuration file. */
200	rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
201	AssertRC(rc);
202
203	#ifdef RT_OS_DARWIN
204	if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
205	#else
206	if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
207	#endif
208	{
209	AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
210	VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
211	return VERR_HWACCM_CONFIG_MISMATCH;
212	}
213
214	if (VMMIsHwVirtExtForced(pVM))
215	pVM->fHWACCMEnabled = true;
216
217	#if HC_ARCH_BITS == 32
218	/* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
219	* (To use the default, don't set 64bitEnabled in CFGM.) */
220	rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
221	AssertLogRelRCReturn(rc, rc);
222	if (pVM->hwaccm.s.fAllow64BitGuests)
223	{
224	# ifdef RT_OS_DARWIN
225	if (!VMMIsHwVirtExtForced(pVM))
226	# else
227	if (!pVM->hwaccm.s.fAllowed)
228	# endif
229	return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
230	}
231	#else
232	/* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
233	* via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
234	rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
235	AssertLogRelRCReturn(rc, rc);
236	#endif
237
238	return VINF_SUCCESS;
239	}
240
241	/**
242	* Initializes the per-VCPU HWACCM.
243	*
244	* @returns VBox status code.
245	* @param pVM The VM to operate on.
246	*/
247	VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
248	{
249	LogFlow(("HWACCMR3InitCPU\n"));
250
251	#ifdef VBOX_WITH_STATISTICS
252	/*
253	* Statistics.
254	*/
255	for (unsigned i=0;i<pVM->cCPUs;i++)
256	{
257	PVMCPU pVCpu = &pVM->aCpus[i];
258	int rc;
259
260	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
261	"/PROF/HWACCM/CPU%d/SwitchToGC", i);
262	AssertRC(rc);
263	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
264	"/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
265	AssertRC(rc);
266	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
267	"/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
268	AssertRC(rc);
269	# if 1 /* temporary for tracking down darwin holdup. */
270	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
271	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
272	AssertRC(rc);
273	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
274	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
275	AssertRC(rc);
276	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
277	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
278	AssertRC(rc);
279	# endif
280	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
281	"/PROF/HWACCM/CPU%d/InGC", i);
282	AssertRC(rc);
283
284	# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
285	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
286	"/PROF/HWACCM/CPU%d/Switcher3264", i);
287	AssertRC(rc);
288	# endif
289
290	# define HWACCM_REG_COUNTER(a, b) \
291	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
292	AssertRC(rc);
293
294	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
295	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
296	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
297	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
298	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
299	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
300	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
301	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
302	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
303	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
304	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
305	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
306	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
307	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
308	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
309	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
310	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
311	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
312	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
313	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
314	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
315	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
316	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
317	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
318	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
319
320	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
321	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
322
323	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
324	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
325	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
326
327	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
328	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
329	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
330	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
331	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
332	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
333	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
334	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
335	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
336
337	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
338	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
339
340	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
341	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
342	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
343
344	for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
345	{
346	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
347	"/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
348	AssertRC(rc);
349	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
350	"/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
351	AssertRC(rc);
352	}
353
354	#undef HWACCM_REG_COUNTER
355
356	pVCpu->hwaccm.s.paStatExitReason = NULL;
357
358	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
359	AssertRC(rc);
360	if (RT_SUCCESS(rc))
361	{
362	const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
363	for (int j=0;j<MAX_EXITREASON_STAT;j++)
364	{
365	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
366	papszDesc[j] ? papszDesc[j] : "Exit reason",
367	"/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
368	AssertRC(rc);
369	}
370	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
371	AssertRC(rc);
372	}
373	pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
374	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
375	Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
376	# else
377	Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
378	# endif
379	}
380	#endif /* VBOX_WITH_STATISTICS */
381
382	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
383	/* Magic marker for searching in crash dumps. */
384	for (unsigned i=0;i<pVM->cCPUs;i++)
385	{
386	PVMCPU pVCpu = &pVM->aCpus[i];
387
388	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
389	strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
390	pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
391	}
392	#endif
393	return VINF_SUCCESS;
394	}
395
396	/**
397	* Turns off normal raw mode features
398	*
399	* @param pVM The VM to operate on.
400	*/
401	static void hwaccmR3DisableRawMode(PVM pVM)
402	{
403	/* Disable PATM & CSAM. */
404	PATMR3AllowPatching(pVM, false);
405	CSAMDisableScanning(pVM);
406
407	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
408	SELMR3DisableMonitoring(pVM);
409	TRPMR3DisableMonitoring(pVM);
410
411	/* The hidden selector registers are now valid. */
412	CPUMSetHiddenSelRegsValid(pVM, true);
413
414	/* Disable the switcher code (safety precaution). */
415	VMMR3DisableSwitcher(pVM);
416
417	/* Disable mapping of the hypervisor into the shadow page table. */
418	PGMR3MappingsDisable(pVM);
419
420	/* Disable the switcher */
421	VMMR3DisableSwitcher(pVM);
422
423	/* Reinit the paging mode to force the new shadow mode. */
424	PGMR3ChangeMode(pVM, PGMMODE_REAL);
425	}
426
427	/**
428	* Initialize VT-x or AMD-V.
429	*
430	* @returns VBox status code.
431	* @param pVM The VM handle.
432	*/
433	VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
434	{
435	int rc;
436
437	if ( !pVM->hwaccm.s.vmx.fSupported
438	&& !pVM->hwaccm.s.svm.fSupported)
439	{
440	LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
441	LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
442	#ifdef RT_OS_DARWIN
443	if (VMMIsHwVirtExtForced(pVM))
444	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
445	#endif
446	return VINF_SUCCESS;
447	}
448
449	if (!pVM->hwaccm.s.fAllowed)
450	return VINF_SUCCESS; /* nothing to do */
451
452	/* Enable VT-x or AMD-V on all host CPUs. */
453	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, 0, NULL);
454	if (RT_FAILURE(rc))
455	{
456	LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
457	return rc;
458	}
459	Assert(!pVM->fHWACCMEnabled \|\| VMMIsHwVirtExtForced(pVM));
460
461	if (pVM->hwaccm.s.vmx.fSupported)
462	{
463	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
464
465	if ( pVM->hwaccm.s.fInitialized == false
466	&& pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
467	{
468	uint64_t val;
469	RTGCPHYS GCPhys = 0;
470
471	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
472	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
473	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
474	LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
475	LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
476	LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
477	LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
478	LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
479
480	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
481	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
482	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
483	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
484	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
485	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
486	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
487	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
488	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
489	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
490	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
491	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
492	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT must be set\n"));
493	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
494	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT must be set\n"));
495	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
496	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI must be set\n"));
497	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
498	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER must be set\n"));
499
500	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
501	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
502	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
503	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
504	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
505	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
506	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
507	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
508	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
509	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
510	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
511	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
512	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
513	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
514	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
515	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
516	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
517	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
518	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
519	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
520	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
521	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
522	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
523	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
524	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
525	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
526	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
527	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
528	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
529	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
530	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
531	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
532	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
533	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
534	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
535	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
536	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
537	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
538	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
539	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
540	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
541	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
542	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
543	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
544
545	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
546	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
547	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT must be set\n"));
548	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
549	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET must be set\n"));
550	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
551	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT must be set\n"));
552	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
553	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT must be set\n"));
554	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
555	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT must be set\n"));
556	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
557	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT must be set\n"));
558	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
559	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT must be set\n"));
560	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
561	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT must be set\n"));
562	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
563	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT must be set\n"));
564	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
565	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT must be set\n"));
566	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
567	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT must be set\n"));
568	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
569	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW must be set\n"));
570	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
571	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT must be set\n"));
572	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
573	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT must be set\n"));
574	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
575	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT must be set\n"));
576	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
577	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS must be set\n"));
578	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
579	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG must be set\n"));
580	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
581	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS must be set\n"));
582	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
583	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT must be set\n"));
584	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
585	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT must be set\n"));
586	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
587	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL must be set\n"));
588
589	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
590	{
591	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
592	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
593	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
594	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
595	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
596	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
597	if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
598	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
599	if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
600	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
601	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
602	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
603	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
604	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
605
606	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
607	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
608	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC must be set\n"));
609	if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
610	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT must be set\n"));
611	if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
612	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC must be set\n"));
613	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
614	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT must be set\n"));
615	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
616	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID must be set\n"));
617	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
618	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT must be set\n"));
619	}
620
621	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
622	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
623	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
624	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
625	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
626	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
627	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
628	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
629	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
630	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
631	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
632	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
633	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
634	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
635	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
636	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
637	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
638	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
639	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG must be set\n"));
640	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
641	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE must be set\n"));
642	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
643	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM must be set\n"));
644	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
645	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON must be set\n"));
646	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
647	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR must be set\n"));
648	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
649	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR must be set\n"));
650	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
651	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR must be set\n"));
652
653	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
654	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
655	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
656	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
657	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
658	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
659	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
660	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
661	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
662	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
663	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
664	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
665	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
666	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
667	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
668	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
669	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
670	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
671	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
672	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
673	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG must be set\n"));
674	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
675	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 must be set\n"));
676	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
677	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ must be set\n"));
678	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
679	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR must be set\n"));
680	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
681	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR must be set\n"));
682	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
683	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR must be set\n"));
684	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
685	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR must be set\n"));
686	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
687	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER must be set\n"));
688
689	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
690	{
691	LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
692
693	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
694	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
695	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
696	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
697	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
698	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
699	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
700	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
701	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
702	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
703	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
704	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
705	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
706	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
707	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
708	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
709	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
710	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
711	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
712	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
713	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
714	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
715	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
716	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
717	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
718	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
719	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
720	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
721	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
722	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
723	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
724	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
725	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
726	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
727	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
728	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
729	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
730	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
731	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
732	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
733	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
734	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
735	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
736	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
737	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
738	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
739	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
740	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
741	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
742	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
743	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
744	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
745	}
746
747	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
748	LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
749	LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
750	LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
751	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
752	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
753
754	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
755	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
756	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
757	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
758	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
759
760	LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
761	LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
762
763	for (unsigned i=0;i<pVM->cCPUs;i++)
764	LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
765
766	#ifdef HWACCM_VTX_WITH_EPT
767	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
768	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
769	#endif /* HWACCM_VTX_WITH_EPT */
770	#ifdef HWACCM_VTX_WITH_VPID
771	if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
772	&& !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
773	pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
774	#endif /* HWACCM_VTX_WITH_VPID */
775
776	/* Only try once. */
777	pVM->hwaccm.s.fInitialized = true;
778
779	/* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
780	#if 1
781	rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
782	#else
783	rc = VERR_NO_MEMORY; /* simulation of no VMMDev Heap. */
784	#endif
785	if (RT_SUCCESS(rc))
786	{
787	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
788	ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
789	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
790	/* Bit set to 0 means redirection enabled. */
791	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
792	/* Allow all port IO, so the VT-x IO intercepts do their job. */
793	memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
794	((unsigned char )pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
795
796	/* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
797	* real and protected mode without paging with EPT.
798	*/
799	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
800	for (unsigned i=0;i<X86_PG_ENTRIES;i++)
801	{
802	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
803	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_G;
804	}
805
806	/* We convert it here every time as pci regions could be reconfigured. */
807	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
808	AssertRC(rc);
809	LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
810
811	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
812	AssertRC(rc);
813	LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
814	}
815	else
816	{
817	LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
818	pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
819	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
820	}
821
822	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
823	AssertRC(rc);
824	if (rc == VINF_SUCCESS)
825	{
826	pVM->fHWACCMEnabled = true;
827	pVM->hwaccm.s.vmx.fEnabled = true;
828	hwaccmR3DisableRawMode(pVM);
829
830	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
831	#ifdef VBOX_ENABLE_64_BITS_GUESTS
832	if (pVM->hwaccm.s.fAllow64BitGuests)
833	{
834	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
835	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
836	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
837	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
838	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
839	}
840	LogRel((pVM->hwaccm.s.fAllow64BitGuests
841	? "HWACCM: 32-bit and 64-bit guests supported.\n"
842	: "HWACCM: 32-bit guests supported.\n"));
843	#else
844	LogRel(("HWACCM: 32-bit guests supported.\n"));
845	#endif
846	LogRel(("HWACCM: VMX enabled!\n"));
847	if (pVM->hwaccm.s.fNestedPaging)
848	{
849	LogRel(("HWACCM: Enabled nested paging\n"));
850	LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(pVM)));
851	}
852	if (pVM->hwaccm.s.vmx.fVPID)
853	LogRel(("HWACCM: Enabled VPID\n"));
854
855	if ( pVM->hwaccm.s.fNestedPaging
856	\|\| pVM->hwaccm.s.vmx.fVPID)
857	{
858	LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
859	LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
860	}
861	}
862	else
863	{
864	LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
865	LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
866	pVM->fHWACCMEnabled = false;
867	}
868	}
869	}
870	else
871	if (pVM->hwaccm.s.svm.fSupported)
872	{
873	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
874
875	if (pVM->hwaccm.s.fInitialized == false)
876	{
877	/* Erratum 170 which requires a forced TLB flush for each world switch:
878	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
879	*
880	* All BH-G1/2 and DH-G1/2 models include a fix:
881	* Athlon X2: 0x6b 1/2
882	* 0x68 1/2
883	* Athlon 64: 0x7f 1
884	* 0x6f 2
885	* Sempron: 0x7f 1/2
886	* 0x6f 2
887	* 0x6c 2
888	* 0x7c 2
889	* Turion 64: 0x68 2
890	*
891	*/
892	uint32_t u32Dummy;
893	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
894	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
895	u32BaseFamily= (u32Version >> 8) & 0xf;
896	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
897	u32Model = ((u32Version >> 4) & 0xf);
898	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
899	u32Stepping = u32Version & 0xf;
900	if ( u32Family == 0xf
901	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
902	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
903	{
904	LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
905	}
906
907	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
908	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
909	LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
910	LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
911	LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
912
913	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
914	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
915	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
916	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
917	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
918	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
919	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
920	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
921	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
922	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
923
924	/* Only try once. */
925	pVM->hwaccm.s.fInitialized = true;
926
927	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
928	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
929
930	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
931	AssertRC(rc);
932	if (rc == VINF_SUCCESS)
933	{
934	pVM->fHWACCMEnabled = true;
935	pVM->hwaccm.s.svm.fEnabled = true;
936
937	if (pVM->hwaccm.s.fNestedPaging)
938	LogRel(("HWACCM: Enabled nested paging\n"));
939
940	hwaccmR3DisableRawMode(pVM);
941	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
942	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
943	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
944	#ifdef VBOX_ENABLE_64_BITS_GUESTS
945	if (pVM->hwaccm.s.fAllow64BitGuests)
946	{
947	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
948	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
949	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
950	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
951	}
952	#endif
953	LogRel((pVM->hwaccm.s.fAllow64BitGuests
954	? "HWACCM: 32-bit and 64-bit guest supported.\n"
955	: "HWACCM: 32-bit guest supported.\n"));
956	}
957	else
958	{
959	pVM->fHWACCMEnabled = false;
960	}
961	}
962	}
963	return VINF_SUCCESS;
964	}
965
966	/**
967	* Applies relocations to data and code managed by this
968	* component. This function will be called at init and
969	* whenever the VMM need to relocate it self inside the GC.
970	*
971	* @param pVM The VM.
972	*/
973	VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
974	{
975	Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
976
977	/* Fetch the current paging mode during the relocate callback during state loading. */
978	if (VMR3GetState(pVM) == VMSTATE_LOADING)
979	{
980	for (unsigned i=0;i<pVM->cCPUs;i++)
981	{
982	PVMCPU pVCpu = &pVM->aCpus[i];
983	/* @todo SMP */
984	pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVM);
985	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMGetGuestMode(pVM);
986	}
987	}
988	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
989	if (pVM->fHWACCMEnabled)
990	{
991	int rc;
992
993	switch(PGMGetHostMode(pVM))
994	{
995	case PGMMODE_32_BIT:
996	pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
997	break;
998
999	case PGMMODE_PAE:
1000	case PGMMODE_PAE_NX:
1001	pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1002	break;
1003
1004	default:
1005	AssertFailed();
1006	break;
1007	}
1008	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1009	AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1010
1011	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1012	AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1013
1014	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1015	AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1016
1017	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1018	AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1019
1020	# ifdef DEBUG
1021	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1022	AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1023	# endif
1024	}
1025	#endif
1026	return;
1027	}
1028
1029	/**
1030	* Checks hardware accelerated raw mode is allowed.
1031	*
1032	* @returns boolean
1033	* @param pVM The VM to operate on.
1034	*/
1035	VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1036	{
1037	return pVM->hwaccm.s.fAllowed;
1038	}
1039
1040	/**
1041	* Notification callback which is called whenever there is a chance that a CR3
1042	* value might have changed.
1043	*
1044	* This is called by PGM.
1045	*
1046	* @param pVM The VM to operate on.
1047	* @param enmShadowMode New shadow paging mode.
1048	* @param enmGuestMode New guest paging mode.
1049	*/
1050	VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1051	{
1052	/* Ignore page mode changes during state loading. */
1053	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1054	return;
1055
1056	PVMCPU pVCpu = VMMGetCpu(pVM);
1057	pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1058
1059	if ( pVM->hwaccm.s.vmx.fEnabled
1060	&& pVM->fHWACCMEnabled)
1061	{
1062	if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1063	&& enmGuestMode >= PGMMODE_PROTECTED)
1064	{
1065	PCPUMCTX pCtx;
1066
1067	pCtx = CPUMQueryGuestCtxPtr(pVM);
1068
1069	/* After a real mode switch to protected mode we must force
1070	* CPL to 0. Our real mode emulation had to set it to 3.
1071	*/
1072	pCtx->ssHid.Attr.n.u2Dpl = 0;
1073	}
1074	}
1075
1076	if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1077	{
1078	/* Keep track of paging mode changes. */
1079	pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1080	pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1081
1082	/* Did we miss a change, because all code was executed in the recompiler? */
1083	if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1084	{
1085	Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1086	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1087	}
1088	}
1089
1090	/* Reset the contents of the read cache. */
1091	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1092	for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1093	pCache->Read.aFieldVal[j] = 0;
1094	}
1095
1096	/**
1097	* Terminates the HWACCM.
1098	*
1099	* Termination means cleaning up and freeing all resources,
1100	* the VM it self is at this point powered off or suspended.
1101	*
1102	* @returns VBox status code.
1103	* @param pVM The VM to operate on.
1104	*/
1105	VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1106	{
1107	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1108	{
1109	PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1110	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1111	}
1112	HWACCMR3TermCPU(pVM);
1113	return 0;
1114	}
1115
1116	/**
1117	* Terminates the per-VCPU HWACCM.
1118	*
1119	* Termination means cleaning up and freeing all resources,
1120	* the VM it self is at this point powered off or suspended.
1121	*
1122	* @returns VBox status code.
1123	* @param pVM The VM to operate on.
1124	*/
1125	VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1126	{
1127	for (unsigned i=0;i<pVM->cCPUs;i++)
1128	{
1129	PVMCPU pVCpu = &pVM->aCpus[i];
1130
1131	if (pVCpu->hwaccm.s.paStatExitReason)
1132	{
1133	MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1134	pVCpu->hwaccm.s.paStatExitReason = NULL;
1135	pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1136	}
1137	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1138	memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1139	pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1140	pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1141	#endif
1142	}
1143	return 0;
1144	}
1145
1146	/**
1147	* The VM is being reset.
1148	*
1149	* For the HWACCM component this means that any GDT/LDT/TSS monitors
1150	* needs to be removed.
1151	*
1152	* @param pVM VM handle.
1153	*/
1154	VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1155	{
1156	LogFlow(("HWACCMR3Reset:\n"));
1157
1158	if (pVM->fHWACCMEnabled)
1159	hwaccmR3DisableRawMode(pVM);
1160
1161	for (unsigned i=0;i<pVM->cCPUs;i++)
1162	{
1163	PVMCPU pVCpu = &pVM->aCpus[i];
1164
1165	/* On first entry we'll sync everything. */
1166	pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1167
1168	pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1169	pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1170
1171	pVCpu->hwaccm.s.Event.fPending = false;
1172
1173	/* Reset state information for real-mode emulation in VT-x. */
1174	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1175	pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1176	pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1177
1178	/* Reset the contents of the read cache. */
1179	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1180	for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1181	pCache->Read.aFieldVal[j] = 0;
1182
1183	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1184	/* Magic marker for searching in crash dumps. */
1185	strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1186	pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1187	#endif
1188	}
1189	}
1190
1191	/**
1192	* Force execution of the current IO code in the recompiler
1193	*
1194	* @returns VBox status code.
1195	* @param pVM The VM to operate on.
1196	* @param pCtx Partial VM execution context
1197	*/
1198	VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
1199	{
1200	PVMCPU pVCpu = VMMGetCpu(pVM);
1201
1202	Assert(pVM->fHWACCMEnabled);
1203	Log(("HWACCMR3EmulateIoBlock\n"));
1204
1205	/* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
1206	if (HWACCMCanEmulateIoBlockEx(pCtx))
1207	{
1208	Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
1209	pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
1210	pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
1211	pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
1212	return VINF_EM_RESCHEDULE_REM;
1213	}
1214	return VINF_SUCCESS;
1215	}
1216
1217	/**
1218	* Checks if we can currently use hardware accelerated raw mode.
1219	*
1220	* @returns boolean
1221	* @param pVM The VM to operate on.
1222	* @param pCtx Partial VM execution context
1223	*/
1224	VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
1225	{
1226	PVMCPU pVCpu = VMMGetCpu(pVM);
1227
1228	Assert(pVM->fHWACCMEnabled);
1229
1230	/* If we're still executing the IO code, then return false. */
1231	if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
1232	&& pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
1233	&& pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
1234	&& pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
1235	return false;
1236
1237	pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
1238
1239	/* AMD-V supports real & protected mode with or without paging. */
1240	if (pVM->hwaccm.s.svm.fEnabled)
1241	{
1242	pVM->hwaccm.s.fActive = true;
1243	return true;
1244	}
1245
1246	pVM->hwaccm.s.fActive = false;
1247
1248	/* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
1249	#ifdef HWACCM_VMX_EMULATE_REALMODE
1250	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1251	{
1252	if (CPUMIsGuestInRealModeEx(pCtx))
1253	{
1254	/* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
1255	* The base must also be equal to (sel << 4).
1256	*/
1257	if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
1258	&& pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
1259	\|\| pCtx->ds != (pCtx->dsHid.u64Base >> 4)
1260	\|\| pCtx->es != (pCtx->esHid.u64Base >> 4)
1261	\|\| pCtx->fs != (pCtx->fsHid.u64Base >> 4)
1262	\|\| pCtx->gs != (pCtx->gsHid.u64Base >> 4)
1263	\|\| pCtx->ss != (pCtx->ssHid.u64Base >> 4))
1264	{
1265	return false;
1266	}
1267	}
1268	else
1269	{
1270	PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
1271	/* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
1272	* from real to protected mode. (all sorts of RPL & DPL assumptions)
1273	*/
1274	PVMCPU pVCpu = VMMGetCpu(pVM);
1275
1276	if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1277	&& enmGuestMode >= PGMMODE_PROTECTED)
1278	{
1279	if ( (pCtx->cs & X86_SEL_RPL)
1280	\|\| (pCtx->ds & X86_SEL_RPL)
1281	\|\| (pCtx->es & X86_SEL_RPL)
1282	\|\| (pCtx->fs & X86_SEL_RPL)
1283	\|\| (pCtx->gs & X86_SEL_RPL)
1284	\|\| (pCtx->ss & X86_SEL_RPL))
1285	{
1286	return false;
1287	}
1288	}
1289	}
1290	}
1291	else
1292	#endif /* HWACCM_VMX_EMULATE_REALMODE */
1293	{
1294	if (!CPUMIsGuestInLongModeEx(pCtx))
1295	{
1296	/** @todo This should (probably) be set on every excursion to the REM,
1297	* however it's too risky right now. So, only apply it when we go
1298	* back to REM for real mode execution. (The XP hack below doesn't
1299	* work reliably without this.)
1300	* Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
1301	pVM->aCpus[0].hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1302
1303	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
1304	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
1305	return false;
1306
1307	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
1308	/* Windows XP; switch to protected mode; all selectors are marked not present in the
1309	* hidden registers (possible recompiler bug; see load_seg_vm) */
1310	if (pCtx->csHid.Attr.n.u1Present == 0)
1311	return false;
1312	if (pCtx->ssHid.Attr.n.u1Present == 0)
1313	return false;
1314
1315	/* Windows XP: possible same as above, but new recompiler requires new heuristics?
1316	VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
1317	/** @todo This check is actually wrong, it doesn't take the direction of the
1318	* stack segment into account. But, it does the job for now. */
1319	if (pCtx->rsp >= pCtx->ssHid.u32Limit)
1320	return false;
1321	#if 0
1322	if ( pCtx->cs >= pCtx->gdtr.cbGdt
1323	\|\| pCtx->ss >= pCtx->gdtr.cbGdt
1324	\|\| pCtx->ds >= pCtx->gdtr.cbGdt
1325	\|\| pCtx->es >= pCtx->gdtr.cbGdt
1326	\|\| pCtx->fs >= pCtx->gdtr.cbGdt
1327	\|\| pCtx->gs >= pCtx->gdtr.cbGdt)
1328	return false;
1329	#endif
1330	}
1331	}
1332
1333	if (pVM->hwaccm.s.vmx.fEnabled)
1334	{
1335	uint32_t mask;
1336
1337	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
1338	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
1339	/* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
1340	mask &= ~X86_CR0_NE;
1341
1342	#ifdef HWACCM_VMX_EMULATE_REALMODE
1343	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1344	{
1345	/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
1346	mask &= ~(X86_CR0_PG\|X86_CR0_PE);
1347	}
1348	else
1349	#endif
1350	{
1351	/* We support protected mode without paging using identity mapping. */
1352	mask &= ~X86_CR0_PG;
1353	}
1354	if ((pCtx->cr0 & mask) != mask)
1355	return false;
1356
1357	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
1358	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
1359	if ((pCtx->cr0 & mask) != 0)
1360	return false;
1361
1362	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
1363	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1364	mask &= ~X86_CR4_VMXE;
1365	if ((pCtx->cr4 & mask) != mask)
1366	return false;
1367
1368	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
1369	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
1370	if ((pCtx->cr4 & mask) != 0)
1371	return false;
1372
1373	pVM->hwaccm.s.fActive = true;
1374	return true;
1375	}
1376
1377	return false;
1378	}
1379
1380	/**
1381	* Notifcation from EM about a rescheduling into hardware assisted execution
1382	* mode.
1383	*
1384	* @param pVCpu Pointer to the current virtual cpu structure.
1385	*/
1386	VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
1387	{
1388	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1389	}
1390
1391	/**
1392	* Notifcation from EM about returning from instruction emulation (REM / EM).
1393	*
1394	* @param pVCpu Pointer to the current virtual cpu structure.
1395	*/
1396	VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
1397	{
1398	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1399	}
1400
1401	/**
1402	* Checks if we are currently using hardware accelerated raw mode.
1403	*
1404	* @returns boolean
1405	* @param pVM The VM to operate on.
1406	*/
1407	VMMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
1408	{
1409	return pVM->hwaccm.s.fActive;
1410	}
1411
1412	/**
1413	* Checks if we are currently using nested paging.
1414	*
1415	* @returns boolean
1416	* @param pVM The VM to operate on.
1417	*/
1418	VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
1419	{
1420	return pVM->hwaccm.s.fNestedPaging;
1421	}
1422
1423	/**
1424	* Checks if we are currently using VPID in VT-x mode.
1425	*
1426	* @returns boolean
1427	* @param pVM The VM to operate on.
1428	*/
1429	VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
1430	{
1431	return pVM->hwaccm.s.vmx.fVPID;
1432	}
1433
1434
1435	/**
1436	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
1437	*
1438	* @returns boolean
1439	* @param pVM The VM to operate on.
1440	*/
1441	VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
1442	{
1443	/* @todo SMP */
1444	return HWACCMIsEnabled(pVM) && pVM->aCpus[0].hwaccm.s.Event.fPending;
1445	}
1446
1447
1448	/**
1449	* Inject an NMI into a running VM
1450	*
1451	* @returns boolean
1452	* @param pVM The VM to operate on.
1453	*/
1454	VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
1455	{
1456	pVM->hwaccm.s.fInjectNMI = true;
1457	return VINF_SUCCESS;
1458	}
1459
1460	/**
1461	* Check fatal VT-x/AMD-V error and produce some meaningful
1462	* log release message.
1463	*
1464	* @param pVM The VM to operate on.
1465	* @param iStatusCode VBox status code
1466	*/
1467	VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
1468	{
1469	for (unsigned i=0;i<pVM->cCPUs;i++)
1470	{
1471	switch(iStatusCode)
1472	{
1473	case VERR_VMX_INVALID_VMCS_FIELD:
1474	break;
1475
1476	case VERR_VMX_INVALID_VMCS_PTR:
1477	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1478	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
1479	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
1480	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
1481	break;
1482
1483	case VERR_VMX_UNABLE_TO_START_VM:
1484	LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1485	LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1486	#if 0 /* @todo dump the current control fields to the release log */
1487	if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
1488	{
1489
1490	}
1491	#endif
1492	break;
1493
1494	case VERR_VMX_UNABLE_TO_RESUME_VM:
1495	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1496	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1497	break;
1498
1499	case VERR_VMX_INVALID_VMXON_PTR:
1500	break;
1501	}
1502	}
1503	}
1504
1505	/**
1506	* Execute state save operation.
1507	*
1508	* @returns VBox status code.
1509	* @param pVM VM Handle.
1510	* @param pSSM SSM operation handle.
1511	*/
1512	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
1513	{
1514	int rc;
1515
1516	Log(("hwaccmR3Save:\n"));
1517
1518	for (unsigned i=0;i<pVM->cCPUs;i++)
1519	{
1520	/*
1521	* Save the basic bits - fortunately all the other things can be resynced on load.
1522	*/
1523	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
1524	AssertRCReturn(rc, rc);
1525	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
1526	AssertRCReturn(rc, rc);
1527	rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
1528	AssertRCReturn(rc, rc);
1529
1530	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
1531	AssertRCReturn(rc, rc);
1532	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
1533	AssertRCReturn(rc, rc);
1534	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
1535	AssertRCReturn(rc, rc);
1536	}
1537
1538	return VINF_SUCCESS;
1539	}
1540
1541	/**
1542	* Execute state load operation.
1543	*
1544	* @returns VBox status code.
1545	* @param pVM VM Handle.
1546	* @param pSSM SSM operation handle.
1547	* @param u32Version Data layout version.
1548	*/
1549	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1550	{
1551	int rc;
1552
1553	Log(("hwaccmR3Load:\n"));
1554
1555	/*
1556	* Validate version.
1557	*/
1558	if ( u32Version != HWACCM_SSM_VERSION
1559	&& u32Version != HWACCM_SSM_VERSION_2_0_X)
1560	{
1561	AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
1562	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1563	}
1564	for (unsigned i=0;i<pVM->cCPUs;i++)
1565	{
1566	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
1567	AssertRCReturn(rc, rc);
1568	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
1569	AssertRCReturn(rc, rc);
1570	rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
1571	AssertRCReturn(rc, rc);
1572
1573	if (u32Version >= HWACCM_SSM_VERSION)
1574	{
1575	uint32_t val;
1576
1577	rc = SSMR3GetU32(pSSM, &val);
1578	AssertRCReturn(rc, rc);
1579	pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
1580
1581	rc = SSMR3GetU32(pSSM, &val);
1582	AssertRCReturn(rc, rc);
1583	pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
1584
1585	rc = SSMR3GetU32(pSSM, &val);
1586	AssertRCReturn(rc, rc);
1587	pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
1588	}
1589	}
1590	return VINF_SUCCESS;
1591	}
1592

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source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 17522

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