VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 18940

Last change on this file since 18940 was 18940, checked in by vboxsync, 16 years ago

Same for hwaccm
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1/* $Id: HWACCM.cpp 18940 2009-04-16 13:23:22Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/csam.h>
35#include <VBox/selm.h>
36#include <VBox/rem.h>
37#include <VBox/hwacc_vmx.h>
38#include <VBox/hwacc_svm.h>
39#include "HWACCMInternal.h"
40#include <VBox/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/string.h>
48#include <iprt/thread.h>
49
50/*******************************************************************************
51* Global Variables *
52*******************************************************************************/
53#ifdef VBOX_WITH_STATISTICS
54# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55# define EXIT_REASON_NIL() NULL
56/** Exit reason descriptions for VT-x, used to describe statistics. */
57static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58{
59 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67 EXIT_REASON_NIL(),
68 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94 EXIT_REASON_NIL(),
95 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96 EXIT_REASON_NIL(),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101 EXIT_REASON_NIL(),
102 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110 EXIT_REASON_NIL(),
111 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115 EXIT_REASON_NIL()
116};
117/** Exit reason descriptions for AMD-V, used to describe statistics. */
118static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119{
120 /** @todo fill in these. */
121 EXIT_REASON_NIL()
122};
123# undef EXIT_REASON
124# undef EXIT_REASON_NIL
125#endif /* VBOX_WITH_STATISTICS */
126
127/*******************************************************************************
128* Internal Functions *
129*******************************************************************************/
130static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
131static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
132
133
134/**
135 * Initializes the HWACCM.
136 *
137 * @returns VBox status code.
138 * @param pVM The VM to operate on.
139 */
140VMMR3DECL(int) HWACCMR3Init(PVM pVM)
141{
142 LogFlow(("HWACCMR3Init\n"));
143
144 /*
145 * Assert alignment and sizes.
146 */
147 AssertCompileMemberAlignment(VM, hwaccm.s, 32));
148 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
149
150 /* Some structure checks. */
151 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
152 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
153 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
154 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
155
156 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
157 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
158 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
159 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
160 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
161 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
162 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
163
164
165 /*
166 * Register the saved state data unit.
167 */
168 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
169 NULL, hwaccmR3Save, NULL,
170 NULL, hwaccmR3Load, NULL);
171 if (RT_FAILURE(rc))
172 return rc;
173
174 /* Misc initialisation. */
175 pVM->hwaccm.s.vmx.fSupported = false;
176 pVM->hwaccm.s.svm.fSupported = false;
177 pVM->hwaccm.s.vmx.fEnabled = false;
178 pVM->hwaccm.s.svm.fEnabled = false;
179
180 pVM->hwaccm.s.fActive = false;
181 pVM->hwaccm.s.fNestedPaging = false;
182
183 /* Disabled by default. */
184 pVM->fHWACCMEnabled = false;
185
186 /*
187 * Check CFGM options.
188 */
189 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
190 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
191 /* Nested paging: disabled by default. */
192 rc = CFGMR3QueryBoolDef(pRoot, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
193 AssertRC(rc);
194
195 /* VT-x VPID: disabled by default. */
196 rc = CFGMR3QueryBoolDef(pRoot, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
197 AssertRC(rc);
198
199 /* HWACCM support must be explicitely enabled in the configuration file. */
200 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
201 AssertRC(rc);
202
203#ifdef RT_OS_DARWIN
204 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
205#else
206 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
207#endif
208 {
209 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
210 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
211 return VERR_HWACCM_CONFIG_MISMATCH;
212 }
213
214 if (VMMIsHwVirtExtForced(pVM))
215 pVM->fHWACCMEnabled = true;
216
217#if HC_ARCH_BITS == 32
218 /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
219 * (To use the default, don't set 64bitEnabled in CFGM.) */
220 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
221 AssertLogRelRCReturn(rc, rc);
222 if (pVM->hwaccm.s.fAllow64BitGuests)
223 {
224# ifdef RT_OS_DARWIN
225 if (!VMMIsHwVirtExtForced(pVM))
226# else
227 if (!pVM->hwaccm.s.fAllowed)
228# endif
229 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
230 }
231#else
232 /* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
233 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
234 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
235 AssertLogRelRCReturn(rc, rc);
236#endif
237
238 return VINF_SUCCESS;
239}
240
241/**
242 * Initializes the per-VCPU HWACCM.
243 *
244 * @returns VBox status code.
245 * @param pVM The VM to operate on.
246 */
247VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
248{
249 LogFlow(("HWACCMR3InitCPU\n"));
250
251#ifdef VBOX_WITH_STATISTICS
252 /*
253 * Statistics.
254 */
255 for (unsigned i=0;i<pVM->cCPUs;i++)
256 {
257 PVMCPU pVCpu = &pVM->aCpus[i];
258 int rc;
259
260 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
261 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
262 AssertRC(rc);
263 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
264 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
265 AssertRC(rc);
266 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
267 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
268 AssertRC(rc);
269# if 1 /* temporary for tracking down darwin holdup. */
270 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
271 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
272 AssertRC(rc);
273 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
274 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
275 AssertRC(rc);
276 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
277 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
278 AssertRC(rc);
279# endif
280 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
281 "/PROF/HWACCM/CPU%d/InGC", i);
282 AssertRC(rc);
283
284# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
285 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
286 "/PROF/HWACCM/CPU%d/Switcher3264", i);
287 AssertRC(rc);
288# endif
289
290# define HWACCM_REG_COUNTER(a, b) \
291 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
292 AssertRC(rc);
293
294 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
295 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
296 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
297 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
298 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
299 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
300 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
301 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
302 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
303 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
304 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
305 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
306 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
307 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
308 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
309 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
310 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
311 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
312 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
313 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
314 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
315 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
316 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
317 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
318 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
319 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
320 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
321 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
322 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
323 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
324 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
325 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
326 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
327
328 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
329 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
330
331 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
332 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
333 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
334
335 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
336 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
337 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
338 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
339 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
340 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
341 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
342 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
343 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
344
345 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
346 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
347
348 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
349 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
350 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
351
352 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
353 {
354 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
355 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
356 AssertRC(rc);
357 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
358 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
359 AssertRC(rc);
360 }
361
362#undef HWACCM_REG_COUNTER
363
364 pVCpu->hwaccm.s.paStatExitReason = NULL;
365
366 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
367 AssertRC(rc);
368 if (RT_SUCCESS(rc))
369 {
370 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
371 for (int j=0;j<MAX_EXITREASON_STAT;j++)
372 {
373 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
374 papszDesc[j] ? papszDesc[j] : "Exit reason",
375 "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
376 AssertRC(rc);
377 }
378 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
379 AssertRC(rc);
380 }
381 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
382# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
383 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
384# else
385 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
386# endif
387 }
388#endif /* VBOX_WITH_STATISTICS */
389
390#ifdef VBOX_WITH_CRASHDUMP_MAGIC
391 /* Magic marker for searching in crash dumps. */
392 for (unsigned i=0;i<pVM->cCPUs;i++)
393 {
394 PVMCPU pVCpu = &pVM->aCpus[i];
395
396 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
397 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
398 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
399 }
400#endif
401 return VINF_SUCCESS;
402}
403
404/**
405 * Turns off normal raw mode features
406 *
407 * @param pVM The VM to operate on.
408 */
409static void hwaccmR3DisableRawMode(PVM pVM)
410{
411 /* Disable PATM & CSAM. */
412 PATMR3AllowPatching(pVM, false);
413 CSAMDisableScanning(pVM);
414
415 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
416 SELMR3DisableMonitoring(pVM);
417 TRPMR3DisableMonitoring(pVM);
418
419 /* Disable the switcher code (safety precaution). */
420 VMMR3DisableSwitcher(pVM);
421
422 /* Disable mapping of the hypervisor into the shadow page table. */
423 PGMR3MappingsDisable(pVM);
424
425 /* Disable the switcher */
426 VMMR3DisableSwitcher(pVM);
427
428 /* Reinit the paging mode to force the new shadow mode. */
429 for (unsigned i=0;i<pVM->cCPUs;i++)
430 {
431 PVMCPU pVCpu = &pVM->aCpus[i];
432
433 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
434 }
435}
436
437/**
438 * Initialize VT-x or AMD-V.
439 *
440 * @returns VBox status code.
441 * @param pVM The VM handle.
442 */
443VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
444{
445 int rc;
446
447 if ( !pVM->hwaccm.s.vmx.fSupported
448 && !pVM->hwaccm.s.svm.fSupported)
449 {
450 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
451 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
452 if (VMMIsHwVirtExtForced(pVM))
453 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
454 return VINF_SUCCESS;
455 }
456
457 if (!pVM->hwaccm.s.fAllowed)
458 return VINF_SUCCESS; /* nothing to do */
459
460 /* Enable VT-x or AMD-V on all host CPUs. */
461 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, 0, NULL);
462 if (RT_FAILURE(rc))
463 {
464 LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
465 return rc;
466 }
467 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
468
469 if (pVM->hwaccm.s.vmx.fSupported)
470 {
471 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
472
473 if ( pVM->hwaccm.s.fInitialized == false
474 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
475 {
476 uint64_t val;
477 RTGCPHYS GCPhys = 0;
478
479 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
480 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
481 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
482 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
483 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
484 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
485 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
486 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
487
488 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
489 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
490 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
491 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
492 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
493 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
494 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
495 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
496 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
497 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
498 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
499 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
500 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
501 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
502 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
503 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
504 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
505 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
506 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
507
508 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
509 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
510 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
511 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
512 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
513 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
514 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
515 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
516 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
517 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
518 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
519 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
520 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
521 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
522 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
523 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
524 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
525 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
526 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
527 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
528 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
529 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
530 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
531 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
532 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
533 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
534 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
535 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
536 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
537 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
538 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
539 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
540 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
541 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
542 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
543 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
544 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
545 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
546 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
547 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
548 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
549 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
550 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
551 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
552
553 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
554 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
555 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
556 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
557 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
558 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
559 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
560 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
561 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
562 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
563 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
564 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
565 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
566 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
567 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
568 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
569 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
570 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
571 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
572 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
573 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
574 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
575 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
576 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
577 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
578 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
579 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
580 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
581 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
582 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
583 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
584 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
585 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
586 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
587 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
588 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
589 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
590 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
591 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
592 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
593 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
594 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
595 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
596
597 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
598 {
599 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
600 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
601 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
602 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
603 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
604 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
605 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
606 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
607 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
608 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
609 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
610 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
611 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
612 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
613
614 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
615 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
616 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
617 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
618 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
619 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
620 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
621 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
622 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
623 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
624 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
625 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
626 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
627 }
628
629 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
630 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
631 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
632 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
633 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
634 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
635 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
636 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
637 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
638 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
639 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
640 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
641 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
642 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
643 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
644 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
645 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
646 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
647 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
648 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
649 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
650 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
651 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
652 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
653 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
654 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
655 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
656 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
657 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
658 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
659 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
660
661 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
662 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
663 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
664 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
665 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
666 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
667 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
668 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
669 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
670 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
671 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
672 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
673 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
674 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
675 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
676 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
677 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
678 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
679 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
680 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
681 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
682 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
683 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
684 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
685 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
686 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
687 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
688 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
689 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
690 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
691 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
692 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
693 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
694 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
695 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
696
697 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
698 {
699 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
700
701 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
702 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
703 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
704 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
705 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
706 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
707 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
708 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
709 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
710 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
711 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
712 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
713 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
714 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
715 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
716 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
717 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
718 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
719 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
720 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
721 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
722 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
723 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
724 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
725 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
726 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
727 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
728 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
729 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
730 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
731 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
732 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
733 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
734 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
735 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
736 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
737 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
738 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
739 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
740 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
741 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
742 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
743 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
744 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
745 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
746 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
747 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
748 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
749 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
750 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
751 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
752 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
753 }
754
755 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
756 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
757 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
758 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
759 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
760 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
761
762 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
763 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
764 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
765 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
766 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
767
768 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
769 LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
770
771 for (unsigned i=0;i<pVM->cCPUs;i++)
772 LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
773
774#ifdef HWACCM_VTX_WITH_EPT
775 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
776 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
777#endif /* HWACCM_VTX_WITH_EPT */
778#ifdef HWACCM_VTX_WITH_VPID
779 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
780 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
781 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
782#endif /* HWACCM_VTX_WITH_VPID */
783
784 /* Only try once. */
785 pVM->hwaccm.s.fInitialized = true;
786
787 /* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
788#if 1
789 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
790#else
791 rc = VERR_NO_MEMORY; /* simulation of no VMMDev Heap. */
792#endif
793 if (RT_SUCCESS(rc))
794 {
795 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
796 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
797 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
798 /* Bit set to 0 means redirection enabled. */
799 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
800 /* Allow all port IO, so the VT-x IO intercepts do their job. */
801 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
802 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
803
804 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
805 * real and protected mode without paging with EPT.
806 */
807 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
808 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
809 {
810 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
811 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
812 }
813
814 /* We convert it here every time as pci regions could be reconfigured. */
815 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
816 AssertRC(rc);
817 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
818
819 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
820 AssertRC(rc);
821 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
822 }
823 else
824 {
825 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
826 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
827 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
828 }
829
830 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
831 AssertRC(rc);
832 if (rc == VINF_SUCCESS)
833 {
834 pVM->fHWACCMEnabled = true;
835 pVM->hwaccm.s.vmx.fEnabled = true;
836 hwaccmR3DisableRawMode(pVM);
837
838 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
839#ifdef VBOX_ENABLE_64_BITS_GUESTS
840 if (pVM->hwaccm.s.fAllow64BitGuests)
841 {
842 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
843 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
844 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
845 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
846 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
847 }
848 LogRel((pVM->hwaccm.s.fAllow64BitGuests
849 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
850 : "HWACCM: 32-bit guests supported.\n"));
851#else
852 LogRel(("HWACCM: 32-bit guests supported.\n"));
853#endif
854 LogRel(("HWACCM: VMX enabled!\n"));
855 if (pVM->hwaccm.s.fNestedPaging)
856 {
857 LogRel(("HWACCM: Enabled nested paging\n"));
858 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
859 }
860 if (pVM->hwaccm.s.vmx.fVPID)
861 LogRel(("HWACCM: Enabled VPID\n"));
862
863 if ( pVM->hwaccm.s.fNestedPaging
864 || pVM->hwaccm.s.vmx.fVPID)
865 {
866 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
867 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
868 }
869 }
870 else
871 {
872 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
873 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
874 pVM->fHWACCMEnabled = false;
875 }
876 }
877 }
878 else
879 if (pVM->hwaccm.s.svm.fSupported)
880 {
881 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
882
883 if (pVM->hwaccm.s.fInitialized == false)
884 {
885 /* Erratum 170 which requires a forced TLB flush for each world switch:
886 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
887 *
888 * All BH-G1/2 and DH-G1/2 models include a fix:
889 * Athlon X2: 0x6b 1/2
890 * 0x68 1/2
891 * Athlon 64: 0x7f 1
892 * 0x6f 2
893 * Sempron: 0x7f 1/2
894 * 0x6f 2
895 * 0x6c 2
896 * 0x7c 2
897 * Turion 64: 0x68 2
898 *
899 */
900 uint32_t u32Dummy;
901 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
902 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
903 u32BaseFamily= (u32Version >> 8) & 0xf;
904 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
905 u32Model = ((u32Version >> 4) & 0xf);
906 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
907 u32Stepping = u32Version & 0xf;
908 if ( u32Family == 0xf
909 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
910 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
911 {
912 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
913 }
914
915 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
916 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
917 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
918 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
919 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
920
921 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
922 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
923 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
924 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
925 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
926 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
927 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
928 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
929 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
930 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
931
932 /* Only try once. */
933 pVM->hwaccm.s.fInitialized = true;
934
935 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
936 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
937
938 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
939 AssertRC(rc);
940 if (rc == VINF_SUCCESS)
941 {
942 pVM->fHWACCMEnabled = true;
943 pVM->hwaccm.s.svm.fEnabled = true;
944
945 if (pVM->hwaccm.s.fNestedPaging)
946 LogRel(("HWACCM: Enabled nested paging\n"));
947
948 hwaccmR3DisableRawMode(pVM);
949 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
950 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
951 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
952#ifdef VBOX_ENABLE_64_BITS_GUESTS
953 if (pVM->hwaccm.s.fAllow64BitGuests)
954 {
955 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
956 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
957 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
958 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
959 }
960#endif
961 LogRel((pVM->hwaccm.s.fAllow64BitGuests
962 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
963 : "HWACCM: 32-bit guest supported.\n"));
964 }
965 else
966 {
967 pVM->fHWACCMEnabled = false;
968 }
969 }
970 }
971 return VINF_SUCCESS;
972}
973
974/**
975 * Applies relocations to data and code managed by this
976 * component. This function will be called at init and
977 * whenever the VMM need to relocate it self inside the GC.
978 *
979 * @param pVM The VM.
980 */
981VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
982{
983 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
984
985 /* Fetch the current paging mode during the relocate callback during state loading. */
986 if (VMR3GetState(pVM) == VMSTATE_LOADING)
987 {
988 for (unsigned i=0;i<pVM->cCPUs;i++)
989 {
990 PVMCPU pVCpu = &pVM->aCpus[i];
991 /* @todo SMP */
992 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
993 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMGetGuestMode(pVCpu);
994 }
995 }
996#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
997 if (pVM->fHWACCMEnabled)
998 {
999 int rc;
1000
1001 switch(PGMGetHostMode(pVM))
1002 {
1003 case PGMMODE_32_BIT:
1004 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1005 break;
1006
1007 case PGMMODE_PAE:
1008 case PGMMODE_PAE_NX:
1009 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1010 break;
1011
1012 default:
1013 AssertFailed();
1014 break;
1015 }
1016 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1017 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1018
1019 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1020 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1021
1022 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1023 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1024
1025 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1026 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1027
1028# ifdef DEBUG
1029 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1030 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1031# endif
1032 }
1033#endif
1034 return;
1035}
1036
1037/**
1038 * Checks hardware accelerated raw mode is allowed.
1039 *
1040 * @returns boolean
1041 * @param pVM The VM to operate on.
1042 */
1043VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1044{
1045 return pVM->hwaccm.s.fAllowed;
1046}
1047
1048/**
1049 * Notification callback which is called whenever there is a chance that a CR3
1050 * value might have changed.
1051 *
1052 * This is called by PGM.
1053 *
1054 * @param pVM The VM to operate on.
1055 * @param pVCpu The VMCPU to operate on.
1056 * @param enmShadowMode New shadow paging mode.
1057 * @param enmGuestMode New guest paging mode.
1058 */
1059VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1060{
1061 /* Ignore page mode changes during state loading. */
1062 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1063 return;
1064
1065 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1066
1067 if ( pVM->hwaccm.s.vmx.fEnabled
1068 && pVM->fHWACCMEnabled)
1069 {
1070 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1071 && enmGuestMode >= PGMMODE_PROTECTED)
1072 {
1073 PCPUMCTX pCtx;
1074
1075 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1076
1077 /* After a real mode switch to protected mode we must force
1078 * CPL to 0. Our real mode emulation had to set it to 3.
1079 */
1080 pCtx->ssHid.Attr.n.u2Dpl = 0;
1081 }
1082 }
1083
1084 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1085 {
1086 /* Keep track of paging mode changes. */
1087 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1088 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1089
1090 /* Did we miss a change, because all code was executed in the recompiler? */
1091 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1092 {
1093 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1094 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1095 }
1096 }
1097
1098 /* Reset the contents of the read cache. */
1099 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1100 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1101 pCache->Read.aFieldVal[j] = 0;
1102}
1103
1104/**
1105 * Terminates the HWACCM.
1106 *
1107 * Termination means cleaning up and freeing all resources,
1108 * the VM it self is at this point powered off or suspended.
1109 *
1110 * @returns VBox status code.
1111 * @param pVM The VM to operate on.
1112 */
1113VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1114{
1115 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1116 {
1117 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1118 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1119 }
1120 HWACCMR3TermCPU(pVM);
1121 return 0;
1122}
1123
1124/**
1125 * Terminates the per-VCPU HWACCM.
1126 *
1127 * Termination means cleaning up and freeing all resources,
1128 * the VM it self is at this point powered off or suspended.
1129 *
1130 * @returns VBox status code.
1131 * @param pVM The VM to operate on.
1132 */
1133VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1134{
1135 for (unsigned i=0;i<pVM->cCPUs;i++)
1136 {
1137 PVMCPU pVCpu = &pVM->aCpus[i];
1138
1139 if (pVCpu->hwaccm.s.paStatExitReason)
1140 {
1141 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1142 pVCpu->hwaccm.s.paStatExitReason = NULL;
1143 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1144 }
1145#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1146 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1147 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1148 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1149#endif
1150 }
1151 return 0;
1152}
1153
1154/**
1155 * The VM is being reset.
1156 *
1157 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1158 * needs to be removed.
1159 *
1160 * @param pVM VM handle.
1161 */
1162VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1163{
1164 LogFlow(("HWACCMR3Reset:\n"));
1165
1166 if (pVM->fHWACCMEnabled)
1167 hwaccmR3DisableRawMode(pVM);
1168
1169 for (unsigned i=0;i<pVM->cCPUs;i++)
1170 {
1171 PVMCPU pVCpu = &pVM->aCpus[i];
1172
1173 /* On first entry we'll sync everything. */
1174 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1175
1176 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1177 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1178
1179 pVCpu->hwaccm.s.Event.fPending = false;
1180
1181 /* Reset state information for real-mode emulation in VT-x. */
1182 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1183 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1184 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1185
1186 /* Reset the contents of the read cache. */
1187 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1188 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1189 pCache->Read.aFieldVal[j] = 0;
1190
1191#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1192 /* Magic marker for searching in crash dumps. */
1193 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1194 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1195#endif
1196 }
1197}
1198
1199/**
1200 * Force execution of the current IO code in the recompiler
1201 *
1202 * @returns VBox status code.
1203 * @param pVM The VM to operate on.
1204 * @param pCtx Partial VM execution context
1205 */
1206VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
1207{
1208 PVMCPU pVCpu = VMMGetCpu(pVM);
1209
1210 Assert(pVM->fHWACCMEnabled);
1211 Log(("HWACCMR3EmulateIoBlock\n"));
1212
1213 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
1214 if (HWACCMCanEmulateIoBlockEx(pCtx))
1215 {
1216 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
1217 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
1218 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
1219 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
1220 return VINF_EM_RESCHEDULE_REM;
1221 }
1222 return VINF_SUCCESS;
1223}
1224
1225/**
1226 * Checks if we can currently use hardware accelerated raw mode.
1227 *
1228 * @returns boolean
1229 * @param pVM The VM to operate on.
1230 * @param pCtx Partial VM execution context
1231 */
1232VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
1233{
1234 PVMCPU pVCpu = VMMGetCpu(pVM);
1235
1236 Assert(pVM->fHWACCMEnabled);
1237
1238 /* If we're still executing the IO code, then return false. */
1239 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
1240 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
1241 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
1242 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
1243 return false;
1244
1245 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
1246
1247 /* AMD-V supports real & protected mode with or without paging. */
1248 if (pVM->hwaccm.s.svm.fEnabled)
1249 {
1250 pVM->hwaccm.s.fActive = true;
1251 return true;
1252 }
1253
1254 pVM->hwaccm.s.fActive = false;
1255
1256 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
1257#ifdef HWACCM_VMX_EMULATE_REALMODE
1258 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1259 {
1260 if (CPUMIsGuestInRealModeEx(pCtx))
1261 {
1262 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
1263 * The base must also be equal to (sel << 4).
1264 */
1265 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
1266 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
1267 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
1268 || pCtx->es != (pCtx->esHid.u64Base >> 4)
1269 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
1270 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
1271 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
1272 {
1273 return false;
1274 }
1275 }
1276 else
1277 {
1278 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
1279 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
1280 * from real to protected mode. (all sorts of RPL & DPL assumptions)
1281 */
1282 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1283 && enmGuestMode >= PGMMODE_PROTECTED)
1284 {
1285 if ( (pCtx->cs & X86_SEL_RPL)
1286 || (pCtx->ds & X86_SEL_RPL)
1287 || (pCtx->es & X86_SEL_RPL)
1288 || (pCtx->fs & X86_SEL_RPL)
1289 || (pCtx->gs & X86_SEL_RPL)
1290 || (pCtx->ss & X86_SEL_RPL))
1291 {
1292 return false;
1293 }
1294 }
1295 }
1296 }
1297 else
1298#endif /* HWACCM_VMX_EMULATE_REALMODE */
1299 {
1300 if (!CPUMIsGuestInLongModeEx(pCtx))
1301 {
1302 /** @todo This should (probably) be set on every excursion to the REM,
1303 * however it's too risky right now. So, only apply it when we go
1304 * back to REM for real mode execution. (The XP hack below doesn't
1305 * work reliably without this.)
1306 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
1307 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
1308
1309 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
1310 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
1311 return false;
1312
1313 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
1314 /* Windows XP; switch to protected mode; all selectors are marked not present in the
1315 * hidden registers (possible recompiler bug; see load_seg_vm) */
1316 if (pCtx->csHid.Attr.n.u1Present == 0)
1317 return false;
1318 if (pCtx->ssHid.Attr.n.u1Present == 0)
1319 return false;
1320
1321 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
1322 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
1323 /** @todo This check is actually wrong, it doesn't take the direction of the
1324 * stack segment into account. But, it does the job for now. */
1325 if (pCtx->rsp >= pCtx->ssHid.u32Limit)
1326 return false;
1327#if 0
1328 if ( pCtx->cs >= pCtx->gdtr.cbGdt
1329 || pCtx->ss >= pCtx->gdtr.cbGdt
1330 || pCtx->ds >= pCtx->gdtr.cbGdt
1331 || pCtx->es >= pCtx->gdtr.cbGdt
1332 || pCtx->fs >= pCtx->gdtr.cbGdt
1333 || pCtx->gs >= pCtx->gdtr.cbGdt)
1334 return false;
1335#endif
1336 }
1337 }
1338
1339 if (pVM->hwaccm.s.vmx.fEnabled)
1340 {
1341 uint32_t mask;
1342
1343 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
1344 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
1345 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
1346 mask &= ~X86_CR0_NE;
1347
1348#ifdef HWACCM_VMX_EMULATE_REALMODE
1349 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1350 {
1351 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
1352 mask &= ~(X86_CR0_PG|X86_CR0_PE);
1353 }
1354 else
1355#endif
1356 {
1357 /* We support protected mode without paging using identity mapping. */
1358 mask &= ~X86_CR0_PG;
1359 }
1360 if ((pCtx->cr0 & mask) != mask)
1361 return false;
1362
1363 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
1364 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
1365 if ((pCtx->cr0 & mask) != 0)
1366 return false;
1367
1368 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
1369 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1370 mask &= ~X86_CR4_VMXE;
1371 if ((pCtx->cr4 & mask) != mask)
1372 return false;
1373
1374 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
1375 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
1376 if ((pCtx->cr4 & mask) != 0)
1377 return false;
1378
1379 pVM->hwaccm.s.fActive = true;
1380 return true;
1381 }
1382
1383 return false;
1384}
1385
1386/**
1387 * Notifcation from EM about a rescheduling into hardware assisted execution
1388 * mode.
1389 *
1390 * @param pVCpu Pointer to the current virtual cpu structure.
1391 */
1392VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
1393{
1394 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
1395}
1396
1397/**
1398 * Notifcation from EM about returning from instruction emulation (REM / EM).
1399 *
1400 * @param pVCpu Pointer to the current virtual cpu structure.
1401 */
1402VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
1403{
1404 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
1405}
1406
1407/**
1408 * Checks if we are currently using hardware accelerated raw mode.
1409 *
1410 * @returns boolean
1411 * @param pVM The VM to operate on.
1412 */
1413VMMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
1414{
1415 return pVM->hwaccm.s.fActive;
1416}
1417
1418/**
1419 * Checks if we are currently using nested paging.
1420 *
1421 * @returns boolean
1422 * @param pVM The VM to operate on.
1423 */
1424VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
1425{
1426 return pVM->hwaccm.s.fNestedPaging;
1427}
1428
1429/**
1430 * Checks if we are currently using VPID in VT-x mode.
1431 *
1432 * @returns boolean
1433 * @param pVM The VM to operate on.
1434 */
1435VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
1436{
1437 return pVM->hwaccm.s.vmx.fVPID;
1438}
1439
1440
1441/**
1442 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
1443 *
1444 * @returns boolean
1445 * @param pVM The VM to operate on.
1446 */
1447VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
1448{
1449 /* @todo SMP */
1450 return HWACCMIsEnabled(pVM) && pVM->aCpus[0].hwaccm.s.Event.fPending;
1451}
1452
1453
1454/**
1455 * Inject an NMI into a running VM
1456 *
1457 * @returns boolean
1458 * @param pVM The VM to operate on.
1459 */
1460VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
1461{
1462 pVM->hwaccm.s.fInjectNMI = true;
1463 return VINF_SUCCESS;
1464}
1465
1466/**
1467 * Check fatal VT-x/AMD-V error and produce some meaningful
1468 * log release message.
1469 *
1470 * @param pVM The VM to operate on.
1471 * @param iStatusCode VBox status code
1472 */
1473VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
1474{
1475 for (unsigned i=0;i<pVM->cCPUs;i++)
1476 {
1477 switch(iStatusCode)
1478 {
1479 case VERR_VMX_INVALID_VMCS_FIELD:
1480 break;
1481
1482 case VERR_VMX_INVALID_VMCS_PTR:
1483 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1484 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
1485 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
1486 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
1487 break;
1488
1489 case VERR_VMX_UNABLE_TO_START_VM:
1490 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1491 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1492#if 0 /* @todo dump the current control fields to the release log */
1493 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
1494 {
1495
1496 }
1497#endif
1498 break;
1499
1500 case VERR_VMX_UNABLE_TO_RESUME_VM:
1501 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1502 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1503 break;
1504
1505 case VERR_VMX_INVALID_VMXON_PTR:
1506 break;
1507 }
1508 }
1509}
1510
1511/**
1512 * Execute state save operation.
1513 *
1514 * @returns VBox status code.
1515 * @param pVM VM Handle.
1516 * @param pSSM SSM operation handle.
1517 */
1518static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
1519{
1520 int rc;
1521
1522 Log(("hwaccmR3Save:\n"));
1523
1524 for (unsigned i=0;i<pVM->cCPUs;i++)
1525 {
1526 /*
1527 * Save the basic bits - fortunately all the other things can be resynced on load.
1528 */
1529 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
1530 AssertRCReturn(rc, rc);
1531 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
1532 AssertRCReturn(rc, rc);
1533 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
1534 AssertRCReturn(rc, rc);
1535
1536 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
1537 AssertRCReturn(rc, rc);
1538 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
1539 AssertRCReturn(rc, rc);
1540 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
1541 AssertRCReturn(rc, rc);
1542 }
1543
1544 return VINF_SUCCESS;
1545}
1546
1547/**
1548 * Execute state load operation.
1549 *
1550 * @returns VBox status code.
1551 * @param pVM VM Handle.
1552 * @param pSSM SSM operation handle.
1553 * @param u32Version Data layout version.
1554 */
1555static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1556{
1557 int rc;
1558
1559 Log(("hwaccmR3Load:\n"));
1560
1561 /*
1562 * Validate version.
1563 */
1564 if ( u32Version != HWACCM_SSM_VERSION
1565 && u32Version != HWACCM_SSM_VERSION_2_0_X)
1566 {
1567 AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
1568 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1569 }
1570 for (unsigned i=0;i<pVM->cCPUs;i++)
1571 {
1572 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
1573 AssertRCReturn(rc, rc);
1574 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
1575 AssertRCReturn(rc, rc);
1576 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
1577 AssertRCReturn(rc, rc);
1578
1579 if (u32Version >= HWACCM_SSM_VERSION)
1580 {
1581 uint32_t val;
1582
1583 rc = SSMR3GetU32(pSSM, &val);
1584 AssertRCReturn(rc, rc);
1585 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
1586
1587 rc = SSMR3GetU32(pSSM, &val);
1588 AssertRCReturn(rc, rc);
1589 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
1590
1591 rc = SSMR3GetU32(pSSM, &val);
1592 AssertRCReturn(rc, rc);
1593 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
1594 }
1595 }
1596 return VINF_SUCCESS;
1597}
1598
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