HWACCM.cpp@ 19702

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1	/* $Id: HWACCM.cpp 19697 2009-05-14 14:00:44Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_HWACCM
26	#include <VBox/cpum.h>
27	#include <VBox/stam.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/trpm.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/patm.h>
34	#include <VBox/csam.h>
35	#include <VBox/selm.h>
36	#include <VBox/rem.h>
37	#include <VBox/hwacc_vmx.h>
38	#include <VBox/hwacc_svm.h>
39	#include "HWACCMInternal.h"
40	#include <VBox/vm.h>
41	#include <VBox/err.h>
42	#include <VBox/param.h>
43
44	#include <iprt/assert.h>
45	#include <VBox/log.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48	#include <iprt/thread.h>
49
50	/*******************************************************************************
51	* Global Variables *
52	*******************************************************************************/
53	#ifdef VBOX_WITH_STATISTICS
54	# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55	# define EXIT_REASON_NIL() NULL
56	/** Exit reason descriptions for VT-x, used to describe statistics. */
57	static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58	{
59	EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60	EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61	EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62	EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63	EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64	EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65	EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66	EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67	EXIT_REASON_NIL(),
68	EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69	EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70	EXIT_REASON_NIL(),
71	EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72	EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73	EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74	EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75	EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76	EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77	EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78	EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79	EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80	EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81	EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82	EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83	EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84	EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85	EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86	EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87	EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88	EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89	EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90	EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91	EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92	EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93	EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94	EXIT_REASON_NIL(),
95	EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96	EXIT_REASON_NIL(),
97	EXIT_REASON_NIL(),
98	EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99	EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100	EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101	EXIT_REASON_NIL(),
102	EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103	EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104	EXIT_REASON_NIL(),
105	EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106	EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107	EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108	EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109	EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110	EXIT_REASON_NIL(),
111	EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112	EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113	EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114	EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115	EXIT_REASON_NIL()
116	};
117	/** Exit reason descriptions for AMD-V, used to describe statistics. */
118	static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119	{
120	/** @todo fill in these. */
121	EXIT_REASON_NIL()
122	};
123	# undef EXIT_REASON
124	# undef EXIT_REASON_NIL
125	#endif /* VBOX_WITH_STATISTICS */
126
127	/*******************************************************************************
128	* Internal Functions *
129	*******************************************************************************/
130	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
131	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
132
133
134	/**
135	* Initializes the HWACCM.
136	*
137	* @returns VBox status code.
138	* @param pVM The VM to operate on.
139	*/
140	VMMR3DECL(int) HWACCMR3Init(PVM pVM)
141	{
142	LogFlow(("HWACCMR3Init\n"));
143
144	/*
145	* Assert alignment and sizes.
146	*/
147	AssertCompileMemberAlignment(VM, hwaccm.s, 32);
148	AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
149
150	/* Some structure checks. */
151	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
152	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
153	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
154	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
155
156	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
157	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
158	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
159	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
160	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
161	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
162	AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
163
164
165	/*
166	* Register the saved state data unit.
167	*/
168	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
169	NULL, hwaccmR3Save, NULL,
170	NULL, hwaccmR3Load, NULL);
171	if (RT_FAILURE(rc))
172	return rc;
173
174	/* Misc initialisation. */
175	pVM->hwaccm.s.vmx.fSupported = false;
176	pVM->hwaccm.s.svm.fSupported = false;
177	pVM->hwaccm.s.vmx.fEnabled = false;
178	pVM->hwaccm.s.svm.fEnabled = false;
179
180	pVM->hwaccm.s.fNestedPaging = false;
181
182	/* Disabled by default. */
183	pVM->fHWACCMEnabled = false;
184
185	/*
186	* Check CFGM options.
187	*/
188	PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
189	PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
190	/* Nested paging: disabled by default. */
191	rc = CFGMR3QueryBoolDef(pRoot, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
192	AssertRC(rc);
193
194	/* VT-x VPID: disabled by default. */
195	rc = CFGMR3QueryBoolDef(pRoot, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
196	AssertRC(rc);
197
198	/* HWACCM support must be explicitely enabled in the configuration file. */
199	rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
200	AssertRC(rc);
201
202	#ifdef RT_OS_DARWIN
203	if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
204	#else
205	if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
206	#endif
207	{
208	AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
209	VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
210	return VERR_HWACCM_CONFIG_MISMATCH;
211	}
212
213	if (VMMIsHwVirtExtForced(pVM))
214	pVM->fHWACCMEnabled = true;
215
216	#if HC_ARCH_BITS == 32
217	/* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
218	* (To use the default, don't set 64bitEnabled in CFGM.) */
219	rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
220	AssertLogRelRCReturn(rc, rc);
221	if (pVM->hwaccm.s.fAllow64BitGuests)
222	{
223	# ifdef RT_OS_DARWIN
224	if (!VMMIsHwVirtExtForced(pVM))
225	# else
226	if (!pVM->hwaccm.s.fAllowed)
227	# endif
228	return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
229	}
230	#else
231	/* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
232	* via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
233	rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
234	AssertLogRelRCReturn(rc, rc);
235	#endif
236
237	return VINF_SUCCESS;
238	}
239
240	/**
241	* Initializes the per-VCPU HWACCM.
242	*
243	* @returns VBox status code.
244	* @param pVM The VM to operate on.
245	*/
246	VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
247	{
248	LogFlow(("HWACCMR3InitCPU\n"));
249
250	for (unsigned i=0;i<pVM->cCPUs;i++)
251	{
252	PVMCPU pVCpu = &pVM->aCpus[i];
253
254	pVCpu->hwaccm.s.fActive = false;
255	}
256
257	#ifdef VBOX_WITH_STATISTICS
258	/*
259	* Statistics.
260	*/
261	for (unsigned i=0;i<pVM->cCPUs;i++)
262	{
263	PVMCPU pVCpu = &pVM->aCpus[i];
264	int rc;
265
266	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
267	"/PROF/HWACCM/CPU%d/SwitchToGC", i);
268	AssertRC(rc);
269	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
270	"/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
271	AssertRC(rc);
272	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
273	"/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
274	AssertRC(rc);
275	# if 1 /* temporary for tracking down darwin holdup. */
276	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
277	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
278	AssertRC(rc);
279	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
280	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
281	AssertRC(rc);
282	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
283	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
284	AssertRC(rc);
285	# endif
286	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
287	"/PROF/HWACCM/CPU%d/InGC", i);
288	AssertRC(rc);
289
290	# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
291	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
292	"/PROF/HWACCM/CPU%d/Switcher3264", i);
293	AssertRC(rc);
294	# endif
295
296	# define HWACCM_REG_COUNTER(a, b) \
297	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
298	AssertRC(rc);
299
300	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
301	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
302	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
303	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
304	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
305	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
306	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
307	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
308	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
309	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
310	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
311	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
312	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
313	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
314	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
315	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
316	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
317	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
318	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
319	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
320	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
321	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
322	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
323	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
324	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
325	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
326	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
327	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
328	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
329	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
330	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
331	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
332	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
333	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
334	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
335	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
336
337	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
338	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
339
340	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
341	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
342	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
343
344	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
345	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
346	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
347	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
348	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
349	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
350	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
351	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
352	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
353	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/TLB/Shootdown");
354
355	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
356	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
357
358	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
359	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
360	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
361
362	for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
363	{
364	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
365	"/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
366	AssertRC(rc);
367	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
368	"/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
369	AssertRC(rc);
370	}
371
372	#undef HWACCM_REG_COUNTER
373
374	pVCpu->hwaccm.s.paStatExitReason = NULL;
375
376	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
377	AssertRC(rc);
378	if (RT_SUCCESS(rc))
379	{
380	const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
381	for (int j=0;j<MAX_EXITREASON_STAT;j++)
382	{
383	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
384	papszDesc[j] ? papszDesc[j] : "Exit reason",
385	"/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
386	AssertRC(rc);
387	}
388	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
389	AssertRC(rc);
390	}
391	pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
392	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
393	Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
394	# else
395	Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
396	# endif
397	}
398	#endif /* VBOX_WITH_STATISTICS */
399
400	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
401	/* Magic marker for searching in crash dumps. */
402	for (unsigned i=0;i<pVM->cCPUs;i++)
403	{
404	PVMCPU pVCpu = &pVM->aCpus[i];
405
406	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
407	strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
408	pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
409	}
410	#endif
411	return VINF_SUCCESS;
412	}
413
414	/**
415	* Turns off normal raw mode features
416	*
417	* @param pVM The VM to operate on.
418	*/
419	static void hwaccmR3DisableRawMode(PVM pVM)
420	{
421	/* Disable PATM & CSAM. */
422	PATMR3AllowPatching(pVM, false);
423	CSAMDisableScanning(pVM);
424
425	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
426	SELMR3DisableMonitoring(pVM);
427	TRPMR3DisableMonitoring(pVM);
428
429	/* Disable the switcher code (safety precaution). */
430	VMMR3DisableSwitcher(pVM);
431
432	/* Disable mapping of the hypervisor into the shadow page table. */
433	PGMR3MappingsDisable(pVM);
434
435	/* Disable the switcher */
436	VMMR3DisableSwitcher(pVM);
437
438	/* Reinit the paging mode to force the new shadow mode. */
439	for (unsigned i=0;i<pVM->cCPUs;i++)
440	{
441	PVMCPU pVCpu = &pVM->aCpus[i];
442
443	PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
444	}
445	}
446
447	/**
448	* Initialize VT-x or AMD-V.
449	*
450	* @returns VBox status code.
451	* @param pVM The VM handle.
452	*/
453	VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
454	{
455	int rc;
456
457	if ( !pVM->hwaccm.s.vmx.fSupported
458	&& !pVM->hwaccm.s.svm.fSupported)
459	{
460	LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
461	LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
462	if (VMMIsHwVirtExtForced(pVM))
463	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
464	return VINF_SUCCESS;
465	}
466
467	if (!pVM->hwaccm.s.fAllowed)
468	return VINF_SUCCESS; /* nothing to do */
469
470	/* Enable VT-x or AMD-V on all host CPUs. */
471	rc = SUPCallVMMR0Ex(pVM->pVMR0, 0 /* VCPU 0 */, VMMR0_DO_HWACC_ENABLE, 0, NULL);
472	if (RT_FAILURE(rc))
473	{
474	LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
475	return rc;
476	}
477	Assert(!pVM->fHWACCMEnabled \|\| VMMIsHwVirtExtForced(pVM));
478
479	if (pVM->hwaccm.s.vmx.fSupported)
480	{
481	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
482
483	if ( pVM->hwaccm.s.fInitialized == false
484	&& pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
485	{
486	uint64_t val;
487	RTGCPHYS GCPhys = 0;
488
489	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
490	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
491	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
492	LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
493	LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
494	LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
495	LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
496	LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
497
498	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
499	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
500	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
501	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
502	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
503	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
504	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
505	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
506	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
507	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
508	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
509	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
510	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT must be set\n"));
511	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
512	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT must be set\n"));
513	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
514	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI must be set\n"));
515	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
516	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER must be set\n"));
517
518	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
519	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
520	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
521	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
522	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
523	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
524	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
525	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
526	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
527	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
528	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
529	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
530	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
531	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
532	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
533	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
534	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
535	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
536	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
537	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
538	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
539	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
540	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
541	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
542	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
543	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
544	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
545	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
546	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
547	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
548	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
549	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
550	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
551	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
552	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
553	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
554	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
555	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
556	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
557	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
558	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
559	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
560	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
561	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
562
563	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
564	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
565	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT must be set\n"));
566	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
567	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET must be set\n"));
568	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
569	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT must be set\n"));
570	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
571	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT must be set\n"));
572	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
573	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT must be set\n"));
574	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
575	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT must be set\n"));
576	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
577	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT must be set\n"));
578	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
579	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT must be set\n"));
580	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
581	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT must be set\n"));
582	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
583	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT must be set\n"));
584	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
585	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT must be set\n"));
586	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
587	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW must be set\n"));
588	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
589	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT must be set\n"));
590	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
591	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT must be set\n"));
592	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
593	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT must be set\n"));
594	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
595	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS must be set\n"));
596	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
597	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG must be set\n"));
598	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
599	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS must be set\n"));
600	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
601	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT must be set\n"));
602	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
603	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT must be set\n"));
604	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
605	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL must be set\n"));
606
607	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
608	{
609	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
610	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
611	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
612	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
613	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
614	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
615	if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
616	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
617	if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
618	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
619	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
620	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
621	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
622	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
623
624	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
625	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
626	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC must be set\n"));
627	if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
628	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT must be set\n"));
629	if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
630	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC must be set\n"));
631	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
632	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT must be set\n"));
633	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
634	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID must be set\n"));
635	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
636	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT must be set\n"));
637	}
638
639	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
640	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
641	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
642	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
643	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
644	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
645	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
646	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
647	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
648	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
649	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
650	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
651	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
652	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
653	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
654	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
655	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
656	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
657	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG must be set\n"));
658	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
659	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE must be set\n"));
660	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
661	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM must be set\n"));
662	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
663	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON must be set\n"));
664	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
665	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR must be set\n"));
666	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
667	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR must be set\n"));
668	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
669	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR must be set\n"));
670
671	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
672	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
673	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
674	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
675	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
676	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
677	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
678	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
679	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
680	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
681	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
682	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
683	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
684	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
685	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
686	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
687	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
688	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
689	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
690	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
691	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG must be set\n"));
692	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
693	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 must be set\n"));
694	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
695	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ must be set\n"));
696	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
697	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR must be set\n"));
698	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
699	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR must be set\n"));
700	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
701	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR must be set\n"));
702	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
703	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR must be set\n"));
704	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
705	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER must be set\n"));
706
707	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
708	{
709	LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
710
711	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
712	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
713	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
714	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
715	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
716	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
717	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
718	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
719	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
720	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
721	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
722	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
723	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
724	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
725	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
726	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
727	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
728	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
729	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
730	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
731	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
732	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
733	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
734	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
735	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
736	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
737	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
738	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
739	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
740	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
741	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
742	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
743	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
744	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
745	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
746	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
747	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
748	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
749	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
750	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
751	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
752	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
753	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
754	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
755	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
756	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
757	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
758	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
759	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
760	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
761	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
762	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
763	}
764
765	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
766	LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
767	LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
768	LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
769	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
770	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
771
772	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
773	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
774	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
775	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
776	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
777
778	LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
779	LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
780
781	for (unsigned i=0;i<pVM->cCPUs;i++)
782	LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
783
784	#ifdef HWACCM_VTX_WITH_EPT
785	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
786	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
787	#endif /* HWACCM_VTX_WITH_EPT */
788	#ifdef HWACCM_VTX_WITH_VPID
789	if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
790	&& !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
791	pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
792	#endif /* HWACCM_VTX_WITH_VPID */
793
794	/* Only try once. */
795	pVM->hwaccm.s.fInitialized = true;
796
797	/* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
798	#if 1
799	rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
800	#else
801	rc = VERR_NO_MEMORY; /* simulation of no VMMDev Heap. */
802	#endif
803	if (RT_SUCCESS(rc))
804	{
805	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
806	ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
807	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
808	/* Bit set to 0 means redirection enabled. */
809	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
810	/* Allow all port IO, so the VT-x IO intercepts do their job. */
811	memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
812	((unsigned char )pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
813
814	/* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
815	* real and protected mode without paging with EPT.
816	*/
817	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
818	for (unsigned i=0;i<X86_PG_ENTRIES;i++)
819	{
820	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
821	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_G;
822	}
823
824	/* We convert it here every time as pci regions could be reconfigured. */
825	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
826	AssertRC(rc);
827	LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
828
829	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
830	AssertRC(rc);
831	LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
832	}
833	else
834	{
835	LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
836	pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
837	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
838	}
839
840	rc = SUPCallVMMR0Ex(pVM->pVMR0, 0 /* VCPU 0 */, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
841	AssertRC(rc);
842	if (rc == VINF_SUCCESS)
843	{
844	pVM->fHWACCMEnabled = true;
845	pVM->hwaccm.s.vmx.fEnabled = true;
846	hwaccmR3DisableRawMode(pVM);
847
848	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
849	#ifdef VBOX_ENABLE_64_BITS_GUESTS
850	if (pVM->hwaccm.s.fAllow64BitGuests)
851	{
852	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
853	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
854	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
855	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
856	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
857	}
858	LogRel((pVM->hwaccm.s.fAllow64BitGuests
859	? "HWACCM: 32-bit and 64-bit guests supported.\n"
860	: "HWACCM: 32-bit guests supported.\n"));
861	#else
862	LogRel(("HWACCM: 32-bit guests supported.\n"));
863	#endif
864	LogRel(("HWACCM: VMX enabled!\n"));
865	if (pVM->hwaccm.s.fNestedPaging)
866	{
867	LogRel(("HWACCM: Enabled nested paging\n"));
868	LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
869	}
870	if (pVM->hwaccm.s.vmx.fVPID)
871	LogRel(("HWACCM: Enabled VPID\n"));
872
873	if ( pVM->hwaccm.s.fNestedPaging
874	\|\| pVM->hwaccm.s.vmx.fVPID)
875	{
876	LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
877	LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
878	}
879	}
880	else
881	{
882	LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
883	LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
884	pVM->fHWACCMEnabled = false;
885	}
886	}
887	}
888	else
889	if (pVM->hwaccm.s.svm.fSupported)
890	{
891	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
892
893	if (pVM->hwaccm.s.fInitialized == false)
894	{
895	/* Erratum 170 which requires a forced TLB flush for each world switch:
896	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
897	*
898	* All BH-G1/2 and DH-G1/2 models include a fix:
899	* Athlon X2: 0x6b 1/2
900	* 0x68 1/2
901	* Athlon 64: 0x7f 1
902	* 0x6f 2
903	* Sempron: 0x7f 1/2
904	* 0x6f 2
905	* 0x6c 2
906	* 0x7c 2
907	* Turion 64: 0x68 2
908	*
909	*/
910	uint32_t u32Dummy;
911	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
912	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
913	u32BaseFamily= (u32Version >> 8) & 0xf;
914	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
915	u32Model = ((u32Version >> 4) & 0xf);
916	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
917	u32Stepping = u32Version & 0xf;
918	if ( u32Family == 0xf
919	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
920	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
921	{
922	LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
923	}
924
925	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
926	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
927	LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
928	LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
929	LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
930
931	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
932	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
933	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
934	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
935	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
936	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
937	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
938	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
939	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
940	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
941
942	/* Only try once. */
943	pVM->hwaccm.s.fInitialized = true;
944
945	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
946	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
947
948	rc = SUPCallVMMR0Ex(pVM->pVMR0, 0 /* VCPU 0 */, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
949	AssertRC(rc);
950	if (rc == VINF_SUCCESS)
951	{
952	pVM->fHWACCMEnabled = true;
953	pVM->hwaccm.s.svm.fEnabled = true;
954
955	if (pVM->hwaccm.s.fNestedPaging)
956	LogRel(("HWACCM: Enabled nested paging\n"));
957
958	hwaccmR3DisableRawMode(pVM);
959	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
960	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
961	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
962	#ifdef VBOX_ENABLE_64_BITS_GUESTS
963	if (pVM->hwaccm.s.fAllow64BitGuests)
964	{
965	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
966	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
967	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
968	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
969	}
970	#endif
971	LogRel((pVM->hwaccm.s.fAllow64BitGuests
972	? "HWACCM: 32-bit and 64-bit guest supported.\n"
973	: "HWACCM: 32-bit guest supported.\n"));
974	}
975	else
976	{
977	pVM->fHWACCMEnabled = false;
978	}
979	}
980	}
981	return VINF_SUCCESS;
982	}
983
984	/**
985	* Applies relocations to data and code managed by this
986	* component. This function will be called at init and
987	* whenever the VMM need to relocate it self inside the GC.
988	*
989	* @param pVM The VM.
990	*/
991	VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
992	{
993	Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
994
995	/* Fetch the current paging mode during the relocate callback during state loading. */
996	if (VMR3GetState(pVM) == VMSTATE_LOADING)
997	{
998	for (unsigned i=0;i<pVM->cCPUs;i++)
999	{
1000	PVMCPU pVCpu = &pVM->aCpus[i];
1001	/* @todo SMP */
1002	pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1003	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMGetGuestMode(pVCpu);
1004	}
1005	}
1006	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1007	if (pVM->fHWACCMEnabled)
1008	{
1009	int rc;
1010
1011	switch(PGMGetHostMode(pVM))
1012	{
1013	case PGMMODE_32_BIT:
1014	pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1015	break;
1016
1017	case PGMMODE_PAE:
1018	case PGMMODE_PAE_NX:
1019	pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1020	break;
1021
1022	default:
1023	AssertFailed();
1024	break;
1025	}
1026	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1027	AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1028
1029	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1030	AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1031
1032	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1033	AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1034
1035	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1036	AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1037
1038	# ifdef DEBUG
1039	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1040	AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1041	# endif
1042	}
1043	#endif
1044	return;
1045	}
1046
1047	/**
1048	* Checks hardware accelerated raw mode is allowed.
1049	*
1050	* @returns boolean
1051	* @param pVM The VM to operate on.
1052	*/
1053	VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1054	{
1055	return pVM->hwaccm.s.fAllowed;
1056	}
1057
1058	/**
1059	* Notification callback which is called whenever there is a chance that a CR3
1060	* value might have changed.
1061	*
1062	* This is called by PGM.
1063	*
1064	* @param pVM The VM to operate on.
1065	* @param pVCpu The VMCPU to operate on.
1066	* @param enmShadowMode New shadow paging mode.
1067	* @param enmGuestMode New guest paging mode.
1068	*/
1069	VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1070	{
1071	/* Ignore page mode changes during state loading. */
1072	if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1073	return;
1074
1075	pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1076
1077	if ( pVM->hwaccm.s.vmx.fEnabled
1078	&& pVM->fHWACCMEnabled)
1079	{
1080	if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1081	&& enmGuestMode >= PGMMODE_PROTECTED)
1082	{
1083	PCPUMCTX pCtx;
1084
1085	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1086
1087	/* After a real mode switch to protected mode we must force
1088	* CPL to 0. Our real mode emulation had to set it to 3.
1089	*/
1090	pCtx->ssHid.Attr.n.u2Dpl = 0;
1091	}
1092	}
1093
1094	if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1095	{
1096	/* Keep track of paging mode changes. */
1097	pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1098	pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1099
1100	/* Did we miss a change, because all code was executed in the recompiler? */
1101	if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1102	{
1103	Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1104	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1105	}
1106	}
1107
1108	/* Reset the contents of the read cache. */
1109	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1110	for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1111	pCache->Read.aFieldVal[j] = 0;
1112	}
1113
1114	/**
1115	* Terminates the HWACCM.
1116	*
1117	* Termination means cleaning up and freeing all resources,
1118	* the VM it self is at this point powered off or suspended.
1119	*
1120	* @returns VBox status code.
1121	* @param pVM The VM to operate on.
1122	*/
1123	VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1124	{
1125	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1126	{
1127	PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1128	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1129	}
1130	HWACCMR3TermCPU(pVM);
1131	return 0;
1132	}
1133
1134	/**
1135	* Terminates the per-VCPU HWACCM.
1136	*
1137	* Termination means cleaning up and freeing all resources,
1138	* the VM it self is at this point powered off or suspended.
1139	*
1140	* @returns VBox status code.
1141	* @param pVM The VM to operate on.
1142	*/
1143	VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1144	{
1145	for (unsigned i=0;i<pVM->cCPUs;i++)
1146	{
1147	PVMCPU pVCpu = &pVM->aCpus[i];
1148
1149	if (pVCpu->hwaccm.s.paStatExitReason)
1150	{
1151	MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1152	pVCpu->hwaccm.s.paStatExitReason = NULL;
1153	pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1154	}
1155	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1156	memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1157	pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1158	pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1159	#endif
1160	}
1161	return 0;
1162	}
1163
1164	/**
1165	* The VM is being reset.
1166	*
1167	* For the HWACCM component this means that any GDT/LDT/TSS monitors
1168	* needs to be removed.
1169	*
1170	* @param pVM VM handle.
1171	*/
1172	VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1173	{
1174	LogFlow(("HWACCMR3Reset:\n"));
1175
1176	if (pVM->fHWACCMEnabled)
1177	hwaccmR3DisableRawMode(pVM);
1178
1179	for (unsigned i=0;i<pVM->cCPUs;i++)
1180	{
1181	PVMCPU pVCpu = &pVM->aCpus[i];
1182
1183	/* On first entry we'll sync everything. */
1184	pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1185
1186	pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1187	pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1188
1189	pVCpu->hwaccm.s.fActive = false;
1190	pVCpu->hwaccm.s.Event.fPending = false;
1191
1192	/* Reset state information for real-mode emulation in VT-x. */
1193	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1194	pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1195	pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1196
1197	/* Reset the contents of the read cache. */
1198	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1199	for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1200	pCache->Read.aFieldVal[j] = 0;
1201
1202	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1203	/* Magic marker for searching in crash dumps. */
1204	strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1205	pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1206	#endif
1207	}
1208	}
1209
1210	/**
1211	* Force execution of the current IO code in the recompiler
1212	*
1213	* @returns VBox status code.
1214	* @param pVM The VM to operate on.
1215	* @param pCtx Partial VM execution context
1216	*/
1217	VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
1218	{
1219	PVMCPU pVCpu = VMMGetCpu(pVM);
1220
1221	Assert(pVM->fHWACCMEnabled);
1222	Log(("HWACCMR3EmulateIoBlock\n"));
1223
1224	/* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
1225	if (HWACCMCanEmulateIoBlockEx(pCtx))
1226	{
1227	Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
1228	pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
1229	pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
1230	pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
1231	return VINF_EM_RESCHEDULE_REM;
1232	}
1233	return VINF_SUCCESS;
1234	}
1235
1236	/**
1237	* Checks if we can currently use hardware accelerated raw mode.
1238	*
1239	* @returns boolean
1240	* @param pVM The VM to operate on.
1241	* @param pCtx Partial VM execution context
1242	*/
1243	VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
1244	{
1245	PVMCPU pVCpu = VMMGetCpu(pVM);
1246
1247	Assert(pVM->fHWACCMEnabled);
1248
1249	/* If we're still executing the IO code, then return false. */
1250	if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
1251	&& pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
1252	&& pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
1253	&& pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
1254	return false;
1255
1256	pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
1257
1258	/* AMD-V supports real & protected mode with or without paging. */
1259	if (pVM->hwaccm.s.svm.fEnabled)
1260	{
1261	pVCpu->hwaccm.s.fActive = true;
1262	return true;
1263	}
1264
1265	pVCpu->hwaccm.s.fActive = false;
1266
1267	/* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
1268	#ifdef HWACCM_VMX_EMULATE_REALMODE
1269	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1270	{
1271	if (CPUMIsGuestInRealModeEx(pCtx))
1272	{
1273	/* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
1274	* The base must also be equal to (sel << 4).
1275	*/
1276	if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
1277	&& pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
1278	\|\| pCtx->ds != (pCtx->dsHid.u64Base >> 4)
1279	\|\| pCtx->es != (pCtx->esHid.u64Base >> 4)
1280	\|\| pCtx->fs != (pCtx->fsHid.u64Base >> 4)
1281	\|\| pCtx->gs != (pCtx->gsHid.u64Base >> 4)
1282	\|\| pCtx->ss != (pCtx->ssHid.u64Base >> 4))
1283	{
1284	return false;
1285	}
1286	}
1287	else
1288	{
1289	PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
1290	/* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
1291	* from real to protected mode. (all sorts of RPL & DPL assumptions)
1292	*/
1293	if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1294	&& enmGuestMode >= PGMMODE_PROTECTED)
1295	{
1296	if ( (pCtx->cs & X86_SEL_RPL)
1297	\|\| (pCtx->ds & X86_SEL_RPL)
1298	\|\| (pCtx->es & X86_SEL_RPL)
1299	\|\| (pCtx->fs & X86_SEL_RPL)
1300	\|\| (pCtx->gs & X86_SEL_RPL)
1301	\|\| (pCtx->ss & X86_SEL_RPL))
1302	{
1303	return false;
1304	}
1305	}
1306	}
1307	}
1308	else
1309	#endif /* HWACCM_VMX_EMULATE_REALMODE */
1310	{
1311	if (!CPUMIsGuestInLongModeEx(pCtx))
1312	{
1313	/** @todo This should (probably) be set on every excursion to the REM,
1314	* however it's too risky right now. So, only apply it when we go
1315	* back to REM for real mode execution. (The XP hack below doesn't
1316	* work reliably without this.)
1317	* Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
1318	pVM->aCpus[0].hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1319
1320	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
1321	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
1322	return false;
1323
1324	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
1325	/* Windows XP; switch to protected mode; all selectors are marked not present in the
1326	* hidden registers (possible recompiler bug; see load_seg_vm) */
1327	if (pCtx->csHid.Attr.n.u1Present == 0)
1328	return false;
1329	if (pCtx->ssHid.Attr.n.u1Present == 0)
1330	return false;
1331
1332	/* Windows XP: possible same as above, but new recompiler requires new heuristics?
1333	VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
1334	/** @todo This check is actually wrong, it doesn't take the direction of the
1335	* stack segment into account. But, it does the job for now. */
1336	if (pCtx->rsp >= pCtx->ssHid.u32Limit)
1337	return false;
1338	#if 0
1339	if ( pCtx->cs >= pCtx->gdtr.cbGdt
1340	\|\| pCtx->ss >= pCtx->gdtr.cbGdt
1341	\|\| pCtx->ds >= pCtx->gdtr.cbGdt
1342	\|\| pCtx->es >= pCtx->gdtr.cbGdt
1343	\|\| pCtx->fs >= pCtx->gdtr.cbGdt
1344	\|\| pCtx->gs >= pCtx->gdtr.cbGdt)
1345	return false;
1346	#endif
1347	}
1348	}
1349
1350	if (pVM->hwaccm.s.vmx.fEnabled)
1351	{
1352	uint32_t mask;
1353
1354	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
1355	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
1356	/* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
1357	mask &= ~X86_CR0_NE;
1358
1359	#ifdef HWACCM_VMX_EMULATE_REALMODE
1360	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1361	{
1362	/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
1363	mask &= ~(X86_CR0_PG\|X86_CR0_PE);
1364	}
1365	else
1366	#endif
1367	{
1368	/* We support protected mode without paging using identity mapping. */
1369	mask &= ~X86_CR0_PG;
1370	}
1371	if ((pCtx->cr0 & mask) != mask)
1372	return false;
1373
1374	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
1375	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
1376	if ((pCtx->cr0 & mask) != 0)
1377	return false;
1378
1379	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
1380	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1381	mask &= ~X86_CR4_VMXE;
1382	if ((pCtx->cr4 & mask) != mask)
1383	return false;
1384
1385	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
1386	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
1387	if ((pCtx->cr4 & mask) != 0)
1388	return false;
1389
1390	pVCpu->hwaccm.s.fActive = true;
1391	return true;
1392	}
1393
1394	return false;
1395	}
1396
1397	/**
1398	* Notifcation from EM about a rescheduling into hardware assisted execution
1399	* mode.
1400	*
1401	* @param pVCpu Pointer to the current virtual cpu structure.
1402	*/
1403	VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
1404	{
1405	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1406	}
1407
1408	/**
1409	* Notifcation from EM about returning from instruction emulation (REM / EM).
1410	*
1411	* @param pVCpu Pointer to the current virtual cpu structure.
1412	*/
1413	VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
1414	{
1415	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
1416	}
1417
1418	/**
1419	* Checks if we are currently using hardware accelerated raw mode.
1420	*
1421	* @returns boolean
1422	* @param pVCpu The VMCPU to operate on.
1423	*/
1424	VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
1425	{
1426	return pVCpu->hwaccm.s.fActive;
1427	}
1428
1429	/**
1430	* Checks if we are currently using nested paging.
1431	*
1432	* @returns boolean
1433	* @param pVM The VM to operate on.
1434	*/
1435	VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
1436	{
1437	return pVM->hwaccm.s.fNestedPaging;
1438	}
1439
1440	/**
1441	* Checks if we are currently using VPID in VT-x mode.
1442	*
1443	* @returns boolean
1444	* @param pVM The VM to operate on.
1445	*/
1446	VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
1447	{
1448	return pVM->hwaccm.s.vmx.fVPID;
1449	}
1450
1451
1452	/**
1453	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
1454	*
1455	* @returns boolean
1456	* @param pVM The VM to operate on.
1457	*/
1458	VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
1459	{
1460	/* @todo SMP */
1461	return HWACCMIsEnabled(pVM) && pVM->aCpus[0].hwaccm.s.Event.fPending;
1462	}
1463
1464
1465	/**
1466	* Inject an NMI into a running VM
1467	*
1468	* @returns boolean
1469	* @param pVM The VM to operate on.
1470	*/
1471	VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
1472	{
1473	pVM->hwaccm.s.fInjectNMI = true;
1474	return VINF_SUCCESS;
1475	}
1476
1477	/**
1478	* Check fatal VT-x/AMD-V error and produce some meaningful
1479	* log release message.
1480	*
1481	* @param pVM The VM to operate on.
1482	* @param iStatusCode VBox status code
1483	*/
1484	VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
1485	{
1486	for (unsigned i=0;i<pVM->cCPUs;i++)
1487	{
1488	switch(iStatusCode)
1489	{
1490	case VERR_VMX_INVALID_VMCS_FIELD:
1491	break;
1492
1493	case VERR_VMX_INVALID_VMCS_PTR:
1494	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1495	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
1496	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
1497	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
1498	break;
1499
1500	case VERR_VMX_UNABLE_TO_START_VM:
1501	LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1502	LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1503	#if 0 /* @todo dump the current control fields to the release log */
1504	if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
1505	{
1506
1507	}
1508	#endif
1509	break;
1510
1511	case VERR_VMX_UNABLE_TO_RESUME_VM:
1512	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1513	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1514	break;
1515
1516	case VERR_VMX_INVALID_VMXON_PTR:
1517	break;
1518	}
1519	}
1520	}
1521
1522	/**
1523	* Execute state save operation.
1524	*
1525	* @returns VBox status code.
1526	* @param pVM VM Handle.
1527	* @param pSSM SSM operation handle.
1528	*/
1529	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
1530	{
1531	int rc;
1532
1533	Log(("hwaccmR3Save:\n"));
1534
1535	for (unsigned i=0;i<pVM->cCPUs;i++)
1536	{
1537	/*
1538	* Save the basic bits - fortunately all the other things can be resynced on load.
1539	*/
1540	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
1541	AssertRCReturn(rc, rc);
1542	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
1543	AssertRCReturn(rc, rc);
1544	rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
1545	AssertRCReturn(rc, rc);
1546
1547	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
1548	AssertRCReturn(rc, rc);
1549	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
1550	AssertRCReturn(rc, rc);
1551	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
1552	AssertRCReturn(rc, rc);
1553	}
1554
1555	return VINF_SUCCESS;
1556	}
1557
1558	/**
1559	* Execute state load operation.
1560	*
1561	* @returns VBox status code.
1562	* @param pVM VM Handle.
1563	* @param pSSM SSM operation handle.
1564	* @param u32Version Data layout version.
1565	*/
1566	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1567	{
1568	int rc;
1569
1570	Log(("hwaccmR3Load:\n"));
1571
1572	/*
1573	* Validate version.
1574	*/
1575	if ( u32Version != HWACCM_SSM_VERSION
1576	&& u32Version != HWACCM_SSM_VERSION_2_0_X)
1577	{
1578	AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
1579	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1580	}
1581	for (unsigned i=0;i<pVM->cCPUs;i++)
1582	{
1583	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
1584	AssertRCReturn(rc, rc);
1585	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
1586	AssertRCReturn(rc, rc);
1587	rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
1588	AssertRCReturn(rc, rc);
1589
1590	if (u32Version >= HWACCM_SSM_VERSION)
1591	{
1592	uint32_t val;
1593
1594	rc = SSMR3GetU32(pSSM, &val);
1595	AssertRCReturn(rc, rc);
1596	pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
1597
1598	rc = SSMR3GetU32(pSSM, &val);
1599	AssertRCReturn(rc, rc);
1600	pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
1601
1602	rc = SSMR3GetU32(pSSM, &val);
1603	AssertRCReturn(rc, rc);
1604	pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
1605	}
1606	}
1607	return VINF_SUCCESS;
1608	}
1609

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source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 19702

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