VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 20088

Last change on this file since 20088 was 20057, checked in by vboxsync, 16 years ago

Backed out 47767 (breaks saved states from yesterday)
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File size: 90.7 KB
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1/* $Id: HWACCM.cpp 20057 2009-05-27 07:35:46Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/csam.h>
35#include <VBox/selm.h>
36#include <VBox/rem.h>
37#include <VBox/hwacc_vmx.h>
38#include <VBox/hwacc_svm.h>
39#include "HWACCMInternal.h"
40#include <VBox/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/string.h>
48#include <iprt/thread.h>
49
50/*******************************************************************************
51* Global Variables *
52*******************************************************************************/
53#ifdef VBOX_WITH_STATISTICS
54# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55# define EXIT_REASON_NIL() NULL
56/** Exit reason descriptions for VT-x, used to describe statistics. */
57static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58{
59 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67 EXIT_REASON_NIL(),
68 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94 EXIT_REASON_NIL(),
95 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96 EXIT_REASON_NIL(),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101 EXIT_REASON_NIL(),
102 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110 EXIT_REASON_NIL(),
111 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115 EXIT_REASON_NIL()
116};
117/** Exit reason descriptions for AMD-V, used to describe statistics. */
118static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119{
120 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
121 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
122 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
123 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
124 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
125 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
126 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
127 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
128 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
129 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
130 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
131 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
132 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
133 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
134 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
135 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
136 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
137 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
152 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
153 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
154 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
155 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
156 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
157 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
158 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
159 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
160 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
161 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
162 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
163 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
164 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
165 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
166 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
167 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
168 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
169 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
184 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
185 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_INTR , 96, "Physical maskable interrupt."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_NMI , 97, "Physical non-maskable interrupt."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_SMI , 98, "System management interrupt."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_INIT , 99, "Physical INIT signal."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_VINTR ,100, "Visual interrupt."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_IDTR_READ ,102, "Read IDTR"),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_GDTR_READ ,103, "Read GDTR"),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_LDTR_READ ,104, "Read LDTR."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,105, "Read TR."),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,106, "Write IDTR."),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,107, "Write GDTR."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,108, "Write LDTR."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,109, "Write TR."),
230 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
231 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
232 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
233 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
234 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
235 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
236 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
237 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
238 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
239 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
240 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
241 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
242 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
243 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
244 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
245 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
246 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
247 EXIT_REASON(SVM_EXIT_TASK_SHUTDOWN ,127, "Shutdown."),
248 EXIT_REASON(SVM_EXIT_TASK_VMRUN ,128, "VMRUN instruction."),
249 EXIT_REASON(SVM_EXIT_TASK_VMCALL ,129, "VMCALL instruction."),
250 EXIT_REASON(SVM_EXIT_TASK_VMLOAD ,130, "VMLOAD instruction."),
251 EXIT_REASON(SVM_EXIT_TASK_VMSAVE ,131, "VMSAVE instruction."),
252 EXIT_REASON(SVM_EXIT_TASK_STGI ,132, "STGI instruction."),
253 EXIT_REASON(SVM_EXIT_TASK_CLGI ,133, "CLGI instruction."),
254 EXIT_REASON(SVM_EXIT_TASK_SKINIT ,134, "SKINIT instruction."),
255 EXIT_REASON(SVM_EXIT_TASK_RDTSCP ,135, "RDTSCP instruction."),
256 EXIT_REASON(SVM_EXIT_TASK_ICEBP ,136, "ICEBP instruction."),
257 EXIT_REASON(SVM_EXIT_TASK_WBINVD ,137, "WBINVD instruction."),
258 EXIT_REASON(SVM_EXIT_TASK_MONITOR ,138, "MONITOR instruction."),
259 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
260 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
261 EXIT_REASON(SVM_EXIT_MWAIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
262 EXIT_REASON_NIL()
263};
264# undef EXIT_REASON
265# undef EXIT_REASON_NIL
266#endif /* VBOX_WITH_STATISTICS */
267
268/*******************************************************************************
269* Internal Functions *
270*******************************************************************************/
271static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
272static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
273
274
275/**
276 * Initializes the HWACCM.
277 *
278 * @returns VBox status code.
279 * @param pVM The VM to operate on.
280 */
281VMMR3DECL(int) HWACCMR3Init(PVM pVM)
282{
283 LogFlow(("HWACCMR3Init\n"));
284
285 /*
286 * Assert alignment and sizes.
287 */
288 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
289 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
290
291 /* Some structure checks. */
292 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
293 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
294 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
295 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
296
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
300 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
303 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
304
305
306 /*
307 * Register the saved state data unit.
308 */
309 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
310 NULL, hwaccmR3Save, NULL,
311 NULL, hwaccmR3Load, NULL);
312 if (RT_FAILURE(rc))
313 return rc;
314
315 /* Misc initialisation. */
316 pVM->hwaccm.s.vmx.fSupported = false;
317 pVM->hwaccm.s.svm.fSupported = false;
318 pVM->hwaccm.s.vmx.fEnabled = false;
319 pVM->hwaccm.s.svm.fEnabled = false;
320
321 pVM->hwaccm.s.fNestedPaging = false;
322
323 /* Disabled by default. */
324 pVM->fHWACCMEnabled = false;
325
326 /*
327 * Check CFGM options.
328 */
329 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
330 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
331 /* Nested paging: disabled by default. */
332 rc = CFGMR3QueryBoolDef(pRoot, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
333 AssertRC(rc);
334
335 /* VT-x VPID: disabled by default. */
336 rc = CFGMR3QueryBoolDef(pRoot, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
337 AssertRC(rc);
338
339 /* HWACCM support must be explicitely enabled in the configuration file. */
340 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
341 AssertRC(rc);
342
343#ifdef RT_OS_DARWIN
344 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
345#else
346 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
347#endif
348 {
349 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
350 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
351 return VERR_HWACCM_CONFIG_MISMATCH;
352 }
353
354 if (VMMIsHwVirtExtForced(pVM))
355 pVM->fHWACCMEnabled = true;
356
357#if HC_ARCH_BITS == 32
358 /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
359 * (To use the default, don't set 64bitEnabled in CFGM.) */
360 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
361 AssertLogRelRCReturn(rc, rc);
362 if (pVM->hwaccm.s.fAllow64BitGuests)
363 {
364# ifdef RT_OS_DARWIN
365 if (!VMMIsHwVirtExtForced(pVM))
366# else
367 if (!pVM->hwaccm.s.fAllowed)
368# endif
369 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
370 }
371#else
372 /* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
373 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
374 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
375 AssertLogRelRCReturn(rc, rc);
376#endif
377
378 return VINF_SUCCESS;
379}
380
381/**
382 * Initializes the per-VCPU HWACCM.
383 *
384 * @returns VBox status code.
385 * @param pVM The VM to operate on.
386 */
387VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
388{
389 LogFlow(("HWACCMR3InitCPU\n"));
390
391 for (unsigned i=0;i<pVM->cCPUs;i++)
392 {
393 PVMCPU pVCpu = &pVM->aCpus[i];
394
395 pVCpu->hwaccm.s.fActive = false;
396 }
397
398#ifdef VBOX_WITH_STATISTICS
399 /*
400 * Statistics.
401 */
402 for (unsigned i=0;i<pVM->cCPUs;i++)
403 {
404 PVMCPU pVCpu = &pVM->aCpus[i];
405 int rc;
406
407 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
408 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
409 AssertRC(rc);
410 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
411 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
412 AssertRC(rc);
413 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
414 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
415 AssertRC(rc);
416# if 1 /* temporary for tracking down darwin holdup. */
417 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
418 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
419 AssertRC(rc);
420 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
421 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
422 AssertRC(rc);
423 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
424 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
425 AssertRC(rc);
426# endif
427 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
428 "/PROF/HWACCM/CPU%d/InGC", i);
429 AssertRC(rc);
430
431# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
432 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
433 "/PROF/HWACCM/CPU%d/Switcher3264", i);
434 AssertRC(rc);
435# endif
436
437# define HWACCM_REG_COUNTER(a, b) \
438 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
439 AssertRC(rc);
440
441 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
442 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
443 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
444 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
445 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
446 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
447 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
448 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
449 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
450 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
451 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
452 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
453 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
454 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
455 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
456 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
457 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
458 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
459 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
460 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
461 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
462 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
463 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
464 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
465 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
466 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
467 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
468 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
469 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
470 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
471 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
472 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
473 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
474 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
475 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
476 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
477
478 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
479 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
480
481 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
482 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
483 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
484
485 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
486 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
487 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
488 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
489 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
490 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
491 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
492 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
493 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
494 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
495 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
496
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
498 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
499
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
503
504 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
505 {
506 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
507 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
508 AssertRC(rc);
509 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
510 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
511 AssertRC(rc);
512 }
513
514#undef HWACCM_REG_COUNTER
515
516 pVCpu->hwaccm.s.paStatExitReason = NULL;
517
518 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
519 AssertRC(rc);
520 if (RT_SUCCESS(rc))
521 {
522 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
523 for (int j=0;j<MAX_EXITREASON_STAT;j++)
524 {
525 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
526 papszDesc[j] ? papszDesc[j] : "Exit reason",
527 "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
528 AssertRC(rc);
529 }
530 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
531 AssertRC(rc);
532 }
533 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
534# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
535 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
536# else
537 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
538# endif
539 }
540#endif /* VBOX_WITH_STATISTICS */
541
542#ifdef VBOX_WITH_CRASHDUMP_MAGIC
543 /* Magic marker for searching in crash dumps. */
544 for (unsigned i=0;i<pVM->cCPUs;i++)
545 {
546 PVMCPU pVCpu = &pVM->aCpus[i];
547
548 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
549 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
550 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
551 }
552#endif
553 return VINF_SUCCESS;
554}
555
556/**
557 * Turns off normal raw mode features
558 *
559 * @param pVM The VM to operate on.
560 */
561static void hwaccmR3DisableRawMode(PVM pVM)
562{
563 /* Disable PATM & CSAM. */
564 PATMR3AllowPatching(pVM, false);
565 CSAMDisableScanning(pVM);
566
567 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
568 SELMR3DisableMonitoring(pVM);
569 TRPMR3DisableMonitoring(pVM);
570
571 /* Disable the switcher code (safety precaution). */
572 VMMR3DisableSwitcher(pVM);
573
574 /* Disable mapping of the hypervisor into the shadow page table. */
575 PGMR3MappingsDisable(pVM);
576
577 /* Disable the switcher */
578 VMMR3DisableSwitcher(pVM);
579
580 /* Reinit the paging mode to force the new shadow mode. */
581 for (unsigned i=0;i<pVM->cCPUs;i++)
582 {
583 PVMCPU pVCpu = &pVM->aCpus[i];
584
585 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
586 }
587}
588
589/**
590 * Initialize VT-x or AMD-V.
591 *
592 * @returns VBox status code.
593 * @param pVM The VM handle.
594 */
595VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
596{
597 int rc;
598
599 if ( !pVM->hwaccm.s.vmx.fSupported
600 && !pVM->hwaccm.s.svm.fSupported)
601 {
602 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
603 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
604 if (VMMIsHwVirtExtForced(pVM))
605 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
606 return VINF_SUCCESS;
607 }
608
609 if (!pVM->hwaccm.s.fAllowed)
610 return VINF_SUCCESS; /* nothing to do */
611
612 /* Enable VT-x or AMD-V on all host CPUs. */
613 rc = SUPCallVMMR0Ex(pVM->pVMR0, 0 /* VCPU 0 */, VMMR0_DO_HWACC_ENABLE, 0, NULL);
614 if (RT_FAILURE(rc))
615 {
616 LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
617 return rc;
618 }
619 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
620
621 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
622
623 if (pVM->hwaccm.s.vmx.fSupported)
624 {
625 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
626
627 if ( pVM->hwaccm.s.fInitialized == false
628 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
629 {
630 uint64_t val;
631 RTGCPHYS GCPhys = 0;
632
633 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
634 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
635 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
636 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
637 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
638 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
639 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
640 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
641
642 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
643 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
644 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
645 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
646 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
647 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
648 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
649 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
650 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
651 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
652 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
653 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
654 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
655 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
656 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
657 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
658 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
659 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
660 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
661
662 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
663 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
664 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
665 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
666 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
667 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
668 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
669 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
670 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
671 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
672 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
673 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
674 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
675 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
676 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
677 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
678 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
679 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
680 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
681 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
682 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
683 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
684 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
685 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
686 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
687 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
688 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
689 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
690 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
691 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
692 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
693 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
694 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
695 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
696 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
697 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
698 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
699 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
700 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
701 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
702 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
703 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
704 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
705 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
706
707 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
708 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
709 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
710 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
711 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
712 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
713 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
714 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
715 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
716 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
717 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
718 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
719 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
720 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
721 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
722 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
723 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
724 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
725 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
726 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
727 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
728 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
729 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
730 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
731 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
732 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
733 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
734 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
735 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
736 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
737 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
738 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
739 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
740 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
741 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
742 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
743 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
744 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
745 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
746 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
747 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
748 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
749 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
750
751 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
752 {
753 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
754 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
755 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
756 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
757 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
758 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
759 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
760 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
761 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
762 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
763 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
764 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
765 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
766 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
767
768 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
769 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
770 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
771 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
772 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
773 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
774 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
775 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
776 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
777 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
778 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
779 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
780 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
781 }
782
783 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
784 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
785 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
786 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
787 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
788 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
789 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
790 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
791 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
792 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
793 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
794 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
795 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
796 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
797 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
798 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
799 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
800 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
801 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
802 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
803 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
804 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
805 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
806 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
807 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
808 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
809 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
810 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
811 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
812 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
813 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
814
815 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
816 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
817 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
818 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
819 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
820 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
821 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
822 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
823 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
824 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
825 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
826 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
827 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
828 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
829 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
830 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
831 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
832 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
833 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
834 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
835 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
836 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
837 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
838 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
839 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
840 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
841 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
842 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
843 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
844 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
845 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
846 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
847 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
848 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
849 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
850
851 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
852 {
853 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
854
855 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
856 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
857 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
858 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
859 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
860 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
861 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
862 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
863 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
864 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
865 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
866 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
867 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
868 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
869 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
870 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
871 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
872 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
873 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
874 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
875 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
876 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
877 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
878 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
879 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
880 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
881 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
882 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
883 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
884 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
885 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
886 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
887 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
888 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
889 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
890 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
891 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
892 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
893 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
894 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
895 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
896 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
897 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
898 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
899 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
900 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
901 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
902 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
903 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
904 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
905 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
906 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
907 }
908
909 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
910 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
911 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
912 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
913 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
914 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
915
916 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
917 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
918 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
919 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
920 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
921
922 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
923 LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
924
925 for (unsigned i=0;i<pVM->cCPUs;i++)
926 LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
927
928#ifdef HWACCM_VTX_WITH_EPT
929 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
930 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
931#endif /* HWACCM_VTX_WITH_EPT */
932#ifdef HWACCM_VTX_WITH_VPID
933 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
934 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
935 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
936#endif /* HWACCM_VTX_WITH_VPID */
937
938 /* Only try once. */
939 pVM->hwaccm.s.fInitialized = true;
940
941 /* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
942#if 1
943 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
944#else
945 rc = VERR_NO_MEMORY; /* simulation of no VMMDev Heap. */
946#endif
947 if (RT_SUCCESS(rc))
948 {
949 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
950 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
951 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
952 /* Bit set to 0 means redirection enabled. */
953 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
954 /* Allow all port IO, so the VT-x IO intercepts do their job. */
955 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
956 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
957
958 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
959 * real and protected mode without paging with EPT.
960 */
961 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
962 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
963 {
964 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
965 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
966 }
967
968 /* We convert it here every time as pci regions could be reconfigured. */
969 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
970 AssertRC(rc);
971 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
972
973 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
974 AssertRC(rc);
975 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
976 }
977 else
978 {
979 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
980 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
981 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
982 }
983
984 rc = SUPCallVMMR0Ex(pVM->pVMR0, 0 /* VCPU 0 */, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
985 AssertRC(rc);
986 if (rc == VINF_SUCCESS)
987 {
988 pVM->fHWACCMEnabled = true;
989 pVM->hwaccm.s.vmx.fEnabled = true;
990 hwaccmR3DisableRawMode(pVM);
991
992 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
993#ifdef VBOX_ENABLE_64_BITS_GUESTS
994 if (pVM->hwaccm.s.fAllow64BitGuests)
995 {
996 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
997 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
998 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
999 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1000 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1001 }
1002 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1003 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1004 : "HWACCM: 32-bit guests supported.\n"));
1005#else
1006 LogRel(("HWACCM: 32-bit guests supported.\n"));
1007#endif
1008 LogRel(("HWACCM: VMX enabled!\n"));
1009 if (pVM->hwaccm.s.fNestedPaging)
1010 {
1011 LogRel(("HWACCM: Enabled nested paging\n"));
1012 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1013 }
1014 if (pVM->hwaccm.s.vmx.fVPID)
1015 LogRel(("HWACCM: Enabled VPID\n"));
1016
1017 if ( pVM->hwaccm.s.fNestedPaging
1018 || pVM->hwaccm.s.vmx.fVPID)
1019 {
1020 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1021 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1022 }
1023 }
1024 else
1025 {
1026 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1027 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1028 pVM->fHWACCMEnabled = false;
1029 }
1030 }
1031 }
1032 else
1033 if (pVM->hwaccm.s.svm.fSupported)
1034 {
1035 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1036
1037 if (pVM->hwaccm.s.fInitialized == false)
1038 {
1039 /* Erratum 170 which requires a forced TLB flush for each world switch:
1040 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1041 *
1042 * All BH-G1/2 and DH-G1/2 models include a fix:
1043 * Athlon X2: 0x6b 1/2
1044 * 0x68 1/2
1045 * Athlon 64: 0x7f 1
1046 * 0x6f 2
1047 * Sempron: 0x7f 1/2
1048 * 0x6f 2
1049 * 0x6c 2
1050 * 0x7c 2
1051 * Turion 64: 0x68 2
1052 *
1053 */
1054 uint32_t u32Dummy;
1055 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1056 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1057 u32BaseFamily= (u32Version >> 8) & 0xf;
1058 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1059 u32Model = ((u32Version >> 4) & 0xf);
1060 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1061 u32Stepping = u32Version & 0xf;
1062 if ( u32Family == 0xf
1063 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1064 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1065 {
1066 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1067 }
1068
1069 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1070 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1071 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1072 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1073 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1074
1075 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1076 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
1077 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
1078 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
1079 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
1080 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
1081 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
1082 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
1083 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
1084 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
1085
1086 /* Only try once. */
1087 pVM->hwaccm.s.fInitialized = true;
1088
1089 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1090 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1091
1092 rc = SUPCallVMMR0Ex(pVM->pVMR0, 0 /* VCPU 0 */, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1093 AssertRC(rc);
1094 if (rc == VINF_SUCCESS)
1095 {
1096 pVM->fHWACCMEnabled = true;
1097 pVM->hwaccm.s.svm.fEnabled = true;
1098
1099 if (pVM->hwaccm.s.fNestedPaging)
1100 LogRel(("HWACCM: Enabled nested paging\n"));
1101
1102 hwaccmR3DisableRawMode(pVM);
1103 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1104 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1105 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1106#ifdef VBOX_ENABLE_64_BITS_GUESTS
1107 if (pVM->hwaccm.s.fAllow64BitGuests)
1108 {
1109 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1110 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1111 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1112 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1113 }
1114#endif
1115 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1116 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1117 : "HWACCM: 32-bit guest supported.\n"));
1118 }
1119 else
1120 {
1121 pVM->fHWACCMEnabled = false;
1122 }
1123 }
1124 }
1125 return VINF_SUCCESS;
1126}
1127
1128/**
1129 * Applies relocations to data and code managed by this
1130 * component. This function will be called at init and
1131 * whenever the VMM need to relocate it self inside the GC.
1132 *
1133 * @param pVM The VM.
1134 */
1135VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1136{
1137 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1138
1139 /* Fetch the current paging mode during the relocate callback during state loading. */
1140 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1141 {
1142 for (unsigned i=0;i<pVM->cCPUs;i++)
1143 {
1144 PVMCPU pVCpu = &pVM->aCpus[i];
1145 /* @todo SMP */
1146 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1147 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMGetGuestMode(pVCpu);
1148 }
1149 }
1150#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1151 if (pVM->fHWACCMEnabled)
1152 {
1153 int rc;
1154
1155 switch(PGMGetHostMode(pVM))
1156 {
1157 case PGMMODE_32_BIT:
1158 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1159 break;
1160
1161 case PGMMODE_PAE:
1162 case PGMMODE_PAE_NX:
1163 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1164 break;
1165
1166 default:
1167 AssertFailed();
1168 break;
1169 }
1170 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1171 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1172
1173 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1174 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1175
1176 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1177 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1178
1179 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1180 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1181
1182# ifdef DEBUG
1183 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1184 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1185# endif
1186 }
1187#endif
1188 return;
1189}
1190
1191/**
1192 * Checks hardware accelerated raw mode is allowed.
1193 *
1194 * @returns boolean
1195 * @param pVM The VM to operate on.
1196 */
1197VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1198{
1199 return pVM->hwaccm.s.fAllowed;
1200}
1201
1202/**
1203 * Notification callback which is called whenever there is a chance that a CR3
1204 * value might have changed.
1205 *
1206 * This is called by PGM.
1207 *
1208 * @param pVM The VM to operate on.
1209 * @param pVCpu The VMCPU to operate on.
1210 * @param enmShadowMode New shadow paging mode.
1211 * @param enmGuestMode New guest paging mode.
1212 */
1213VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1214{
1215 /* Ignore page mode changes during state loading. */
1216 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1217 return;
1218
1219 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1220
1221 if ( pVM->hwaccm.s.vmx.fEnabled
1222 && pVM->fHWACCMEnabled)
1223 {
1224 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1225 && enmGuestMode >= PGMMODE_PROTECTED)
1226 {
1227 PCPUMCTX pCtx;
1228
1229 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1230
1231 /* After a real mode switch to protected mode we must force
1232 * CPL to 0. Our real mode emulation had to set it to 3.
1233 */
1234 pCtx->ssHid.Attr.n.u2Dpl = 0;
1235 }
1236 }
1237
1238 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1239 {
1240 /* Keep track of paging mode changes. */
1241 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1242 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1243
1244 /* Did we miss a change, because all code was executed in the recompiler? */
1245 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1246 {
1247 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1248 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1249 }
1250 }
1251
1252 /* Reset the contents of the read cache. */
1253 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1254 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1255 pCache->Read.aFieldVal[j] = 0;
1256}
1257
1258/**
1259 * Terminates the HWACCM.
1260 *
1261 * Termination means cleaning up and freeing all resources,
1262 * the VM it self is at this point powered off or suspended.
1263 *
1264 * @returns VBox status code.
1265 * @param pVM The VM to operate on.
1266 */
1267VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1268{
1269 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1270 {
1271 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1272 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1273 }
1274 HWACCMR3TermCPU(pVM);
1275 return 0;
1276}
1277
1278/**
1279 * Terminates the per-VCPU HWACCM.
1280 *
1281 * Termination means cleaning up and freeing all resources,
1282 * the VM it self is at this point powered off or suspended.
1283 *
1284 * @returns VBox status code.
1285 * @param pVM The VM to operate on.
1286 */
1287VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1288{
1289 for (unsigned i=0;i<pVM->cCPUs;i++)
1290 {
1291 PVMCPU pVCpu = &pVM->aCpus[i];
1292
1293 if (pVCpu->hwaccm.s.paStatExitReason)
1294 {
1295 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1296 pVCpu->hwaccm.s.paStatExitReason = NULL;
1297 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1298 }
1299#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1300 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1301 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1302 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1303#endif
1304 }
1305 return 0;
1306}
1307
1308/**
1309 * The VM is being reset.
1310 *
1311 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1312 * needs to be removed.
1313 *
1314 * @param pVM VM handle.
1315 */
1316VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1317{
1318 LogFlow(("HWACCMR3Reset:\n"));
1319
1320 if (pVM->fHWACCMEnabled)
1321 hwaccmR3DisableRawMode(pVM);
1322
1323 for (unsigned i=0;i<pVM->cCPUs;i++)
1324 {
1325 PVMCPU pVCpu = &pVM->aCpus[i];
1326
1327 /* On first entry we'll sync everything. */
1328 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1329
1330 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1331 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1332
1333 pVCpu->hwaccm.s.fActive = false;
1334 pVCpu->hwaccm.s.Event.fPending = false;
1335
1336 /* Reset state information for real-mode emulation in VT-x. */
1337 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1338 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1339 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1340
1341 /* Reset the contents of the read cache. */
1342 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1343 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1344 pCache->Read.aFieldVal[j] = 0;
1345
1346#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1347 /* Magic marker for searching in crash dumps. */
1348 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1349 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1350#endif
1351 }
1352}
1353
1354/**
1355 * Force execution of the current IO code in the recompiler
1356 *
1357 * @returns VBox status code.
1358 * @param pVM The VM to operate on.
1359 * @param pCtx Partial VM execution context
1360 */
1361VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
1362{
1363 PVMCPU pVCpu = VMMGetCpu(pVM);
1364
1365 Assert(pVM->fHWACCMEnabled);
1366 Log(("HWACCMR3EmulateIoBlock\n"));
1367
1368 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
1369 if (HWACCMCanEmulateIoBlockEx(pCtx))
1370 {
1371 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
1372 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
1373 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
1374 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
1375 return VINF_EM_RESCHEDULE_REM;
1376 }
1377 return VINF_SUCCESS;
1378}
1379
1380/**
1381 * Checks if we can currently use hardware accelerated raw mode.
1382 *
1383 * @returns boolean
1384 * @param pVM The VM to operate on.
1385 * @param pCtx Partial VM execution context
1386 */
1387VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
1388{
1389 PVMCPU pVCpu = VMMGetCpu(pVM);
1390
1391 Assert(pVM->fHWACCMEnabled);
1392
1393 /* If we're still executing the IO code, then return false. */
1394 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
1395 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
1396 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
1397 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
1398 return false;
1399
1400 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
1401
1402 /* AMD-V supports real & protected mode with or without paging. */
1403 if (pVM->hwaccm.s.svm.fEnabled)
1404 {
1405 pVCpu->hwaccm.s.fActive = true;
1406 return true;
1407 }
1408
1409 pVCpu->hwaccm.s.fActive = false;
1410
1411 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
1412#ifdef HWACCM_VMX_EMULATE_REALMODE
1413 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1414 {
1415 if (CPUMIsGuestInRealModeEx(pCtx))
1416 {
1417 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
1418 * The base must also be equal to (sel << 4).
1419 */
1420 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
1421 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
1422 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
1423 || pCtx->es != (pCtx->esHid.u64Base >> 4)
1424 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
1425 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
1426 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
1427 {
1428 return false;
1429 }
1430 }
1431 else
1432 {
1433 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
1434 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
1435 * from real to protected mode. (all sorts of RPL & DPL assumptions)
1436 */
1437 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1438 && enmGuestMode >= PGMMODE_PROTECTED)
1439 {
1440 if ( (pCtx->cs & X86_SEL_RPL)
1441 || (pCtx->ds & X86_SEL_RPL)
1442 || (pCtx->es & X86_SEL_RPL)
1443 || (pCtx->fs & X86_SEL_RPL)
1444 || (pCtx->gs & X86_SEL_RPL)
1445 || (pCtx->ss & X86_SEL_RPL))
1446 {
1447 return false;
1448 }
1449 }
1450 }
1451 }
1452 else
1453#endif /* HWACCM_VMX_EMULATE_REALMODE */
1454 {
1455 if (!CPUMIsGuestInLongModeEx(pCtx))
1456 {
1457 /** @todo This should (probably) be set on every excursion to the REM,
1458 * however it's too risky right now. So, only apply it when we go
1459 * back to REM for real mode execution. (The XP hack below doesn't
1460 * work reliably without this.)
1461 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
1462 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
1463
1464 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
1465 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
1466 return false;
1467
1468 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
1469 /* Windows XP; switch to protected mode; all selectors are marked not present in the
1470 * hidden registers (possible recompiler bug; see load_seg_vm) */
1471 if (pCtx->csHid.Attr.n.u1Present == 0)
1472 return false;
1473 if (pCtx->ssHid.Attr.n.u1Present == 0)
1474 return false;
1475
1476 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
1477 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
1478 /** @todo This check is actually wrong, it doesn't take the direction of the
1479 * stack segment into account. But, it does the job for now. */
1480 if (pCtx->rsp >= pCtx->ssHid.u32Limit)
1481 return false;
1482#if 0
1483 if ( pCtx->cs >= pCtx->gdtr.cbGdt
1484 || pCtx->ss >= pCtx->gdtr.cbGdt
1485 || pCtx->ds >= pCtx->gdtr.cbGdt
1486 || pCtx->es >= pCtx->gdtr.cbGdt
1487 || pCtx->fs >= pCtx->gdtr.cbGdt
1488 || pCtx->gs >= pCtx->gdtr.cbGdt)
1489 return false;
1490#endif
1491 }
1492 }
1493
1494 if (pVM->hwaccm.s.vmx.fEnabled)
1495 {
1496 uint32_t mask;
1497
1498 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
1499 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
1500 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
1501 mask &= ~X86_CR0_NE;
1502
1503#ifdef HWACCM_VMX_EMULATE_REALMODE
1504 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1505 {
1506 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
1507 mask &= ~(X86_CR0_PG|X86_CR0_PE);
1508 }
1509 else
1510#endif
1511 {
1512 /* We support protected mode without paging using identity mapping. */
1513 mask &= ~X86_CR0_PG;
1514 }
1515 if ((pCtx->cr0 & mask) != mask)
1516 return false;
1517
1518 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
1519 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
1520 if ((pCtx->cr0 & mask) != 0)
1521 return false;
1522
1523 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
1524 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1525 mask &= ~X86_CR4_VMXE;
1526 if ((pCtx->cr4 & mask) != mask)
1527 return false;
1528
1529 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
1530 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
1531 if ((pCtx->cr4 & mask) != 0)
1532 return false;
1533
1534 pVCpu->hwaccm.s.fActive = true;
1535 return true;
1536 }
1537
1538 return false;
1539}
1540
1541/**
1542 * Notifcation from EM about a rescheduling into hardware assisted execution
1543 * mode.
1544 *
1545 * @param pVCpu Pointer to the current virtual cpu structure.
1546 */
1547VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
1548{
1549 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
1550}
1551
1552/**
1553 * Notifcation from EM about returning from instruction emulation (REM / EM).
1554 *
1555 * @param pVCpu Pointer to the current virtual cpu structure.
1556 */
1557VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
1558{
1559 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
1560}
1561
1562/**
1563 * Checks if we are currently using hardware accelerated raw mode.
1564 *
1565 * @returns boolean
1566 * @param pVCpu The VMCPU to operate on.
1567 */
1568VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
1569{
1570 return pVCpu->hwaccm.s.fActive;
1571}
1572
1573/**
1574 * Checks if we are currently using nested paging.
1575 *
1576 * @returns boolean
1577 * @param pVM The VM to operate on.
1578 */
1579VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
1580{
1581 return pVM->hwaccm.s.fNestedPaging;
1582}
1583
1584/**
1585 * Checks if we are currently using VPID in VT-x mode.
1586 *
1587 * @returns boolean
1588 * @param pVM The VM to operate on.
1589 */
1590VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
1591{
1592 return pVM->hwaccm.s.vmx.fVPID;
1593}
1594
1595
1596/**
1597 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
1598 *
1599 * @returns boolean
1600 * @param pVM The VM to operate on.
1601 */
1602VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
1603{
1604 /* @todo SMP */
1605 return HWACCMIsEnabled(pVM) && pVM->aCpus[0].hwaccm.s.Event.fPending;
1606}
1607
1608
1609/**
1610 * Inject an NMI into a running VM
1611 *
1612 * @returns boolean
1613 * @param pVM The VM to operate on.
1614 */
1615VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
1616{
1617 pVM->hwaccm.s.fInjectNMI = true;
1618 return VINF_SUCCESS;
1619}
1620
1621/**
1622 * Check fatal VT-x/AMD-V error and produce some meaningful
1623 * log release message.
1624 *
1625 * @param pVM The VM to operate on.
1626 * @param iStatusCode VBox status code
1627 */
1628VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
1629{
1630 for (unsigned i=0;i<pVM->cCPUs;i++)
1631 {
1632 switch(iStatusCode)
1633 {
1634 case VERR_VMX_INVALID_VMCS_FIELD:
1635 break;
1636
1637 case VERR_VMX_INVALID_VMCS_PTR:
1638 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1639 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
1640 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
1641 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
1642 break;
1643
1644 case VERR_VMX_UNABLE_TO_START_VM:
1645 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1646 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1647#if 0 /* @todo dump the current control fields to the release log */
1648 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
1649 {
1650
1651 }
1652#endif
1653 break;
1654
1655 case VERR_VMX_UNABLE_TO_RESUME_VM:
1656 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1657 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1658 break;
1659
1660 case VERR_VMX_INVALID_VMXON_PTR:
1661 break;
1662 }
1663 }
1664}
1665
1666/**
1667 * Execute state save operation.
1668 *
1669 * @returns VBox status code.
1670 * @param pVM VM Handle.
1671 * @param pSSM SSM operation handle.
1672 */
1673static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
1674{
1675 int rc;
1676
1677 Log(("hwaccmR3Save:\n"));
1678
1679 for (unsigned i=0;i<pVM->cCPUs;i++)
1680 {
1681 /*
1682 * Save the basic bits - fortunately all the other things can be resynced on load.
1683 */
1684 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
1685 AssertRCReturn(rc, rc);
1686 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
1687 AssertRCReturn(rc, rc);
1688 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
1689 AssertRCReturn(rc, rc);
1690
1691 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
1692 AssertRCReturn(rc, rc);
1693 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
1694 AssertRCReturn(rc, rc);
1695 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
1696 AssertRCReturn(rc, rc);
1697 }
1698
1699 return VINF_SUCCESS;
1700}
1701
1702/**
1703 * Execute state load operation.
1704 *
1705 * @returns VBox status code.
1706 * @param pVM VM Handle.
1707 * @param pSSM SSM operation handle.
1708 * @param u32Version Data layout version.
1709 */
1710static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1711{
1712 int rc;
1713
1714 Log(("hwaccmR3Load:\n"));
1715
1716 /*
1717 * Validate version.
1718 */
1719 if ( u32Version != HWACCM_SSM_VERSION
1720 && u32Version != HWACCM_SSM_VERSION_2_0_X)
1721 {
1722 AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
1723 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1724 }
1725 for (unsigned i=0;i<pVM->cCPUs;i++)
1726 {
1727 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
1728 AssertRCReturn(rc, rc);
1729 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
1730 AssertRCReturn(rc, rc);
1731 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
1732 AssertRCReturn(rc, rc);
1733
1734 if (u32Version >= HWACCM_SSM_VERSION)
1735 {
1736 uint32_t val;
1737
1738 rc = SSMR3GetU32(pSSM, &val);
1739 AssertRCReturn(rc, rc);
1740 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
1741
1742 rc = SSMR3GetU32(pSSM, &val);
1743 AssertRCReturn(rc, rc);
1744 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
1745
1746 rc = SSMR3GetU32(pSSM, &val);
1747 AssertRCReturn(rc, rc);
1748 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
1749 }
1750 }
1751 return VINF_SUCCESS;
1752}
1753
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