VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 21987

Last change on this file since 21987 was 21987, checked in by vboxsync, 15 years ago

TPR patching updates
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File size: 116.0 KB
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1/* $Id: HWACCM.cpp 21987 2009-08-05 12:14:31Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/csam.h>
35#include <VBox/selm.h>
36#include <VBox/rem.h>
37#include <VBox/hwacc_vmx.h>
38#include <VBox/hwacc_svm.h>
39#include "HWACCMInternal.h"
40#include <VBox/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/string.h>
48#include <iprt/thread.h>
49
50/*******************************************************************************
51* Global Variables *
52*******************************************************************************/
53#ifdef VBOX_WITH_STATISTICS
54# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55# define EXIT_REASON_NIL() NULL
56/** Exit reason descriptions for VT-x, used to describe statistics. */
57static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58{
59 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67 EXIT_REASON_NIL(),
68 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94 EXIT_REASON_NIL(),
95 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96 EXIT_REASON_NIL(),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101 EXIT_REASON_NIL(),
102 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110 EXIT_REASON_NIL(),
111 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115 EXIT_REASON_NIL()
116};
117/** Exit reason descriptions for AMD-V, used to describe statistics. */
118static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119{
120 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
121 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
122 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
123 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
124 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
125 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
126 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
127 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
128 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
129 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
130 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
131 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
132 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
133 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
134 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
135 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
136 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
137 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
152 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
153 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
154 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
155 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
156 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
157 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
158 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
159 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
160 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
161 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
162 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
163 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
164 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
165 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
166 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
167 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
168 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
169 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
184 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
185 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_INTR , 96, "Physical maskable interrupt."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_NMI , 97, "Physical non-maskable interrupt."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_SMI , 98, "System management interrupt."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_INIT , 99, "Physical INIT signal."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_VINTR ,100, "Visual interrupt."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_IDTR_READ ,102, "Read IDTR"),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_GDTR_READ ,103, "Read GDTR"),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_LDTR_READ ,104, "Read LDTR."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,105, "Read TR."),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,106, "Write IDTR."),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,107, "Write GDTR."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,108, "Write LDTR."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,109, "Write TR."),
230 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
231 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
232 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
233 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
234 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
235 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
236 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
237 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
238 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
239 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
240 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
241 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
242 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
243 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
244 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
245 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
246 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
247 EXIT_REASON(SVM_EXIT_TASK_SHUTDOWN ,127, "Shutdown."),
248 EXIT_REASON(SVM_EXIT_TASK_VMRUN ,128, "VMRUN instruction."),
249 EXIT_REASON(SVM_EXIT_TASK_VMCALL ,129, "VMCALL instruction."),
250 EXIT_REASON(SVM_EXIT_TASK_VMLOAD ,130, "VMLOAD instruction."),
251 EXIT_REASON(SVM_EXIT_TASK_VMSAVE ,131, "VMSAVE instruction."),
252 EXIT_REASON(SVM_EXIT_TASK_STGI ,132, "STGI instruction."),
253 EXIT_REASON(SVM_EXIT_TASK_CLGI ,133, "CLGI instruction."),
254 EXIT_REASON(SVM_EXIT_TASK_SKINIT ,134, "SKINIT instruction."),
255 EXIT_REASON(SVM_EXIT_TASK_RDTSCP ,135, "RDTSCP instruction."),
256 EXIT_REASON(SVM_EXIT_TASK_ICEBP ,136, "ICEBP instruction."),
257 EXIT_REASON(SVM_EXIT_TASK_WBINVD ,137, "WBINVD instruction."),
258 EXIT_REASON(SVM_EXIT_TASK_MONITOR ,138, "MONITOR instruction."),
259 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
260 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
261 EXIT_REASON(SVM_EXIT_MWAIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
262 EXIT_REASON_NIL()
263};
264# undef EXIT_REASON
265# undef EXIT_REASON_NIL
266#endif /* VBOX_WITH_STATISTICS */
267
268/*******************************************************************************
269* Internal Functions *
270*******************************************************************************/
271static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
272static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
273
274
275/**
276 * Initializes the HWACCM.
277 *
278 * @returns VBox status code.
279 * @param pVM The VM to operate on.
280 */
281VMMR3DECL(int) HWACCMR3Init(PVM pVM)
282{
283 LogFlow(("HWACCMR3Init\n"));
284
285 /*
286 * Assert alignment and sizes.
287 */
288 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
289 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
290
291 /* Some structure checks. */
292 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
293 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
294 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
295 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
296
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
300 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
303 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
304
305
306 /*
307 * Register the saved state data unit.
308 */
309 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
310 NULL, hwaccmR3Save, NULL,
311 NULL, hwaccmR3Load, NULL);
312 if (RT_FAILURE(rc))
313 return rc;
314
315 /* Misc initialisation. */
316 pVM->hwaccm.s.vmx.fSupported = false;
317 pVM->hwaccm.s.svm.fSupported = false;
318 pVM->hwaccm.s.vmx.fEnabled = false;
319 pVM->hwaccm.s.svm.fEnabled = false;
320
321 pVM->hwaccm.s.fNestedPaging = false;
322
323 /* Disabled by default. */
324 pVM->fHWACCMEnabled = false;
325
326 /*
327 * Check CFGM options.
328 */
329 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
330 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
331 /* Nested paging: disabled by default. */
332 rc = CFGMR3QueryBoolDef(pRoot, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
333 AssertRC(rc);
334
335 /* VT-x VPID: disabled by default. */
336 rc = CFGMR3QueryBoolDef(pRoot, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
337 AssertRC(rc);
338
339 /* HWACCM support must be explicitely enabled in the configuration file. */
340 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
341 AssertRC(rc);
342
343#ifdef RT_OS_DARWIN
344 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
345#else
346 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
347#endif
348 {
349 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
350 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
351 return VERR_HWACCM_CONFIG_MISMATCH;
352 }
353
354 if (VMMIsHwVirtExtForced(pVM))
355 pVM->fHWACCMEnabled = true;
356
357#if HC_ARCH_BITS == 32
358 /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
359 * (To use the default, don't set 64bitEnabled in CFGM.) */
360 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
361 AssertLogRelRCReturn(rc, rc);
362 if (pVM->hwaccm.s.fAllow64BitGuests)
363 {
364# ifdef RT_OS_DARWIN
365 if (!VMMIsHwVirtExtForced(pVM))
366# else
367 if (!pVM->hwaccm.s.fAllowed)
368# endif
369 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
370 }
371#else
372 /* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
373 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
374 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
375 AssertLogRelRCReturn(rc, rc);
376#endif
377
378 /* Max number of resume loops. */
379 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
380 AssertRC(rc);
381
382 return VINF_SUCCESS;
383}
384
385/**
386 * Initializes the per-VCPU HWACCM.
387 *
388 * @returns VBox status code.
389 * @param pVM The VM to operate on.
390 */
391VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
392{
393 LogFlow(("HWACCMR3InitCPU\n"));
394
395 for (unsigned i=0;i<pVM->cCPUs;i++)
396 {
397 PVMCPU pVCpu = &pVM->aCpus[i];
398
399 pVCpu->hwaccm.s.fActive = false;
400 }
401
402#ifdef VBOX_WITH_STATISTICS
403 STAM_REG(pVM, &pVM->hwaccm.s.StatPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
404 STAM_REG(pVM, &pVM->hwaccm.s.StatPatchFailure, STAMTYPE_COUNTER, "/HWACCM/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
405
406 /*
407 * Statistics.
408 */
409 for (unsigned i=0;i<pVM->cCPUs;i++)
410 {
411 PVMCPU pVCpu = &pVM->aCpus[i];
412 int rc;
413
414 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
415 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
416 AssertRC(rc);
417 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
418 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
419 AssertRC(rc);
420 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
421 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
422 AssertRC(rc);
423# if 1 /* temporary for tracking down darwin holdup. */
424 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
425 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
426 AssertRC(rc);
427 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
428 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
429 AssertRC(rc);
430 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
431 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
432 AssertRC(rc);
433# endif
434 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
435 "/PROF/HWACCM/CPU%d/InGC", i);
436 AssertRC(rc);
437
438# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
439 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
440 "/PROF/HWACCM/CPU%d/Switcher3264", i);
441 AssertRC(rc);
442# endif
443
444# define HWACCM_REG_COUNTER(a, b) \
445 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
446 AssertRC(rc);
447
448 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
449 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
450 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
451 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
452 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
453 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
454 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
455 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
456 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
457 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
458 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
459 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
460 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
461 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
462 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
463 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
464 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
465 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
466 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
467 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
468 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
469 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
470 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
471 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
472 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
473 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
474 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
475 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
476 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
477 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
478 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
479 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
480 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
481 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
482 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
483 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
484 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
485
486 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
487 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
488
489 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
490 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
491 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
492
493 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
494 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
495 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
496 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
498 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
499 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
503 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
504
505 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
506 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
507
508 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
509 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
510 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
511
512 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
513 {
514 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
515 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
516 AssertRC(rc);
517 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
518 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
519 AssertRC(rc);
520 }
521
522#undef HWACCM_REG_COUNTER
523
524 pVCpu->hwaccm.s.paStatExitReason = NULL;
525
526 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
527 AssertRC(rc);
528 if (RT_SUCCESS(rc))
529 {
530 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
531 for (int j=0;j<MAX_EXITREASON_STAT;j++)
532 {
533 if (papszDesc[j])
534 {
535 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
536 papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
537 AssertRC(rc);
538 }
539 }
540 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
541 AssertRC(rc);
542 }
543 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
544# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
545 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
546# else
547 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
548# endif
549
550 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
551 AssertRCReturn(rc, rc);
552 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
553# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
554 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
555# else
556 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
557# endif
558 for (unsigned j = 0; j < 255; j++)
559 STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
560 (j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
561
562 }
563#endif /* VBOX_WITH_STATISTICS */
564
565#ifdef VBOX_WITH_CRASHDUMP_MAGIC
566 /* Magic marker for searching in crash dumps. */
567 for (unsigned i=0;i<pVM->cCPUs;i++)
568 {
569 PVMCPU pVCpu = &pVM->aCpus[i];
570
571 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
572 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
573 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
574 }
575#endif
576 return VINF_SUCCESS;
577}
578
579/**
580 * Turns off normal raw mode features
581 *
582 * @param pVM The VM to operate on.
583 */
584static void hwaccmR3DisableRawMode(PVM pVM)
585{
586 /* Disable PATM & CSAM. */
587 PATMR3AllowPatching(pVM, false);
588 CSAMDisableScanning(pVM);
589
590 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
591 SELMR3DisableMonitoring(pVM);
592 TRPMR3DisableMonitoring(pVM);
593
594 /* Disable the switcher code (safety precaution). */
595 VMMR3DisableSwitcher(pVM);
596
597 /* Disable mapping of the hypervisor into the shadow page table. */
598 PGMR3MappingsDisable(pVM);
599
600 /* Disable the switcher */
601 VMMR3DisableSwitcher(pVM);
602
603 /* Reinit the paging mode to force the new shadow mode. */
604 for (unsigned i=0;i<pVM->cCPUs;i++)
605 {
606 PVMCPU pVCpu = &pVM->aCpus[i];
607
608 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
609 }
610}
611
612/**
613 * Initialize VT-x or AMD-V.
614 *
615 * @returns VBox status code.
616 * @param pVM The VM handle.
617 */
618VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
619{
620 int rc;
621
622 if ( !pVM->hwaccm.s.vmx.fSupported
623 && !pVM->hwaccm.s.svm.fSupported)
624 {
625 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
626 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
627 if (VMMIsHwVirtExtForced(pVM))
628 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
629 return VINF_SUCCESS;
630 }
631
632 if (!pVM->hwaccm.s.fAllowed)
633 return VINF_SUCCESS; /* nothing to do */
634
635 /* Enable VT-x or AMD-V on all host CPUs. */
636 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
637 if (RT_FAILURE(rc))
638 {
639 LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
640 return rc;
641 }
642 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
643
644 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
645
646 if (pVM->hwaccm.s.vmx.fSupported)
647 {
648 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
649
650 if ( pVM->hwaccm.s.fInitialized == false
651 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
652 {
653 uint64_t val;
654 RTGCPHYS GCPhys = 0;
655
656 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
657 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
658 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
659 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
660 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
661 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
662 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
663 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
664
665 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
666 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
667 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
668 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
669 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
670 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
671 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
672 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
673 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
674 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
675 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
676 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
677 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
678 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
679 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
680 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
681 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
682 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
683 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
684
685 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
686 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
687 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
688 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
689 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
690 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
691 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
692 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
693 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
694 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
695 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
696 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
697 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
698 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
699 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
700 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
701 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
702 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
703 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
704 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
705 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
706 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
707 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
708 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
709 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
710 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
711 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
712 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
713 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
714 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
715 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
716 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
717 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
718 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
719 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
720 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
721 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
722 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
723 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
724 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
725 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
726 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
727 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
728 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
729
730 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
731 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
732 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
733 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
734 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
735 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
736 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
737 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
738 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
739 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
740 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
741 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
742 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
743 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
744 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
745 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
746 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
747 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
748 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
749 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
750 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
751 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
752 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
753 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
754 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
755 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
756 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
757 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
758 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
759 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
760 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
761 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
762 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
763 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
764 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
765 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
766 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
767 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
768 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
769 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
770 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
771 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
772 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
773
774 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
775 {
776 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
777 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
778 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
779 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
780 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
781 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
782 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
783 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
784 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
785 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
786 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
787 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
788 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
789 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
790
791 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
792 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
793 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
794 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
795 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
796 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
797 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
798 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
799 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
800 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
801 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
802 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
803 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
804 }
805
806 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
807 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
808 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
809 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
810 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
811 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
812 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
813 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
814 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
815 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
816 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
817 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
818 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
819 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
820 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
821 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
822 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
823 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
824 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
825 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
826 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
827 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
828 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
829 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
830 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
831 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
832 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
833 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
834 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
835 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
836 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
837
838 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
839 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
840 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
841 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
842 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
843 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
844 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
845 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
846 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
847 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
848 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
849 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
850 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
851 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
852 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
853 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
854 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
855 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
856 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
857 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
858 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
859 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
860 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
861 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
862 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
863 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
864 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
865 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
866 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
867 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
868 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
869 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
870 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
871 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
872 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
873
874 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
875 {
876 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
877
878 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
879 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
880 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
881 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
882 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
883 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
884 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
885 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
886 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
887 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
888 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
889 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
890 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
891 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
892 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
893 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
894 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
895 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
896 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
897 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
898 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
899 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
900 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
901 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
902 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
903 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
904 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
905 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
906 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
907 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
908 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
909 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
910 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
911 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
912 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
913 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
914 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
915 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
916 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
917 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
918 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
919 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
920 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
921 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
922 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
923 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
924 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
925 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
926 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
927 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
928 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
929 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
930 }
931
932 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
933 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
934 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
935 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
936 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
937 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
938
939 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
940 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
941 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
942 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
943 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
944
945 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
946 LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
947
948 for (unsigned i=0;i<pVM->cCPUs;i++)
949 LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
950
951#ifdef HWACCM_VTX_WITH_EPT
952 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
953 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
954#endif /* HWACCM_VTX_WITH_EPT */
955#ifdef HWACCM_VTX_WITH_VPID
956 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
957 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
958 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
959#endif /* HWACCM_VTX_WITH_VPID */
960
961 /* Only try once. */
962 pVM->hwaccm.s.fInitialized = true;
963
964 /* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
965#if 1
966 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
967#else
968 rc = VERR_NO_MEMORY; /* simulation of no VMMDev Heap. */
969#endif
970 if (RT_SUCCESS(rc))
971 {
972 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
973 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
974 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
975 /* Bit set to 0 means redirection enabled. */
976 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
977 /* Allow all port IO, so the VT-x IO intercepts do their job. */
978 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
979 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
980
981 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
982 * real and protected mode without paging with EPT.
983 */
984 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
985 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
986 {
987 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
988 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
989 }
990
991 /* We convert it here every time as pci regions could be reconfigured. */
992 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
993 AssertRC(rc);
994 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
995
996 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
997 AssertRC(rc);
998 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
999 }
1000 else
1001 {
1002 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1003 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1004 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1005 }
1006
1007 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1008 AssertRC(rc);
1009 if (rc == VINF_SUCCESS)
1010 {
1011 pVM->fHWACCMEnabled = true;
1012 pVM->hwaccm.s.vmx.fEnabled = true;
1013 hwaccmR3DisableRawMode(pVM);
1014
1015 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1016#ifdef VBOX_ENABLE_64_BITS_GUESTS
1017 if (pVM->hwaccm.s.fAllow64BitGuests)
1018 {
1019 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1020 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1021 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1022 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1023 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1024 }
1025 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1026 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1027 : "HWACCM: 32-bit guests supported.\n"));
1028#else
1029 LogRel(("HWACCM: 32-bit guests supported.\n"));
1030#endif
1031 LogRel(("HWACCM: VMX enabled!\n"));
1032 if (pVM->hwaccm.s.fNestedPaging)
1033 {
1034 LogRel(("HWACCM: Enabled nested paging\n"));
1035 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1036 }
1037 if (pVM->hwaccm.s.vmx.fVPID)
1038 LogRel(("HWACCM: Enabled VPID\n"));
1039
1040 if ( pVM->hwaccm.s.fNestedPaging
1041 || pVM->hwaccm.s.vmx.fVPID)
1042 {
1043 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1044 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1045 }
1046 }
1047 else
1048 {
1049 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1050 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1051 pVM->fHWACCMEnabled = false;
1052 }
1053 }
1054 }
1055 else
1056 if (pVM->hwaccm.s.svm.fSupported)
1057 {
1058 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1059
1060 if (pVM->hwaccm.s.fInitialized == false)
1061 {
1062 /* Erratum 170 which requires a forced TLB flush for each world switch:
1063 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1064 *
1065 * All BH-G1/2 and DH-G1/2 models include a fix:
1066 * Athlon X2: 0x6b 1/2
1067 * 0x68 1/2
1068 * Athlon 64: 0x7f 1
1069 * 0x6f 2
1070 * Sempron: 0x7f 1/2
1071 * 0x6f 2
1072 * 0x6c 2
1073 * 0x7c 2
1074 * Turion 64: 0x68 2
1075 *
1076 */
1077 uint32_t u32Dummy;
1078 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1079 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1080 u32BaseFamily= (u32Version >> 8) & 0xf;
1081 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1082 u32Model = ((u32Version >> 4) & 0xf);
1083 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1084 u32Stepping = u32Version & 0xf;
1085 if ( u32Family == 0xf
1086 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1087 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1088 {
1089 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1090 }
1091
1092 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1093 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1094 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1095 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1096 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1097
1098 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1099 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
1100 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
1101 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
1102 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
1103 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
1104 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
1105 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
1106 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
1107 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
1108
1109 /* Only try once. */
1110 pVM->hwaccm.s.fInitialized = true;
1111
1112 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1113 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1114
1115 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1116 AssertRC(rc);
1117 if (rc == VINF_SUCCESS)
1118 {
1119 pVM->fHWACCMEnabled = true;
1120 pVM->hwaccm.s.svm.fEnabled = true;
1121
1122 if (pVM->hwaccm.s.fNestedPaging)
1123 LogRel(("HWACCM: Enabled nested paging\n"));
1124
1125 hwaccmR3DisableRawMode(pVM);
1126 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1127 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1128 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1129#ifdef VBOX_ENABLE_64_BITS_GUESTS
1130 if (pVM->hwaccm.s.fAllow64BitGuests)
1131 {
1132 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1133 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1134 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1135 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1136 }
1137#endif
1138 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1139 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1140 : "HWACCM: 32-bit guest supported.\n"));
1141 }
1142 else
1143 {
1144 pVM->fHWACCMEnabled = false;
1145 }
1146 }
1147 }
1148 return VINF_SUCCESS;
1149}
1150
1151/**
1152 * Applies relocations to data and code managed by this
1153 * component. This function will be called at init and
1154 * whenever the VMM need to relocate it self inside the GC.
1155 *
1156 * @param pVM The VM.
1157 */
1158VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1159{
1160 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1161
1162 /* Fetch the current paging mode during the relocate callback during state loading. */
1163 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1164 {
1165 for (unsigned i=0;i<pVM->cCPUs;i++)
1166 {
1167 PVMCPU pVCpu = &pVM->aCpus[i];
1168
1169 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1170 Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1171 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1172 }
1173 }
1174#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1175 if (pVM->fHWACCMEnabled)
1176 {
1177 int rc;
1178
1179 switch(PGMGetHostMode(pVM))
1180 {
1181 case PGMMODE_32_BIT:
1182 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1183 break;
1184
1185 case PGMMODE_PAE:
1186 case PGMMODE_PAE_NX:
1187 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1188 break;
1189
1190 default:
1191 AssertFailed();
1192 break;
1193 }
1194 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1195 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1196
1197 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1198 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1199
1200 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1201 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1202
1203 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1204 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1205
1206# ifdef DEBUG
1207 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1208 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1209# endif
1210 }
1211#endif
1212 return;
1213}
1214
1215/**
1216 * Checks hardware accelerated raw mode is allowed.
1217 *
1218 * @returns boolean
1219 * @param pVM The VM to operate on.
1220 */
1221VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1222{
1223 return pVM->hwaccm.s.fAllowed;
1224}
1225
1226/**
1227 * Notification callback which is called whenever there is a chance that a CR3
1228 * value might have changed.
1229 *
1230 * This is called by PGM.
1231 *
1232 * @param pVM The VM to operate on.
1233 * @param pVCpu The VMCPU to operate on.
1234 * @param enmShadowMode New shadow paging mode.
1235 * @param enmGuestMode New guest paging mode.
1236 */
1237VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1238{
1239 /* Ignore page mode changes during state loading. */
1240 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1241 return;
1242
1243 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1244
1245 if ( pVM->hwaccm.s.vmx.fEnabled
1246 && pVM->fHWACCMEnabled)
1247 {
1248 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1249 && enmGuestMode >= PGMMODE_PROTECTED)
1250 {
1251 PCPUMCTX pCtx;
1252
1253 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1254
1255 /* After a real mode switch to protected mode we must force
1256 * CPL to 0. Our real mode emulation had to set it to 3.
1257 */
1258 pCtx->ssHid.Attr.n.u2Dpl = 0;
1259 }
1260 }
1261
1262 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1263 {
1264 /* Keep track of paging mode changes. */
1265 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1266 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1267
1268 /* Did we miss a change, because all code was executed in the recompiler? */
1269 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1270 {
1271 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1272 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1273 }
1274 }
1275
1276 /* Reset the contents of the read cache. */
1277 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1278 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1279 pCache->Read.aFieldVal[j] = 0;
1280}
1281
1282/**
1283 * Terminates the HWACCM.
1284 *
1285 * Termination means cleaning up and freeing all resources,
1286 * the VM it self is at this point powered off or suspended.
1287 *
1288 * @returns VBox status code.
1289 * @param pVM The VM to operate on.
1290 */
1291VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1292{
1293 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1294 {
1295 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1296 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1297 }
1298 HWACCMR3TermCPU(pVM);
1299 return 0;
1300}
1301
1302/**
1303 * Terminates the per-VCPU HWACCM.
1304 *
1305 * Termination means cleaning up and freeing all resources,
1306 * the VM it self is at this point powered off or suspended.
1307 *
1308 * @returns VBox status code.
1309 * @param pVM The VM to operate on.
1310 */
1311VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1312{
1313 for (unsigned i=0;i<pVM->cCPUs;i++)
1314 {
1315 PVMCPU pVCpu = &pVM->aCpus[i];
1316
1317#ifdef VBOX_WITH_STATISTICS
1318 if (pVCpu->hwaccm.s.paStatExitReason)
1319 {
1320 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1321 pVCpu->hwaccm.s.paStatExitReason = NULL;
1322 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1323 }
1324 if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1325 {
1326 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1327 pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1328 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1329 }
1330#endif
1331
1332#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1333 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1334 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1335 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1336#endif
1337 }
1338 return 0;
1339}
1340
1341/**
1342 * The VM is being reset.
1343 *
1344 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1345 * needs to be removed.
1346 *
1347 * @param pVM VM handle.
1348 */
1349VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1350{
1351 LogFlow(("HWACCMR3Reset:\n"));
1352
1353 if (pVM->fHWACCMEnabled)
1354 hwaccmR3DisableRawMode(pVM);
1355
1356 for (unsigned i=0;i<pVM->cCPUs;i++)
1357 {
1358 PVMCPU pVCpu = &pVM->aCpus[i];
1359
1360 /* On first entry we'll sync everything. */
1361 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1362
1363 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1364 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1365
1366 pVCpu->hwaccm.s.fActive = false;
1367 pVCpu->hwaccm.s.Event.fPending = false;
1368
1369 /* Reset state information for real-mode emulation in VT-x. */
1370 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1371 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1372 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1373
1374 /* Reset the contents of the read cache. */
1375 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1376 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1377 pCache->Read.aFieldVal[j] = 0;
1378
1379#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1380 /* Magic marker for searching in crash dumps. */
1381 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1382 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1383#endif
1384 }
1385
1386 /* Clear all patch information. */
1387 pVM->hwaccm.s.pGuestPatchMem = 0;
1388 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1389 pVM->hwaccm.s.cbGuestPatchMem = 0;
1390 pVM->hwaccm.s.svm.cPatches = 0;
1391 pVM->hwaccm.s.svm.PatchTree = 0;
1392 pVM->hwaccm.s.svm.fTPRPatchingActive = false;
1393 ASMMemZero32(pVM->hwaccm.s.svm.aPatches, sizeof(pVM->hwaccm.s.svm.aPatches));
1394}
1395
1396/**
1397 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1398 *
1399 * @returns VBox status code.
1400 * @param pVM The VM handle.
1401 * @param pVCpu The VMCPU for the EMT we're being called on.
1402 * @param pvUser Unused
1403 *
1404 */
1405DECLCALLBACK(int) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1406{
1407 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1408
1409 /* Only execute the handler on the VCPU the original patch request was issued. */
1410 if (pVCpu->idCpu != idCpu)
1411 return VINF_SUCCESS;
1412
1413 Log(("hwaccmR3RemovePatches\n"));
1414 for (unsigned i = 0; i < pVM->hwaccm.s.svm.cPatches; i++)
1415 {
1416 uint8_t szInstr[15];
1417 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[i];
1418 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1419 int rc;
1420
1421#ifdef LOG_ENABLED
1422 char szOutput[256];
1423
1424 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1425 if (VBOX_SUCCESS(rc))
1426 Log(("Patched instr: %s\n", szOutput));
1427#endif
1428
1429 /* Check if the instruction is still the same. */
1430 rc = PGMPhysSimpleReadGCPtr(pVCpu, szInstr, pInstrGC, pPatch->cbNewOp);
1431 if (rc != VINF_SUCCESS)
1432 {
1433 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1434 continue; /* swapped out or otherwise removed; skip it. */
1435 }
1436
1437 if (memcmp(szInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1438 {
1439 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1440 continue; /* skip it. */
1441 }
1442
1443 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1444 AssertRC(rc);
1445
1446#ifdef LOG_ENABLED
1447 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1448 if (VBOX_SUCCESS(rc))
1449 Log(("Original instr: %s\n", szOutput));
1450#endif
1451 }
1452 pVM->hwaccm.s.svm.cPatches = 0;
1453 pVM->hwaccm.s.svm.PatchTree = 0;
1454 pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1455 pVM->hwaccm.s.svm.fTPRPatchingActive = false;
1456 return VINF_SUCCESS;
1457}
1458
1459/**
1460 * Enable patching in a VT-x/AMD-V guest
1461 *
1462 * @returns VBox status code.
1463 * @param pVM The VM to operate on.
1464 * @param pPatchMem Patch memory range
1465 * @param cbPatchMem Size of the memory range
1466 */
1467VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1468{
1469 Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1470
1471 /* Current TPR patching only applies to AMD cpus.
1472 * May need to be extended to Intel CPUs without the APIC TPR hardware optimization.
1473 */
1474 if (CPUMGetCPUVendor(pVM) != CPUMCPUVENDOR_AMD)
1475 return VERR_NOT_SUPPORTED;
1476
1477 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)VMMGetCpuId(pVM));
1478 AssertRC(rc);
1479
1480 pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1481 pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1482 pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1483 return VINF_SUCCESS;
1484}
1485
1486/**
1487 * Disable patching in a VT-x/AMD-V guest
1488 *
1489 * @returns VBox status code.
1490 * @param pVM The VM to operate on.
1491 * @param pPatchMem Patch memory range
1492 * @param cbPatchMem Size of the memory range
1493 */
1494VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1495{
1496 Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1497
1498 Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1499 Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1500
1501 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)VMMGetCpuId(pVM));
1502 AssertRC(rc);
1503
1504 pVM->hwaccm.s.pGuestPatchMem = 0;
1505 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1506 pVM->hwaccm.s.cbGuestPatchMem = 0;
1507 pVM->hwaccm.s.svm.fTPRPatchingActive = false;
1508 return VINF_SUCCESS;
1509}
1510
1511
1512/**
1513 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1514 *
1515 * @returns VBox status code.
1516 * @param pVM The VM handle.
1517 * @param pVCpu The VMCPU for the EMT we're being called on.
1518 * @param pvUser User specified CPU context
1519 *
1520 */
1521DECLCALLBACK(int) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1522{
1523 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1524 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1525 RTGCPTR oldrip = pCtx->rip;
1526 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1527 unsigned cbOp;
1528
1529 /* Only execute the handler on the VCPU the original patch request was issued. */
1530 if (pVCpu->idCpu != idCpu)
1531 return VINF_SUCCESS;
1532
1533 Log(("hwaccmR3ReplaceTprInstr: %RGv\n", pCtx->rip));
1534
1535 /* Two or more VCPUs were racing to patch this instruction. */
1536 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.svm.PatchTree, (AVLOU32KEY)pCtx->eip);
1537 if (pPatch)
1538 return VINF_SUCCESS;
1539
1540 Assert(pVM->hwaccm.s.svm.cPatches < RT_ELEMENTS(pVM->hwaccm.s.svm.aPatches));
1541
1542 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1543 AssertRC(rc);
1544 if ( rc == VINF_SUCCESS
1545 && pDis->pCurInstr->opcode == OP_MOV
1546 && cbOp >= 3)
1547 {
1548 uint8_t aVMMCall[3] = { 0xf, 0x1, 0xd9};
1549 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1550 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1551
1552 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1553 AssertRC(rc);
1554
1555 pPatch->cbOp = cbOp;
1556
1557 if (pDis->param1.flags == USE_DISPLACEMENT32)
1558 {
1559 /* write. */
1560 if (pDis->param2.flags == USE_REG_GEN32)
1561 {
1562 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1563 pPatch->uSrcOperand = pDis->param2.base.reg_gen;
1564 }
1565 else
1566 {
1567 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1568 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1569 pPatch->uSrcOperand = pDis->param2.parval;
1570 }
1571 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1572 AssertRC(rc);
1573
1574 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1575 pPatch->cbNewOp = sizeof(aVMMCall);
1576 }
1577 else
1578 {
1579 RTGCPTR oldrip = pCtx->rip;
1580 uint32_t oldcbOp = cbOp;
1581 uint32_t uMmioReg = pDis->param1.base.reg_gen;
1582
1583 /* read */
1584 Assert(pDis->param1.flags == USE_REG_GEN32);
1585
1586 /* Found:
1587 * mov eax, dword [fffe0080] (5 bytes)
1588 * Check if next instruction is:
1589 * shr eax, 4
1590 */
1591 pCtx->rip += cbOp;
1592 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1593 pCtx->rip = oldrip;
1594 if ( rc == VINF_SUCCESS
1595 && pDis->pCurInstr->opcode == OP_SHR
1596 && pDis->param1.flags == USE_REG_GEN32
1597 && pDis->param1.base.reg_gen == uMmioReg
1598 && pDis->param2.flags == USE_IMMEDIATE8
1599 && pDis->param2.parval == 4
1600 && oldcbOp + cbOp < sizeof(pVM->hwaccm.s.svm.aPatches[idx].aOpcode))
1601 {
1602 uint8_t szInstr[15];
1603
1604 /* Replacing two instructions now. */
1605 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, oldcbOp + cbOp);
1606 AssertRC(rc);
1607
1608 pPatch->cbOp = oldcbOp + cbOp;
1609
1610 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1611 szInstr[0] = 0xF0;
1612 szInstr[1] = 0x0F;
1613 szInstr[2] = 0x20;
1614 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
1615 for (unsigned i = 4; i < pPatch->cbOp; i++)
1616 szInstr[i] = 0x90; /* nop */
1617
1618 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, pPatch->cbOp);
1619 AssertRC(rc);
1620
1621 memcpy(pPatch->aNewOpcode, szInstr, pPatch->cbOp);
1622 pPatch->cbNewOp = pPatch->cbOp;
1623
1624 Log(("Acceptable read/shr candidate!\n"));
1625 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1626 }
1627 else
1628 {
1629 pPatch->enmType = HWACCMTPRINSTR_READ;
1630 pPatch->uDstOperand = pDis->param1.base.reg_gen;
1631
1632 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1633 AssertRC(rc);
1634
1635 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1636 pPatch->cbNewOp = sizeof(aVMMCall);
1637 }
1638 }
1639
1640 pPatch->Core.Key = pCtx->eip;
1641 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1642 AssertRC(rc);
1643
1644 pVM->hwaccm.s.svm.cPatches++;
1645 return VINF_SUCCESS;
1646 }
1647
1648 /* Save invalid patch, so we will not try again. */
1649 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1650
1651#ifdef LOG_ENABLED
1652 char szOutput[256];
1653 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1654 if (VBOX_SUCCESS(rc))
1655 Log(("Failed to patch instr: %s\n", szOutput));
1656#endif
1657
1658 pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1659 pPatch->Core.Key = pCtx->eip;
1660 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1661 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1662 AssertRC(rc);
1663 pVM->hwaccm.s.svm.cPatches++;
1664 return VINF_SUCCESS;
1665}
1666
1667/**
1668 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1669 *
1670 * @returns VBox status code.
1671 * @param pVM The VM handle.
1672 * @param pVCpu The VMCPU for the EMT we're being called on.
1673 * @param pvUser User specified CPU context
1674 *
1675 */
1676DECLCALLBACK(int) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1677{
1678 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1679 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1680 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1681 unsigned cbOp;
1682 int rc;
1683#ifdef LOG_ENABLED
1684 RTGCPTR pInstr;
1685 char szOutput[256];
1686#endif
1687
1688 /* Only execute the handler on the VCPU the original patch request was issued. */
1689 if (pVCpu->idCpu != idCpu)
1690 return VINF_SUCCESS;
1691
1692 Log(("hwaccmR3PatchTprInstr %RGv\n", pCtx->rip));
1693
1694 Assert(pVM->hwaccm.s.svm.cPatches < RT_ELEMENTS(pVM->hwaccm.s.svm.aPatches));
1695
1696 /* Two or more VCPUs were racing to patch this instruction. */
1697 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.svm.PatchTree, (AVLOU32KEY)pCtx->eip);
1698 if (pPatch)
1699 return VINF_SUCCESS;
1700
1701 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1702 AssertRC(rc);
1703 if ( rc == VINF_SUCCESS
1704 && pDis->pCurInstr->opcode == OP_MOV
1705 && cbOp >= 5)
1706 {
1707 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1708 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1709 uint8_t aPatch[64];
1710 uint32_t off = 0;
1711
1712#ifdef LOG_ENABLED
1713 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1714 if (VBOX_SUCCESS(rc))
1715 Log(("Original instr: %s\n", szOutput));
1716#endif
1717
1718 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1719 AssertRC(rc);
1720
1721 pPatch->cbOp = cbOp;
1722 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
1723
1724 if (pDis->param1.flags == USE_DISPLACEMENT32)
1725 {
1726 /*
1727 * TPR write:
1728 *
1729 * push ECX [51]
1730 * push EDX [52]
1731 * push EAX [50]
1732 * xor EDX,EDX [31 D2]
1733 * mov EAX,EAX [89 C0]
1734 * or
1735 * mov EAX,0000000CCh [B8 CC 00 00 00]
1736 * mov ECX,0C0000082h [B9 82 00 00 C0]
1737 * wrmsr [0F 30]
1738 * pop EAX [58]
1739 * pop EDX [5A]
1740 * pop ECX [59]
1741 * jmp return_address [E9 return_address]
1742 *
1743 */
1744 aPatch[off++] = 0x51; /* push ecx */
1745 aPatch[off++] = 0x52; /* push edx */
1746 aPatch[off++] = 0x50; /* push eax */
1747 aPatch[off++] = 0x31; /* xor edx, edx */
1748 aPatch[off++] = 0xD2;
1749 if (pDis->param2.flags == USE_REG_GEN32)
1750 {
1751 if (pDis->param2.base.reg_gen != USE_REG_EAX)
1752 {
1753 aPatch[off++] = 0x89; /* mov eax, src_reg */
1754 aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, USE_REG_EAX);
1755 }
1756 }
1757 else
1758 {
1759 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1760 aPatch[off++] = 0xB8; /* mov eax, immediate */
1761 *(uint32_t *)&aPatch[off] = pDis->param2.parval;
1762 off += sizeof(uint32_t);
1763 }
1764 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1765 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1766 off += sizeof(uint32_t);
1767
1768 aPatch[off++] = 0x0F; /* wrmsr */
1769 aPatch[off++] = 0x30;
1770 aPatch[off++] = 0x58; /* pop eax */
1771 aPatch[off++] = 0x5A; /* pop edx */
1772 aPatch[off++] = 0x59; /* pop ecx */
1773 }
1774 else
1775 {
1776 /*
1777 * TPR read:
1778 *
1779 * push ECX [51]
1780 * push EDX [52]
1781 * push EAX [50]
1782 * mov ECX,0C0000082h [B9 82 00 00 C0]
1783 * rdmsr [0F 32]
1784 * mov EAX,EAX [89 C0]
1785 * pop EAX [58]
1786 * pop EDX [5A]
1787 * pop ECX [59]
1788 * jmp return_address [E9 return_address]
1789 *
1790 */
1791 Assert(pDis->param1.flags == USE_REG_GEN32);
1792
1793 if (pDis->param1.base.reg_gen != USE_REG_ECX)
1794 aPatch[off++] = 0x51; /* push ecx */
1795 if (pDis->param1.base.reg_gen != USE_REG_EDX)
1796 aPatch[off++] = 0x52; /* push edx */
1797 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1798 aPatch[off++] = 0x50; /* push eax */
1799
1800 aPatch[off++] = 0x31; /* xor edx, edx */
1801 aPatch[off++] = 0xD2;
1802
1803 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1804 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1805 off += sizeof(uint32_t);
1806
1807 aPatch[off++] = 0x0F; /* rdmsr */
1808 aPatch[off++] = 0x32;
1809
1810 aPatch[off++] = 0x89; /* mov dst_reg, eax */
1811 aPatch[off++] = MAKE_MODRM(3, USE_REG_EAX, pDis->param1.base.reg_gen);
1812
1813 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1814 aPatch[off++] = 0x58; /* pop eax */
1815 if (pDis->param1.base.reg_gen != USE_REG_EDX)
1816 aPatch[off++] = 0x5A; /* pop edx */
1817 if (pDis->param1.base.reg_gen != USE_REG_ECX)
1818 aPatch[off++] = 0x59; /* pop ecx */
1819 }
1820 aPatch[off++] = 0xE9; /* jmp return_address */
1821 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
1822 off += sizeof(RTRCUINTPTR);
1823
1824 if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
1825 {
1826 /* Write new code to the patch buffer. */
1827 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
1828 AssertRC(rc);
1829
1830#ifdef LOG_ENABLED
1831 pInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
1832 while (true)
1833 {
1834 uint32_t cb;
1835
1836 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pInstr, 0, szOutput, sizeof(szOutput), &cb);
1837 if (VBOX_SUCCESS(rc))
1838 Log(("Patch instr %s\n", szOutput));
1839
1840 pInstr += cb;
1841
1842 if (pInstr >= pVM->hwaccm.s.pFreeGuestPatchMem + off)
1843 break;
1844 }
1845#endif
1846
1847 pPatch->aNewOpcode[0] = 0xE9;
1848 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
1849
1850 /* Overwrite the TPR instruction with a jump. */
1851 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
1852 AssertRC(rc);
1853
1854#ifdef LOG_ENABLED
1855 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1856 if (VBOX_SUCCESS(rc))
1857 Log(("Jump: %s\n", szOutput));
1858#endif
1859 pVM->hwaccm.s.pFreeGuestPatchMem += off;
1860 pPatch->cbNewOp = 5;
1861
1862 pPatch->Core.Key = pCtx->eip;
1863 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1864 AssertRC(rc);
1865
1866 pVM->hwaccm.s.svm.cPatches++;
1867 pVM->hwaccm.s.svm.fTPRPatchingActive = true;
1868 return VINF_SUCCESS;
1869 }
1870 else
1871 Log(("Ran out of space in our patch buffer!\n"));
1872 }
1873
1874 /* Save invalid patch, so we will not try again. */
1875 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1876
1877#ifdef LOG_ENABLED
1878 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1879 if (VBOX_SUCCESS(rc))
1880 Log(("Failed to patch instr: %s\n", szOutput));
1881#endif
1882
1883 pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1884 pPatch->Core.Key = pCtx->eip;
1885 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1886 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1887 AssertRC(rc);
1888 pVM->hwaccm.s.svm.cPatches++;
1889 return VINF_SUCCESS;
1890}
1891
1892/**
1893 * Attempt to patch TPR mmio instructions
1894 *
1895 * @returns VBox status code.
1896 * @param pVM The VM to operate on.
1897 * @param pVCpu The VM CPU to operate on.
1898 * @param pCtx CPU context
1899 */
1900VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1901{
1902 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, (pVM->hwaccm.s.pGuestPatchMem) ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr, (void *)pVCpu->idCpu);
1903 AssertRC(rc);
1904 return rc;
1905}
1906
1907/**
1908 * Force execution of the current IO code in the recompiler
1909 *
1910 * @returns VBox status code.
1911 * @param pVM The VM to operate on.
1912 * @param pCtx Partial VM execution context
1913 */
1914VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
1915{
1916 PVMCPU pVCpu = VMMGetCpu(pVM);
1917
1918 Assert(pVM->fHWACCMEnabled);
1919 Log(("HWACCMR3EmulateIoBlock\n"));
1920
1921 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
1922 if (HWACCMCanEmulateIoBlockEx(pCtx))
1923 {
1924 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
1925 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
1926 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
1927 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
1928 return VINF_EM_RESCHEDULE_REM;
1929 }
1930 return VINF_SUCCESS;
1931}
1932
1933/**
1934 * Checks if we can currently use hardware accelerated raw mode.
1935 *
1936 * @returns boolean
1937 * @param pVM The VM to operate on.
1938 * @param pCtx Partial VM execution context
1939 */
1940VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
1941{
1942 PVMCPU pVCpu = VMMGetCpu(pVM);
1943
1944 Assert(pVM->fHWACCMEnabled);
1945
1946 /* If we're still executing the IO code, then return false. */
1947 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
1948 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
1949 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
1950 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
1951 return false;
1952
1953 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
1954
1955 /* AMD-V supports real & protected mode with or without paging. */
1956 if (pVM->hwaccm.s.svm.fEnabled)
1957 {
1958 pVCpu->hwaccm.s.fActive = true;
1959 return true;
1960 }
1961
1962 pVCpu->hwaccm.s.fActive = false;
1963
1964 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
1965#ifdef HWACCM_VMX_EMULATE_REALMODE
1966 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1967 {
1968 if (CPUMIsGuestInRealModeEx(pCtx))
1969 {
1970 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
1971 * The base must also be equal to (sel << 4).
1972 */
1973 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
1974 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
1975 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
1976 || pCtx->es != (pCtx->esHid.u64Base >> 4)
1977 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
1978 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
1979 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
1980 {
1981 return false;
1982 }
1983 }
1984 else
1985 {
1986 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
1987 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
1988 * from real to protected mode. (all sorts of RPL & DPL assumptions)
1989 */
1990 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1991 && enmGuestMode >= PGMMODE_PROTECTED)
1992 {
1993 if ( (pCtx->cs & X86_SEL_RPL)
1994 || (pCtx->ds & X86_SEL_RPL)
1995 || (pCtx->es & X86_SEL_RPL)
1996 || (pCtx->fs & X86_SEL_RPL)
1997 || (pCtx->gs & X86_SEL_RPL)
1998 || (pCtx->ss & X86_SEL_RPL))
1999 {
2000 return false;
2001 }
2002 }
2003 }
2004 }
2005 else
2006#endif /* HWACCM_VMX_EMULATE_REALMODE */
2007 {
2008 if (!CPUMIsGuestInLongModeEx(pCtx))
2009 {
2010 /** @todo This should (probably) be set on every excursion to the REM,
2011 * however it's too risky right now. So, only apply it when we go
2012 * back to REM for real mode execution. (The XP hack below doesn't
2013 * work reliably without this.)
2014 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2015 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2016
2017 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2018 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
2019 return false;
2020
2021 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2022 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2023 * hidden registers (possible recompiler bug; see load_seg_vm) */
2024 if (pCtx->csHid.Attr.n.u1Present == 0)
2025 return false;
2026 if (pCtx->ssHid.Attr.n.u1Present == 0)
2027 return false;
2028
2029 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2030 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2031 /** @todo This check is actually wrong, it doesn't take the direction of the
2032 * stack segment into account. But, it does the job for now. */
2033 if (pCtx->rsp >= pCtx->ssHid.u32Limit)
2034 return false;
2035#if 0
2036 if ( pCtx->cs >= pCtx->gdtr.cbGdt
2037 || pCtx->ss >= pCtx->gdtr.cbGdt
2038 || pCtx->ds >= pCtx->gdtr.cbGdt
2039 || pCtx->es >= pCtx->gdtr.cbGdt
2040 || pCtx->fs >= pCtx->gdtr.cbGdt
2041 || pCtx->gs >= pCtx->gdtr.cbGdt)
2042 return false;
2043#endif
2044 }
2045 }
2046
2047 if (pVM->hwaccm.s.vmx.fEnabled)
2048 {
2049 uint32_t mask;
2050
2051 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2052 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2053 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2054 mask &= ~X86_CR0_NE;
2055
2056#ifdef HWACCM_VMX_EMULATE_REALMODE
2057 if (pVM->hwaccm.s.vmx.pRealModeTSS)
2058 {
2059 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2060 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2061 }
2062 else
2063#endif
2064 {
2065 /* We support protected mode without paging using identity mapping. */
2066 mask &= ~X86_CR0_PG;
2067 }
2068 if ((pCtx->cr0 & mask) != mask)
2069 return false;
2070
2071 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2072 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2073 if ((pCtx->cr0 & mask) != 0)
2074 return false;
2075
2076 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2077 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2078 mask &= ~X86_CR4_VMXE;
2079 if ((pCtx->cr4 & mask) != mask)
2080 return false;
2081
2082 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2083 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2084 if ((pCtx->cr4 & mask) != 0)
2085 return false;
2086
2087 pVCpu->hwaccm.s.fActive = true;
2088 return true;
2089 }
2090
2091 return false;
2092}
2093
2094/**
2095 * Notifcation from EM about a rescheduling into hardware assisted execution
2096 * mode.
2097 *
2098 * @param pVCpu Pointer to the current virtual cpu structure.
2099 */
2100VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2101{
2102 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2103}
2104
2105/**
2106 * Notifcation from EM about returning from instruction emulation (REM / EM).
2107 *
2108 * @param pVCpu Pointer to the current virtual cpu structure.
2109 */
2110VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2111{
2112 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2113}
2114
2115/**
2116 * Checks if we are currently using hardware accelerated raw mode.
2117 *
2118 * @returns boolean
2119 * @param pVCpu The VMCPU to operate on.
2120 */
2121VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2122{
2123 return pVCpu->hwaccm.s.fActive;
2124}
2125
2126/**
2127 * Checks if we are currently using nested paging.
2128 *
2129 * @returns boolean
2130 * @param pVM The VM to operate on.
2131 */
2132VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2133{
2134 return pVM->hwaccm.s.fNestedPaging;
2135}
2136
2137/**
2138 * Checks if we are currently using VPID in VT-x mode.
2139 *
2140 * @returns boolean
2141 * @param pVM The VM to operate on.
2142 */
2143VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2144{
2145 return pVM->hwaccm.s.vmx.fVPID;
2146}
2147
2148
2149/**
2150 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2151 *
2152 * @returns boolean
2153 * @param pVM The VM to operate on.
2154 */
2155VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2156{
2157 return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2158}
2159
2160/**
2161 * Restart an I/O instruction that was refused in ring-0
2162 *
2163 * @returns VBox status code
2164 * @param pVM The VM to operate on.
2165 * @param pVCpu The VMCPU to operate on.
2166 * @param pCtx VCPU register context
2167 */
2168VMMR3DECL(int) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2169{
2170 HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2171 int rc;
2172
2173 pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2174
2175 if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2176 || enmType == HWACCMPENDINGIO_INVALID)
2177 return VERR_NOT_FOUND;
2178
2179 switch (enmType)
2180 {
2181 case HWACCMPENDINGIO_PORT_READ:
2182 {
2183 uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2184 uint32_t u32Val = 0;
2185
2186 rc = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2187 &u32Val,
2188 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2189 if (IOM_SUCCESS(rc))
2190 {
2191 /* Write back to the EAX register. */
2192 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2193 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2194 }
2195 break;
2196 }
2197
2198 case HWACCMPENDINGIO_PORT_WRITE:
2199 rc = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2200 pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2201 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2202 if (IOM_SUCCESS(rc))
2203 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2204 break;
2205
2206 default:
2207 AssertFailed();
2208 return VERR_INTERNAL_ERROR;
2209 }
2210
2211 return rc;
2212}
2213
2214/**
2215 * Inject an NMI into a running VM (only VCPU 0!)
2216 *
2217 * @returns boolean
2218 * @param pVM The VM to operate on.
2219 */
2220VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2221{
2222 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2223 return VINF_SUCCESS;
2224}
2225
2226/**
2227 * Check fatal VT-x/AMD-V error and produce some meaningful
2228 * log release message.
2229 *
2230 * @param pVM The VM to operate on.
2231 * @param iStatusCode VBox status code
2232 */
2233VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2234{
2235 for (unsigned i=0;i<pVM->cCPUs;i++)
2236 {
2237 switch(iStatusCode)
2238 {
2239 case VERR_VMX_INVALID_VMCS_FIELD:
2240 break;
2241
2242 case VERR_VMX_INVALID_VMCS_PTR:
2243 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
2244 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2245 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2246 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2247 break;
2248
2249 case VERR_VMX_UNABLE_TO_START_VM:
2250 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2251 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2252#if 0 /* @todo dump the current control fields to the release log */
2253 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2254 {
2255
2256 }
2257#endif
2258 break;
2259
2260 case VERR_VMX_UNABLE_TO_RESUME_VM:
2261 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2262 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2263 break;
2264
2265 case VERR_VMX_INVALID_VMXON_PTR:
2266 break;
2267 }
2268 }
2269}
2270
2271/**
2272 * Execute state save operation.
2273 *
2274 * @returns VBox status code.
2275 * @param pVM VM Handle.
2276 * @param pSSM SSM operation handle.
2277 */
2278static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2279{
2280 int rc;
2281
2282 Log(("hwaccmR3Save:\n"));
2283
2284 for (unsigned i=0;i<pVM->cCPUs;i++)
2285 {
2286 /*
2287 * Save the basic bits - fortunately all the other things can be resynced on load.
2288 */
2289 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2290 AssertRCReturn(rc, rc);
2291 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2292 AssertRCReturn(rc, rc);
2293 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2294 AssertRCReturn(rc, rc);
2295
2296 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2297 AssertRCReturn(rc, rc);
2298 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2299 AssertRCReturn(rc, rc);
2300 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2301 AssertRCReturn(rc, rc);
2302 }
2303#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2304 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2305 AssertRCReturn(rc, rc);
2306 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2307 AssertRCReturn(rc, rc);
2308 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2309 AssertRCReturn(rc, rc);
2310
2311 /* Store all the guest patch records too. */
2312 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.svm.cPatches);
2313 AssertRCReturn(rc, rc);
2314
2315 for (unsigned i = 0; i < pVM->hwaccm.s.svm.cPatches; i++)
2316 {
2317 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[i];
2318
2319 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2320 AssertRCReturn(rc, rc);
2321
2322 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2323 AssertRCReturn(rc, rc);
2324
2325 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2326 AssertRCReturn(rc, rc);
2327
2328 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2329 AssertRCReturn(rc, rc);
2330
2331 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2332 AssertRCReturn(rc, rc);
2333
2334 AssertCompileSize(HWACCMTPRINSTR, 4);
2335 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2336 AssertRCReturn(rc, rc);
2337
2338 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2339 AssertRCReturn(rc, rc);
2340
2341 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2342 AssertRCReturn(rc, rc);
2343
2344 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2345 AssertRCReturn(rc, rc);
2346
2347 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2348 AssertRCReturn(rc, rc);
2349 }
2350#endif
2351 return VINF_SUCCESS;
2352}
2353
2354/**
2355 * Execute state load operation.
2356 *
2357 * @returns VBox status code.
2358 * @param pVM VM Handle.
2359 * @param pSSM SSM operation handle.
2360 * @param u32Version Data layout version.
2361 */
2362static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2363{
2364 int rc;
2365
2366 Log(("hwaccmR3Load:\n"));
2367
2368 /*
2369 * Validate version.
2370 */
2371 if ( u32Version != HWACCM_SSM_VERSION
2372 && u32Version != HWACCM_SSM_VERSION_NO_PATCHING
2373 && u32Version != HWACCM_SSM_VERSION_2_0_X)
2374 {
2375 AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
2376 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2377 }
2378 for (unsigned i=0;i<pVM->cCPUs;i++)
2379 {
2380 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2381 AssertRCReturn(rc, rc);
2382 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2383 AssertRCReturn(rc, rc);
2384 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2385 AssertRCReturn(rc, rc);
2386
2387 if (u32Version >= HWACCM_SSM_VERSION_NO_PATCHING)
2388 {
2389 uint32_t val;
2390
2391 rc = SSMR3GetU32(pSSM, &val);
2392 AssertRCReturn(rc, rc);
2393 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2394
2395 rc = SSMR3GetU32(pSSM, &val);
2396 AssertRCReturn(rc, rc);
2397 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2398
2399 rc = SSMR3GetU32(pSSM, &val);
2400 AssertRCReturn(rc, rc);
2401 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2402 }
2403 }
2404#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2405 if (u32Version > HWACCM_SSM_VERSION_NO_PATCHING)
2406 {
2407 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2408 AssertRCReturn(rc, rc);
2409 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2410 AssertRCReturn(rc, rc);
2411 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2412 AssertRCReturn(rc, rc);
2413
2414 /* Fetch all TPR patch records. */
2415 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.svm.cPatches);
2416 AssertRCReturn(rc, rc);
2417
2418 for (unsigned i = 0; i < pVM->hwaccm.s.svm.cPatches; i++)
2419 {
2420 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[i];
2421
2422 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2423 AssertRCReturn(rc, rc);
2424
2425 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2426 AssertRCReturn(rc, rc);
2427
2428 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2429 AssertRCReturn(rc, rc);
2430
2431 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2432 AssertRCReturn(rc, rc);
2433
2434 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2435 AssertRCReturn(rc, rc);
2436
2437 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2438 AssertRCReturn(rc, rc);
2439
2440 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2441 AssertRCReturn(rc, rc);
2442
2443 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2444 AssertRCReturn(rc, rc);
2445
2446 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2447 AssertRCReturn(rc, rc);
2448
2449 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2450 AssertRCReturn(rc, rc);
2451
2452 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
2453 AssertRC(rc);
2454 }
2455 }
2456#endif
2457 return VINF_SUCCESS;
2458}
2459
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