VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 22015

Last change on this file since 22015 was 22015, checked in by vboxsync, 15 years ago

Removed unnecessary TPR patch instructions
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 117.8 KB
Line 
1/* $Id: HWACCM.cpp 22015 2009-08-06 08:39:54Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/csam.h>
35#include <VBox/selm.h>
36#include <VBox/rem.h>
37#include <VBox/hwacc_vmx.h>
38#include <VBox/hwacc_svm.h>
39#include "HWACCMInternal.h"
40#include <VBox/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/string.h>
48#include <iprt/thread.h>
49
50/*******************************************************************************
51* Global Variables *
52*******************************************************************************/
53#ifdef VBOX_WITH_STATISTICS
54# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55# define EXIT_REASON_NIL() NULL
56/** Exit reason descriptions for VT-x, used to describe statistics. */
57static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58{
59 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67 EXIT_REASON_NIL(),
68 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94 EXIT_REASON_NIL(),
95 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96 EXIT_REASON_NIL(),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101 EXIT_REASON_NIL(),
102 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110 EXIT_REASON_NIL(),
111 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115 EXIT_REASON_NIL()
116};
117/** Exit reason descriptions for AMD-V, used to describe statistics. */
118static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119{
120 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
121 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
122 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
123 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
124 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
125 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
126 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
127 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
128 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
129 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
130 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
131 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
132 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
133 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
134 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
135 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
136 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
137 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
152 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
153 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
154 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
155 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
156 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
157 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
158 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
159 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
160 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
161 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
162 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
163 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
164 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
165 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
166 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
167 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
168 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
169 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
184 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
185 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_INTR , 96, "Physical maskable interrupt."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_NMI , 97, "Physical non-maskable interrupt."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_SMI , 98, "System management interrupt."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_INIT , 99, "Physical INIT signal."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_VINTR ,100, "Visual interrupt."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_IDTR_READ ,102, "Read IDTR"),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_GDTR_READ ,103, "Read GDTR"),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_LDTR_READ ,104, "Read LDTR."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,105, "Read TR."),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,106, "Write IDTR."),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,107, "Write GDTR."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,108, "Write LDTR."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,109, "Write TR."),
230 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
231 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
232 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
233 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
234 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
235 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
236 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
237 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
238 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
239 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
240 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
241 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
242 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
243 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
244 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
245 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
246 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
247 EXIT_REASON(SVM_EXIT_TASK_SHUTDOWN ,127, "Shutdown."),
248 EXIT_REASON(SVM_EXIT_TASK_VMRUN ,128, "VMRUN instruction."),
249 EXIT_REASON(SVM_EXIT_TASK_VMCALL ,129, "VMCALL instruction."),
250 EXIT_REASON(SVM_EXIT_TASK_VMLOAD ,130, "VMLOAD instruction."),
251 EXIT_REASON(SVM_EXIT_TASK_VMSAVE ,131, "VMSAVE instruction."),
252 EXIT_REASON(SVM_EXIT_TASK_STGI ,132, "STGI instruction."),
253 EXIT_REASON(SVM_EXIT_TASK_CLGI ,133, "CLGI instruction."),
254 EXIT_REASON(SVM_EXIT_TASK_SKINIT ,134, "SKINIT instruction."),
255 EXIT_REASON(SVM_EXIT_TASK_RDTSCP ,135, "RDTSCP instruction."),
256 EXIT_REASON(SVM_EXIT_TASK_ICEBP ,136, "ICEBP instruction."),
257 EXIT_REASON(SVM_EXIT_TASK_WBINVD ,137, "WBINVD instruction."),
258 EXIT_REASON(SVM_EXIT_TASK_MONITOR ,138, "MONITOR instruction."),
259 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
260 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
261 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
262 EXIT_REASON_NIL()
263};
264# undef EXIT_REASON
265# undef EXIT_REASON_NIL
266#endif /* VBOX_WITH_STATISTICS */
267
268/*******************************************************************************
269* Internal Functions *
270*******************************************************************************/
271static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
272static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
273
274
275/**
276 * Initializes the HWACCM.
277 *
278 * @returns VBox status code.
279 * @param pVM The VM to operate on.
280 */
281VMMR3DECL(int) HWACCMR3Init(PVM pVM)
282{
283 LogFlow(("HWACCMR3Init\n"));
284
285 /*
286 * Assert alignment and sizes.
287 */
288 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
289 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
290
291 /* Some structure checks. */
292 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
293 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
294 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
295 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
296
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
300 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
303 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
304
305
306 /*
307 * Register the saved state data unit.
308 */
309 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
310 NULL, hwaccmR3Save, NULL,
311 NULL, hwaccmR3Load, NULL);
312 if (RT_FAILURE(rc))
313 return rc;
314
315 /* Misc initialisation. */
316 pVM->hwaccm.s.vmx.fSupported = false;
317 pVM->hwaccm.s.svm.fSupported = false;
318 pVM->hwaccm.s.vmx.fEnabled = false;
319 pVM->hwaccm.s.svm.fEnabled = false;
320
321 pVM->hwaccm.s.fNestedPaging = false;
322
323 /* Disabled by default. */
324 pVM->fHWACCMEnabled = false;
325
326 /*
327 * Check CFGM options.
328 */
329 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
330 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
331 /* Nested paging: disabled by default. */
332 rc = CFGMR3QueryBoolDef(pRoot, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
333 AssertRC(rc);
334
335 /* VT-x VPID: disabled by default. */
336 rc = CFGMR3QueryBoolDef(pRoot, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
337 AssertRC(rc);
338
339 /* HWACCM support must be explicitely enabled in the configuration file. */
340 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
341 AssertRC(rc);
342
343#ifdef RT_OS_DARWIN
344 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
345#else
346 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
347#endif
348 {
349 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
350 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
351 return VERR_HWACCM_CONFIG_MISMATCH;
352 }
353
354 if (VMMIsHwVirtExtForced(pVM))
355 pVM->fHWACCMEnabled = true;
356
357#if HC_ARCH_BITS == 32
358 /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
359 * (To use the default, don't set 64bitEnabled in CFGM.) */
360 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
361 AssertLogRelRCReturn(rc, rc);
362 if (pVM->hwaccm.s.fAllow64BitGuests)
363 {
364# ifdef RT_OS_DARWIN
365 if (!VMMIsHwVirtExtForced(pVM))
366# else
367 if (!pVM->hwaccm.s.fAllowed)
368# endif
369 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
370 }
371#else
372 /* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
373 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
374 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
375 AssertLogRelRCReturn(rc, rc);
376#endif
377
378 /* Max number of resume loops. */
379 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
380 AssertRC(rc);
381
382 return VINF_SUCCESS;
383}
384
385/**
386 * Initializes the per-VCPU HWACCM.
387 *
388 * @returns VBox status code.
389 * @param pVM The VM to operate on.
390 */
391VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
392{
393 LogFlow(("HWACCMR3InitCPU\n"));
394
395 for (unsigned i=0;i<pVM->cCPUs;i++)
396 {
397 PVMCPU pVCpu = &pVM->aCpus[i];
398
399 pVCpu->hwaccm.s.fActive = false;
400 }
401
402#ifdef VBOX_WITH_STATISTICS
403 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
404 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
405 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
406 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
407
408 /*
409 * Statistics.
410 */
411 for (unsigned i=0;i<pVM->cCPUs;i++)
412 {
413 PVMCPU pVCpu = &pVM->aCpus[i];
414 int rc;
415
416 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
417 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
418 AssertRC(rc);
419 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
420 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
421 AssertRC(rc);
422 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
423 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
424 AssertRC(rc);
425# if 1 /* temporary for tracking down darwin holdup. */
426 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
427 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
428 AssertRC(rc);
429 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
430 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
431 AssertRC(rc);
432 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
433 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
434 AssertRC(rc);
435# endif
436 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
437 "/PROF/HWACCM/CPU%d/InGC", i);
438 AssertRC(rc);
439
440# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
441 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
442 "/PROF/HWACCM/CPU%d/Switcher3264", i);
443 AssertRC(rc);
444# endif
445
446# define HWACCM_REG_COUNTER(a, b) \
447 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
448 AssertRC(rc);
449
450 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
451 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
452 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
453 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
454 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
455 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
456 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
457 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
458 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
459 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
460 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
461 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
462 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
463 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
464 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
465 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
466 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
467 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
468 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
469 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
470 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
471 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
472 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
473 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
474 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
475 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
476 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
477 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
478 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
479 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
480 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
481 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
482 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
483 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
484 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
485 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
486 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
487
488 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
489 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
490
491 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
492 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
493 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
494
495 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
496 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
498 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
499 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
503 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
504 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
505 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
506
507 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
508 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
509
510 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
511 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
512 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
513
514 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
515 {
516 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
517 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
518 AssertRC(rc);
519 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
520 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
521 AssertRC(rc);
522 }
523
524#undef HWACCM_REG_COUNTER
525
526 pVCpu->hwaccm.s.paStatExitReason = NULL;
527
528 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
529 AssertRC(rc);
530 if (RT_SUCCESS(rc))
531 {
532 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
533 for (int j=0;j<MAX_EXITREASON_STAT;j++)
534 {
535 if (papszDesc[j])
536 {
537 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
538 papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
539 AssertRC(rc);
540 }
541 }
542 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
543 AssertRC(rc);
544 }
545 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
546# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
547 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
548# else
549 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
550# endif
551
552 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
553 AssertRCReturn(rc, rc);
554 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
555# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
556 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
557# else
558 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
559# endif
560 for (unsigned j = 0; j < 255; j++)
561 STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
562 (j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
563
564 }
565#endif /* VBOX_WITH_STATISTICS */
566
567#ifdef VBOX_WITH_CRASHDUMP_MAGIC
568 /* Magic marker for searching in crash dumps. */
569 for (unsigned i=0;i<pVM->cCPUs;i++)
570 {
571 PVMCPU pVCpu = &pVM->aCpus[i];
572
573 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
574 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
575 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
576 }
577#endif
578 return VINF_SUCCESS;
579}
580
581/**
582 * Turns off normal raw mode features
583 *
584 * @param pVM The VM to operate on.
585 */
586static void hwaccmR3DisableRawMode(PVM pVM)
587{
588 /* Disable PATM & CSAM. */
589 PATMR3AllowPatching(pVM, false);
590 CSAMDisableScanning(pVM);
591
592 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
593 SELMR3DisableMonitoring(pVM);
594 TRPMR3DisableMonitoring(pVM);
595
596 /* Disable the switcher code (safety precaution). */
597 VMMR3DisableSwitcher(pVM);
598
599 /* Disable mapping of the hypervisor into the shadow page table. */
600 PGMR3MappingsDisable(pVM);
601
602 /* Disable the switcher */
603 VMMR3DisableSwitcher(pVM);
604
605 /* Reinit the paging mode to force the new shadow mode. */
606 for (unsigned i=0;i<pVM->cCPUs;i++)
607 {
608 PVMCPU pVCpu = &pVM->aCpus[i];
609
610 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
611 }
612}
613
614/**
615 * Initialize VT-x or AMD-V.
616 *
617 * @returns VBox status code.
618 * @param pVM The VM handle.
619 */
620VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
621{
622 int rc;
623
624 if ( !pVM->hwaccm.s.vmx.fSupported
625 && !pVM->hwaccm.s.svm.fSupported)
626 {
627 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
628 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
629 if (VMMIsHwVirtExtForced(pVM))
630 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
631 return VINF_SUCCESS;
632 }
633
634 if (!pVM->hwaccm.s.fAllowed)
635 return VINF_SUCCESS; /* nothing to do */
636
637 /* Enable VT-x or AMD-V on all host CPUs. */
638 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
639 if (RT_FAILURE(rc))
640 {
641 LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
642 return rc;
643 }
644 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
645
646 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
647
648 if (pVM->hwaccm.s.vmx.fSupported)
649 {
650 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
651
652 if ( pVM->hwaccm.s.fInitialized == false
653 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
654 {
655 uint64_t val;
656 RTGCPHYS GCPhys = 0;
657
658 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
659 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
660 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
661 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
662 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
663 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
664 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
665 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
666
667 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
668 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
669 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
670 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
671 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
672 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
673 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
674 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
675 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
676 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
677 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
678 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
679 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
680 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
681 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
682 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
683 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
684 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
685 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
686
687 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
688 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
689 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
690 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
691 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
692 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
693 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
694 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
695 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
696 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
697 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
698 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
699 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
700 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
701 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
702 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
703 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
704 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
705 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
706 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
707 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
708 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
709 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
710 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
711 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
712 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
713 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
714 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
715 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
716 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
717 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
718 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
719 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
720 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
721 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
722 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
723 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
724 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
725 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
726 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
727 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
728 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
729 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
730 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
731
732 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
733 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
734 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
735 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
736 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
737 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
738 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
739 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
740 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
741 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
742 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
743 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
744 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
745 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
746 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
747 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
748 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
749 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
750 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
751 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
752 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
753 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
754 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
755 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
756 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
757 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
758 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
759 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
760 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
761 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
762 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
763 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
764 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
765 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
766 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
767 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
768 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
769 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
770 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
771 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
772 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
773 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
774 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
775
776 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
777 {
778 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
779 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
780 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
781 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
782 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
783 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
784 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
785 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
786 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
787 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
788 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
789 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
790 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
791 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
792
793 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
794 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
795 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
796 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
797 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
798 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
799 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
800 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
801 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
802 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
803 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
804 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
805 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
806 }
807
808 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
809 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
810 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
811 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
812 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
813 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
814 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
815 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
816 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
817 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
818 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
819 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
820 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
821 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
822 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
823 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
824 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
825 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
826 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
827 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
828 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
829 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
830 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
831 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
832 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
833 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
834 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
835 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
836 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
837 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
838 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
839
840 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
841 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
842 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
843 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
844 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
845 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
846 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
847 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
848 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
849 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
850 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
851 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
852 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
853 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
854 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
855 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
856 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
857 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
858 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
859 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
860 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
861 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
862 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
863 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
864 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
865 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
866 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
867 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
868 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
869 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
870 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
871 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
872 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
873 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
874 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
875
876 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
877 {
878 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
879
880 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
881 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
882 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
883 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
884 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
885 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
886 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
887 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
888 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
889 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
890 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
891 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
892 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
893 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
894 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
895 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
896 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
897 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
898 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
899 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
900 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
901 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
902 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
903 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
904 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
905 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
906 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
907 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
908 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
909 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
910 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
911 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
912 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
913 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
914 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
915 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
916 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
917 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
918 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
919 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
920 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
921 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
922 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
923 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
924 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
925 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
926 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
927 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
928 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
929 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
930 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
931 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
932 }
933
934 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
935 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
936 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
937 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
938 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
939 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
940
941 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
942 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
943 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
944 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
945 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
946
947 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
948 LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
949
950 for (unsigned i=0;i<pVM->cCPUs;i++)
951 LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
952
953#ifdef HWACCM_VTX_WITH_EPT
954 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
955 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
956#endif /* HWACCM_VTX_WITH_EPT */
957#ifdef HWACCM_VTX_WITH_VPID
958 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
959 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
960 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
961#endif /* HWACCM_VTX_WITH_VPID */
962
963 /* Only try once. */
964 pVM->hwaccm.s.fInitialized = true;
965
966 /* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
967#if 1
968 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
969#else
970 rc = VERR_NO_MEMORY; /* simulation of no VMMDev Heap. */
971#endif
972 if (RT_SUCCESS(rc))
973 {
974 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
975 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
976 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
977 /* Bit set to 0 means redirection enabled. */
978 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
979 /* Allow all port IO, so the VT-x IO intercepts do their job. */
980 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
981 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
982
983 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
984 * real and protected mode without paging with EPT.
985 */
986 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
987 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
988 {
989 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
990 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
991 }
992
993 /* We convert it here every time as pci regions could be reconfigured. */
994 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
995 AssertRC(rc);
996 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
997
998 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
999 AssertRC(rc);
1000 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1001 }
1002 else
1003 {
1004 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1005 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1006 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1007 }
1008
1009 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1010 AssertRC(rc);
1011 if (rc == VINF_SUCCESS)
1012 {
1013 pVM->fHWACCMEnabled = true;
1014 pVM->hwaccm.s.vmx.fEnabled = true;
1015 hwaccmR3DisableRawMode(pVM);
1016
1017 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1018#ifdef VBOX_ENABLE_64_BITS_GUESTS
1019 if (pVM->hwaccm.s.fAllow64BitGuests)
1020 {
1021 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1022 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1023 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1024 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1025 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1026 }
1027 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1028 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1029 : "HWACCM: 32-bit guests supported.\n"));
1030#else
1031 LogRel(("HWACCM: 32-bit guests supported.\n"));
1032#endif
1033 LogRel(("HWACCM: VMX enabled!\n"));
1034 if (pVM->hwaccm.s.fNestedPaging)
1035 {
1036 LogRel(("HWACCM: Enabled nested paging\n"));
1037 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1038 }
1039 if (pVM->hwaccm.s.vmx.fVPID)
1040 LogRel(("HWACCM: Enabled VPID\n"));
1041
1042 if ( pVM->hwaccm.s.fNestedPaging
1043 || pVM->hwaccm.s.vmx.fVPID)
1044 {
1045 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1046 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1047 }
1048 }
1049 else
1050 {
1051 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1052 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1053 pVM->fHWACCMEnabled = false;
1054 }
1055 }
1056 }
1057 else
1058 if (pVM->hwaccm.s.svm.fSupported)
1059 {
1060 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1061
1062 if (pVM->hwaccm.s.fInitialized == false)
1063 {
1064 /* Erratum 170 which requires a forced TLB flush for each world switch:
1065 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1066 *
1067 * All BH-G1/2 and DH-G1/2 models include a fix:
1068 * Athlon X2: 0x6b 1/2
1069 * 0x68 1/2
1070 * Athlon 64: 0x7f 1
1071 * 0x6f 2
1072 * Sempron: 0x7f 1/2
1073 * 0x6f 2
1074 * 0x6c 2
1075 * 0x7c 2
1076 * Turion 64: 0x68 2
1077 *
1078 */
1079 uint32_t u32Dummy;
1080 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1081 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1082 u32BaseFamily= (u32Version >> 8) & 0xf;
1083 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1084 u32Model = ((u32Version >> 4) & 0xf);
1085 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1086 u32Stepping = u32Version & 0xf;
1087 if ( u32Family == 0xf
1088 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1089 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1090 {
1091 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1092 }
1093
1094 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1095 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1096 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1097 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1098 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1099
1100 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1101 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
1102 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
1103 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
1104 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
1105 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
1106 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
1107 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
1108 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
1109 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
1110
1111 /* Only try once. */
1112 pVM->hwaccm.s.fInitialized = true;
1113
1114 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1115 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1116
1117 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1118 AssertRC(rc);
1119 if (rc == VINF_SUCCESS)
1120 {
1121 pVM->fHWACCMEnabled = true;
1122 pVM->hwaccm.s.svm.fEnabled = true;
1123
1124 if (pVM->hwaccm.s.fNestedPaging)
1125 LogRel(("HWACCM: Enabled nested paging\n"));
1126
1127 hwaccmR3DisableRawMode(pVM);
1128 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1129 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1130 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1131#ifdef VBOX_ENABLE_64_BITS_GUESTS
1132 if (pVM->hwaccm.s.fAllow64BitGuests)
1133 {
1134 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1135 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1136 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1137 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1138 }
1139#endif
1140 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1141 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1142 : "HWACCM: 32-bit guest supported.\n"));
1143 }
1144 else
1145 {
1146 pVM->fHWACCMEnabled = false;
1147 }
1148 }
1149 }
1150 return VINF_SUCCESS;
1151}
1152
1153/**
1154 * Applies relocations to data and code managed by this
1155 * component. This function will be called at init and
1156 * whenever the VMM need to relocate it self inside the GC.
1157 *
1158 * @param pVM The VM.
1159 */
1160VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1161{
1162 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1163
1164 /* Fetch the current paging mode during the relocate callback during state loading. */
1165 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1166 {
1167 for (unsigned i=0;i<pVM->cCPUs;i++)
1168 {
1169 PVMCPU pVCpu = &pVM->aCpus[i];
1170
1171 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1172 Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1173 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1174 }
1175 }
1176#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1177 if (pVM->fHWACCMEnabled)
1178 {
1179 int rc;
1180
1181 switch(PGMGetHostMode(pVM))
1182 {
1183 case PGMMODE_32_BIT:
1184 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1185 break;
1186
1187 case PGMMODE_PAE:
1188 case PGMMODE_PAE_NX:
1189 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1190 break;
1191
1192 default:
1193 AssertFailed();
1194 break;
1195 }
1196 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1197 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1198
1199 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1200 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1201
1202 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1203 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1204
1205 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1206 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1207
1208# ifdef DEBUG
1209 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1210 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1211# endif
1212 }
1213#endif
1214 return;
1215}
1216
1217/**
1218 * Checks hardware accelerated raw mode is allowed.
1219 *
1220 * @returns boolean
1221 * @param pVM The VM to operate on.
1222 */
1223VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1224{
1225 return pVM->hwaccm.s.fAllowed;
1226}
1227
1228/**
1229 * Notification callback which is called whenever there is a chance that a CR3
1230 * value might have changed.
1231 *
1232 * This is called by PGM.
1233 *
1234 * @param pVM The VM to operate on.
1235 * @param pVCpu The VMCPU to operate on.
1236 * @param enmShadowMode New shadow paging mode.
1237 * @param enmGuestMode New guest paging mode.
1238 */
1239VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1240{
1241 /* Ignore page mode changes during state loading. */
1242 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1243 return;
1244
1245 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1246
1247 if ( pVM->hwaccm.s.vmx.fEnabled
1248 && pVM->fHWACCMEnabled)
1249 {
1250 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1251 && enmGuestMode >= PGMMODE_PROTECTED)
1252 {
1253 PCPUMCTX pCtx;
1254
1255 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1256
1257 /* After a real mode switch to protected mode we must force
1258 * CPL to 0. Our real mode emulation had to set it to 3.
1259 */
1260 pCtx->ssHid.Attr.n.u2Dpl = 0;
1261 }
1262 }
1263
1264 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1265 {
1266 /* Keep track of paging mode changes. */
1267 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1268 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1269
1270 /* Did we miss a change, because all code was executed in the recompiler? */
1271 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1272 {
1273 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1274 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1275 }
1276 }
1277
1278 /* Reset the contents of the read cache. */
1279 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1280 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1281 pCache->Read.aFieldVal[j] = 0;
1282}
1283
1284/**
1285 * Terminates the HWACCM.
1286 *
1287 * Termination means cleaning up and freeing all resources,
1288 * the VM it self is at this point powered off or suspended.
1289 *
1290 * @returns VBox status code.
1291 * @param pVM The VM to operate on.
1292 */
1293VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1294{
1295 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1296 {
1297 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1298 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1299 }
1300 HWACCMR3TermCPU(pVM);
1301 return 0;
1302}
1303
1304/**
1305 * Terminates the per-VCPU HWACCM.
1306 *
1307 * Termination means cleaning up and freeing all resources,
1308 * the VM it self is at this point powered off or suspended.
1309 *
1310 * @returns VBox status code.
1311 * @param pVM The VM to operate on.
1312 */
1313VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1314{
1315 for (unsigned i=0;i<pVM->cCPUs;i++)
1316 {
1317 PVMCPU pVCpu = &pVM->aCpus[i];
1318
1319#ifdef VBOX_WITH_STATISTICS
1320 if (pVCpu->hwaccm.s.paStatExitReason)
1321 {
1322 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1323 pVCpu->hwaccm.s.paStatExitReason = NULL;
1324 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1325 }
1326 if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1327 {
1328 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1329 pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1330 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1331 }
1332#endif
1333
1334#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1335 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1336 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1337 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1338#endif
1339 }
1340 return 0;
1341}
1342
1343/**
1344 * The VM is being reset.
1345 *
1346 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1347 * needs to be removed.
1348 *
1349 * @param pVM VM handle.
1350 */
1351VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1352{
1353 LogFlow(("HWACCMR3Reset:\n"));
1354
1355 if (pVM->fHWACCMEnabled)
1356 hwaccmR3DisableRawMode(pVM);
1357
1358 for (unsigned i=0;i<pVM->cCPUs;i++)
1359 {
1360 PVMCPU pVCpu = &pVM->aCpus[i];
1361
1362 /* On first entry we'll sync everything. */
1363 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1364
1365 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1366 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1367
1368 pVCpu->hwaccm.s.fActive = false;
1369 pVCpu->hwaccm.s.Event.fPending = false;
1370
1371 /* Reset state information for real-mode emulation in VT-x. */
1372 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1373 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1374 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1375
1376 /* Reset the contents of the read cache. */
1377 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1378 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1379 pCache->Read.aFieldVal[j] = 0;
1380
1381#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1382 /* Magic marker for searching in crash dumps. */
1383 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1384 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1385#endif
1386 }
1387
1388 /* Clear all patch information. */
1389 pVM->hwaccm.s.pGuestPatchMem = 0;
1390 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1391 pVM->hwaccm.s.cbGuestPatchMem = 0;
1392 pVM->hwaccm.s.svm.cPatches = 0;
1393 pVM->hwaccm.s.svm.PatchTree = 0;
1394 pVM->hwaccm.s.svm.fTPRPatchingActive = false;
1395 ASMMemZero32(pVM->hwaccm.s.svm.aPatches, sizeof(pVM->hwaccm.s.svm.aPatches));
1396}
1397
1398/**
1399 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1400 *
1401 * @returns VBox status code.
1402 * @param pVM The VM handle.
1403 * @param pVCpu The VMCPU for the EMT we're being called on.
1404 * @param pvUser Unused
1405 *
1406 */
1407DECLCALLBACK(int) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1408{
1409 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1410
1411 /* Only execute the handler on the VCPU the original patch request was issued. */
1412 if (pVCpu->idCpu != idCpu)
1413 return VINF_SUCCESS;
1414
1415 Log(("hwaccmR3RemovePatches\n"));
1416 for (unsigned i = 0; i < pVM->hwaccm.s.svm.cPatches; i++)
1417 {
1418 uint8_t szInstr[15];
1419 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[i];
1420 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1421 int rc;
1422
1423#ifdef LOG_ENABLED
1424 char szOutput[256];
1425
1426 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1427 if (VBOX_SUCCESS(rc))
1428 Log(("Patched instr: %s\n", szOutput));
1429#endif
1430
1431 /* Check if the instruction is still the same. */
1432 rc = PGMPhysSimpleReadGCPtr(pVCpu, szInstr, pInstrGC, pPatch->cbNewOp);
1433 if (rc != VINF_SUCCESS)
1434 {
1435 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1436 continue; /* swapped out or otherwise removed; skip it. */
1437 }
1438
1439 if (memcmp(szInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1440 {
1441 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1442 continue; /* skip it. */
1443 }
1444
1445 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1446 AssertRC(rc);
1447
1448#ifdef LOG_ENABLED
1449 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1450 if (VBOX_SUCCESS(rc))
1451 Log(("Original instr: %s\n", szOutput));
1452#endif
1453 }
1454 pVM->hwaccm.s.svm.cPatches = 0;
1455 pVM->hwaccm.s.svm.PatchTree = 0;
1456 pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1457 pVM->hwaccm.s.svm.fTPRPatchingActive = false;
1458 return VINF_SUCCESS;
1459}
1460
1461/**
1462 * Enable patching in a VT-x/AMD-V guest
1463 *
1464 * @returns VBox status code.
1465 * @param pVM The VM to operate on.
1466 * @param idCpu VCPU to execute hwaccmR3RemovePatches on
1467 * @param pPatchMem Patch memory range
1468 * @param cbPatchMem Size of the memory range
1469 */
1470int hwaccmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1471{
1472 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)idCpu);
1473 AssertRC(rc);
1474
1475 pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1476 pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1477 pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1478 return VINF_SUCCESS;
1479}
1480
1481/**
1482 * Enable patching in a VT-x/AMD-V guest
1483 *
1484 * @returns VBox status code.
1485 * @param pVM The VM to operate on.
1486 * @param pPatchMem Patch memory range
1487 * @param cbPatchMem Size of the memory range
1488 */
1489VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1490{
1491 Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1492
1493 /* Current TPR patching only applies to AMD cpus.
1494 * Needs to be extended to Intel CPUs without the APIC TPR hardware optimization.
1495 */
1496 if (CPUMGetCPUVendor(pVM) != CPUMCPUVENDOR_AMD)
1497 return VERR_NOT_SUPPORTED;
1498
1499 if (pVM->cCPUs > 1)
1500 {
1501 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1502 PVMREQ pReq;
1503 int rc = VMR3ReqCallU(pVM->pUVM, VMCPUID_ANY_QUEUE, &pReq, 0, VMREQFLAGS_NO_WAIT,
1504 (PFNRT)hwaccmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1505 AssertRC(rc);
1506 return rc;
1507 }
1508 else
1509 return hwaccmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1510}
1511
1512/**
1513 * Disable patching in a VT-x/AMD-V guest
1514 *
1515 * @returns VBox status code.
1516 * @param pVM The VM to operate on.
1517 * @param pPatchMem Patch memory range
1518 * @param cbPatchMem Size of the memory range
1519 */
1520VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1521{
1522 Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1523
1524 Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1525 Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1526
1527 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1528 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)VMMGetCpuId(pVM));
1529 AssertRC(rc);
1530
1531 pVM->hwaccm.s.pGuestPatchMem = 0;
1532 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1533 pVM->hwaccm.s.cbGuestPatchMem = 0;
1534 pVM->hwaccm.s.svm.fTPRPatchingActive = false;
1535 return VINF_SUCCESS;
1536}
1537
1538
1539/**
1540 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1541 *
1542 * @returns VBox status code.
1543 * @param pVM The VM handle.
1544 * @param pVCpu The VMCPU for the EMT we're being called on.
1545 * @param pvUser User specified CPU context
1546 *
1547 */
1548DECLCALLBACK(int) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1549{
1550 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1551 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1552 RTGCPTR oldrip = pCtx->rip;
1553 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1554 unsigned cbOp;
1555
1556 /* Only execute the handler on the VCPU the original patch request was issued. */
1557 if (pVCpu->idCpu != idCpu)
1558 return VINF_SUCCESS;
1559
1560 Log(("hwaccmR3ReplaceTprInstr: %RGv\n", pCtx->rip));
1561
1562 /* Two or more VCPUs were racing to patch this instruction. */
1563 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.svm.PatchTree, (AVLOU32KEY)pCtx->eip);
1564 if (pPatch)
1565 return VINF_SUCCESS;
1566
1567 Assert(pVM->hwaccm.s.svm.cPatches < RT_ELEMENTS(pVM->hwaccm.s.svm.aPatches));
1568
1569 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1570 AssertRC(rc);
1571 if ( rc == VINF_SUCCESS
1572 && pDis->pCurInstr->opcode == OP_MOV
1573 && cbOp >= 3)
1574 {
1575 uint8_t aVMMCall[3] = { 0xf, 0x1, 0xd9};
1576 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1577 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1578
1579 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1580 AssertRC(rc);
1581
1582 pPatch->cbOp = cbOp;
1583
1584 if (pDis->param1.flags == USE_DISPLACEMENT32)
1585 {
1586 /* write. */
1587 if (pDis->param2.flags == USE_REG_GEN32)
1588 {
1589 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1590 pPatch->uSrcOperand = pDis->param2.base.reg_gen;
1591 }
1592 else
1593 {
1594 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1595 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1596 pPatch->uSrcOperand = pDis->param2.parval;
1597 }
1598 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1599 AssertRC(rc);
1600
1601 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1602 pPatch->cbNewOp = sizeof(aVMMCall);
1603 }
1604 else
1605 {
1606 RTGCPTR oldrip = pCtx->rip;
1607 uint32_t oldcbOp = cbOp;
1608 uint32_t uMmioReg = pDis->param1.base.reg_gen;
1609
1610 /* read */
1611 Assert(pDis->param1.flags == USE_REG_GEN32);
1612
1613 /* Found:
1614 * mov eax, dword [fffe0080] (5 bytes)
1615 * Check if next instruction is:
1616 * shr eax, 4
1617 */
1618 pCtx->rip += cbOp;
1619 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1620 pCtx->rip = oldrip;
1621 if ( rc == VINF_SUCCESS
1622 && pDis->pCurInstr->opcode == OP_SHR
1623 && pDis->param1.flags == USE_REG_GEN32
1624 && pDis->param1.base.reg_gen == uMmioReg
1625 && pDis->param2.flags == USE_IMMEDIATE8
1626 && pDis->param2.parval == 4
1627 && oldcbOp + cbOp < sizeof(pVM->hwaccm.s.svm.aPatches[idx].aOpcode))
1628 {
1629 uint8_t szInstr[15];
1630
1631 /* Replacing two instructions now. */
1632 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, oldcbOp + cbOp);
1633 AssertRC(rc);
1634
1635 pPatch->cbOp = oldcbOp + cbOp;
1636
1637 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1638 szInstr[0] = 0xF0;
1639 szInstr[1] = 0x0F;
1640 szInstr[2] = 0x20;
1641 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
1642 for (unsigned i = 4; i < pPatch->cbOp; i++)
1643 szInstr[i] = 0x90; /* nop */
1644
1645 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, pPatch->cbOp);
1646 AssertRC(rc);
1647
1648 memcpy(pPatch->aNewOpcode, szInstr, pPatch->cbOp);
1649 pPatch->cbNewOp = pPatch->cbOp;
1650
1651 Log(("Acceptable read/shr candidate!\n"));
1652 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1653 }
1654 else
1655 {
1656 pPatch->enmType = HWACCMTPRINSTR_READ;
1657 pPatch->uDstOperand = pDis->param1.base.reg_gen;
1658
1659 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1660 AssertRC(rc);
1661
1662 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1663 pPatch->cbNewOp = sizeof(aVMMCall);
1664 }
1665 }
1666
1667 pPatch->Core.Key = pCtx->eip;
1668 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1669 AssertRC(rc);
1670
1671 pVM->hwaccm.s.svm.cPatches++;
1672 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceSuccess);
1673 return VINF_SUCCESS;
1674 }
1675
1676 /* Save invalid patch, so we will not try again. */
1677 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1678
1679#ifdef LOG_ENABLED
1680 char szOutput[256];
1681 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1682 if (VBOX_SUCCESS(rc))
1683 Log(("Failed to patch instr: %s\n", szOutput));
1684#endif
1685
1686 pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1687 pPatch->Core.Key = pCtx->eip;
1688 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1689 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1690 AssertRC(rc);
1691 pVM->hwaccm.s.svm.cPatches++;
1692 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceFailure);
1693 return VINF_SUCCESS;
1694}
1695
1696/**
1697 * Callback to patch a TPR instruction (jump to generated code)
1698 *
1699 * @returns VBox status code.
1700 * @param pVM The VM handle.
1701 * @param pVCpu The VMCPU for the EMT we're being called on.
1702 * @param pvUser User specified CPU context
1703 *
1704 */
1705DECLCALLBACK(int) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1706{
1707 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1708 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1709 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1710 unsigned cbOp;
1711 int rc;
1712#ifdef LOG_ENABLED
1713 RTGCPTR pInstr;
1714 char szOutput[256];
1715#endif
1716
1717 /* Only execute the handler on the VCPU the original patch request was issued. */
1718 if (pVCpu->idCpu != idCpu)
1719 return VINF_SUCCESS;
1720
1721 Log(("hwaccmR3PatchTprInstr %RGv\n", pCtx->rip));
1722
1723 Assert(pVM->hwaccm.s.svm.cPatches < RT_ELEMENTS(pVM->hwaccm.s.svm.aPatches));
1724
1725 /* Two or more VCPUs were racing to patch this instruction. */
1726 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.svm.PatchTree, (AVLOU32KEY)pCtx->eip);
1727 if (pPatch)
1728 return VINF_SUCCESS;
1729
1730 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1731 AssertRC(rc);
1732 if ( rc == VINF_SUCCESS
1733 && pDis->pCurInstr->opcode == OP_MOV
1734 && cbOp >= 5)
1735 {
1736 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1737 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1738 uint8_t aPatch[64];
1739 uint32_t off = 0;
1740
1741#ifdef LOG_ENABLED
1742 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1743 if (VBOX_SUCCESS(rc))
1744 Log(("Original instr: %s\n", szOutput));
1745#endif
1746
1747 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1748 AssertRC(rc);
1749
1750 pPatch->cbOp = cbOp;
1751 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
1752
1753 if (pDis->param1.flags == USE_DISPLACEMENT32)
1754 {
1755 /*
1756 * TPR write:
1757 *
1758 * push ECX [51]
1759 * push EDX [52]
1760 * push EAX [50]
1761 * xor EDX,EDX [31 D2]
1762 * mov EAX,EAX [89 C0]
1763 * or
1764 * mov EAX,0000000CCh [B8 CC 00 00 00]
1765 * mov ECX,0C0000082h [B9 82 00 00 C0]
1766 * wrmsr [0F 30]
1767 * pop EAX [58]
1768 * pop EDX [5A]
1769 * pop ECX [59]
1770 * jmp return_address [E9 return_address]
1771 *
1772 */
1773 bool fUsesEax = (pDis->param2.flags == USE_REG_GEN32 && pDis->param2.base.reg_gen == USE_REG_EAX);
1774
1775 aPatch[off++] = 0x51; /* push ecx */
1776 aPatch[off++] = 0x52; /* push edx */
1777 if (!fUsesEax)
1778 aPatch[off++] = 0x50; /* push eax */
1779 aPatch[off++] = 0x31; /* xor edx, edx */
1780 aPatch[off++] = 0xD2;
1781 if (pDis->param2.flags == USE_REG_GEN32)
1782 {
1783 if (!fUsesEax)
1784 {
1785 aPatch[off++] = 0x89; /* mov eax, src_reg */
1786 aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, USE_REG_EAX);
1787 }
1788 }
1789 else
1790 {
1791 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1792 aPatch[off++] = 0xB8; /* mov eax, immediate */
1793 *(uint32_t *)&aPatch[off] = pDis->param2.parval;
1794 off += sizeof(uint32_t);
1795 }
1796 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1797 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1798 off += sizeof(uint32_t);
1799
1800 aPatch[off++] = 0x0F; /* wrmsr */
1801 aPatch[off++] = 0x30;
1802 if (!fUsesEax)
1803 aPatch[off++] = 0x58; /* pop eax */
1804 aPatch[off++] = 0x5A; /* pop edx */
1805 aPatch[off++] = 0x59; /* pop ecx */
1806 }
1807 else
1808 {
1809 /*
1810 * TPR read:
1811 *
1812 * push ECX [51]
1813 * push EDX [52]
1814 * push EAX [50]
1815 * mov ECX,0C0000082h [B9 82 00 00 C0]
1816 * rdmsr [0F 32]
1817 * mov EAX,EAX [89 C0]
1818 * pop EAX [58]
1819 * pop EDX [5A]
1820 * pop ECX [59]
1821 * jmp return_address [E9 return_address]
1822 *
1823 */
1824 Assert(pDis->param1.flags == USE_REG_GEN32);
1825
1826 if (pDis->param1.base.reg_gen != USE_REG_ECX)
1827 aPatch[off++] = 0x51; /* push ecx */
1828 if (pDis->param1.base.reg_gen != USE_REG_EDX)
1829 aPatch[off++] = 0x52; /* push edx */
1830 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1831 aPatch[off++] = 0x50; /* push eax */
1832
1833 aPatch[off++] = 0x31; /* xor edx, edx */
1834 aPatch[off++] = 0xD2;
1835
1836 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1837 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1838 off += sizeof(uint32_t);
1839
1840 aPatch[off++] = 0x0F; /* rdmsr */
1841 aPatch[off++] = 0x32;
1842
1843 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1844 {
1845 aPatch[off++] = 0x89; /* mov dst_reg, eax */
1846 aPatch[off++] = MAKE_MODRM(3, USE_REG_EAX, pDis->param1.base.reg_gen);
1847 }
1848
1849 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1850 aPatch[off++] = 0x58; /* pop eax */
1851 if (pDis->param1.base.reg_gen != USE_REG_EDX)
1852 aPatch[off++] = 0x5A; /* pop edx */
1853 if (pDis->param1.base.reg_gen != USE_REG_ECX)
1854 aPatch[off++] = 0x59; /* pop ecx */
1855 }
1856 aPatch[off++] = 0xE9; /* jmp return_address */
1857 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
1858 off += sizeof(RTRCUINTPTR);
1859
1860 if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
1861 {
1862 /* Write new code to the patch buffer. */
1863 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
1864 AssertRC(rc);
1865
1866#ifdef LOG_ENABLED
1867 pInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
1868 while (true)
1869 {
1870 uint32_t cb;
1871
1872 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pInstr, 0, szOutput, sizeof(szOutput), &cb);
1873 if (VBOX_SUCCESS(rc))
1874 Log(("Patch instr %s\n", szOutput));
1875
1876 pInstr += cb;
1877
1878 if (pInstr >= pVM->hwaccm.s.pFreeGuestPatchMem + off)
1879 break;
1880 }
1881#endif
1882
1883 pPatch->aNewOpcode[0] = 0xE9;
1884 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
1885
1886 /* Overwrite the TPR instruction with a jump. */
1887 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
1888 AssertRC(rc);
1889
1890#ifdef LOG_ENABLED
1891 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1892 if (VBOX_SUCCESS(rc))
1893 Log(("Jump: %s\n", szOutput));
1894#endif
1895 pVM->hwaccm.s.pFreeGuestPatchMem += off;
1896 pPatch->cbNewOp = 5;
1897
1898 pPatch->Core.Key = pCtx->eip;
1899 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1900 AssertRC(rc);
1901
1902 pVM->hwaccm.s.svm.cPatches++;
1903 pVM->hwaccm.s.svm.fTPRPatchingActive = true;
1904 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchSuccess);
1905 return VINF_SUCCESS;
1906 }
1907 else
1908 Log(("Ran out of space in our patch buffer!\n"));
1909 }
1910
1911 /* Save invalid patch, so we will not try again. */
1912 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1913
1914#ifdef LOG_ENABLED
1915 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1916 if (VBOX_SUCCESS(rc))
1917 Log(("Failed to patch instr: %s\n", szOutput));
1918#endif
1919
1920 pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1921 pPatch->Core.Key = pCtx->eip;
1922 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1923 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1924 AssertRC(rc);
1925 pVM->hwaccm.s.svm.cPatches++;
1926 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchFailure);
1927 return VINF_SUCCESS;
1928}
1929
1930/**
1931 * Attempt to patch TPR mmio instructions
1932 *
1933 * @returns VBox status code.
1934 * @param pVM The VM to operate on.
1935 * @param pVCpu The VM CPU to operate on.
1936 * @param pCtx CPU context
1937 */
1938VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1939{
1940 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, (pVM->hwaccm.s.pGuestPatchMem) ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr, (void *)pVCpu->idCpu);
1941 AssertRC(rc);
1942 return rc;
1943}
1944
1945/**
1946 * Force execution of the current IO code in the recompiler
1947 *
1948 * @returns VBox status code.
1949 * @param pVM The VM to operate on.
1950 * @param pCtx Partial VM execution context
1951 */
1952VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
1953{
1954 PVMCPU pVCpu = VMMGetCpu(pVM);
1955
1956 Assert(pVM->fHWACCMEnabled);
1957 Log(("HWACCMR3EmulateIoBlock\n"));
1958
1959 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
1960 if (HWACCMCanEmulateIoBlockEx(pCtx))
1961 {
1962 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
1963 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
1964 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
1965 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
1966 return VINF_EM_RESCHEDULE_REM;
1967 }
1968 return VINF_SUCCESS;
1969}
1970
1971/**
1972 * Checks if we can currently use hardware accelerated raw mode.
1973 *
1974 * @returns boolean
1975 * @param pVM The VM to operate on.
1976 * @param pCtx Partial VM execution context
1977 */
1978VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
1979{
1980 PVMCPU pVCpu = VMMGetCpu(pVM);
1981
1982 Assert(pVM->fHWACCMEnabled);
1983
1984 /* If we're still executing the IO code, then return false. */
1985 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
1986 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
1987 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
1988 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
1989 return false;
1990
1991 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
1992
1993 /* AMD-V supports real & protected mode with or without paging. */
1994 if (pVM->hwaccm.s.svm.fEnabled)
1995 {
1996 pVCpu->hwaccm.s.fActive = true;
1997 return true;
1998 }
1999
2000 pVCpu->hwaccm.s.fActive = false;
2001
2002 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2003#ifdef HWACCM_VMX_EMULATE_REALMODE
2004 if (pVM->hwaccm.s.vmx.pRealModeTSS)
2005 {
2006 if (CPUMIsGuestInRealModeEx(pCtx))
2007 {
2008 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
2009 * The base must also be equal to (sel << 4).
2010 */
2011 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
2012 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
2013 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
2014 || pCtx->es != (pCtx->esHid.u64Base >> 4)
2015 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
2016 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
2017 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
2018 {
2019 return false;
2020 }
2021 }
2022 else
2023 {
2024 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2025 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
2026 * from real to protected mode. (all sorts of RPL & DPL assumptions)
2027 */
2028 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2029 && enmGuestMode >= PGMMODE_PROTECTED)
2030 {
2031 if ( (pCtx->cs & X86_SEL_RPL)
2032 || (pCtx->ds & X86_SEL_RPL)
2033 || (pCtx->es & X86_SEL_RPL)
2034 || (pCtx->fs & X86_SEL_RPL)
2035 || (pCtx->gs & X86_SEL_RPL)
2036 || (pCtx->ss & X86_SEL_RPL))
2037 {
2038 return false;
2039 }
2040 }
2041 }
2042 }
2043 else
2044#endif /* HWACCM_VMX_EMULATE_REALMODE */
2045 {
2046 if (!CPUMIsGuestInLongModeEx(pCtx))
2047 {
2048 /** @todo This should (probably) be set on every excursion to the REM,
2049 * however it's too risky right now. So, only apply it when we go
2050 * back to REM for real mode execution. (The XP hack below doesn't
2051 * work reliably without this.)
2052 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2053 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2054
2055 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2056 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
2057 return false;
2058
2059 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2060 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2061 * hidden registers (possible recompiler bug; see load_seg_vm) */
2062 if (pCtx->csHid.Attr.n.u1Present == 0)
2063 return false;
2064 if (pCtx->ssHid.Attr.n.u1Present == 0)
2065 return false;
2066
2067 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2068 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2069 /** @todo This check is actually wrong, it doesn't take the direction of the
2070 * stack segment into account. But, it does the job for now. */
2071 if (pCtx->rsp >= pCtx->ssHid.u32Limit)
2072 return false;
2073#if 0
2074 if ( pCtx->cs >= pCtx->gdtr.cbGdt
2075 || pCtx->ss >= pCtx->gdtr.cbGdt
2076 || pCtx->ds >= pCtx->gdtr.cbGdt
2077 || pCtx->es >= pCtx->gdtr.cbGdt
2078 || pCtx->fs >= pCtx->gdtr.cbGdt
2079 || pCtx->gs >= pCtx->gdtr.cbGdt)
2080 return false;
2081#endif
2082 }
2083 }
2084
2085 if (pVM->hwaccm.s.vmx.fEnabled)
2086 {
2087 uint32_t mask;
2088
2089 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2090 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2091 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2092 mask &= ~X86_CR0_NE;
2093
2094#ifdef HWACCM_VMX_EMULATE_REALMODE
2095 if (pVM->hwaccm.s.vmx.pRealModeTSS)
2096 {
2097 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2098 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2099 }
2100 else
2101#endif
2102 {
2103 /* We support protected mode without paging using identity mapping. */
2104 mask &= ~X86_CR0_PG;
2105 }
2106 if ((pCtx->cr0 & mask) != mask)
2107 return false;
2108
2109 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2110 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2111 if ((pCtx->cr0 & mask) != 0)
2112 return false;
2113
2114 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2115 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2116 mask &= ~X86_CR4_VMXE;
2117 if ((pCtx->cr4 & mask) != mask)
2118 return false;
2119
2120 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2121 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2122 if ((pCtx->cr4 & mask) != 0)
2123 return false;
2124
2125 pVCpu->hwaccm.s.fActive = true;
2126 return true;
2127 }
2128
2129 return false;
2130}
2131
2132/**
2133 * Notifcation from EM about a rescheduling into hardware assisted execution
2134 * mode.
2135 *
2136 * @param pVCpu Pointer to the current virtual cpu structure.
2137 */
2138VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2139{
2140 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2141}
2142
2143/**
2144 * Notifcation from EM about returning from instruction emulation (REM / EM).
2145 *
2146 * @param pVCpu Pointer to the current virtual cpu structure.
2147 */
2148VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2149{
2150 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2151}
2152
2153/**
2154 * Checks if we are currently using hardware accelerated raw mode.
2155 *
2156 * @returns boolean
2157 * @param pVCpu The VMCPU to operate on.
2158 */
2159VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2160{
2161 return pVCpu->hwaccm.s.fActive;
2162}
2163
2164/**
2165 * Checks if we are currently using nested paging.
2166 *
2167 * @returns boolean
2168 * @param pVM The VM to operate on.
2169 */
2170VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2171{
2172 return pVM->hwaccm.s.fNestedPaging;
2173}
2174
2175/**
2176 * Checks if we are currently using VPID in VT-x mode.
2177 *
2178 * @returns boolean
2179 * @param pVM The VM to operate on.
2180 */
2181VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2182{
2183 return pVM->hwaccm.s.vmx.fVPID;
2184}
2185
2186
2187/**
2188 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2189 *
2190 * @returns boolean
2191 * @param pVM The VM to operate on.
2192 */
2193VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2194{
2195 return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2196}
2197
2198/**
2199 * Restart an I/O instruction that was refused in ring-0
2200 *
2201 * @returns VBox status code
2202 * @param pVM The VM to operate on.
2203 * @param pVCpu The VMCPU to operate on.
2204 * @param pCtx VCPU register context
2205 */
2206VMMR3DECL(int) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2207{
2208 HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2209 int rc;
2210
2211 pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2212
2213 if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2214 || enmType == HWACCMPENDINGIO_INVALID)
2215 return VERR_NOT_FOUND;
2216
2217 switch (enmType)
2218 {
2219 case HWACCMPENDINGIO_PORT_READ:
2220 {
2221 uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2222 uint32_t u32Val = 0;
2223
2224 rc = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2225 &u32Val,
2226 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2227 if (IOM_SUCCESS(rc))
2228 {
2229 /* Write back to the EAX register. */
2230 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2231 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2232 }
2233 break;
2234 }
2235
2236 case HWACCMPENDINGIO_PORT_WRITE:
2237 rc = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2238 pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2239 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2240 if (IOM_SUCCESS(rc))
2241 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2242 break;
2243
2244 default:
2245 AssertFailed();
2246 return VERR_INTERNAL_ERROR;
2247 }
2248
2249 return rc;
2250}
2251
2252/**
2253 * Inject an NMI into a running VM (only VCPU 0!)
2254 *
2255 * @returns boolean
2256 * @param pVM The VM to operate on.
2257 */
2258VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2259{
2260 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2261 return VINF_SUCCESS;
2262}
2263
2264/**
2265 * Check fatal VT-x/AMD-V error and produce some meaningful
2266 * log release message.
2267 *
2268 * @param pVM The VM to operate on.
2269 * @param iStatusCode VBox status code
2270 */
2271VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2272{
2273 for (unsigned i=0;i<pVM->cCPUs;i++)
2274 {
2275 switch(iStatusCode)
2276 {
2277 case VERR_VMX_INVALID_VMCS_FIELD:
2278 break;
2279
2280 case VERR_VMX_INVALID_VMCS_PTR:
2281 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
2282 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2283 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2284 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2285 break;
2286
2287 case VERR_VMX_UNABLE_TO_START_VM:
2288 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2289 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2290#if 0 /* @todo dump the current control fields to the release log */
2291 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2292 {
2293
2294 }
2295#endif
2296 break;
2297
2298 case VERR_VMX_UNABLE_TO_RESUME_VM:
2299 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2300 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2301 break;
2302
2303 case VERR_VMX_INVALID_VMXON_PTR:
2304 break;
2305 }
2306 }
2307}
2308
2309/**
2310 * Execute state save operation.
2311 *
2312 * @returns VBox status code.
2313 * @param pVM VM Handle.
2314 * @param pSSM SSM operation handle.
2315 */
2316static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2317{
2318 int rc;
2319
2320 Log(("hwaccmR3Save:\n"));
2321
2322 for (unsigned i=0;i<pVM->cCPUs;i++)
2323 {
2324 /*
2325 * Save the basic bits - fortunately all the other things can be resynced on load.
2326 */
2327 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2328 AssertRCReturn(rc, rc);
2329 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2330 AssertRCReturn(rc, rc);
2331 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2332 AssertRCReturn(rc, rc);
2333
2334 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2335 AssertRCReturn(rc, rc);
2336 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2337 AssertRCReturn(rc, rc);
2338 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2339 AssertRCReturn(rc, rc);
2340 }
2341#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2342 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2343 AssertRCReturn(rc, rc);
2344 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2345 AssertRCReturn(rc, rc);
2346 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2347 AssertRCReturn(rc, rc);
2348
2349 /* Store all the guest patch records too. */
2350 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.svm.cPatches);
2351 AssertRCReturn(rc, rc);
2352
2353 for (unsigned i = 0; i < pVM->hwaccm.s.svm.cPatches; i++)
2354 {
2355 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[i];
2356
2357 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2358 AssertRCReturn(rc, rc);
2359
2360 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2361 AssertRCReturn(rc, rc);
2362
2363 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2364 AssertRCReturn(rc, rc);
2365
2366 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2367 AssertRCReturn(rc, rc);
2368
2369 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2370 AssertRCReturn(rc, rc);
2371
2372 AssertCompileSize(HWACCMTPRINSTR, 4);
2373 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2374 AssertRCReturn(rc, rc);
2375
2376 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2377 AssertRCReturn(rc, rc);
2378
2379 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2380 AssertRCReturn(rc, rc);
2381
2382 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2383 AssertRCReturn(rc, rc);
2384
2385 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2386 AssertRCReturn(rc, rc);
2387 }
2388#endif
2389 return VINF_SUCCESS;
2390}
2391
2392/**
2393 * Execute state load operation.
2394 *
2395 * @returns VBox status code.
2396 * @param pVM VM Handle.
2397 * @param pSSM SSM operation handle.
2398 * @param u32Version Data layout version.
2399 */
2400static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2401{
2402 int rc;
2403
2404 Log(("hwaccmR3Load:\n"));
2405
2406 /*
2407 * Validate version.
2408 */
2409 if ( u32Version != HWACCM_SSM_VERSION
2410 && u32Version != HWACCM_SSM_VERSION_NO_PATCHING
2411 && u32Version != HWACCM_SSM_VERSION_2_0_X)
2412 {
2413 AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
2414 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2415 }
2416 for (unsigned i=0;i<pVM->cCPUs;i++)
2417 {
2418 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2419 AssertRCReturn(rc, rc);
2420 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2421 AssertRCReturn(rc, rc);
2422 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2423 AssertRCReturn(rc, rc);
2424
2425 if (u32Version >= HWACCM_SSM_VERSION_NO_PATCHING)
2426 {
2427 uint32_t val;
2428
2429 rc = SSMR3GetU32(pSSM, &val);
2430 AssertRCReturn(rc, rc);
2431 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2432
2433 rc = SSMR3GetU32(pSSM, &val);
2434 AssertRCReturn(rc, rc);
2435 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2436
2437 rc = SSMR3GetU32(pSSM, &val);
2438 AssertRCReturn(rc, rc);
2439 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2440 }
2441 }
2442#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2443 if (u32Version > HWACCM_SSM_VERSION_NO_PATCHING)
2444 {
2445 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2446 AssertRCReturn(rc, rc);
2447 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2448 AssertRCReturn(rc, rc);
2449 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2450 AssertRCReturn(rc, rc);
2451
2452 /* Fetch all TPR patch records. */
2453 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.svm.cPatches);
2454 AssertRCReturn(rc, rc);
2455
2456 for (unsigned i = 0; i < pVM->hwaccm.s.svm.cPatches; i++)
2457 {
2458 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[i];
2459
2460 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2461 AssertRCReturn(rc, rc);
2462
2463 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2464 AssertRCReturn(rc, rc);
2465
2466 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2467 AssertRCReturn(rc, rc);
2468
2469 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2470 AssertRCReturn(rc, rc);
2471
2472 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2473 AssertRCReturn(rc, rc);
2474
2475 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2476 AssertRCReturn(rc, rc);
2477
2478 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2479 AssertRCReturn(rc, rc);
2480
2481 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2482 AssertRCReturn(rc, rc);
2483
2484 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2485 AssertRCReturn(rc, rc);
2486
2487 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2488 AssertRCReturn(rc, rc);
2489
2490 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
2491 AssertRC(rc);
2492 }
2493 }
2494#endif
2495 return VINF_SUCCESS;
2496}
2497
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