VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 22244

Last change on this file since 22244 was 22242, checked in by vboxsync, 15 years ago

Made TSC underflow checking more generic.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 118.1 KB
Line 
1/* $Id: HWACCM.cpp 22242 2009-08-13 15:38:35Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/csam.h>
35#include <VBox/selm.h>
36#include <VBox/rem.h>
37#include <VBox/hwacc_vmx.h>
38#include <VBox/hwacc_svm.h>
39#include "HWACCMInternal.h"
40#include <VBox/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/string.h>
48#include <iprt/thread.h>
49
50/*******************************************************************************
51* Global Variables *
52*******************************************************************************/
53#ifdef VBOX_WITH_STATISTICS
54# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55# define EXIT_REASON_NIL() NULL
56/** Exit reason descriptions for VT-x, used to describe statistics. */
57static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58{
59 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67 EXIT_REASON_NIL(),
68 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94 EXIT_REASON_NIL(),
95 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96 EXIT_REASON_NIL(),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101 EXIT_REASON_NIL(),
102 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110 EXIT_REASON_NIL(),
111 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115 EXIT_REASON_NIL()
116};
117/** Exit reason descriptions for AMD-V, used to describe statistics. */
118static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119{
120 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
121 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
122 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
123 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
124 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
125 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
126 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
127 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
128 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
129 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
130 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
131 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
132 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
133 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
134 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
135 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
136 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
137 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
152 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
153 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
154 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
155 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
156 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
157 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
158 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
159 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
160 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
161 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
162 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
163 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
164 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
165 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
166 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
167 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
168 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
169 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
184 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
185 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_INTR , 96, "Physical maskable interrupt."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_NMI , 97, "Physical non-maskable interrupt."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_SMI , 98, "System management interrupt."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_INIT , 99, "Physical INIT signal."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_VINTR ,100, "Visual interrupt."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_IDTR_READ ,102, "Read IDTR"),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_GDTR_READ ,103, "Read GDTR"),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_LDTR_READ ,104, "Read LDTR."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,105, "Read TR."),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,106, "Write IDTR."),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,107, "Write GDTR."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,108, "Write LDTR."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,109, "Write TR."),
230 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
231 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
232 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
233 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
234 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
235 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
236 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
237 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
238 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
239 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
240 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
241 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
242 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
243 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
244 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
245 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
246 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
247 EXIT_REASON(SVM_EXIT_TASK_SHUTDOWN ,127, "Shutdown."),
248 EXIT_REASON(SVM_EXIT_TASK_VMRUN ,128, "VMRUN instruction."),
249 EXIT_REASON(SVM_EXIT_TASK_VMCALL ,129, "VMCALL instruction."),
250 EXIT_REASON(SVM_EXIT_TASK_VMLOAD ,130, "VMLOAD instruction."),
251 EXIT_REASON(SVM_EXIT_TASK_VMSAVE ,131, "VMSAVE instruction."),
252 EXIT_REASON(SVM_EXIT_TASK_STGI ,132, "STGI instruction."),
253 EXIT_REASON(SVM_EXIT_TASK_CLGI ,133, "CLGI instruction."),
254 EXIT_REASON(SVM_EXIT_TASK_SKINIT ,134, "SKINIT instruction."),
255 EXIT_REASON(SVM_EXIT_TASK_RDTSCP ,135, "RDTSCP instruction."),
256 EXIT_REASON(SVM_EXIT_TASK_ICEBP ,136, "ICEBP instruction."),
257 EXIT_REASON(SVM_EXIT_TASK_WBINVD ,137, "WBINVD instruction."),
258 EXIT_REASON(SVM_EXIT_TASK_MONITOR ,138, "MONITOR instruction."),
259 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
260 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
261 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
262 EXIT_REASON_NIL()
263};
264# undef EXIT_REASON
265# undef EXIT_REASON_NIL
266#endif /* VBOX_WITH_STATISTICS */
267
268/*******************************************************************************
269* Internal Functions *
270*******************************************************************************/
271static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
272static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
273
274
275/**
276 * Initializes the HWACCM.
277 *
278 * @returns VBox status code.
279 * @param pVM The VM to operate on.
280 */
281VMMR3DECL(int) HWACCMR3Init(PVM pVM)
282{
283 LogFlow(("HWACCMR3Init\n"));
284
285 /*
286 * Assert alignment and sizes.
287 */
288 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
289 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
290
291 /* Some structure checks. */
292 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
293 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
294 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
295 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
296
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
300 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
303 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
304
305
306 /*
307 * Register the saved state data unit.
308 */
309 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
310 NULL, hwaccmR3Save, NULL,
311 NULL, hwaccmR3Load, NULL);
312 if (RT_FAILURE(rc))
313 return rc;
314
315 /* Misc initialisation. */
316 pVM->hwaccm.s.vmx.fSupported = false;
317 pVM->hwaccm.s.svm.fSupported = false;
318 pVM->hwaccm.s.vmx.fEnabled = false;
319 pVM->hwaccm.s.svm.fEnabled = false;
320
321 pVM->hwaccm.s.fNestedPaging = false;
322
323 /* Disabled by default. */
324 pVM->fHWACCMEnabled = false;
325
326 /*
327 * Check CFGM options.
328 */
329 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
330 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
331 /* Nested paging: disabled by default. */
332 rc = CFGMR3QueryBoolDef(pRoot, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
333 AssertRC(rc);
334
335 /* VT-x VPID: disabled by default. */
336 rc = CFGMR3QueryBoolDef(pRoot, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
337 AssertRC(rc);
338
339 /* HWACCM support must be explicitely enabled in the configuration file. */
340 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
341 AssertRC(rc);
342
343#ifdef RT_OS_DARWIN
344 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
345#else
346 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
347#endif
348 {
349 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
350 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
351 return VERR_HWACCM_CONFIG_MISMATCH;
352 }
353
354 if (VMMIsHwVirtExtForced(pVM))
355 pVM->fHWACCMEnabled = true;
356
357#if HC_ARCH_BITS == 32
358 /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
359 * (To use the default, don't set 64bitEnabled in CFGM.) */
360 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
361 AssertLogRelRCReturn(rc, rc);
362 if (pVM->hwaccm.s.fAllow64BitGuests)
363 {
364# ifdef RT_OS_DARWIN
365 if (!VMMIsHwVirtExtForced(pVM))
366# else
367 if (!pVM->hwaccm.s.fAllowed)
368# endif
369 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
370 }
371#else
372 /* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
373 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
374 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
375 AssertLogRelRCReturn(rc, rc);
376#endif
377
378 /* Max number of resume loops. */
379 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
380 AssertRC(rc);
381
382 return VINF_SUCCESS;
383}
384
385/**
386 * Initializes the per-VCPU HWACCM.
387 *
388 * @returns VBox status code.
389 * @param pVM The VM to operate on.
390 */
391VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
392{
393 LogFlow(("HWACCMR3InitCPU\n"));
394
395 for (unsigned i=0;i<pVM->cCPUs;i++)
396 {
397 PVMCPU pVCpu = &pVM->aCpus[i];
398
399 pVCpu->hwaccm.s.fActive = false;
400 }
401
402#ifdef VBOX_WITH_STATISTICS
403 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
404 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
405 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
406 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
407
408 /*
409 * Statistics.
410 */
411 for (unsigned i=0;i<pVM->cCPUs;i++)
412 {
413 PVMCPU pVCpu = &pVM->aCpus[i];
414 int rc;
415
416 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
417 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
418 AssertRC(rc);
419 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
420 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
421 AssertRC(rc);
422 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
423 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
424 AssertRC(rc);
425# if 1 /* temporary for tracking down darwin holdup. */
426 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
427 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
428 AssertRC(rc);
429 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
430 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
431 AssertRC(rc);
432 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
433 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
434 AssertRC(rc);
435# endif
436 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
437 "/PROF/HWACCM/CPU%d/InGC", i);
438 AssertRC(rc);
439
440# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
441 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
442 "/PROF/HWACCM/CPU%d/Switcher3264", i);
443 AssertRC(rc);
444# endif
445
446# define HWACCM_REG_COUNTER(a, b) \
447 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
448 AssertRC(rc);
449
450 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
451 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
452 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
453 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
454 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
455 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
456 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
457 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
458 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
459 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
460 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
461 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
462 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
463 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
464 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
465 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
466 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
467 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
468 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
469 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
470 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
471 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
472 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
473 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
474 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
475 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
476 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
477 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
478 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
479 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
480 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
481 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
482 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
483 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
484 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
485 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
486 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
487
488 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
489 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
490
491 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
492 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
493 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
494
495 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
496 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
498 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
499 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
503 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
504 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
505 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
506
507 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
508 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
509 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow, "/HWACCM/CPU%d/TSC/InterceptOverflow");
510
511 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
512 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
513 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
514
515 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
516 {
517 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
518 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
519 AssertRC(rc);
520 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
521 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
522 AssertRC(rc);
523 }
524
525#undef HWACCM_REG_COUNTER
526
527 pVCpu->hwaccm.s.paStatExitReason = NULL;
528
529 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
530 AssertRC(rc);
531 if (RT_SUCCESS(rc))
532 {
533 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
534 for (int j=0;j<MAX_EXITREASON_STAT;j++)
535 {
536 if (papszDesc[j])
537 {
538 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
539 papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
540 AssertRC(rc);
541 }
542 }
543 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
544 AssertRC(rc);
545 }
546 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
547# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
548 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
549# else
550 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
551# endif
552
553 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
554 AssertRCReturn(rc, rc);
555 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
556# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
557 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
558# else
559 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
560# endif
561 for (unsigned j = 0; j < 255; j++)
562 STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
563 (j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
564
565 }
566#endif /* VBOX_WITH_STATISTICS */
567
568#ifdef VBOX_WITH_CRASHDUMP_MAGIC
569 /* Magic marker for searching in crash dumps. */
570 for (unsigned i=0;i<pVM->cCPUs;i++)
571 {
572 PVMCPU pVCpu = &pVM->aCpus[i];
573
574 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
575 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
576 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
577 }
578#endif
579 return VINF_SUCCESS;
580}
581
582/**
583 * Turns off normal raw mode features
584 *
585 * @param pVM The VM to operate on.
586 */
587static void hwaccmR3DisableRawMode(PVM pVM)
588{
589 /* Disable PATM & CSAM. */
590 PATMR3AllowPatching(pVM, false);
591 CSAMDisableScanning(pVM);
592
593 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
594 SELMR3DisableMonitoring(pVM);
595 TRPMR3DisableMonitoring(pVM);
596
597 /* Disable the switcher code (safety precaution). */
598 VMMR3DisableSwitcher(pVM);
599
600 /* Disable mapping of the hypervisor into the shadow page table. */
601 PGMR3MappingsDisable(pVM);
602
603 /* Disable the switcher */
604 VMMR3DisableSwitcher(pVM);
605
606 /* Reinit the paging mode to force the new shadow mode. */
607 for (unsigned i=0;i<pVM->cCPUs;i++)
608 {
609 PVMCPU pVCpu = &pVM->aCpus[i];
610
611 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
612 }
613}
614
615/**
616 * Initialize VT-x or AMD-V.
617 *
618 * @returns VBox status code.
619 * @param pVM The VM handle.
620 */
621VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
622{
623 int rc;
624
625 if ( !pVM->hwaccm.s.vmx.fSupported
626 && !pVM->hwaccm.s.svm.fSupported)
627 {
628 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
629 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
630 if (VMMIsHwVirtExtForced(pVM))
631 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
632 return VINF_SUCCESS;
633 }
634
635 if (!pVM->hwaccm.s.fAllowed)
636 return VINF_SUCCESS; /* nothing to do */
637
638 /* Enable VT-x or AMD-V on all host CPUs. */
639 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
640 if (RT_FAILURE(rc))
641 {
642 LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
643 return rc;
644 }
645 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
646
647 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
648
649 if (pVM->hwaccm.s.vmx.fSupported)
650 {
651 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
652
653 if ( pVM->hwaccm.s.fInitialized == false
654 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
655 {
656 uint64_t val;
657 RTGCPHYS GCPhys = 0;
658
659 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
660 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
661 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
662 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
663 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
664 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
665 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
666 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
667
668 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
669 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
670 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
671 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
672 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
673 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
674 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
675 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
676 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
677 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
678 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
679 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
680 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
681 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
682 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
683 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
684 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
685 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
686 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
687
688 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
689 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
690 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
691 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
692 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
693 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
694 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
695 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
696 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
697 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
698 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
699 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
700 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
701 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
702 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
703 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
704 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
705 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
706 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
707 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
708 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
709 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
710 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
711 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
712 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
713 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
714 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
715 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
716 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
717 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
718 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
719 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
720 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
721 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
722 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
723 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
724 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
725 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
726 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
727 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
728 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
729 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
730 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
731 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
732
733 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
734 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
735 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
736 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
737 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
738 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
739 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
740 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
741 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
742 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
743 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
744 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
745 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
746 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
747 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
748 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
749 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
750 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
751 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
752 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
753 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
754 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
755 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
756 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
757 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
758 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
759 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
760 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
761 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
762 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
763 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
764 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
765 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
766 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
767 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
768 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
769 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
770 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
771 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
772 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
773 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
774 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
775 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
776
777 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
778 {
779 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
780 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
781 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
782 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
783 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
784 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
785 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
786 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
787 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
788 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
789 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
790 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
791 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
792 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
793
794 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
795 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
796 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
797 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
798 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
799 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
800 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
801 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
802 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
803 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
804 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
805 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
806 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
807 }
808
809 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
810 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
811 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
812 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
813 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
814 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
815 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
816 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
817 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
818 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
819 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
820 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
821 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
822 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
823 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
824 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
825 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
826 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
827 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
828 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
829 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
830 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
831 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
832 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
833 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
834 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
835 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
836 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
837 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
838 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
839 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
840
841 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
842 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
843 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
844 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
845 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
846 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
847 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
848 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
849 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
850 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
851 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
852 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
853 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
854 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
855 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
856 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
857 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
858 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
859 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
860 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
861 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
862 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
863 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
864 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
865 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
866 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
867 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
868 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
869 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
870 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
871 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
872 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
873 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
874 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
875 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
876
877 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
878 {
879 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
880
881 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
882 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
883 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
884 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
885 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
886 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
887 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
888 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
889 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
890 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
891 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
892 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
893 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
894 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
895 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
896 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
897 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
898 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
899 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
900 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
901 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
902 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
903 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
904 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
905 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
906 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
907 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
908 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
909 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
910 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
911 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
912 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
913 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
914 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
915 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
916 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
917 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
918 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
919 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
920 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
921 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
922 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
923 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
924 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
925 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
926 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
927 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
928 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
929 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
930 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
931 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
932 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
933 }
934
935 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
936 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
937 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
938 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
939 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
940 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
941
942 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
943 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
944 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
945 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
946 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
947
948 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
949
950 /* Paranoia */
951 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc) >= 512);
952
953 for (unsigned i=0;i<pVM->cCPUs;i++)
954 {
955 LogRel(("HWACCM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pMSRBitmapPhys));
956 LogRel(("HWACCM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
957 }
958
959#ifdef HWACCM_VTX_WITH_EPT
960 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
961 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
962#endif /* HWACCM_VTX_WITH_EPT */
963#ifdef HWACCM_VTX_WITH_VPID
964 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
965 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
966 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
967#endif /* HWACCM_VTX_WITH_VPID */
968
969 /* Only try once. */
970 pVM->hwaccm.s.fInitialized = true;
971
972 /* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
973#if 1
974 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
975#else
976 rc = VERR_NO_MEMORY; /* simulation of no VMMDev Heap. */
977#endif
978 if (RT_SUCCESS(rc))
979 {
980 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
981 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
982 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
983 /* Bit set to 0 means redirection enabled. */
984 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
985 /* Allow all port IO, so the VT-x IO intercepts do their job. */
986 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
987 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
988
989 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
990 * real and protected mode without paging with EPT.
991 */
992 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
993 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
994 {
995 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
996 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
997 }
998
999 /* We convert it here every time as pci regions could be reconfigured. */
1000 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1001 AssertRC(rc);
1002 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1003
1004 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1005 AssertRC(rc);
1006 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1007 }
1008 else
1009 {
1010 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1011 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1012 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1013 }
1014
1015 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1016 AssertRC(rc);
1017 if (rc == VINF_SUCCESS)
1018 {
1019 pVM->fHWACCMEnabled = true;
1020 pVM->hwaccm.s.vmx.fEnabled = true;
1021 hwaccmR3DisableRawMode(pVM);
1022
1023 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1024#ifdef VBOX_ENABLE_64_BITS_GUESTS
1025 if (pVM->hwaccm.s.fAllow64BitGuests)
1026 {
1027 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1028 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1029 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1030 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1031 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1032 }
1033 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1034 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1035 : "HWACCM: 32-bit guests supported.\n"));
1036#else
1037 LogRel(("HWACCM: 32-bit guests supported.\n"));
1038#endif
1039 LogRel(("HWACCM: VMX enabled!\n"));
1040 if (pVM->hwaccm.s.fNestedPaging)
1041 {
1042 LogRel(("HWACCM: Enabled nested paging\n"));
1043 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1044 }
1045 if (pVM->hwaccm.s.vmx.fVPID)
1046 LogRel(("HWACCM: Enabled VPID\n"));
1047
1048 if ( pVM->hwaccm.s.fNestedPaging
1049 || pVM->hwaccm.s.vmx.fVPID)
1050 {
1051 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1052 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1053 }
1054 }
1055 else
1056 {
1057 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1058 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1059 pVM->fHWACCMEnabled = false;
1060 }
1061 }
1062 }
1063 else
1064 if (pVM->hwaccm.s.svm.fSupported)
1065 {
1066 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1067
1068 if (pVM->hwaccm.s.fInitialized == false)
1069 {
1070 /* Erratum 170 which requires a forced TLB flush for each world switch:
1071 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1072 *
1073 * All BH-G1/2 and DH-G1/2 models include a fix:
1074 * Athlon X2: 0x6b 1/2
1075 * 0x68 1/2
1076 * Athlon 64: 0x7f 1
1077 * 0x6f 2
1078 * Sempron: 0x7f 1/2
1079 * 0x6f 2
1080 * 0x6c 2
1081 * 0x7c 2
1082 * Turion 64: 0x68 2
1083 *
1084 */
1085 uint32_t u32Dummy;
1086 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1087 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1088 u32BaseFamily= (u32Version >> 8) & 0xf;
1089 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1090 u32Model = ((u32Version >> 4) & 0xf);
1091 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1092 u32Stepping = u32Version & 0xf;
1093 if ( u32Family == 0xf
1094 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1095 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1096 {
1097 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1098 }
1099
1100 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1101 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1102 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1103 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1104 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1105
1106 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1107 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
1108 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
1109 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
1110 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
1111 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
1112 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
1113 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
1114 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
1115 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
1116
1117 /* Only try once. */
1118 pVM->hwaccm.s.fInitialized = true;
1119
1120 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1121 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1122
1123 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1124 AssertRC(rc);
1125 if (rc == VINF_SUCCESS)
1126 {
1127 pVM->fHWACCMEnabled = true;
1128 pVM->hwaccm.s.svm.fEnabled = true;
1129
1130 if (pVM->hwaccm.s.fNestedPaging)
1131 LogRel(("HWACCM: Enabled nested paging\n"));
1132
1133 hwaccmR3DisableRawMode(pVM);
1134 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1135 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1136 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1137#ifdef VBOX_ENABLE_64_BITS_GUESTS
1138 if (pVM->hwaccm.s.fAllow64BitGuests)
1139 {
1140 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1141 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1142 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1143 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1144 }
1145#endif
1146 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1147 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1148 : "HWACCM: 32-bit guest supported.\n"));
1149 }
1150 else
1151 {
1152 pVM->fHWACCMEnabled = false;
1153 }
1154 }
1155 }
1156 return VINF_SUCCESS;
1157}
1158
1159/**
1160 * Applies relocations to data and code managed by this
1161 * component. This function will be called at init and
1162 * whenever the VMM need to relocate it self inside the GC.
1163 *
1164 * @param pVM The VM.
1165 */
1166VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1167{
1168 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1169
1170 /* Fetch the current paging mode during the relocate callback during state loading. */
1171 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1172 {
1173 for (unsigned i=0;i<pVM->cCPUs;i++)
1174 {
1175 PVMCPU pVCpu = &pVM->aCpus[i];
1176
1177 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1178 Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1179 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1180 }
1181 }
1182#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1183 if (pVM->fHWACCMEnabled)
1184 {
1185 int rc;
1186
1187 switch(PGMGetHostMode(pVM))
1188 {
1189 case PGMMODE_32_BIT:
1190 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1191 break;
1192
1193 case PGMMODE_PAE:
1194 case PGMMODE_PAE_NX:
1195 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1196 break;
1197
1198 default:
1199 AssertFailed();
1200 break;
1201 }
1202 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1203 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1204
1205 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1206 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1207
1208 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1209 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1210
1211 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1212 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1213
1214# ifdef DEBUG
1215 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1216 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1217# endif
1218 }
1219#endif
1220 return;
1221}
1222
1223/**
1224 * Checks hardware accelerated raw mode is allowed.
1225 *
1226 * @returns boolean
1227 * @param pVM The VM to operate on.
1228 */
1229VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1230{
1231 return pVM->hwaccm.s.fAllowed;
1232}
1233
1234/**
1235 * Notification callback which is called whenever there is a chance that a CR3
1236 * value might have changed.
1237 *
1238 * This is called by PGM.
1239 *
1240 * @param pVM The VM to operate on.
1241 * @param pVCpu The VMCPU to operate on.
1242 * @param enmShadowMode New shadow paging mode.
1243 * @param enmGuestMode New guest paging mode.
1244 */
1245VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1246{
1247 /* Ignore page mode changes during state loading. */
1248 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1249 return;
1250
1251 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1252
1253 if ( pVM->hwaccm.s.vmx.fEnabled
1254 && pVM->fHWACCMEnabled)
1255 {
1256 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1257 && enmGuestMode >= PGMMODE_PROTECTED)
1258 {
1259 PCPUMCTX pCtx;
1260
1261 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1262
1263 /* After a real mode switch to protected mode we must force
1264 * CPL to 0. Our real mode emulation had to set it to 3.
1265 */
1266 pCtx->ssHid.Attr.n.u2Dpl = 0;
1267 }
1268 }
1269
1270 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1271 {
1272 /* Keep track of paging mode changes. */
1273 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1274 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1275
1276 /* Did we miss a change, because all code was executed in the recompiler? */
1277 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1278 {
1279 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1280 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1281 }
1282 }
1283
1284 /* Reset the contents of the read cache. */
1285 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1286 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1287 pCache->Read.aFieldVal[j] = 0;
1288}
1289
1290/**
1291 * Terminates the HWACCM.
1292 *
1293 * Termination means cleaning up and freeing all resources,
1294 * the VM it self is at this point powered off or suspended.
1295 *
1296 * @returns VBox status code.
1297 * @param pVM The VM to operate on.
1298 */
1299VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1300{
1301 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1302 {
1303 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1304 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1305 }
1306 HWACCMR3TermCPU(pVM);
1307 return 0;
1308}
1309
1310/**
1311 * Terminates the per-VCPU HWACCM.
1312 *
1313 * Termination means cleaning up and freeing all resources,
1314 * the VM it self is at this point powered off or suspended.
1315 *
1316 * @returns VBox status code.
1317 * @param pVM The VM to operate on.
1318 */
1319VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1320{
1321 for (unsigned i=0;i<pVM->cCPUs;i++)
1322 {
1323 PVMCPU pVCpu = &pVM->aCpus[i];
1324
1325#ifdef VBOX_WITH_STATISTICS
1326 if (pVCpu->hwaccm.s.paStatExitReason)
1327 {
1328 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1329 pVCpu->hwaccm.s.paStatExitReason = NULL;
1330 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1331 }
1332 if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1333 {
1334 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1335 pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1336 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1337 }
1338#endif
1339
1340#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1341 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1342 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1343 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1344#endif
1345 }
1346 return 0;
1347}
1348
1349/**
1350 * The VM is being reset.
1351 *
1352 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1353 * needs to be removed.
1354 *
1355 * @param pVM VM handle.
1356 */
1357VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1358{
1359 LogFlow(("HWACCMR3Reset:\n"));
1360
1361 if (pVM->fHWACCMEnabled)
1362 hwaccmR3DisableRawMode(pVM);
1363
1364 for (unsigned i=0;i<pVM->cCPUs;i++)
1365 {
1366 PVMCPU pVCpu = &pVM->aCpus[i];
1367
1368 /* On first entry we'll sync everything. */
1369 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1370
1371 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1372 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1373
1374 pVCpu->hwaccm.s.fActive = false;
1375 pVCpu->hwaccm.s.Event.fPending = false;
1376
1377 /* Reset state information for real-mode emulation in VT-x. */
1378 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1379 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1380 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1381
1382 /* Reset the contents of the read cache. */
1383 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1384 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1385 pCache->Read.aFieldVal[j] = 0;
1386
1387#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1388 /* Magic marker for searching in crash dumps. */
1389 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1390 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1391#endif
1392 }
1393
1394 /* Clear all patch information. */
1395 pVM->hwaccm.s.pGuestPatchMem = 0;
1396 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1397 pVM->hwaccm.s.cbGuestPatchMem = 0;
1398 pVM->hwaccm.s.svm.cPatches = 0;
1399 pVM->hwaccm.s.svm.PatchTree = 0;
1400 pVM->hwaccm.s.svm.fTPRPatchingActive = false;
1401 ASMMemZero32(pVM->hwaccm.s.svm.aPatches, sizeof(pVM->hwaccm.s.svm.aPatches));
1402}
1403
1404/**
1405 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1406 *
1407 * @returns VBox status code.
1408 * @param pVM The VM handle.
1409 * @param pVCpu The VMCPU for the EMT we're being called on.
1410 * @param pvUser Unused
1411 *
1412 */
1413DECLCALLBACK(int) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1414{
1415 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1416
1417 /* Only execute the handler on the VCPU the original patch request was issued. */
1418 if (pVCpu->idCpu != idCpu)
1419 return VINF_SUCCESS;
1420
1421 Log(("hwaccmR3RemovePatches\n"));
1422 for (unsigned i = 0; i < pVM->hwaccm.s.svm.cPatches; i++)
1423 {
1424 uint8_t szInstr[15];
1425 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[i];
1426 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1427 int rc;
1428
1429#ifdef LOG_ENABLED
1430 char szOutput[256];
1431
1432 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1433 if (VBOX_SUCCESS(rc))
1434 Log(("Patched instr: %s\n", szOutput));
1435#endif
1436
1437 /* Check if the instruction is still the same. */
1438 rc = PGMPhysSimpleReadGCPtr(pVCpu, szInstr, pInstrGC, pPatch->cbNewOp);
1439 if (rc != VINF_SUCCESS)
1440 {
1441 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1442 continue; /* swapped out or otherwise removed; skip it. */
1443 }
1444
1445 if (memcmp(szInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1446 {
1447 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1448 continue; /* skip it. */
1449 }
1450
1451 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1452 AssertRC(rc);
1453
1454#ifdef LOG_ENABLED
1455 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1456 if (VBOX_SUCCESS(rc))
1457 Log(("Original instr: %s\n", szOutput));
1458#endif
1459 }
1460 pVM->hwaccm.s.svm.cPatches = 0;
1461 pVM->hwaccm.s.svm.PatchTree = 0;
1462 pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1463 pVM->hwaccm.s.svm.fTPRPatchingActive = false;
1464 return VINF_SUCCESS;
1465}
1466
1467/**
1468 * Enable patching in a VT-x/AMD-V guest
1469 *
1470 * @returns VBox status code.
1471 * @param pVM The VM to operate on.
1472 * @param idCpu VCPU to execute hwaccmR3RemovePatches on
1473 * @param pPatchMem Patch memory range
1474 * @param cbPatchMem Size of the memory range
1475 */
1476int hwaccmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1477{
1478 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)idCpu);
1479 AssertRC(rc);
1480
1481 pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1482 pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1483 pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1484 return VINF_SUCCESS;
1485}
1486
1487/**
1488 * Enable patching in a VT-x/AMD-V guest
1489 *
1490 * @returns VBox status code.
1491 * @param pVM The VM to operate on.
1492 * @param pPatchMem Patch memory range
1493 * @param cbPatchMem Size of the memory range
1494 */
1495VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1496{
1497 Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1498
1499 /* Current TPR patching only applies to AMD cpus.
1500 * Needs to be extended to Intel CPUs without the APIC TPR hardware optimization.
1501 */
1502 if (CPUMGetCPUVendor(pVM) != CPUMCPUVENDOR_AMD)
1503 return VERR_NOT_SUPPORTED;
1504
1505 if (pVM->cCPUs > 1)
1506 {
1507 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1508 PVMREQ pReq;
1509 int rc = VMR3ReqCallU(pVM->pUVM, VMCPUID_ANY_QUEUE, &pReq, 0, VMREQFLAGS_NO_WAIT,
1510 (PFNRT)hwaccmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1511 AssertRC(rc);
1512 return rc;
1513 }
1514 else
1515 return hwaccmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1516}
1517
1518/**
1519 * Disable patching in a VT-x/AMD-V guest
1520 *
1521 * @returns VBox status code.
1522 * @param pVM The VM to operate on.
1523 * @param pPatchMem Patch memory range
1524 * @param cbPatchMem Size of the memory range
1525 */
1526VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1527{
1528 Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1529
1530 Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1531 Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1532
1533 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1534 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)VMMGetCpuId(pVM));
1535 AssertRC(rc);
1536
1537 pVM->hwaccm.s.pGuestPatchMem = 0;
1538 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1539 pVM->hwaccm.s.cbGuestPatchMem = 0;
1540 pVM->hwaccm.s.svm.fTPRPatchingActive = false;
1541 return VINF_SUCCESS;
1542}
1543
1544
1545/**
1546 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1547 *
1548 * @returns VBox status code.
1549 * @param pVM The VM handle.
1550 * @param pVCpu The VMCPU for the EMT we're being called on.
1551 * @param pvUser User specified CPU context
1552 *
1553 */
1554DECLCALLBACK(int) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1555{
1556 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1557 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1558 RTGCPTR oldrip = pCtx->rip;
1559 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1560 unsigned cbOp;
1561
1562 /* Only execute the handler on the VCPU the original patch request was issued. */
1563 if (pVCpu->idCpu != idCpu)
1564 return VINF_SUCCESS;
1565
1566 Log(("hwaccmR3ReplaceTprInstr: %RGv\n", pCtx->rip));
1567
1568 /* Two or more VCPUs were racing to patch this instruction. */
1569 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.svm.PatchTree, (AVLOU32KEY)pCtx->eip);
1570 if (pPatch)
1571 return VINF_SUCCESS;
1572
1573 Assert(pVM->hwaccm.s.svm.cPatches < RT_ELEMENTS(pVM->hwaccm.s.svm.aPatches));
1574
1575 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1576 AssertRC(rc);
1577 if ( rc == VINF_SUCCESS
1578 && pDis->pCurInstr->opcode == OP_MOV
1579 && cbOp >= 3)
1580 {
1581 uint8_t aVMMCall[3] = { 0xf, 0x1, 0xd9};
1582 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1583 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1584
1585 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1586 AssertRC(rc);
1587
1588 pPatch->cbOp = cbOp;
1589
1590 if (pDis->param1.flags == USE_DISPLACEMENT32)
1591 {
1592 /* write. */
1593 if (pDis->param2.flags == USE_REG_GEN32)
1594 {
1595 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1596 pPatch->uSrcOperand = pDis->param2.base.reg_gen;
1597 }
1598 else
1599 {
1600 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1601 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1602 pPatch->uSrcOperand = pDis->param2.parval;
1603 }
1604 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1605 AssertRC(rc);
1606
1607 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1608 pPatch->cbNewOp = sizeof(aVMMCall);
1609 }
1610 else
1611 {
1612 RTGCPTR oldrip = pCtx->rip;
1613 uint32_t oldcbOp = cbOp;
1614 uint32_t uMmioReg = pDis->param1.base.reg_gen;
1615
1616 /* read */
1617 Assert(pDis->param1.flags == USE_REG_GEN32);
1618
1619 /* Found:
1620 * mov eax, dword [fffe0080] (5 bytes)
1621 * Check if next instruction is:
1622 * shr eax, 4
1623 */
1624 pCtx->rip += cbOp;
1625 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1626 pCtx->rip = oldrip;
1627 if ( rc == VINF_SUCCESS
1628 && pDis->pCurInstr->opcode == OP_SHR
1629 && pDis->param1.flags == USE_REG_GEN32
1630 && pDis->param1.base.reg_gen == uMmioReg
1631 && pDis->param2.flags == USE_IMMEDIATE8
1632 && pDis->param2.parval == 4
1633 && oldcbOp + cbOp < sizeof(pVM->hwaccm.s.svm.aPatches[idx].aOpcode))
1634 {
1635 uint8_t szInstr[15];
1636
1637 /* Replacing two instructions now. */
1638 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, oldcbOp + cbOp);
1639 AssertRC(rc);
1640
1641 pPatch->cbOp = oldcbOp + cbOp;
1642
1643 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1644 szInstr[0] = 0xF0;
1645 szInstr[1] = 0x0F;
1646 szInstr[2] = 0x20;
1647 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
1648 for (unsigned i = 4; i < pPatch->cbOp; i++)
1649 szInstr[i] = 0x90; /* nop */
1650
1651 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, pPatch->cbOp);
1652 AssertRC(rc);
1653
1654 memcpy(pPatch->aNewOpcode, szInstr, pPatch->cbOp);
1655 pPatch->cbNewOp = pPatch->cbOp;
1656
1657 Log(("Acceptable read/shr candidate!\n"));
1658 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1659 }
1660 else
1661 {
1662 pPatch->enmType = HWACCMTPRINSTR_READ;
1663 pPatch->uDstOperand = pDis->param1.base.reg_gen;
1664
1665 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1666 AssertRC(rc);
1667
1668 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1669 pPatch->cbNewOp = sizeof(aVMMCall);
1670 }
1671 }
1672
1673 pPatch->Core.Key = pCtx->eip;
1674 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1675 AssertRC(rc);
1676
1677 pVM->hwaccm.s.svm.cPatches++;
1678 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceSuccess);
1679 return VINF_SUCCESS;
1680 }
1681
1682 /* Save invalid patch, so we will not try again. */
1683 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1684
1685#ifdef LOG_ENABLED
1686 char szOutput[256];
1687 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1688 if (VBOX_SUCCESS(rc))
1689 Log(("Failed to patch instr: %s\n", szOutput));
1690#endif
1691
1692 pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1693 pPatch->Core.Key = pCtx->eip;
1694 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1695 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1696 AssertRC(rc);
1697 pVM->hwaccm.s.svm.cPatches++;
1698 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceFailure);
1699 return VINF_SUCCESS;
1700}
1701
1702/**
1703 * Callback to patch a TPR instruction (jump to generated code)
1704 *
1705 * @returns VBox status code.
1706 * @param pVM The VM handle.
1707 * @param pVCpu The VMCPU for the EMT we're being called on.
1708 * @param pvUser User specified CPU context
1709 *
1710 */
1711DECLCALLBACK(int) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1712{
1713 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1714 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1715 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1716 unsigned cbOp;
1717 int rc;
1718#ifdef LOG_ENABLED
1719 RTGCPTR pInstr;
1720 char szOutput[256];
1721#endif
1722
1723 /* Only execute the handler on the VCPU the original patch request was issued. */
1724 if (pVCpu->idCpu != idCpu)
1725 return VINF_SUCCESS;
1726
1727 Log(("hwaccmR3PatchTprInstr %RGv\n", pCtx->rip));
1728
1729 Assert(pVM->hwaccm.s.svm.cPatches < RT_ELEMENTS(pVM->hwaccm.s.svm.aPatches));
1730
1731 /* Two or more VCPUs were racing to patch this instruction. */
1732 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.svm.PatchTree, (AVLOU32KEY)pCtx->eip);
1733 if (pPatch)
1734 return VINF_SUCCESS;
1735
1736 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1737 AssertRC(rc);
1738 if ( rc == VINF_SUCCESS
1739 && pDis->pCurInstr->opcode == OP_MOV
1740 && cbOp >= 5)
1741 {
1742 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1743 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1744 uint8_t aPatch[64];
1745 uint32_t off = 0;
1746
1747#ifdef LOG_ENABLED
1748 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1749 if (VBOX_SUCCESS(rc))
1750 Log(("Original instr: %s\n", szOutput));
1751#endif
1752
1753 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1754 AssertRC(rc);
1755
1756 pPatch->cbOp = cbOp;
1757 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
1758
1759 if (pDis->param1.flags == USE_DISPLACEMENT32)
1760 {
1761 /*
1762 * TPR write:
1763 *
1764 * push ECX [51]
1765 * push EDX [52]
1766 * push EAX [50]
1767 * xor EDX,EDX [31 D2]
1768 * mov EAX,EAX [89 C0]
1769 * or
1770 * mov EAX,0000000CCh [B8 CC 00 00 00]
1771 * mov ECX,0C0000082h [B9 82 00 00 C0]
1772 * wrmsr [0F 30]
1773 * pop EAX [58]
1774 * pop EDX [5A]
1775 * pop ECX [59]
1776 * jmp return_address [E9 return_address]
1777 *
1778 */
1779 bool fUsesEax = (pDis->param2.flags == USE_REG_GEN32 && pDis->param2.base.reg_gen == USE_REG_EAX);
1780
1781 aPatch[off++] = 0x51; /* push ecx */
1782 aPatch[off++] = 0x52; /* push edx */
1783 if (!fUsesEax)
1784 aPatch[off++] = 0x50; /* push eax */
1785 aPatch[off++] = 0x31; /* xor edx, edx */
1786 aPatch[off++] = 0xD2;
1787 if (pDis->param2.flags == USE_REG_GEN32)
1788 {
1789 if (!fUsesEax)
1790 {
1791 aPatch[off++] = 0x89; /* mov eax, src_reg */
1792 aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, USE_REG_EAX);
1793 }
1794 }
1795 else
1796 {
1797 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1798 aPatch[off++] = 0xB8; /* mov eax, immediate */
1799 *(uint32_t *)&aPatch[off] = pDis->param2.parval;
1800 off += sizeof(uint32_t);
1801 }
1802 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1803 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1804 off += sizeof(uint32_t);
1805
1806 aPatch[off++] = 0x0F; /* wrmsr */
1807 aPatch[off++] = 0x30;
1808 if (!fUsesEax)
1809 aPatch[off++] = 0x58; /* pop eax */
1810 aPatch[off++] = 0x5A; /* pop edx */
1811 aPatch[off++] = 0x59; /* pop ecx */
1812 }
1813 else
1814 {
1815 /*
1816 * TPR read:
1817 *
1818 * push ECX [51]
1819 * push EDX [52]
1820 * push EAX [50]
1821 * mov ECX,0C0000082h [B9 82 00 00 C0]
1822 * rdmsr [0F 32]
1823 * mov EAX,EAX [89 C0]
1824 * pop EAX [58]
1825 * pop EDX [5A]
1826 * pop ECX [59]
1827 * jmp return_address [E9 return_address]
1828 *
1829 */
1830 Assert(pDis->param1.flags == USE_REG_GEN32);
1831
1832 if (pDis->param1.base.reg_gen != USE_REG_ECX)
1833 aPatch[off++] = 0x51; /* push ecx */
1834 if (pDis->param1.base.reg_gen != USE_REG_EDX)
1835 aPatch[off++] = 0x52; /* push edx */
1836 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1837 aPatch[off++] = 0x50; /* push eax */
1838
1839 aPatch[off++] = 0x31; /* xor edx, edx */
1840 aPatch[off++] = 0xD2;
1841
1842 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1843 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1844 off += sizeof(uint32_t);
1845
1846 aPatch[off++] = 0x0F; /* rdmsr */
1847 aPatch[off++] = 0x32;
1848
1849 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1850 {
1851 aPatch[off++] = 0x89; /* mov dst_reg, eax */
1852 aPatch[off++] = MAKE_MODRM(3, USE_REG_EAX, pDis->param1.base.reg_gen);
1853 }
1854
1855 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1856 aPatch[off++] = 0x58; /* pop eax */
1857 if (pDis->param1.base.reg_gen != USE_REG_EDX)
1858 aPatch[off++] = 0x5A; /* pop edx */
1859 if (pDis->param1.base.reg_gen != USE_REG_ECX)
1860 aPatch[off++] = 0x59; /* pop ecx */
1861 }
1862 aPatch[off++] = 0xE9; /* jmp return_address */
1863 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
1864 off += sizeof(RTRCUINTPTR);
1865
1866 if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
1867 {
1868 /* Write new code to the patch buffer. */
1869 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
1870 AssertRC(rc);
1871
1872#ifdef LOG_ENABLED
1873 pInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
1874 while (true)
1875 {
1876 uint32_t cb;
1877
1878 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pInstr, 0, szOutput, sizeof(szOutput), &cb);
1879 if (VBOX_SUCCESS(rc))
1880 Log(("Patch instr %s\n", szOutput));
1881
1882 pInstr += cb;
1883
1884 if (pInstr >= pVM->hwaccm.s.pFreeGuestPatchMem + off)
1885 break;
1886 }
1887#endif
1888
1889 pPatch->aNewOpcode[0] = 0xE9;
1890 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
1891
1892 /* Overwrite the TPR instruction with a jump. */
1893 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
1894 AssertRC(rc);
1895
1896#ifdef LOG_ENABLED
1897 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1898 if (VBOX_SUCCESS(rc))
1899 Log(("Jump: %s\n", szOutput));
1900#endif
1901 pVM->hwaccm.s.pFreeGuestPatchMem += off;
1902 pPatch->cbNewOp = 5;
1903
1904 pPatch->Core.Key = pCtx->eip;
1905 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1906 AssertRC(rc);
1907
1908 pVM->hwaccm.s.svm.cPatches++;
1909 pVM->hwaccm.s.svm.fTPRPatchingActive = true;
1910 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchSuccess);
1911 return VINF_SUCCESS;
1912 }
1913 else
1914 Log(("Ran out of space in our patch buffer!\n"));
1915 }
1916
1917 /* Save invalid patch, so we will not try again. */
1918 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1919
1920#ifdef LOG_ENABLED
1921 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1922 if (VBOX_SUCCESS(rc))
1923 Log(("Failed to patch instr: %s\n", szOutput));
1924#endif
1925
1926 pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1927 pPatch->Core.Key = pCtx->eip;
1928 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1929 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1930 AssertRC(rc);
1931 pVM->hwaccm.s.svm.cPatches++;
1932 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchFailure);
1933 return VINF_SUCCESS;
1934}
1935
1936/**
1937 * Attempt to patch TPR mmio instructions
1938 *
1939 * @returns VBox status code.
1940 * @param pVM The VM to operate on.
1941 * @param pVCpu The VM CPU to operate on.
1942 * @param pCtx CPU context
1943 */
1944VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1945{
1946 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, (pVM->hwaccm.s.pGuestPatchMem) ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr, (void *)pVCpu->idCpu);
1947 AssertRC(rc);
1948 return rc;
1949}
1950
1951/**
1952 * Force execution of the current IO code in the recompiler
1953 *
1954 * @returns VBox status code.
1955 * @param pVM The VM to operate on.
1956 * @param pCtx Partial VM execution context
1957 */
1958VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
1959{
1960 PVMCPU pVCpu = VMMGetCpu(pVM);
1961
1962 Assert(pVM->fHWACCMEnabled);
1963 Log(("HWACCMR3EmulateIoBlock\n"));
1964
1965 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
1966 if (HWACCMCanEmulateIoBlockEx(pCtx))
1967 {
1968 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
1969 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
1970 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
1971 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
1972 return VINF_EM_RESCHEDULE_REM;
1973 }
1974 return VINF_SUCCESS;
1975}
1976
1977/**
1978 * Checks if we can currently use hardware accelerated raw mode.
1979 *
1980 * @returns boolean
1981 * @param pVM The VM to operate on.
1982 * @param pCtx Partial VM execution context
1983 */
1984VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
1985{
1986 PVMCPU pVCpu = VMMGetCpu(pVM);
1987
1988 Assert(pVM->fHWACCMEnabled);
1989
1990 /* If we're still executing the IO code, then return false. */
1991 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
1992 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
1993 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
1994 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
1995 return false;
1996
1997 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
1998
1999 /* AMD-V supports real & protected mode with or without paging. */
2000 if (pVM->hwaccm.s.svm.fEnabled)
2001 {
2002 pVCpu->hwaccm.s.fActive = true;
2003 return true;
2004 }
2005
2006 pVCpu->hwaccm.s.fActive = false;
2007
2008 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2009#ifdef HWACCM_VMX_EMULATE_REALMODE
2010 if (pVM->hwaccm.s.vmx.pRealModeTSS)
2011 {
2012 if (CPUMIsGuestInRealModeEx(pCtx))
2013 {
2014 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
2015 * The base must also be equal to (sel << 4).
2016 */
2017 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
2018 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
2019 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
2020 || pCtx->es != (pCtx->esHid.u64Base >> 4)
2021 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
2022 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
2023 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
2024 {
2025 return false;
2026 }
2027 }
2028 else
2029 {
2030 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2031 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
2032 * from real to protected mode. (all sorts of RPL & DPL assumptions)
2033 */
2034 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2035 && enmGuestMode >= PGMMODE_PROTECTED)
2036 {
2037 if ( (pCtx->cs & X86_SEL_RPL)
2038 || (pCtx->ds & X86_SEL_RPL)
2039 || (pCtx->es & X86_SEL_RPL)
2040 || (pCtx->fs & X86_SEL_RPL)
2041 || (pCtx->gs & X86_SEL_RPL)
2042 || (pCtx->ss & X86_SEL_RPL))
2043 {
2044 return false;
2045 }
2046 }
2047 }
2048 }
2049 else
2050#endif /* HWACCM_VMX_EMULATE_REALMODE */
2051 {
2052 if (!CPUMIsGuestInLongModeEx(pCtx))
2053 {
2054 /** @todo This should (probably) be set on every excursion to the REM,
2055 * however it's too risky right now. So, only apply it when we go
2056 * back to REM for real mode execution. (The XP hack below doesn't
2057 * work reliably without this.)
2058 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2059 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2060
2061 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2062 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
2063 return false;
2064
2065 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2066 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2067 * hidden registers (possible recompiler bug; see load_seg_vm) */
2068 if (pCtx->csHid.Attr.n.u1Present == 0)
2069 return false;
2070 if (pCtx->ssHid.Attr.n.u1Present == 0)
2071 return false;
2072
2073 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2074 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2075 /** @todo This check is actually wrong, it doesn't take the direction of the
2076 * stack segment into account. But, it does the job for now. */
2077 if (pCtx->rsp >= pCtx->ssHid.u32Limit)
2078 return false;
2079#if 0
2080 if ( pCtx->cs >= pCtx->gdtr.cbGdt
2081 || pCtx->ss >= pCtx->gdtr.cbGdt
2082 || pCtx->ds >= pCtx->gdtr.cbGdt
2083 || pCtx->es >= pCtx->gdtr.cbGdt
2084 || pCtx->fs >= pCtx->gdtr.cbGdt
2085 || pCtx->gs >= pCtx->gdtr.cbGdt)
2086 return false;
2087#endif
2088 }
2089 }
2090
2091 if (pVM->hwaccm.s.vmx.fEnabled)
2092 {
2093 uint32_t mask;
2094
2095 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2096 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2097 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2098 mask &= ~X86_CR0_NE;
2099
2100#ifdef HWACCM_VMX_EMULATE_REALMODE
2101 if (pVM->hwaccm.s.vmx.pRealModeTSS)
2102 {
2103 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2104 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2105 }
2106 else
2107#endif
2108 {
2109 /* We support protected mode without paging using identity mapping. */
2110 mask &= ~X86_CR0_PG;
2111 }
2112 if ((pCtx->cr0 & mask) != mask)
2113 return false;
2114
2115 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2116 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2117 if ((pCtx->cr0 & mask) != 0)
2118 return false;
2119
2120 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2121 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2122 mask &= ~X86_CR4_VMXE;
2123 if ((pCtx->cr4 & mask) != mask)
2124 return false;
2125
2126 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2127 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2128 if ((pCtx->cr4 & mask) != 0)
2129 return false;
2130
2131 pVCpu->hwaccm.s.fActive = true;
2132 return true;
2133 }
2134
2135 return false;
2136}
2137
2138/**
2139 * Notifcation from EM about a rescheduling into hardware assisted execution
2140 * mode.
2141 *
2142 * @param pVCpu Pointer to the current virtual cpu structure.
2143 */
2144VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2145{
2146 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2147}
2148
2149/**
2150 * Notifcation from EM about returning from instruction emulation (REM / EM).
2151 *
2152 * @param pVCpu Pointer to the current virtual cpu structure.
2153 */
2154VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2155{
2156 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2157}
2158
2159/**
2160 * Checks if we are currently using hardware accelerated raw mode.
2161 *
2162 * @returns boolean
2163 * @param pVCpu The VMCPU to operate on.
2164 */
2165VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2166{
2167 return pVCpu->hwaccm.s.fActive;
2168}
2169
2170/**
2171 * Checks if we are currently using nested paging.
2172 *
2173 * @returns boolean
2174 * @param pVM The VM to operate on.
2175 */
2176VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2177{
2178 return pVM->hwaccm.s.fNestedPaging;
2179}
2180
2181/**
2182 * Checks if we are currently using VPID in VT-x mode.
2183 *
2184 * @returns boolean
2185 * @param pVM The VM to operate on.
2186 */
2187VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2188{
2189 return pVM->hwaccm.s.vmx.fVPID;
2190}
2191
2192
2193/**
2194 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2195 *
2196 * @returns boolean
2197 * @param pVM The VM to operate on.
2198 */
2199VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2200{
2201 return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2202}
2203
2204/**
2205 * Restart an I/O instruction that was refused in ring-0
2206 *
2207 * @returns VBox status code
2208 * @param pVM The VM to operate on.
2209 * @param pVCpu The VMCPU to operate on.
2210 * @param pCtx VCPU register context
2211 */
2212VMMR3DECL(int) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2213{
2214 HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2215 int rc;
2216
2217 pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2218
2219 if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2220 || enmType == HWACCMPENDINGIO_INVALID)
2221 return VERR_NOT_FOUND;
2222
2223 switch (enmType)
2224 {
2225 case HWACCMPENDINGIO_PORT_READ:
2226 {
2227 uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2228 uint32_t u32Val = 0;
2229
2230 rc = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2231 &u32Val,
2232 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2233 if (IOM_SUCCESS(rc))
2234 {
2235 /* Write back to the EAX register. */
2236 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2237 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2238 }
2239 break;
2240 }
2241
2242 case HWACCMPENDINGIO_PORT_WRITE:
2243 rc = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2244 pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2245 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2246 if (IOM_SUCCESS(rc))
2247 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2248 break;
2249
2250 default:
2251 AssertFailed();
2252 return VERR_INTERNAL_ERROR;
2253 }
2254
2255 return rc;
2256}
2257
2258/**
2259 * Inject an NMI into a running VM (only VCPU 0!)
2260 *
2261 * @returns boolean
2262 * @param pVM The VM to operate on.
2263 */
2264VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2265{
2266 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2267 return VINF_SUCCESS;
2268}
2269
2270/**
2271 * Check fatal VT-x/AMD-V error and produce some meaningful
2272 * log release message.
2273 *
2274 * @param pVM The VM to operate on.
2275 * @param iStatusCode VBox status code
2276 */
2277VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2278{
2279 for (unsigned i=0;i<pVM->cCPUs;i++)
2280 {
2281 switch(iStatusCode)
2282 {
2283 case VERR_VMX_INVALID_VMCS_FIELD:
2284 break;
2285
2286 case VERR_VMX_INVALID_VMCS_PTR:
2287 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
2288 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2289 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2290 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2291 break;
2292
2293 case VERR_VMX_UNABLE_TO_START_VM:
2294 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2295 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2296#if 0 /* @todo dump the current control fields to the release log */
2297 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2298 {
2299
2300 }
2301#endif
2302 break;
2303
2304 case VERR_VMX_UNABLE_TO_RESUME_VM:
2305 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2306 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2307 break;
2308
2309 case VERR_VMX_INVALID_VMXON_PTR:
2310 break;
2311 }
2312 }
2313}
2314
2315/**
2316 * Execute state save operation.
2317 *
2318 * @returns VBox status code.
2319 * @param pVM VM Handle.
2320 * @param pSSM SSM operation handle.
2321 */
2322static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2323{
2324 int rc;
2325
2326 Log(("hwaccmR3Save:\n"));
2327
2328 for (unsigned i=0;i<pVM->cCPUs;i++)
2329 {
2330 /*
2331 * Save the basic bits - fortunately all the other things can be resynced on load.
2332 */
2333 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2334 AssertRCReturn(rc, rc);
2335 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2336 AssertRCReturn(rc, rc);
2337 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2338 AssertRCReturn(rc, rc);
2339
2340 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2341 AssertRCReturn(rc, rc);
2342 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2343 AssertRCReturn(rc, rc);
2344 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2345 AssertRCReturn(rc, rc);
2346 }
2347#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2348 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2349 AssertRCReturn(rc, rc);
2350 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2351 AssertRCReturn(rc, rc);
2352 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2353 AssertRCReturn(rc, rc);
2354
2355 /* Store all the guest patch records too. */
2356 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.svm.cPatches);
2357 AssertRCReturn(rc, rc);
2358
2359 for (unsigned i = 0; i < pVM->hwaccm.s.svm.cPatches; i++)
2360 {
2361 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[i];
2362
2363 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2364 AssertRCReturn(rc, rc);
2365
2366 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2367 AssertRCReturn(rc, rc);
2368
2369 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2370 AssertRCReturn(rc, rc);
2371
2372 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2373 AssertRCReturn(rc, rc);
2374
2375 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2376 AssertRCReturn(rc, rc);
2377
2378 AssertCompileSize(HWACCMTPRINSTR, 4);
2379 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2380 AssertRCReturn(rc, rc);
2381
2382 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2383 AssertRCReturn(rc, rc);
2384
2385 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2386 AssertRCReturn(rc, rc);
2387
2388 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2389 AssertRCReturn(rc, rc);
2390
2391 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2392 AssertRCReturn(rc, rc);
2393 }
2394#endif
2395 return VINF_SUCCESS;
2396}
2397
2398/**
2399 * Execute state load operation.
2400 *
2401 * @returns VBox status code.
2402 * @param pVM VM Handle.
2403 * @param pSSM SSM operation handle.
2404 * @param u32Version Data layout version.
2405 */
2406static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2407{
2408 int rc;
2409
2410 Log(("hwaccmR3Load:\n"));
2411
2412 /*
2413 * Validate version.
2414 */
2415 if ( u32Version != HWACCM_SSM_VERSION
2416 && u32Version != HWACCM_SSM_VERSION_NO_PATCHING
2417 && u32Version != HWACCM_SSM_VERSION_2_0_X)
2418 {
2419 AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
2420 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2421 }
2422 for (unsigned i=0;i<pVM->cCPUs;i++)
2423 {
2424 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2425 AssertRCReturn(rc, rc);
2426 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2427 AssertRCReturn(rc, rc);
2428 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2429 AssertRCReturn(rc, rc);
2430
2431 if (u32Version >= HWACCM_SSM_VERSION_NO_PATCHING)
2432 {
2433 uint32_t val;
2434
2435 rc = SSMR3GetU32(pSSM, &val);
2436 AssertRCReturn(rc, rc);
2437 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2438
2439 rc = SSMR3GetU32(pSSM, &val);
2440 AssertRCReturn(rc, rc);
2441 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2442
2443 rc = SSMR3GetU32(pSSM, &val);
2444 AssertRCReturn(rc, rc);
2445 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2446 }
2447 }
2448#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2449 if (u32Version > HWACCM_SSM_VERSION_NO_PATCHING)
2450 {
2451 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2452 AssertRCReturn(rc, rc);
2453 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2454 AssertRCReturn(rc, rc);
2455 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2456 AssertRCReturn(rc, rc);
2457
2458 /* Fetch all TPR patch records. */
2459 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.svm.cPatches);
2460 AssertRCReturn(rc, rc);
2461
2462 for (unsigned i = 0; i < pVM->hwaccm.s.svm.cPatches; i++)
2463 {
2464 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[i];
2465
2466 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2467 AssertRCReturn(rc, rc);
2468
2469 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2470 AssertRCReturn(rc, rc);
2471
2472 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2473 AssertRCReturn(rc, rc);
2474
2475 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2476 AssertRCReturn(rc, rc);
2477
2478 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2479 AssertRCReturn(rc, rc);
2480
2481 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2482 AssertRCReturn(rc, rc);
2483
2484 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2485 AssertRCReturn(rc, rc);
2486
2487 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2488 AssertRCReturn(rc, rc);
2489
2490 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2491 AssertRCReturn(rc, rc);
2492
2493 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2494 AssertRCReturn(rc, rc);
2495
2496 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
2497 AssertRC(rc);
2498 }
2499 }
2500#endif
2501 return VINF_SUCCESS;
2502}
2503
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette