VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 23244

Last change on this file since 23244 was 23244, checked in by vboxsync, 15 years ago

Fixed tpr patch restore
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 120.9 KB
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1/* $Id: HWACCM.cpp 23244 2009-09-23 08:11:50Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/csam.h>
35#include <VBox/selm.h>
36#include <VBox/rem.h>
37#include <VBox/hwacc_vmx.h>
38#include <VBox/hwacc_svm.h>
39#include "HWACCMInternal.h"
40#include <VBox/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/string.h>
48#include <iprt/thread.h>
49
50/*******************************************************************************
51* Global Variables *
52*******************************************************************************/
53#ifdef VBOX_WITH_STATISTICS
54# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55# define EXIT_REASON_NIL() NULL
56/** Exit reason descriptions for VT-x, used to describe statistics. */
57static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58{
59 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67 EXIT_REASON_NIL(),
68 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94 EXIT_REASON_NIL(),
95 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96 EXIT_REASON_NIL(),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101 EXIT_REASON_NIL(),
102 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110 EXIT_REASON_NIL(),
111 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115 EXIT_REASON_NIL()
116};
117/** Exit reason descriptions for AMD-V, used to describe statistics. */
118static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119{
120 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
121 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
122 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
123 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
124 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
125 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
126 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
127 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
128 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
129 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
130 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
131 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
132 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
133 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
134 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
135 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
136 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
137 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
152 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
153 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
154 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
155 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
156 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
157 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
158 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
159 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
160 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
161 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
162 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
163 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
164 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
165 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
166 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
167 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
168 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
169 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
184 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
185 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_INTR , 96, "Physical maskable interrupt."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_NMI , 97, "Physical non-maskable interrupt."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_SMI , 98, "System management interrupt."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_INIT , 99, "Physical INIT signal."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_VINTR ,100, "Visual interrupt."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_IDTR_READ ,102, "Read IDTR"),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_GDTR_READ ,103, "Read GDTR"),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_LDTR_READ ,104, "Read LDTR."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,105, "Read TR."),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,106, "Write IDTR."),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,107, "Write GDTR."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,108, "Write LDTR."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,109, "Write TR."),
230 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
231 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
232 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
233 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
234 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
235 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
236 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
237 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
238 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
239 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
240 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
241 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
242 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
243 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
244 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
245 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
246 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
247 EXIT_REASON(SVM_EXIT_TASK_SHUTDOWN ,127, "Shutdown."),
248 EXIT_REASON(SVM_EXIT_TASK_VMRUN ,128, "VMRUN instruction."),
249 EXIT_REASON(SVM_EXIT_TASK_VMCALL ,129, "VMCALL instruction."),
250 EXIT_REASON(SVM_EXIT_TASK_VMLOAD ,130, "VMLOAD instruction."),
251 EXIT_REASON(SVM_EXIT_TASK_VMSAVE ,131, "VMSAVE instruction."),
252 EXIT_REASON(SVM_EXIT_TASK_STGI ,132, "STGI instruction."),
253 EXIT_REASON(SVM_EXIT_TASK_CLGI ,133, "CLGI instruction."),
254 EXIT_REASON(SVM_EXIT_TASK_SKINIT ,134, "SKINIT instruction."),
255 EXIT_REASON(SVM_EXIT_TASK_RDTSCP ,135, "RDTSCP instruction."),
256 EXIT_REASON(SVM_EXIT_TASK_ICEBP ,136, "ICEBP instruction."),
257 EXIT_REASON(SVM_EXIT_TASK_WBINVD ,137, "WBINVD instruction."),
258 EXIT_REASON(SVM_EXIT_TASK_MONITOR ,138, "MONITOR instruction."),
259 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
260 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
261 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
262 EXIT_REASON_NIL()
263};
264# undef EXIT_REASON
265# undef EXIT_REASON_NIL
266#endif /* VBOX_WITH_STATISTICS */
267
268/*******************************************************************************
269* Internal Functions *
270*******************************************************************************/
271static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
272static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
273
274
275/**
276 * Initializes the HWACCM.
277 *
278 * @returns VBox status code.
279 * @param pVM The VM to operate on.
280 */
281VMMR3DECL(int) HWACCMR3Init(PVM pVM)
282{
283 LogFlow(("HWACCMR3Init\n"));
284
285 /*
286 * Assert alignment and sizes.
287 */
288 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
289 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
290
291 /* Some structure checks. */
292 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
293 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
294 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
295 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
296
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
300 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
303 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
304
305
306 /*
307 * Register the saved state data unit.
308 */
309 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
310 NULL, NULL, NULL,
311 NULL, hwaccmR3Save, NULL,
312 NULL, hwaccmR3Load, NULL);
313 if (RT_FAILURE(rc))
314 return rc;
315
316 /* Misc initialisation. */
317 pVM->hwaccm.s.vmx.fSupported = false;
318 pVM->hwaccm.s.svm.fSupported = false;
319 pVM->hwaccm.s.vmx.fEnabled = false;
320 pVM->hwaccm.s.svm.fEnabled = false;
321
322 pVM->hwaccm.s.fNestedPaging = false;
323
324 /* Disabled by default. */
325 pVM->fHWACCMEnabled = false;
326
327 /*
328 * Check CFGM options.
329 */
330 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
331 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
332 /* Nested paging: disabled by default. */
333 rc = CFGMR3QueryBoolDef(pRoot, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
334 AssertRC(rc);
335
336 /* VT-x VPID: disabled by default. */
337 rc = CFGMR3QueryBoolDef(pRoot, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
338 AssertRC(rc);
339
340 /* HWACCM support must be explicitely enabled in the configuration file. */
341 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
342 AssertRC(rc);
343
344 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
345 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hwaccm.s.fTRPPatchingAllowed, false);
346 AssertRC(rc);
347
348#ifdef RT_OS_DARWIN
349 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
350#else
351 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
352#endif
353 {
354 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
355 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
356 return VERR_HWACCM_CONFIG_MISMATCH;
357 }
358
359 if (VMMIsHwVirtExtForced(pVM))
360 pVM->fHWACCMEnabled = true;
361
362#if HC_ARCH_BITS == 32
363 /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
364 * (To use the default, don't set 64bitEnabled in CFGM.) */
365 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
366 AssertLogRelRCReturn(rc, rc);
367 if (pVM->hwaccm.s.fAllow64BitGuests)
368 {
369# ifdef RT_OS_DARWIN
370 if (!VMMIsHwVirtExtForced(pVM))
371# else
372 if (!pVM->hwaccm.s.fAllowed)
373# endif
374 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
375 }
376#else
377 /* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
378 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
379 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
380 AssertLogRelRCReturn(rc, rc);
381#endif
382
383 /* Max number of resume loops. */
384 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
385 AssertRC(rc);
386
387 return VINF_SUCCESS;
388}
389
390/**
391 * Initializes the per-VCPU HWACCM.
392 *
393 * @returns VBox status code.
394 * @param pVM The VM to operate on.
395 */
396VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
397{
398 LogFlow(("HWACCMR3InitCPU\n"));
399
400 for (VMCPUID i = 0; i < pVM->cCpus; i++)
401 {
402 PVMCPU pVCpu = &pVM->aCpus[i];
403
404 pVCpu->hwaccm.s.fActive = false;
405 }
406
407#ifdef VBOX_WITH_STATISTICS
408 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
409 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
410 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
411 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
412
413 /*
414 * Statistics.
415 */
416 for (VMCPUID i = 0; i < pVM->cCpus; i++)
417 {
418 PVMCPU pVCpu = &pVM->aCpus[i];
419 int rc;
420
421 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
422 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
423 AssertRC(rc);
424 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
425 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
426 AssertRC(rc);
427 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
428 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
429 AssertRC(rc);
430# if 1 /* temporary for tracking down darwin holdup. */
431 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
432 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
433 AssertRC(rc);
434 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
435 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
436 AssertRC(rc);
437 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
438 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
439 AssertRC(rc);
440# endif
441 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
442 "/PROF/HWACCM/CPU%d/InGC", i);
443 AssertRC(rc);
444
445# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
446 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
447 "/PROF/HWACCM/CPU%d/Switcher3264", i);
448 AssertRC(rc);
449# endif
450
451# define HWACCM_REG_COUNTER(a, b) \
452 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
453 AssertRC(rc);
454
455 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
456 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
457 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
458 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
459 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
460 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
461 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
462 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
463 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
464 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
465 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
466 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
467 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
468 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
469 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
470 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
471 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
472 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
473 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
474 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
475 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
476 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
477 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
478 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
479 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
480 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
481 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
482 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
483 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
484 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
485 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
486 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
487 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
488 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
489 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
490 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
491 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
492
493 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
494 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
495
496 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
498 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
499
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
503 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
504 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
505 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
506 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
507 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
508 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
509 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
510 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
511
512 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
513 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
514 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow, "/HWACCM/CPU%d/TSC/InterceptOverflow");
515
516 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
517 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
518 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
519
520 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
521 {
522 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
523 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
524 AssertRC(rc);
525 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
526 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
527 AssertRC(rc);
528 }
529
530#undef HWACCM_REG_COUNTER
531
532 pVCpu->hwaccm.s.paStatExitReason = NULL;
533
534 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
535 AssertRC(rc);
536 if (RT_SUCCESS(rc))
537 {
538 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
539 for (int j=0;j<MAX_EXITREASON_STAT;j++)
540 {
541 if (papszDesc[j])
542 {
543 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
544 papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
545 AssertRC(rc);
546 }
547 }
548 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
549 AssertRC(rc);
550 }
551 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
552# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
553 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
554# else
555 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
556# endif
557
558 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
559 AssertRCReturn(rc, rc);
560 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
561# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
562 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
563# else
564 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
565# endif
566 for (unsigned j = 0; j < 255; j++)
567 STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
568 (j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
569
570 }
571#endif /* VBOX_WITH_STATISTICS */
572
573#ifdef VBOX_WITH_CRASHDUMP_MAGIC
574 /* Magic marker for searching in crash dumps. */
575 for (VMCPUID i = 0; i < pVM->cCpus; i++)
576 {
577 PVMCPU pVCpu = &pVM->aCpus[i];
578
579 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
580 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
581 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
582 }
583#endif
584 return VINF_SUCCESS;
585}
586
587/**
588 * Turns off normal raw mode features
589 *
590 * @param pVM The VM to operate on.
591 */
592static void hwaccmR3DisableRawMode(PVM pVM)
593{
594 /* Disable PATM & CSAM. */
595 PATMR3AllowPatching(pVM, false);
596 CSAMDisableScanning(pVM);
597
598 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
599 SELMR3DisableMonitoring(pVM);
600 TRPMR3DisableMonitoring(pVM);
601
602 /* Disable the switcher code (safety precaution). */
603 VMMR3DisableSwitcher(pVM);
604
605 /* Disable mapping of the hypervisor into the shadow page table. */
606 PGMR3MappingsDisable(pVM);
607
608 /* Disable the switcher */
609 VMMR3DisableSwitcher(pVM);
610
611 /* Reinit the paging mode to force the new shadow mode. */
612 for (VMCPUID i = 0; i < pVM->cCpus; i++)
613 {
614 PVMCPU pVCpu = &pVM->aCpus[i];
615
616 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
617 }
618}
619
620/**
621 * Initialize VT-x or AMD-V.
622 *
623 * @returns VBox status code.
624 * @param pVM The VM handle.
625 */
626VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
627{
628 int rc;
629
630 if ( !pVM->hwaccm.s.vmx.fSupported
631 && !pVM->hwaccm.s.svm.fSupported)
632 {
633 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
634 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
635 if (VMMIsHwVirtExtForced(pVM))
636 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
637 return VINF_SUCCESS;
638 }
639
640 if (pVM->hwaccm.s.vmx.fSupported)
641 {
642 rc = SUPR3QueryVTxSupported();
643 if (RT_FAILURE(rc))
644 {
645#ifdef RT_OS_LINUX
646 LogRel(("HWACCM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
647#else
648 LogRel(("HWACCM: The host kernel does not support VT-x!\n"));
649#endif
650 if ( pVM->cCpus > 1
651 || VMMIsHwVirtExtForced(pVM))
652 return rc;
653
654 /* silently fall back to raw mode */
655 return VINF_SUCCESS;
656 }
657 }
658
659 if (!pVM->hwaccm.s.fAllowed)
660 return VINF_SUCCESS; /* nothing to do */
661
662 /* Enable VT-x or AMD-V on all host CPUs. */
663 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
664 if (RT_FAILURE(rc))
665 {
666 LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
667 return rc;
668 }
669 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
670
671 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
672 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
673 if (!pVM->hwaccm.s.fHasIoApic)
674 {
675 Assert(!pVM->hwaccm.s.fTRPPatchingAllowed); /* paranoia */
676 pVM->hwaccm.s.fTRPPatchingAllowed = false;
677 }
678
679 if (pVM->hwaccm.s.vmx.fSupported)
680 {
681 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
682
683 if ( pVM->hwaccm.s.fInitialized == false
684 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
685 {
686 uint64_t val;
687 RTGCPHYS GCPhys = 0;
688
689 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
690 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
691 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
692 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
693 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
694 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
695 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
696 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
697
698 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
699 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
700 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
701 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
702 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
703 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
704 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
705 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
706 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
707 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
708 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
709 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
710 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
711 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
712 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
713 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
714 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
715 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
716 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
717
718 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
719 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
720 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
721 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
722 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
723 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
724 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
725 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
726 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
727 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
728 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
729 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
730 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
731 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
732 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
733 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
734 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
735 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
736 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
737 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
738 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
739 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
740 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
741 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
742 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
743 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
744 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
745 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
746 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
747 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
748 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
749 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
750 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
751 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
752 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
753 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
754 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
755 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
756 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
757 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
758 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
759 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
760 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
761 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
762
763 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
764 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
765 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
766 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
767 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
768 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
769 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
770 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
771 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
772 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
773 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
774 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
775 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
776 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
777 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
778 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
779 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
780 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
781 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
782 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
783 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
784 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
785 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
786 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
787 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
788 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
789 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
790 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
791 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
792 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
793 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
794 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
795 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
796 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
797 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
798 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
799 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
800 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
801 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
802 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
803 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
804 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
805 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
806
807 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
808 {
809 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
810 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
811 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
812 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
813 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
814 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
815 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
816 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
817 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
818 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
819 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
820 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
821 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
822 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
823
824 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
825 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
826 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
827 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
828 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
829 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
830 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
831 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
832 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
833 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
834 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
835 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
836 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
837 }
838
839 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
840 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
841 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
842 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
843 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
844 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
845 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
846 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
847 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
848 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
849 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
850 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
851 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
852 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
853 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
854 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
855 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
856 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
857 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
858 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
859 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
860 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
861 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
862 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
863 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
864 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
865 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
866 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
867 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
868 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
869 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
870
871 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
872 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
873 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
874 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
875 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
876 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
877 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
878 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
879 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
880 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
881 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
882 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
883 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
884 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
885 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
886 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
887 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
888 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
889 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
890 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
891 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
892 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
893 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
894 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
895 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
896 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
897 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
898 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
899 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
900 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
901 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
902 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
903 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
904 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
905 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
906
907 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
908 {
909 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
910
911 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
912 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
913 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
914 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
915 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
916 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
917 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
918 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
919 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
920 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
921 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
922 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
923 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
924 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
925 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
926 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
927 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
928 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
929 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
930 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
931 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
932 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
933 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
934 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
935 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
936 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
937 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
938 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
939 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
940 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
941 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
942 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
943 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
944 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
945 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
946 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
947 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
948 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
949 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
950 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
951 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
952 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
953 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
954 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
955 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
956 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
957 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
958 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
959 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
960 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
961 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
962 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
963 }
964
965 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
966 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
967 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
968 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
969 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
970 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
971
972 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
973 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
974 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
975 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
976 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
977
978 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
979
980 /* Paranoia */
981 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc) >= 512);
982
983 for (VMCPUID i = 0; i < pVM->cCpus; i++)
984 {
985 LogRel(("HWACCM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pMSRBitmapPhys));
986 LogRel(("HWACCM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
987 }
988
989#ifdef HWACCM_VTX_WITH_EPT
990 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
991 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
992#endif /* HWACCM_VTX_WITH_EPT */
993#ifdef HWACCM_VTX_WITH_VPID
994 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
995 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
996 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
997#endif /* HWACCM_VTX_WITH_VPID */
998
999 /* Only try once. */
1000 pVM->hwaccm.s.fInitialized = true;
1001
1002 /* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
1003#if 1
1004 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
1005#else
1006 rc = VERR_NO_MEMORY; /* simulation of no VMMDev Heap. */
1007#endif
1008 if (RT_SUCCESS(rc))
1009 {
1010 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1011 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
1012 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
1013 /* Bit set to 0 means redirection enabled. */
1014 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
1015 /* Allow all port IO, so the VT-x IO intercepts do their job. */
1016 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
1017 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
1018
1019 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1020 * real and protected mode without paging with EPT.
1021 */
1022 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1023 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
1024 {
1025 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1026 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
1027 }
1028
1029 /* We convert it here every time as pci regions could be reconfigured. */
1030 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1031 AssertRC(rc);
1032 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1033
1034 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1035 AssertRC(rc);
1036 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1037 }
1038 else
1039 {
1040 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1041 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1042 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1043 }
1044
1045 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1046 AssertRC(rc);
1047 if (rc == VINF_SUCCESS)
1048 {
1049 pVM->fHWACCMEnabled = true;
1050 pVM->hwaccm.s.vmx.fEnabled = true;
1051 hwaccmR3DisableRawMode(pVM);
1052
1053 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1054#ifdef VBOX_ENABLE_64_BITS_GUESTS
1055 if (pVM->hwaccm.s.fAllow64BitGuests)
1056 {
1057 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1058 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1059 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1060 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1061 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1062 }
1063 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1064 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1065 : "HWACCM: 32-bit guests supported.\n"));
1066#else
1067 LogRel(("HWACCM: 32-bit guests supported.\n"));
1068#endif
1069 LogRel(("HWACCM: VMX enabled!\n"));
1070 if (pVM->hwaccm.s.fNestedPaging)
1071 {
1072 LogRel(("HWACCM: Enabled nested paging\n"));
1073 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1074 }
1075 if (pVM->hwaccm.s.vmx.fVPID)
1076 LogRel(("HWACCM: Enabled VPID\n"));
1077
1078 if ( pVM->hwaccm.s.fNestedPaging
1079 || pVM->hwaccm.s.vmx.fVPID)
1080 {
1081 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1082 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1083 }
1084 }
1085 else
1086 {
1087 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1088 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1089 pVM->fHWACCMEnabled = false;
1090 }
1091 }
1092 }
1093 else
1094 if (pVM->hwaccm.s.svm.fSupported)
1095 {
1096 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1097
1098 if (pVM->hwaccm.s.fInitialized == false)
1099 {
1100 /* Erratum 170 which requires a forced TLB flush for each world switch:
1101 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1102 *
1103 * All BH-G1/2 and DH-G1/2 models include a fix:
1104 * Athlon X2: 0x6b 1/2
1105 * 0x68 1/2
1106 * Athlon 64: 0x7f 1
1107 * 0x6f 2
1108 * Sempron: 0x7f 1/2
1109 * 0x6f 2
1110 * 0x6c 2
1111 * 0x7c 2
1112 * Turion 64: 0x68 2
1113 *
1114 */
1115 uint32_t u32Dummy;
1116 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1117 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1118 u32BaseFamily= (u32Version >> 8) & 0xf;
1119 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1120 u32Model = ((u32Version >> 4) & 0xf);
1121 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1122 u32Stepping = u32Version & 0xf;
1123 if ( u32Family == 0xf
1124 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1125 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1126 {
1127 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1128 }
1129
1130 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1131 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1132 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1133 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1134 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1135
1136 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1137 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
1138 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
1139 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
1140 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
1141 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
1142 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
1143 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
1144 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
1145 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
1146
1147 /* Only try once. */
1148 pVM->hwaccm.s.fInitialized = true;
1149
1150 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1151 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1152
1153 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1154 AssertRC(rc);
1155 if (rc == VINF_SUCCESS)
1156 {
1157 pVM->fHWACCMEnabled = true;
1158 pVM->hwaccm.s.svm.fEnabled = true;
1159
1160 if (pVM->hwaccm.s.fNestedPaging)
1161 LogRel(("HWACCM: Enabled nested paging\n"));
1162
1163 hwaccmR3DisableRawMode(pVM);
1164 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1165 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1166 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1167#ifdef VBOX_ENABLE_64_BITS_GUESTS
1168 if (pVM->hwaccm.s.fAllow64BitGuests)
1169 {
1170 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1171 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1172 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1173 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1174 }
1175#endif
1176 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1177 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1178 : "HWACCM: 32-bit guest supported.\n"));
1179
1180 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1181 }
1182 else
1183 {
1184 pVM->fHWACCMEnabled = false;
1185 }
1186 }
1187 }
1188 return VINF_SUCCESS;
1189}
1190
1191/**
1192 * Applies relocations to data and code managed by this
1193 * component. This function will be called at init and
1194 * whenever the VMM need to relocate it self inside the GC.
1195 *
1196 * @param pVM The VM.
1197 */
1198VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1199{
1200 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1201
1202 /* Fetch the current paging mode during the relocate callback during state loading. */
1203 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1204 {
1205 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1206 {
1207 PVMCPU pVCpu = &pVM->aCpus[i];
1208
1209 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1210 Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1211 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1212 }
1213 }
1214#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1215 if (pVM->fHWACCMEnabled)
1216 {
1217 int rc;
1218
1219 switch(PGMGetHostMode(pVM))
1220 {
1221 case PGMMODE_32_BIT:
1222 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1223 break;
1224
1225 case PGMMODE_PAE:
1226 case PGMMODE_PAE_NX:
1227 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1228 break;
1229
1230 default:
1231 AssertFailed();
1232 break;
1233 }
1234 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1235 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1236
1237 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1238 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1239
1240 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1241 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1242
1243 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1244 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1245
1246# ifdef DEBUG
1247 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1248 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1249# endif
1250 }
1251#endif
1252 return;
1253}
1254
1255/**
1256 * Checks hardware accelerated raw mode is allowed.
1257 *
1258 * @returns boolean
1259 * @param pVM The VM to operate on.
1260 */
1261VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1262{
1263 return pVM->hwaccm.s.fAllowed;
1264}
1265
1266/**
1267 * Notification callback which is called whenever there is a chance that a CR3
1268 * value might have changed.
1269 *
1270 * This is called by PGM.
1271 *
1272 * @param pVM The VM to operate on.
1273 * @param pVCpu The VMCPU to operate on.
1274 * @param enmShadowMode New shadow paging mode.
1275 * @param enmGuestMode New guest paging mode.
1276 */
1277VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1278{
1279 /* Ignore page mode changes during state loading. */
1280 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1281 return;
1282
1283 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1284
1285 if ( pVM->hwaccm.s.vmx.fEnabled
1286 && pVM->fHWACCMEnabled)
1287 {
1288 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1289 && enmGuestMode >= PGMMODE_PROTECTED)
1290 {
1291 PCPUMCTX pCtx;
1292
1293 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1294
1295 /* After a real mode switch to protected mode we must force
1296 * CPL to 0. Our real mode emulation had to set it to 3.
1297 */
1298 pCtx->ssHid.Attr.n.u2Dpl = 0;
1299 }
1300 }
1301
1302 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1303 {
1304 /* Keep track of paging mode changes. */
1305 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1306 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1307
1308 /* Did we miss a change, because all code was executed in the recompiler? */
1309 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1310 {
1311 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1312 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1313 }
1314 }
1315
1316 /* Reset the contents of the read cache. */
1317 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1318 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1319 pCache->Read.aFieldVal[j] = 0;
1320}
1321
1322/**
1323 * Terminates the HWACCM.
1324 *
1325 * Termination means cleaning up and freeing all resources,
1326 * the VM it self is at this point powered off or suspended.
1327 *
1328 * @returns VBox status code.
1329 * @param pVM The VM to operate on.
1330 */
1331VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1332{
1333 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1334 {
1335 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1336 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1337 }
1338 HWACCMR3TermCPU(pVM);
1339 return 0;
1340}
1341
1342/**
1343 * Terminates the per-VCPU HWACCM.
1344 *
1345 * Termination means cleaning up and freeing all resources,
1346 * the VM it self is at this point powered off or suspended.
1347 *
1348 * @returns VBox status code.
1349 * @param pVM The VM to operate on.
1350 */
1351VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1352{
1353 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1354 {
1355 PVMCPU pVCpu = &pVM->aCpus[i];
1356
1357#ifdef VBOX_WITH_STATISTICS
1358 if (pVCpu->hwaccm.s.paStatExitReason)
1359 {
1360 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1361 pVCpu->hwaccm.s.paStatExitReason = NULL;
1362 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1363 }
1364 if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1365 {
1366 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1367 pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1368 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1369 }
1370#endif
1371
1372#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1373 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1374 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1375 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1376#endif
1377 }
1378 return 0;
1379}
1380
1381/**
1382 * The VM is being reset.
1383 *
1384 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1385 * needs to be removed.
1386 *
1387 * @param pVM VM handle.
1388 */
1389VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1390{
1391 LogFlow(("HWACCMR3Reset:\n"));
1392
1393 if (pVM->fHWACCMEnabled)
1394 hwaccmR3DisableRawMode(pVM);
1395
1396 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1397 {
1398 PVMCPU pVCpu = &pVM->aCpus[i];
1399
1400 /* On first entry we'll sync everything. */
1401 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1402
1403 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1404 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1405
1406 pVCpu->hwaccm.s.fActive = false;
1407 pVCpu->hwaccm.s.Event.fPending = false;
1408
1409 /* Reset state information for real-mode emulation in VT-x. */
1410 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1411 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1412 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1413
1414 /* Reset the contents of the read cache. */
1415 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1416 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1417 pCache->Read.aFieldVal[j] = 0;
1418
1419#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1420 /* Magic marker for searching in crash dumps. */
1421 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1422 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1423#endif
1424 }
1425
1426 /* Clear all patch information. */
1427 pVM->hwaccm.s.pGuestPatchMem = 0;
1428 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1429 pVM->hwaccm.s.cbGuestPatchMem = 0;
1430 pVM->hwaccm.s.svm.cPatches = 0;
1431 pVM->hwaccm.s.svm.PatchTree = 0;
1432 pVM->hwaccm.s.svm.fTPRPatchingActive = false;
1433 ASMMemZero32(pVM->hwaccm.s.svm.aPatches, sizeof(pVM->hwaccm.s.svm.aPatches));
1434}
1435
1436/**
1437 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1438 *
1439 * @returns VBox strict status code.
1440 * @param pVM The VM handle.
1441 * @param pVCpu The VMCPU for the EMT we're being called on.
1442 * @param pvUser Unused
1443 *
1444 */
1445DECLCALLBACK(VBOXSTRICTRC) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1446{
1447 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1448
1449 /* Only execute the handler on the VCPU the original patch request was issued. */
1450 if (pVCpu->idCpu != idCpu)
1451 return VINF_SUCCESS;
1452
1453 Log(("hwaccmR3RemovePatches\n"));
1454 for (unsigned i = 0; i < pVM->hwaccm.s.svm.cPatches; i++)
1455 {
1456 uint8_t szInstr[15];
1457 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[i];
1458 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1459 int rc;
1460
1461#ifdef LOG_ENABLED
1462 char szOutput[256];
1463
1464 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1465 if (VBOX_SUCCESS(rc))
1466 Log(("Patched instr: %s\n", szOutput));
1467#endif
1468
1469 /* Check if the instruction is still the same. */
1470 rc = PGMPhysSimpleReadGCPtr(pVCpu, szInstr, pInstrGC, pPatch->cbNewOp);
1471 if (rc != VINF_SUCCESS)
1472 {
1473 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1474 continue; /* swapped out or otherwise removed; skip it. */
1475 }
1476
1477 if (memcmp(szInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1478 {
1479 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1480 continue; /* skip it. */
1481 }
1482
1483 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1484 AssertRC(rc);
1485
1486#ifdef LOG_ENABLED
1487 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1488 if (VBOX_SUCCESS(rc))
1489 Log(("Original instr: %s\n", szOutput));
1490#endif
1491 }
1492 pVM->hwaccm.s.svm.cPatches = 0;
1493 pVM->hwaccm.s.svm.PatchTree = 0;
1494 pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1495 pVM->hwaccm.s.svm.fTPRPatchingActive = false;
1496 return VINF_SUCCESS;
1497}
1498
1499/**
1500 * Enable patching in a VT-x/AMD-V guest
1501 *
1502 * @returns VBox status code.
1503 * @param pVM The VM to operate on.
1504 * @param idCpu VCPU to execute hwaccmR3RemovePatches on
1505 * @param pPatchMem Patch memory range
1506 * @param cbPatchMem Size of the memory range
1507 */
1508int hwaccmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1509{
1510 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)idCpu);
1511 AssertRC(rc);
1512
1513 pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1514 pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1515 pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1516 return VINF_SUCCESS;
1517}
1518
1519/**
1520 * Enable patching in a VT-x/AMD-V guest
1521 *
1522 * @returns VBox status code.
1523 * @param pVM The VM to operate on.
1524 * @param pPatchMem Patch memory range
1525 * @param cbPatchMem Size of the memory range
1526 */
1527VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1528{
1529 Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1530
1531 /* Current TPR patching only applies to AMD cpus.
1532 * Needs to be extended to Intel CPUs without the APIC TPR hardware optimization.
1533 */
1534 if (CPUMGetCPUVendor(pVM) != CPUMCPUVENDOR_AMD)
1535 return VERR_NOT_SUPPORTED;
1536
1537 if (pVM->cCpus > 1)
1538 {
1539 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1540 int rc = VMR3ReqCallNoWaitU(pVM->pUVM, VMCPUID_ANY_QUEUE,
1541 (PFNRT)hwaccmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1542 AssertRC(rc);
1543 return rc;
1544 }
1545 return hwaccmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1546}
1547
1548/**
1549 * Disable patching in a VT-x/AMD-V guest
1550 *
1551 * @returns VBox status code.
1552 * @param pVM The VM to operate on.
1553 * @param pPatchMem Patch memory range
1554 * @param cbPatchMem Size of the memory range
1555 */
1556VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1557{
1558 Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1559
1560 Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1561 Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1562
1563 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1564 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)VMMGetCpuId(pVM));
1565 AssertRC(rc);
1566
1567 pVM->hwaccm.s.pGuestPatchMem = 0;
1568 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1569 pVM->hwaccm.s.cbGuestPatchMem = 0;
1570 pVM->hwaccm.s.svm.fTPRPatchingActive = false;
1571 return VINF_SUCCESS;
1572}
1573
1574
1575/**
1576 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1577 *
1578 * @returns VBox strict status code.
1579 * @param pVM The VM handle.
1580 * @param pVCpu The VMCPU for the EMT we're being called on.
1581 * @param pvUser User specified CPU context
1582 *
1583 */
1584DECLCALLBACK(VBOXSTRICTRC) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1585{
1586 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1587 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1588 RTGCPTR oldrip = pCtx->rip;
1589 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1590 unsigned cbOp;
1591
1592 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1593 if (pVCpu->idCpu != idCpu)
1594 return VINF_SUCCESS;
1595
1596 Log(("hwaccmR3ReplaceTprInstr: %RGv\n", pCtx->rip));
1597
1598 /* Two or more VCPUs were racing to patch this instruction. */
1599 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.svm.PatchTree, (AVLOU32KEY)pCtx->eip);
1600 if (pPatch)
1601 return VINF_SUCCESS;
1602
1603 Assert(pVM->hwaccm.s.svm.cPatches < RT_ELEMENTS(pVM->hwaccm.s.svm.aPatches));
1604
1605 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1606 AssertRC(rc);
1607 if ( rc == VINF_SUCCESS
1608 && pDis->pCurInstr->opcode == OP_MOV
1609 && cbOp >= 3)
1610 {
1611 uint8_t aVMMCall[3] = { 0xf, 0x1, 0xd9};
1612 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1613 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1614
1615 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1616 AssertRC(rc);
1617
1618 pPatch->cbOp = cbOp;
1619
1620 if (pDis->param1.flags == USE_DISPLACEMENT32)
1621 {
1622 /* write. */
1623 if (pDis->param2.flags == USE_REG_GEN32)
1624 {
1625 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1626 pPatch->uSrcOperand = pDis->param2.base.reg_gen;
1627 }
1628 else
1629 {
1630 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1631 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1632 pPatch->uSrcOperand = pDis->param2.parval;
1633 }
1634 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1635 AssertRC(rc);
1636
1637 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1638 pPatch->cbNewOp = sizeof(aVMMCall);
1639 }
1640 else
1641 {
1642 RTGCPTR oldrip = pCtx->rip;
1643 uint32_t oldcbOp = cbOp;
1644 uint32_t uMmioReg = pDis->param1.base.reg_gen;
1645
1646 /* read */
1647 Assert(pDis->param1.flags == USE_REG_GEN32);
1648
1649 /* Found:
1650 * mov eax, dword [fffe0080] (5 bytes)
1651 * Check if next instruction is:
1652 * shr eax, 4
1653 */
1654 pCtx->rip += cbOp;
1655 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1656 pCtx->rip = oldrip;
1657 if ( rc == VINF_SUCCESS
1658 && pDis->pCurInstr->opcode == OP_SHR
1659 && pDis->param1.flags == USE_REG_GEN32
1660 && pDis->param1.base.reg_gen == uMmioReg
1661 && pDis->param2.flags == USE_IMMEDIATE8
1662 && pDis->param2.parval == 4
1663 && oldcbOp + cbOp < sizeof(pVM->hwaccm.s.svm.aPatches[idx].aOpcode))
1664 {
1665 uint8_t szInstr[15];
1666
1667 /* Replacing two instructions now. */
1668 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, oldcbOp + cbOp);
1669 AssertRC(rc);
1670
1671 pPatch->cbOp = oldcbOp + cbOp;
1672
1673 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1674 szInstr[0] = 0xF0;
1675 szInstr[1] = 0x0F;
1676 szInstr[2] = 0x20;
1677 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
1678 for (unsigned i = 4; i < pPatch->cbOp; i++)
1679 szInstr[i] = 0x90; /* nop */
1680
1681 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, pPatch->cbOp);
1682 AssertRC(rc);
1683
1684 memcpy(pPatch->aNewOpcode, szInstr, pPatch->cbOp);
1685 pPatch->cbNewOp = pPatch->cbOp;
1686
1687 Log(("Acceptable read/shr candidate!\n"));
1688 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1689 }
1690 else
1691 {
1692 pPatch->enmType = HWACCMTPRINSTR_READ;
1693 pPatch->uDstOperand = pDis->param1.base.reg_gen;
1694
1695 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1696 AssertRC(rc);
1697
1698 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1699 pPatch->cbNewOp = sizeof(aVMMCall);
1700 }
1701 }
1702
1703 pPatch->Core.Key = pCtx->eip;
1704 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1705 AssertRC(rc);
1706
1707 pVM->hwaccm.s.svm.cPatches++;
1708 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceSuccess);
1709 return VINF_SUCCESS;
1710 }
1711
1712 /* Save invalid patch, so we will not try again. */
1713 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1714
1715#ifdef LOG_ENABLED
1716 char szOutput[256];
1717 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1718 if (VBOX_SUCCESS(rc))
1719 Log(("Failed to patch instr: %s\n", szOutput));
1720#endif
1721
1722 pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1723 pPatch->Core.Key = pCtx->eip;
1724 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1725 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1726 AssertRC(rc);
1727 pVM->hwaccm.s.svm.cPatches++;
1728 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceFailure);
1729 return VINF_SUCCESS;
1730}
1731
1732/**
1733 * Callback to patch a TPR instruction (jump to generated code)
1734 *
1735 * @returns VBox strict status code.
1736 * @param pVM The VM handle.
1737 * @param pVCpu The VMCPU for the EMT we're being called on.
1738 * @param pvUser User specified CPU context
1739 *
1740 */
1741DECLCALLBACK(VBOXSTRICTRC) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1742{
1743 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1744 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1745 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1746 unsigned cbOp;
1747 int rc;
1748#ifdef LOG_ENABLED
1749 RTGCPTR pInstr;
1750 char szOutput[256];
1751#endif
1752
1753 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1754 if (pVCpu->idCpu != idCpu)
1755 return VINF_SUCCESS;
1756
1757 Assert(pVM->hwaccm.s.svm.cPatches < RT_ELEMENTS(pVM->hwaccm.s.svm.aPatches));
1758
1759 /* Two or more VCPUs were racing to patch this instruction. */
1760 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.svm.PatchTree, (AVLOU32KEY)pCtx->eip);
1761 if (pPatch)
1762 {
1763 Log(("hwaccmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
1764 return VINF_SUCCESS;
1765 }
1766
1767 Log(("hwaccmR3PatchTprInstr %RGv\n", pCtx->rip));
1768
1769 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1770 AssertRC(rc);
1771 if ( rc == VINF_SUCCESS
1772 && pDis->pCurInstr->opcode == OP_MOV
1773 && cbOp >= 5)
1774 {
1775 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1776 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1777 uint8_t aPatch[64];
1778 uint32_t off = 0;
1779
1780#ifdef LOG_ENABLED
1781 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1782 if (VBOX_SUCCESS(rc))
1783 Log(("Original instr: %s\n", szOutput));
1784#endif
1785
1786 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1787 AssertRC(rc);
1788
1789 pPatch->cbOp = cbOp;
1790 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
1791
1792 if (pDis->param1.flags == USE_DISPLACEMENT32)
1793 {
1794 /*
1795 * TPR write:
1796 *
1797 * push ECX [51]
1798 * push EDX [52]
1799 * push EAX [50]
1800 * xor EDX,EDX [31 D2]
1801 * mov EAX,EAX [89 C0]
1802 * or
1803 * mov EAX,0000000CCh [B8 CC 00 00 00]
1804 * mov ECX,0C0000082h [B9 82 00 00 C0]
1805 * wrmsr [0F 30]
1806 * pop EAX [58]
1807 * pop EDX [5A]
1808 * pop ECX [59]
1809 * jmp return_address [E9 return_address]
1810 *
1811 */
1812 bool fUsesEax = (pDis->param2.flags == USE_REG_GEN32 && pDis->param2.base.reg_gen == USE_REG_EAX);
1813
1814 aPatch[off++] = 0x51; /* push ecx */
1815 aPatch[off++] = 0x52; /* push edx */
1816 if (!fUsesEax)
1817 aPatch[off++] = 0x50; /* push eax */
1818 aPatch[off++] = 0x31; /* xor edx, edx */
1819 aPatch[off++] = 0xD2;
1820 if (pDis->param2.flags == USE_REG_GEN32)
1821 {
1822 if (!fUsesEax)
1823 {
1824 aPatch[off++] = 0x89; /* mov eax, src_reg */
1825 aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, USE_REG_EAX);
1826 }
1827 }
1828 else
1829 {
1830 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1831 aPatch[off++] = 0xB8; /* mov eax, immediate */
1832 *(uint32_t *)&aPatch[off] = pDis->param2.parval;
1833 off += sizeof(uint32_t);
1834 }
1835 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1836 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1837 off += sizeof(uint32_t);
1838
1839 aPatch[off++] = 0x0F; /* wrmsr */
1840 aPatch[off++] = 0x30;
1841 if (!fUsesEax)
1842 aPatch[off++] = 0x58; /* pop eax */
1843 aPatch[off++] = 0x5A; /* pop edx */
1844 aPatch[off++] = 0x59; /* pop ecx */
1845 }
1846 else
1847 {
1848 /*
1849 * TPR read:
1850 *
1851 * push ECX [51]
1852 * push EDX [52]
1853 * push EAX [50]
1854 * mov ECX,0C0000082h [B9 82 00 00 C0]
1855 * rdmsr [0F 32]
1856 * mov EAX,EAX [89 C0]
1857 * pop EAX [58]
1858 * pop EDX [5A]
1859 * pop ECX [59]
1860 * jmp return_address [E9 return_address]
1861 *
1862 */
1863 Assert(pDis->param1.flags == USE_REG_GEN32);
1864
1865 if (pDis->param1.base.reg_gen != USE_REG_ECX)
1866 aPatch[off++] = 0x51; /* push ecx */
1867 if (pDis->param1.base.reg_gen != USE_REG_EDX)
1868 aPatch[off++] = 0x52; /* push edx */
1869 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1870 aPatch[off++] = 0x50; /* push eax */
1871
1872 aPatch[off++] = 0x31; /* xor edx, edx */
1873 aPatch[off++] = 0xD2;
1874
1875 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1876 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1877 off += sizeof(uint32_t);
1878
1879 aPatch[off++] = 0x0F; /* rdmsr */
1880 aPatch[off++] = 0x32;
1881
1882 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1883 {
1884 aPatch[off++] = 0x89; /* mov dst_reg, eax */
1885 aPatch[off++] = MAKE_MODRM(3, USE_REG_EAX, pDis->param1.base.reg_gen);
1886 }
1887
1888 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1889 aPatch[off++] = 0x58; /* pop eax */
1890 if (pDis->param1.base.reg_gen != USE_REG_EDX)
1891 aPatch[off++] = 0x5A; /* pop edx */
1892 if (pDis->param1.base.reg_gen != USE_REG_ECX)
1893 aPatch[off++] = 0x59; /* pop ecx */
1894 }
1895 aPatch[off++] = 0xE9; /* jmp return_address */
1896 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
1897 off += sizeof(RTRCUINTPTR);
1898
1899 if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
1900 {
1901 /* Write new code to the patch buffer. */
1902 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
1903 AssertRC(rc);
1904
1905#ifdef LOG_ENABLED
1906 pInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
1907 while (true)
1908 {
1909 uint32_t cb;
1910
1911 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pInstr, 0, szOutput, sizeof(szOutput), &cb);
1912 if (VBOX_SUCCESS(rc))
1913 Log(("Patch instr %s\n", szOutput));
1914
1915 pInstr += cb;
1916
1917 if (pInstr >= pVM->hwaccm.s.pFreeGuestPatchMem + off)
1918 break;
1919 }
1920#endif
1921
1922 pPatch->aNewOpcode[0] = 0xE9;
1923 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
1924
1925 /* Overwrite the TPR instruction with a jump. */
1926 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
1927 AssertRC(rc);
1928
1929#ifdef LOG_ENABLED
1930 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1931 if (VBOX_SUCCESS(rc))
1932 Log(("Jump: %s\n", szOutput));
1933#endif
1934 pVM->hwaccm.s.pFreeGuestPatchMem += off;
1935 pPatch->cbNewOp = 5;
1936
1937 pPatch->Core.Key = pCtx->eip;
1938 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1939 AssertRC(rc);
1940
1941 pVM->hwaccm.s.svm.cPatches++;
1942 pVM->hwaccm.s.svm.fTPRPatchingActive = true;
1943 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchSuccess);
1944 return VINF_SUCCESS;
1945 }
1946 else
1947 Log(("Ran out of space in our patch buffer!\n"));
1948 }
1949
1950 /* Save invalid patch, so we will not try again. */
1951 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1952
1953#ifdef LOG_ENABLED
1954 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1955 if (VBOX_SUCCESS(rc))
1956 Log(("Failed to patch instr: %s\n", szOutput));
1957#endif
1958
1959 pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1960 pPatch->Core.Key = pCtx->eip;
1961 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1962 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1963 AssertRC(rc);
1964 pVM->hwaccm.s.svm.cPatches++;
1965 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchFailure);
1966 return VINF_SUCCESS;
1967}
1968
1969/**
1970 * Attempt to patch TPR mmio instructions
1971 *
1972 * @returns VBox status code.
1973 * @param pVM The VM to operate on.
1974 * @param pVCpu The VM CPU to operate on.
1975 * @param pCtx CPU context
1976 */
1977VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1978{
1979 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, (pVM->hwaccm.s.pGuestPatchMem) ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr, (void *)pVCpu->idCpu);
1980 AssertRC(rc);
1981 return rc;
1982}
1983
1984/**
1985 * Force execution of the current IO code in the recompiler
1986 *
1987 * @returns VBox status code.
1988 * @param pVM The VM to operate on.
1989 * @param pCtx Partial VM execution context
1990 */
1991VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
1992{
1993 PVMCPU pVCpu = VMMGetCpu(pVM);
1994
1995 Assert(pVM->fHWACCMEnabled);
1996 Log(("HWACCMR3EmulateIoBlock\n"));
1997
1998 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
1999 if (HWACCMCanEmulateIoBlockEx(pCtx))
2000 {
2001 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
2002 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
2003 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2004 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2005 return VINF_EM_RESCHEDULE_REM;
2006 }
2007 return VINF_SUCCESS;
2008}
2009
2010/**
2011 * Checks if we can currently use hardware accelerated raw mode.
2012 *
2013 * @returns boolean
2014 * @param pVM The VM to operate on.
2015 * @param pCtx Partial VM execution context
2016 */
2017VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2018{
2019 PVMCPU pVCpu = VMMGetCpu(pVM);
2020
2021 Assert(pVM->fHWACCMEnabled);
2022
2023 /* If we're still executing the IO code, then return false. */
2024 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
2025 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2026 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2027 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
2028 return false;
2029
2030 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
2031
2032 /* AMD-V supports real & protected mode with or without paging. */
2033 if (pVM->hwaccm.s.svm.fEnabled)
2034 {
2035 pVCpu->hwaccm.s.fActive = true;
2036 return true;
2037 }
2038
2039 pVCpu->hwaccm.s.fActive = false;
2040
2041 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2042#ifdef HWACCM_VMX_EMULATE_REALMODE
2043 if (pVM->hwaccm.s.vmx.pRealModeTSS)
2044 {
2045 if (CPUMIsGuestInRealModeEx(pCtx))
2046 {
2047 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
2048 * The base must also be equal to (sel << 4).
2049 */
2050 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
2051 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
2052 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
2053 || pCtx->es != (pCtx->esHid.u64Base >> 4)
2054 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
2055 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
2056 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
2057 {
2058 return false;
2059 }
2060 }
2061 else
2062 {
2063 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2064 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
2065 * from real to protected mode. (all sorts of RPL & DPL assumptions)
2066 */
2067 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2068 && enmGuestMode >= PGMMODE_PROTECTED)
2069 {
2070 if ( (pCtx->cs & X86_SEL_RPL)
2071 || (pCtx->ds & X86_SEL_RPL)
2072 || (pCtx->es & X86_SEL_RPL)
2073 || (pCtx->fs & X86_SEL_RPL)
2074 || (pCtx->gs & X86_SEL_RPL)
2075 || (pCtx->ss & X86_SEL_RPL))
2076 {
2077 return false;
2078 }
2079 }
2080 }
2081 }
2082 else
2083#endif /* HWACCM_VMX_EMULATE_REALMODE */
2084 {
2085 if (!CPUMIsGuestInLongModeEx(pCtx))
2086 {
2087 /** @todo This should (probably) be set on every excursion to the REM,
2088 * however it's too risky right now. So, only apply it when we go
2089 * back to REM for real mode execution. (The XP hack below doesn't
2090 * work reliably without this.)
2091 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2092 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2093
2094 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2095 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
2096 return false;
2097
2098 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2099 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2100 * hidden registers (possible recompiler bug; see load_seg_vm) */
2101 if (pCtx->csHid.Attr.n.u1Present == 0)
2102 return false;
2103 if (pCtx->ssHid.Attr.n.u1Present == 0)
2104 return false;
2105
2106 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2107 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2108 /** @todo This check is actually wrong, it doesn't take the direction of the
2109 * stack segment into account. But, it does the job for now. */
2110 if (pCtx->rsp >= pCtx->ssHid.u32Limit)
2111 return false;
2112#if 0
2113 if ( pCtx->cs >= pCtx->gdtr.cbGdt
2114 || pCtx->ss >= pCtx->gdtr.cbGdt
2115 || pCtx->ds >= pCtx->gdtr.cbGdt
2116 || pCtx->es >= pCtx->gdtr.cbGdt
2117 || pCtx->fs >= pCtx->gdtr.cbGdt
2118 || pCtx->gs >= pCtx->gdtr.cbGdt)
2119 return false;
2120#endif
2121 }
2122 }
2123
2124 if (pVM->hwaccm.s.vmx.fEnabled)
2125 {
2126 uint32_t mask;
2127
2128 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2129 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2130 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2131 mask &= ~X86_CR0_NE;
2132
2133#ifdef HWACCM_VMX_EMULATE_REALMODE
2134 if (pVM->hwaccm.s.vmx.pRealModeTSS)
2135 {
2136 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2137 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2138 }
2139 else
2140#endif
2141 {
2142 /* We support protected mode without paging using identity mapping. */
2143 mask &= ~X86_CR0_PG;
2144 }
2145 if ((pCtx->cr0 & mask) != mask)
2146 return false;
2147
2148 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2149 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2150 if ((pCtx->cr0 & mask) != 0)
2151 return false;
2152
2153 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2154 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2155 mask &= ~X86_CR4_VMXE;
2156 if ((pCtx->cr4 & mask) != mask)
2157 return false;
2158
2159 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2160 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2161 if ((pCtx->cr4 & mask) != 0)
2162 return false;
2163
2164 pVCpu->hwaccm.s.fActive = true;
2165 return true;
2166 }
2167
2168 return false;
2169}
2170
2171/**
2172 * Notifcation from EM about a rescheduling into hardware assisted execution
2173 * mode.
2174 *
2175 * @param pVCpu Pointer to the current virtual cpu structure.
2176 */
2177VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2178{
2179 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2180}
2181
2182/**
2183 * Notifcation from EM about returning from instruction emulation (REM / EM).
2184 *
2185 * @param pVCpu Pointer to the current virtual cpu structure.
2186 */
2187VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2188{
2189 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2190}
2191
2192/**
2193 * Checks if we are currently using hardware accelerated raw mode.
2194 *
2195 * @returns boolean
2196 * @param pVCpu The VMCPU to operate on.
2197 */
2198VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2199{
2200 return pVCpu->hwaccm.s.fActive;
2201}
2202
2203/**
2204 * Checks if we are currently using nested paging.
2205 *
2206 * @returns boolean
2207 * @param pVM The VM to operate on.
2208 */
2209VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2210{
2211 return pVM->hwaccm.s.fNestedPaging;
2212}
2213
2214/**
2215 * Checks if we are currently using VPID in VT-x mode.
2216 *
2217 * @returns boolean
2218 * @param pVM The VM to operate on.
2219 */
2220VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2221{
2222 return pVM->hwaccm.s.vmx.fVPID;
2223}
2224
2225
2226/**
2227 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2228 *
2229 * @returns boolean
2230 * @param pVM The VM to operate on.
2231 */
2232VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2233{
2234 return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2235}
2236
2237/**
2238 * Restart an I/O instruction that was refused in ring-0
2239 *
2240 * @returns Strict VBox status code. Informational status codes other than the one documented
2241 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2242 * @retval VINF_SUCCESS Success.
2243 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2244 * status code must be passed on to EM.
2245 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2246 *
2247 * @param pVM The VM to operate on.
2248 * @param pVCpu The VMCPU to operate on.
2249 * @param pCtx VCPU register context
2250 */
2251VMMR3DECL(VBOXSTRICTRC) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2252{
2253 HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2254
2255 pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2256
2257 if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2258 || enmType == HWACCMPENDINGIO_INVALID)
2259 return VERR_NOT_FOUND;
2260
2261 VBOXSTRICTRC rcStrict;
2262 switch (enmType)
2263 {
2264 case HWACCMPENDINGIO_PORT_READ:
2265 {
2266 uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2267 uint32_t u32Val = 0;
2268
2269 rcStrict = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2270 &u32Val,
2271 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2272 if (IOM_SUCCESS(rcStrict))
2273 {
2274 /* Write back to the EAX register. */
2275 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2276 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2277 }
2278 break;
2279 }
2280
2281 case HWACCMPENDINGIO_PORT_WRITE:
2282 rcStrict = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2283 pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2284 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2285 if (IOM_SUCCESS(rcStrict))
2286 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2287 break;
2288
2289 default:
2290 AssertFailed();
2291 return VERR_INTERNAL_ERROR;
2292 }
2293
2294 return rcStrict;
2295}
2296
2297/**
2298 * Inject an NMI into a running VM (only VCPU 0!)
2299 *
2300 * @returns boolean
2301 * @param pVM The VM to operate on.
2302 */
2303VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2304{
2305 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2306 return VINF_SUCCESS;
2307}
2308
2309/**
2310 * Check fatal VT-x/AMD-V error and produce some meaningful
2311 * log release message.
2312 *
2313 * @param pVM The VM to operate on.
2314 * @param iStatusCode VBox status code
2315 */
2316VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2317{
2318 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2319 {
2320 switch(iStatusCode)
2321 {
2322 case VERR_VMX_INVALID_VMCS_FIELD:
2323 break;
2324
2325 case VERR_VMX_INVALID_VMCS_PTR:
2326 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
2327 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2328 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2329 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2330 break;
2331
2332 case VERR_VMX_UNABLE_TO_START_VM:
2333 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2334 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2335#if 0 /* @todo dump the current control fields to the release log */
2336 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2337 {
2338
2339 }
2340#endif
2341 break;
2342
2343 case VERR_VMX_UNABLE_TO_RESUME_VM:
2344 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2345 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2346 break;
2347
2348 case VERR_VMX_INVALID_VMXON_PTR:
2349 break;
2350 }
2351 }
2352}
2353
2354/**
2355 * Execute state save operation.
2356 *
2357 * @returns VBox status code.
2358 * @param pVM VM Handle.
2359 * @param pSSM SSM operation handle.
2360 */
2361static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2362{
2363 int rc;
2364
2365 Log(("hwaccmR3Save:\n"));
2366
2367 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2368 {
2369 /*
2370 * Save the basic bits - fortunately all the other things can be resynced on load.
2371 */
2372 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2373 AssertRCReturn(rc, rc);
2374 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2375 AssertRCReturn(rc, rc);
2376 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2377 AssertRCReturn(rc, rc);
2378
2379 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2380 AssertRCReturn(rc, rc);
2381 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2382 AssertRCReturn(rc, rc);
2383 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2384 AssertRCReturn(rc, rc);
2385 }
2386#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2387 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2388 AssertRCReturn(rc, rc);
2389 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2390 AssertRCReturn(rc, rc);
2391 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2392 AssertRCReturn(rc, rc);
2393
2394 /* Store all the guest patch records too. */
2395 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.svm.cPatches);
2396 AssertRCReturn(rc, rc);
2397
2398 for (unsigned i = 0; i < pVM->hwaccm.s.svm.cPatches; i++)
2399 {
2400 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[i];
2401
2402 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2403 AssertRCReturn(rc, rc);
2404
2405 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2406 AssertRCReturn(rc, rc);
2407
2408 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2409 AssertRCReturn(rc, rc);
2410
2411 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2412 AssertRCReturn(rc, rc);
2413
2414 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2415 AssertRCReturn(rc, rc);
2416
2417 AssertCompileSize(HWACCMTPRINSTR, 4);
2418 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2419 AssertRCReturn(rc, rc);
2420
2421 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2422 AssertRCReturn(rc, rc);
2423
2424 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2425 AssertRCReturn(rc, rc);
2426
2427 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2428 AssertRCReturn(rc, rc);
2429
2430 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2431 AssertRCReturn(rc, rc);
2432 }
2433#endif
2434 return VINF_SUCCESS;
2435}
2436
2437/**
2438 * Execute state load operation.
2439 *
2440 * @returns VBox status code.
2441 * @param pVM VM Handle.
2442 * @param pSSM SSM operation handle.
2443 * @param uVersion Data layout version.
2444 * @param uPass The data pass.
2445 */
2446static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2447{
2448 int rc;
2449
2450 Log(("hwaccmR3Load:\n"));
2451 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2452
2453 /*
2454 * Validate version.
2455 */
2456 if ( uVersion != HWACCM_SSM_VERSION
2457 && uVersion != HWACCM_SSM_VERSION_NO_PATCHING
2458 && uVersion != HWACCM_SSM_VERSION_2_0_X)
2459 {
2460 AssertMsgFailed(("hwaccmR3Load: Invalid version uVersion=%d!\n", uVersion));
2461 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2462 }
2463 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2464 {
2465 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2466 AssertRCReturn(rc, rc);
2467 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2468 AssertRCReturn(rc, rc);
2469 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2470 AssertRCReturn(rc, rc);
2471
2472 if (uVersion >= HWACCM_SSM_VERSION_NO_PATCHING)
2473 {
2474 uint32_t val;
2475
2476 rc = SSMR3GetU32(pSSM, &val);
2477 AssertRCReturn(rc, rc);
2478 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2479
2480 rc = SSMR3GetU32(pSSM, &val);
2481 AssertRCReturn(rc, rc);
2482 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2483
2484 rc = SSMR3GetU32(pSSM, &val);
2485 AssertRCReturn(rc, rc);
2486 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2487 }
2488 }
2489#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2490 if (uVersion > HWACCM_SSM_VERSION_NO_PATCHING)
2491 {
2492 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2493 AssertRCReturn(rc, rc);
2494 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2495 AssertRCReturn(rc, rc);
2496 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2497 AssertRCReturn(rc, rc);
2498
2499 /* Fetch all TPR patch records. */
2500 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.svm.cPatches);
2501 AssertRCReturn(rc, rc);
2502
2503 for (unsigned i = 0; i < pVM->hwaccm.s.svm.cPatches; i++)
2504 {
2505 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[i];
2506
2507 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2508 AssertRCReturn(rc, rc);
2509
2510 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2511 AssertRCReturn(rc, rc);
2512
2513 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2514 AssertRCReturn(rc, rc);
2515
2516 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2517 AssertRCReturn(rc, rc);
2518
2519 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2520 AssertRCReturn(rc, rc);
2521
2522 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2523 AssertRCReturn(rc, rc);
2524
2525 if (pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT)
2526 pVM->hwaccm.s.svm.fTPRPatchingActive = true;
2527
2528 Assert(pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT || pVM->hwaccm.s.svm.fTPRPatchingActive == false);
2529
2530 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2531 AssertRCReturn(rc, rc);
2532
2533 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2534 AssertRCReturn(rc, rc);
2535
2536 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2537 AssertRCReturn(rc, rc);
2538
2539 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2540 AssertRCReturn(rc, rc);
2541
2542 Log(("hwaccmR3Load: patch %d\n", i));
2543 Log(("Key = %x\n", pPatch->Core.Key));
2544 Log(("cbOp = %d\n", pPatch->cbOp));
2545 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2546 Log(("type = %d\n", pPatch->enmType));
2547 Log(("srcop = %d\n", pPatch->uSrcOperand));
2548 Log(("dstop = %d\n", pPatch->uDstOperand));
2549 Log(("cFaults = %d\n", pPatch->cFaults));
2550 Log(("target = %x\n", pPatch->pJumpTarget));
2551 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
2552 AssertRC(rc);
2553 }
2554 }
2555#endif
2556 return VINF_SUCCESS;
2557}
2558
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