VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 24869

Last change on this file since 24869 was 24869, checked in by vboxsync, 15 years ago

Compile fix
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1/* $Id: HWACCM.cpp 24869 2009-11-23 13:37:22Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/csam.h>
35#include <VBox/selm.h>
36#include <VBox/rem.h>
37#include <VBox/hwacc_vmx.h>
38#include <VBox/hwacc_svm.h>
39#include "HWACCMInternal.h"
40#include <VBox/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/string.h>
48#include <iprt/thread.h>
49
50/*******************************************************************************
51* Global Variables *
52*******************************************************************************/
53#ifdef VBOX_WITH_STATISTICS
54# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55# define EXIT_REASON_NIL() NULL
56/** Exit reason descriptions for VT-x, used to describe statistics. */
57static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58{
59 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67 EXIT_REASON_NIL(),
68 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94 EXIT_REASON_NIL(),
95 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96 EXIT_REASON_NIL(),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101 EXIT_REASON_NIL(),
102 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110 EXIT_REASON_NIL(),
111 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115 EXIT_REASON_NIL()
116};
117/** Exit reason descriptions for AMD-V, used to describe statistics. */
118static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119{
120 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
121 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
122 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
123 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
124 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
125 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
126 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
127 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
128 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
129 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
130 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
131 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
132 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
133 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
134 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
135 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
136 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
137 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
152 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
153 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
154 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
155 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
156 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
157 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
158 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
159 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
160 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
161 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
162 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
163 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
164 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
165 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
166 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
167 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
168 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
169 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
184 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
185 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_INTR , 96, "Physical maskable interrupt."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_NMI , 97, "Physical non-maskable interrupt."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_SMI , 98, "System management interrupt."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_INIT , 99, "Physical INIT signal."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_VINTR ,100, "Visual interrupt."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_IDTR_READ ,102, "Read IDTR"),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_GDTR_READ ,103, "Read GDTR"),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_LDTR_READ ,104, "Read LDTR."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,105, "Read TR."),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,106, "Write IDTR."),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,107, "Write GDTR."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,108, "Write LDTR."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,109, "Write TR."),
230 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
231 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
232 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
233 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
234 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
235 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
236 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
237 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
238 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
239 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
240 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
241 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
242 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
243 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
244 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
245 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
246 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
247 EXIT_REASON(SVM_EXIT_TASK_SHUTDOWN ,127, "Shutdown."),
248 EXIT_REASON(SVM_EXIT_TASK_VMRUN ,128, "VMRUN instruction."),
249 EXIT_REASON(SVM_EXIT_TASK_VMCALL ,129, "VMCALL instruction."),
250 EXIT_REASON(SVM_EXIT_TASK_VMLOAD ,130, "VMLOAD instruction."),
251 EXIT_REASON(SVM_EXIT_TASK_VMSAVE ,131, "VMSAVE instruction."),
252 EXIT_REASON(SVM_EXIT_TASK_STGI ,132, "STGI instruction."),
253 EXIT_REASON(SVM_EXIT_TASK_CLGI ,133, "CLGI instruction."),
254 EXIT_REASON(SVM_EXIT_TASK_SKINIT ,134, "SKINIT instruction."),
255 EXIT_REASON(SVM_EXIT_TASK_RDTSCP ,135, "RDTSCP instruction."),
256 EXIT_REASON(SVM_EXIT_TASK_ICEBP ,136, "ICEBP instruction."),
257 EXIT_REASON(SVM_EXIT_TASK_WBINVD ,137, "WBINVD instruction."),
258 EXIT_REASON(SVM_EXIT_TASK_MONITOR ,138, "MONITOR instruction."),
259 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
260 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
261 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
262 EXIT_REASON_NIL()
263};
264# undef EXIT_REASON
265# undef EXIT_REASON_NIL
266#endif /* VBOX_WITH_STATISTICS */
267
268/*******************************************************************************
269* Internal Functions *
270*******************************************************************************/
271static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
272static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
273
274
275/**
276 * Initializes the HWACCM.
277 *
278 * @returns VBox status code.
279 * @param pVM The VM to operate on.
280 */
281VMMR3DECL(int) HWACCMR3Init(PVM pVM)
282{
283 LogFlow(("HWACCMR3Init\n"));
284
285 /*
286 * Assert alignment and sizes.
287 */
288 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
289 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
290
291 /* Some structure checks. */
292 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
293 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
294 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
295 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
296
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
300 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
303 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
304
305
306 /*
307 * Register the saved state data unit.
308 */
309 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
310 NULL, NULL, NULL,
311 NULL, hwaccmR3Save, NULL,
312 NULL, hwaccmR3Load, NULL);
313 if (RT_FAILURE(rc))
314 return rc;
315
316 /* Misc initialisation. */
317 pVM->hwaccm.s.vmx.fSupported = false;
318 pVM->hwaccm.s.svm.fSupported = false;
319 pVM->hwaccm.s.vmx.fEnabled = false;
320 pVM->hwaccm.s.svm.fEnabled = false;
321
322 pVM->hwaccm.s.fNestedPaging = false;
323
324 /* Disabled by default. */
325 pVM->fHWACCMEnabled = false;
326
327 /*
328 * Check CFGM options.
329 */
330 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
331 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
332 /* Nested paging: disabled by default. */
333 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
334 AssertRC(rc);
335
336 /* VT-x VPID: disabled by default. */
337 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
338 AssertRC(rc);
339
340 /* HWACCM support must be explicitely enabled in the configuration file. */
341 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
342 AssertRC(rc);
343
344 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
345 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hwaccm.s.fTRPPatchingAllowed, false);
346 AssertRC(rc);
347
348#ifdef RT_OS_DARWIN
349 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
350#else
351 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
352#endif
353 {
354 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
355 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
356 return VERR_HWACCM_CONFIG_MISMATCH;
357 }
358
359 if (VMMIsHwVirtExtForced(pVM))
360 pVM->fHWACCMEnabled = true;
361
362#if HC_ARCH_BITS == 32
363 /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
364 * (To use the default, don't set 64bitEnabled in CFGM.) */
365 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
366 AssertLogRelRCReturn(rc, rc);
367 if (pVM->hwaccm.s.fAllow64BitGuests)
368 {
369# ifdef RT_OS_DARWIN
370 if (!VMMIsHwVirtExtForced(pVM))
371# else
372 if (!pVM->hwaccm.s.fAllowed)
373# endif
374 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
375 }
376#else
377 /* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
378 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
379 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
380 AssertLogRelRCReturn(rc, rc);
381#endif
382
383
384 /** Determine the init method for AMD-V and VT-x; either one global init for each host CPU
385 * or local init each time we wish to execute guest code.
386 *
387 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
388 */
389 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hwaccm.s.fGlobalInit,
390#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
391 false
392#else
393 true
394#endif
395 );
396
397 /* Max number of resume loops. */
398 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
399 AssertRC(rc);
400
401 return VINF_SUCCESS;
402}
403
404/**
405 * Initializes the per-VCPU HWACCM.
406 *
407 * @returns VBox status code.
408 * @param pVM The VM to operate on.
409 */
410VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
411{
412 LogFlow(("HWACCMR3InitCPU\n"));
413
414 for (VMCPUID i = 0; i < pVM->cCpus; i++)
415 {
416 PVMCPU pVCpu = &pVM->aCpus[i];
417
418 pVCpu->hwaccm.s.fActive = false;
419 }
420
421#ifdef VBOX_WITH_STATISTICS
422 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
423 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
424 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
425 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
426
427 /*
428 * Statistics.
429 */
430 for (VMCPUID i = 0; i < pVM->cCpus; i++)
431 {
432 PVMCPU pVCpu = &pVM->aCpus[i];
433 int rc;
434
435 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of RTMpPokeCpu",
436 "/PROF/HWACCM/CPU%d/Poke", i);
437 AssertRC(rc);
438 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait",
439 "/PROF/HWACCM/CPU%d/PokeWait", i);
440 AssertRC(rc);
441 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait when RTMpPokeCpu fails",
442 "/PROF/HWACCM/CPU%d/PokeWaitFailed", i);
443 AssertRC(rc);
444 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
445 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
446 AssertRC(rc);
447 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
448 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
449 AssertRC(rc);
450 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
451 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
452 AssertRC(rc);
453# if 1 /* temporary for tracking down darwin holdup. */
454 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
455 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
456 AssertRC(rc);
457 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
458 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
459 AssertRC(rc);
460 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
461 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
462 AssertRC(rc);
463# endif
464 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
465 "/PROF/HWACCM/CPU%d/InGC", i);
466 AssertRC(rc);
467
468# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
469 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
470 "/PROF/HWACCM/CPU%d/Switcher3264", i);
471 AssertRC(rc);
472# endif
473
474# define HWACCM_REG_COUNTER(a, b) \
475 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
476 AssertRC(rc);
477
478 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
479 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
480 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
481 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
482 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
483 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
484 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
485 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
486 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
487 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
488 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
489 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
490 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
491 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
492 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
493 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
494 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
495 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
496 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
498 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
499 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
503 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
504 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
505 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
506 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
507 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
508 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
509 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
510 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
511 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
512 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
513 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
514 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
515
516 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
517 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
518
519 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
520 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
521 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
522
523 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPage, "/HWACCM/CPU%d/Flush/Page");
524 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
525 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
526 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLB, "/HWACCM/CPU%d/Flush/TLB");
527 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
528 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
529 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
530 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
531 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
532 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
533 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
534 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
535 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
536
537 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
538 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
539 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow, "/HWACCM/CPU%d/TSC/InterceptOverflow");
540
541 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
542 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
543 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
544
545 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
546 {
547 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
548 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
549 AssertRC(rc);
550 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
551 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
552 AssertRC(rc);
553 }
554
555#undef HWACCM_REG_COUNTER
556
557 pVCpu->hwaccm.s.paStatExitReason = NULL;
558
559 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
560 AssertRC(rc);
561 if (RT_SUCCESS(rc))
562 {
563 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
564 for (int j=0;j<MAX_EXITREASON_STAT;j++)
565 {
566 if (papszDesc[j])
567 {
568 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
569 papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
570 AssertRC(rc);
571 }
572 }
573 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
574 AssertRC(rc);
575 }
576 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
577# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
578 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
579# else
580 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
581# endif
582
583 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
584 AssertRCReturn(rc, rc);
585 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
586# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
587 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
588# else
589 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
590# endif
591 for (unsigned j = 0; j < 255; j++)
592 STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
593 (j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
594
595 }
596#endif /* VBOX_WITH_STATISTICS */
597
598#ifdef VBOX_WITH_CRASHDUMP_MAGIC
599 /* Magic marker for searching in crash dumps. */
600 for (VMCPUID i = 0; i < pVM->cCpus; i++)
601 {
602 PVMCPU pVCpu = &pVM->aCpus[i];
603
604 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
605 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
606 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
607 }
608#endif
609 return VINF_SUCCESS;
610}
611
612/**
613 * Turns off normal raw mode features
614 *
615 * @param pVM The VM to operate on.
616 */
617static void hwaccmR3DisableRawMode(PVM pVM)
618{
619 /* Disable PATM & CSAM. */
620 PATMR3AllowPatching(pVM, false);
621 CSAMDisableScanning(pVM);
622
623 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
624 SELMR3DisableMonitoring(pVM);
625 TRPMR3DisableMonitoring(pVM);
626
627 /* Disable the switcher code (safety precaution). */
628 VMMR3DisableSwitcher(pVM);
629
630 /* Disable mapping of the hypervisor into the shadow page table. */
631 PGMR3MappingsDisable(pVM);
632
633 /* Disable the switcher */
634 VMMR3DisableSwitcher(pVM);
635
636 /* Reinit the paging mode to force the new shadow mode. */
637 for (VMCPUID i = 0; i < pVM->cCpus; i++)
638 {
639 PVMCPU pVCpu = &pVM->aCpus[i];
640
641 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
642 }
643}
644
645/**
646 * Initialize VT-x or AMD-V.
647 *
648 * @returns VBox status code.
649 * @param pVM The VM handle.
650 */
651VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
652{
653 int rc;
654
655 if ( !pVM->hwaccm.s.vmx.fSupported
656 && !pVM->hwaccm.s.svm.fSupported)
657 {
658 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
659 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
660 if (VMMIsHwVirtExtForced(pVM))
661 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
662 return VINF_SUCCESS;
663 }
664
665 if (pVM->hwaccm.s.vmx.fSupported)
666 {
667 rc = SUPR3QueryVTxSupported();
668 if (RT_FAILURE(rc))
669 {
670#ifdef RT_OS_LINUX
671 LogRel(("HWACCM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
672#else
673 LogRel(("HWACCM: The host kernel does not support VT-x!\n"));
674#endif
675 if ( pVM->cCpus > 1
676 || VMMIsHwVirtExtForced(pVM))
677 return rc;
678
679 /* silently fall back to raw mode */
680 return VINF_SUCCESS;
681 }
682 }
683
684 if (!pVM->hwaccm.s.fAllowed)
685 return VINF_SUCCESS; /* nothing to do */
686
687 /* Enable VT-x or AMD-V on all host CPUs. */
688 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
689 if (RT_FAILURE(rc))
690 {
691 LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
692 return rc;
693 }
694 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
695
696 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
697 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
698 if (!pVM->hwaccm.s.fHasIoApic)
699 {
700 Assert(!pVM->hwaccm.s.fTRPPatchingAllowed); /* paranoia */
701 pVM->hwaccm.s.fTRPPatchingAllowed = false;
702 }
703
704 if (pVM->hwaccm.s.vmx.fSupported)
705 {
706 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
707
708 if ( pVM->hwaccm.s.fInitialized == false
709 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
710 {
711 uint64_t val;
712 RTGCPHYS GCPhys = 0;
713
714 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
715 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
716 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
717 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
718 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
719 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
720 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
721 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
722
723 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
724 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
725 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
726 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
727 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
728 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
729 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
730 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
731 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
732 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
733 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
734 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
735 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
736 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
737 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
738 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
739 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
740 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
741 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
742
743 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
744 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
745 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
746 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
747 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
748 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
749 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
750 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
751 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
752 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
753 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
754 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
755 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
756 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
757 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
758 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
759 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
760 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
761 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
762 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
763 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
764 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
765 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
766 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
767 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
768 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
769 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
770 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
771 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
772 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
773 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
774 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
775 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
776 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
777 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
778 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
779 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
780 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
781 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
782 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
783 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
784 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
785 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
786 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
787
788 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
789 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
790 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
791 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
792 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
793 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
794 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
795 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
796 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
797 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
798 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
799 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
800 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
801 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
802 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
803 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
804 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
805 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
806 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
807 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
808 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
809 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
810 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
811 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
812 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
813 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
814 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
815 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
816 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
817 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
818 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
819 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
820 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
821 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
822 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
823 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
824 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
825 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
826 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
827 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
828 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
829 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
830 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
831
832 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
833 {
834 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
835 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
836 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
837 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
838 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
839 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
840 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
841 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
842 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
843 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT\n"));
844 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
845 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
846 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
847 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
848 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
849 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
850 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
851 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE\n"));
852 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
853 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT\n"));
854
855 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
856 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
857 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
858 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
859 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
860 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
861 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT *must* be set\n"));
862 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
863 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
864 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
865 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
866 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
867 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
868 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
869 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
870 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
871 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE *must* be set\n"));
872 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
873 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT *must* be set\n"));
874 }
875
876 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
877 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
878 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
879 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
880 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
881 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
882 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
883 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
884 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
885 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
886 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
887 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
888 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
889 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
890 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
891 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
892 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
893 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
894 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
895 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
896 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
897 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
898 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
899 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
900 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
901 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
902 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
903 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
904 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
905 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
906 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
907
908 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
909 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
910 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
911 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
912 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
913 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
914 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
915 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
916 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
917 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
918 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
919 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
920 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
921 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
922 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
923 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
924 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
925 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
926 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
927 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
928 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
929 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
930 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
931 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
932 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
933 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
934 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
935 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
936 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
937 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
938 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
939 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
940 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
941 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
942 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
943
944 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
945 {
946 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
947
948 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
949 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
950 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
951 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
952 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
953 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
954 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
955 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
956 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
957 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
958 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
959 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
960 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
961 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
962 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
963 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
964 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
965 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
966 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
967 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
968 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
969 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
970 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
971 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
972 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
973 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
974 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
975 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
976 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
977 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
978 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
979 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
980 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
981 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
982 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
983 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
984 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
985 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
986 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
987 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
988 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
989 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
990 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
991 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
992 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
993 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
994 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
995 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
996 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
997 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
998 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
999 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
1000 }
1001
1002 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
1003 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1004 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1005 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1006 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1007 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1008
1009 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
1010 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
1011 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
1012 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
1013 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
1014
1015 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
1016
1017 /* Paranoia */
1018 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc) >= 512);
1019
1020 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1021 {
1022 LogRel(("HWACCM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pMSRBitmapPhys));
1023 LogRel(("HWACCM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1024 }
1025
1026#ifdef HWACCM_VTX_WITH_EPT
1027 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1028 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1029#endif /* HWACCM_VTX_WITH_EPT */
1030#ifdef HWACCM_VTX_WITH_VPID
1031 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1032 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
1033 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
1034#endif /* HWACCM_VTX_WITH_VPID */
1035
1036 /* Only try once. */
1037 pVM->hwaccm.s.fInitialized = true;
1038
1039 /* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
1040#if 1
1041 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
1042#else
1043 rc = VERR_NO_MEMORY; /* simulation of no VMMDev Heap. */
1044#endif
1045 if (RT_SUCCESS(rc))
1046 {
1047 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1048 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
1049 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
1050 /* Bit set to 0 means redirection enabled. */
1051 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
1052 /* Allow all port IO, so the VT-x IO intercepts do their job. */
1053 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
1054 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
1055
1056 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1057 * real and protected mode without paging with EPT.
1058 */
1059 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1060 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
1061 {
1062 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1063 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
1064 }
1065
1066 /* We convert it here every time as pci regions could be reconfigured. */
1067 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1068 AssertRC(rc);
1069 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1070
1071 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1072 AssertRC(rc);
1073 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1074 }
1075 else
1076 {
1077 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1078 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1079 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1080 }
1081
1082 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1083 AssertRC(rc);
1084 if (rc == VINF_SUCCESS)
1085 {
1086 pVM->fHWACCMEnabled = true;
1087 pVM->hwaccm.s.vmx.fEnabled = true;
1088 hwaccmR3DisableRawMode(pVM);
1089
1090 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1091#ifdef VBOX_ENABLE_64_BITS_GUESTS
1092 if (pVM->hwaccm.s.fAllow64BitGuests)
1093 {
1094 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1095 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1096 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1097 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1098 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1099 }
1100 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1101 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1102 : "HWACCM: 32-bit guests supported.\n"));
1103#else
1104 LogRel(("HWACCM: 32-bit guests supported.\n"));
1105#endif
1106 LogRel(("HWACCM: VMX enabled!\n"));
1107 if (pVM->hwaccm.s.fNestedPaging)
1108 {
1109 LogRel(("HWACCM: Enabled nested paging\n"));
1110 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1111 }
1112 if (pVM->hwaccm.s.vmx.fVPID)
1113 LogRel(("HWACCM: Enabled VPID\n"));
1114
1115 if ( pVM->hwaccm.s.fNestedPaging
1116 || pVM->hwaccm.s.vmx.fVPID)
1117 {
1118 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1119 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1120 }
1121
1122 /* TPR patching status logging. */
1123 if (pVM->hwaccm.s.fTRPPatchingAllowed)
1124 {
1125 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1126 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1127 {
1128 pVM->hwaccm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1129 LogRel(("HWACCM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1130 }
1131 else
1132 {
1133 uint32_t u32Eax, u32Dummy;
1134
1135 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1136 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1137 if ( u32Eax < 0x80000001
1138 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1139 {
1140 pVM->hwaccm.s.fTRPPatchingAllowed = false;
1141 LogRel(("HWACCM: TPR patching disabled (long mode not supported).\n"));
1142 }
1143 }
1144 }
1145 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1146 }
1147 else
1148 {
1149 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1150 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1151 pVM->fHWACCMEnabled = false;
1152 }
1153 }
1154 }
1155 else
1156 if (pVM->hwaccm.s.svm.fSupported)
1157 {
1158 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1159
1160 if (pVM->hwaccm.s.fInitialized == false)
1161 {
1162 /* Erratum 170 which requires a forced TLB flush for each world switch:
1163 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1164 *
1165 * All BH-G1/2 and DH-G1/2 models include a fix:
1166 * Athlon X2: 0x6b 1/2
1167 * 0x68 1/2
1168 * Athlon 64: 0x7f 1
1169 * 0x6f 2
1170 * Sempron: 0x7f 1/2
1171 * 0x6f 2
1172 * 0x6c 2
1173 * 0x7c 2
1174 * Turion 64: 0x68 2
1175 *
1176 */
1177 uint32_t u32Dummy;
1178 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1179 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1180 u32BaseFamily= (u32Version >> 8) & 0xf;
1181 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1182 u32Model = ((u32Version >> 4) & 0xf);
1183 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1184 u32Stepping = u32Version & 0xf;
1185 if ( u32Family == 0xf
1186 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1187 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1188 {
1189 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1190 }
1191
1192 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1193 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1194 LogRel(("HWACCM: AMD HWCR MSR = %RX64\n", pVM->hwaccm.s.svm.msrHWCR));
1195 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1196 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1197 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1198
1199 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1200 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
1201 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
1202 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
1203 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
1204 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
1205 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
1206 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
1207 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
1208 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
1209 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER)
1210 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER\n"));
1211
1212 /* Only try once. */
1213 pVM->hwaccm.s.fInitialized = true;
1214
1215 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1216 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1217
1218 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1219 AssertRC(rc);
1220 if (rc == VINF_SUCCESS)
1221 {
1222 pVM->fHWACCMEnabled = true;
1223 pVM->hwaccm.s.svm.fEnabled = true;
1224
1225 if (pVM->hwaccm.s.fNestedPaging)
1226 LogRel(("HWACCM: Enabled nested paging\n"));
1227
1228 hwaccmR3DisableRawMode(pVM);
1229 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1230 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1231 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1232#ifdef VBOX_ENABLE_64_BITS_GUESTS
1233 if (pVM->hwaccm.s.fAllow64BitGuests)
1234 {
1235 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1236 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1237 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1238 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1239 }
1240#endif
1241 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1242 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1243 : "HWACCM: 32-bit guest supported.\n"));
1244
1245 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1246 }
1247 else
1248 {
1249 pVM->fHWACCMEnabled = false;
1250 }
1251 }
1252 }
1253 if (pVM->fHWACCMEnabled)
1254 LogRel(("HWACCM: VT-x/AMD-V init method: %s\n", (pVM->hwaccm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1255 return VINF_SUCCESS;
1256}
1257
1258/**
1259 * Applies relocations to data and code managed by this
1260 * component. This function will be called at init and
1261 * whenever the VMM need to relocate it self inside the GC.
1262 *
1263 * @param pVM The VM.
1264 */
1265VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1266{
1267 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1268
1269 /* Fetch the current paging mode during the relocate callback during state loading. */
1270 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1271 {
1272 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1273 {
1274 PVMCPU pVCpu = &pVM->aCpus[i];
1275
1276 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1277 Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1278 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1279 }
1280 }
1281#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1282 if (pVM->fHWACCMEnabled)
1283 {
1284 int rc;
1285
1286 switch(PGMGetHostMode(pVM))
1287 {
1288 case PGMMODE_32_BIT:
1289 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1290 break;
1291
1292 case PGMMODE_PAE:
1293 case PGMMODE_PAE_NX:
1294 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1295 break;
1296
1297 default:
1298 AssertFailed();
1299 break;
1300 }
1301 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1302 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1303
1304 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1305 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1306
1307 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1308 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1309
1310 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1311 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1312
1313# ifdef DEBUG
1314 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1315 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1316# endif
1317 }
1318#endif
1319 return;
1320}
1321
1322/**
1323 * Checks hardware accelerated raw mode is allowed.
1324 *
1325 * @returns boolean
1326 * @param pVM The VM to operate on.
1327 */
1328VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1329{
1330 return pVM->hwaccm.s.fAllowed;
1331}
1332
1333/**
1334 * Notification callback which is called whenever there is a chance that a CR3
1335 * value might have changed.
1336 *
1337 * This is called by PGM.
1338 *
1339 * @param pVM The VM to operate on.
1340 * @param pVCpu The VMCPU to operate on.
1341 * @param enmShadowMode New shadow paging mode.
1342 * @param enmGuestMode New guest paging mode.
1343 */
1344VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1345{
1346 /* Ignore page mode changes during state loading. */
1347 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1348 return;
1349
1350 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1351
1352 if ( pVM->hwaccm.s.vmx.fEnabled
1353 && pVM->fHWACCMEnabled)
1354 {
1355 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1356 && enmGuestMode >= PGMMODE_PROTECTED)
1357 {
1358 PCPUMCTX pCtx;
1359
1360 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1361
1362 /* After a real mode switch to protected mode we must force
1363 * CPL to 0. Our real mode emulation had to set it to 3.
1364 */
1365 pCtx->ssHid.Attr.n.u2Dpl = 0;
1366 }
1367 }
1368
1369 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1370 {
1371 /* Keep track of paging mode changes. */
1372 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1373 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1374
1375 /* Did we miss a change, because all code was executed in the recompiler? */
1376 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1377 {
1378 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1379 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1380 }
1381 }
1382
1383 /* Reset the contents of the read cache. */
1384 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1385 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1386 pCache->Read.aFieldVal[j] = 0;
1387}
1388
1389/**
1390 * Terminates the HWACCM.
1391 *
1392 * Termination means cleaning up and freeing all resources,
1393 * the VM it self is at this point powered off or suspended.
1394 *
1395 * @returns VBox status code.
1396 * @param pVM The VM to operate on.
1397 */
1398VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1399{
1400 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1401 {
1402 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1403 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1404 }
1405 HWACCMR3TermCPU(pVM);
1406 return 0;
1407}
1408
1409/**
1410 * Terminates the per-VCPU HWACCM.
1411 *
1412 * Termination means cleaning up and freeing all resources,
1413 * the VM it self is at this point powered off or suspended.
1414 *
1415 * @returns VBox status code.
1416 * @param pVM The VM to operate on.
1417 */
1418VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1419{
1420 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1421 {
1422 PVMCPU pVCpu = &pVM->aCpus[i];
1423
1424#ifdef VBOX_WITH_STATISTICS
1425 if (pVCpu->hwaccm.s.paStatExitReason)
1426 {
1427 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1428 pVCpu->hwaccm.s.paStatExitReason = NULL;
1429 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1430 }
1431 if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1432 {
1433 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1434 pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1435 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1436 }
1437#endif
1438
1439#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1440 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1441 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1442 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1443#endif
1444 }
1445 return 0;
1446}
1447
1448/**
1449 * The VM is being reset.
1450 *
1451 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1452 * needs to be removed.
1453 *
1454 * @param pVM VM handle.
1455 */
1456VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1457{
1458 LogFlow(("HWACCMR3Reset:\n"));
1459
1460 if (pVM->fHWACCMEnabled)
1461 hwaccmR3DisableRawMode(pVM);
1462
1463 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1464 {
1465 PVMCPU pVCpu = &pVM->aCpus[i];
1466
1467 /* On first entry we'll sync everything. */
1468 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1469
1470 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1471 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1472
1473 pVCpu->hwaccm.s.fActive = false;
1474 pVCpu->hwaccm.s.Event.fPending = false;
1475
1476 /* Reset state information for real-mode emulation in VT-x. */
1477 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1478 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1479 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1480
1481 /* Reset the contents of the read cache. */
1482 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1483 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1484 pCache->Read.aFieldVal[j] = 0;
1485
1486#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1487 /* Magic marker for searching in crash dumps. */
1488 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1489 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1490#endif
1491 }
1492
1493 /* Clear all patch information. */
1494 pVM->hwaccm.s.pGuestPatchMem = 0;
1495 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1496 pVM->hwaccm.s.cbGuestPatchMem = 0;
1497 pVM->hwaccm.s.cPatches = 0;
1498 pVM->hwaccm.s.PatchTree = 0;
1499 pVM->hwaccm.s.fTPRPatchingActive = false;
1500 ASMMemZero32(pVM->hwaccm.s.aPatches, sizeof(pVM->hwaccm.s.aPatches));
1501}
1502
1503/**
1504 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1505 *
1506 * @returns VBox strict status code.
1507 * @param pVM The VM handle.
1508 * @param pVCpu The VMCPU for the EMT we're being called on.
1509 * @param pvUser Unused
1510 *
1511 */
1512DECLCALLBACK(VBOXSTRICTRC) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1513{
1514 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1515
1516 /* Only execute the handler on the VCPU the original patch request was issued. */
1517 if (pVCpu->idCpu != idCpu)
1518 return VINF_SUCCESS;
1519
1520 Log(("hwaccmR3RemovePatches\n"));
1521 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
1522 {
1523 uint8_t szInstr[15];
1524 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
1525 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1526 int rc;
1527
1528#ifdef LOG_ENABLED
1529 char szOutput[256];
1530
1531 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1532 if (VBOX_SUCCESS(rc))
1533 Log(("Patched instr: %s\n", szOutput));
1534#endif
1535
1536 /* Check if the instruction is still the same. */
1537 rc = PGMPhysSimpleReadGCPtr(pVCpu, szInstr, pInstrGC, pPatch->cbNewOp);
1538 if (rc != VINF_SUCCESS)
1539 {
1540 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1541 continue; /* swapped out or otherwise removed; skip it. */
1542 }
1543
1544 if (memcmp(szInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1545 {
1546 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1547 continue; /* skip it. */
1548 }
1549
1550 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1551 AssertRC(rc);
1552
1553#ifdef LOG_ENABLED
1554 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1555 if (VBOX_SUCCESS(rc))
1556 Log(("Original instr: %s\n", szOutput));
1557#endif
1558 }
1559 pVM->hwaccm.s.cPatches = 0;
1560 pVM->hwaccm.s.PatchTree = 0;
1561 pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1562 pVM->hwaccm.s.fTPRPatchingActive = false;
1563 return VINF_SUCCESS;
1564}
1565
1566/**
1567 * Enable patching in a VT-x/AMD-V guest
1568 *
1569 * @returns VBox status code.
1570 * @param pVM The VM to operate on.
1571 * @param idCpu VCPU to execute hwaccmR3RemovePatches on
1572 * @param pPatchMem Patch memory range
1573 * @param cbPatchMem Size of the memory range
1574 */
1575int hwaccmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1576{
1577 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)idCpu);
1578 AssertRC(rc);
1579
1580 pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1581 pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1582 pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1583 return VINF_SUCCESS;
1584}
1585
1586/**
1587 * Enable patching in a VT-x/AMD-V guest
1588 *
1589 * @returns VBox status code.
1590 * @param pVM The VM to operate on.
1591 * @param pPatchMem Patch memory range
1592 * @param cbPatchMem Size of the memory range
1593 */
1594VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1595{
1596 Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1597 if (pVM->cCpus > 1)
1598 {
1599 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1600 int rc = VMR3ReqCallNoWaitU(pVM->pUVM, VMCPUID_ANY_QUEUE,
1601 (PFNRT)hwaccmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1602 AssertRC(rc);
1603 return rc;
1604 }
1605 return hwaccmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1606}
1607
1608/**
1609 * Disable patching in a VT-x/AMD-V guest
1610 *
1611 * @returns VBox status code.
1612 * @param pVM The VM to operate on.
1613 * @param pPatchMem Patch memory range
1614 * @param cbPatchMem Size of the memory range
1615 */
1616VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1617{
1618 Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1619
1620 Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1621 Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1622
1623 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1624 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)VMMGetCpuId(pVM));
1625 AssertRC(rc);
1626
1627 pVM->hwaccm.s.pGuestPatchMem = 0;
1628 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1629 pVM->hwaccm.s.cbGuestPatchMem = 0;
1630 pVM->hwaccm.s.fTPRPatchingActive = false;
1631 return VINF_SUCCESS;
1632}
1633
1634
1635/**
1636 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1637 *
1638 * @returns VBox strict status code.
1639 * @param pVM The VM handle.
1640 * @param pVCpu The VMCPU for the EMT we're being called on.
1641 * @param pvUser User specified CPU context
1642 *
1643 */
1644DECLCALLBACK(VBOXSTRICTRC) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1645{
1646 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1647 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1648 RTGCPTR oldrip = pCtx->rip;
1649 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1650 unsigned cbOp;
1651
1652 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1653 if (pVCpu->idCpu != idCpu)
1654 return VINF_SUCCESS;
1655
1656 Log(("hwaccmR3ReplaceTprInstr: %RGv\n", pCtx->rip));
1657
1658 /* Two or more VCPUs were racing to patch this instruction. */
1659 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1660 if (pPatch)
1661 return VINF_SUCCESS;
1662
1663 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1664
1665 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1666 AssertRC(rc);
1667 if ( rc == VINF_SUCCESS
1668 && pDis->pCurInstr->opcode == OP_MOV
1669 && cbOp >= 3)
1670 {
1671 uint8_t aVMMCall[3] = { 0xf, 0x1, 0xd9};
1672 uint32_t idx = pVM->hwaccm.s.cPatches;
1673 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[idx];
1674
1675 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1676 AssertRC(rc);
1677
1678 pPatch->cbOp = cbOp;
1679
1680 if (pDis->param1.flags == USE_DISPLACEMENT32)
1681 {
1682 /* write. */
1683 if (pDis->param2.flags == USE_REG_GEN32)
1684 {
1685 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1686 pPatch->uSrcOperand = pDis->param2.base.reg_gen;
1687 }
1688 else
1689 {
1690 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1691 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1692 pPatch->uSrcOperand = pDis->param2.parval;
1693 }
1694 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1695 AssertRC(rc);
1696
1697 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1698 pPatch->cbNewOp = sizeof(aVMMCall);
1699 }
1700 else
1701 {
1702 RTGCPTR oldrip = pCtx->rip;
1703 uint32_t oldcbOp = cbOp;
1704 uint32_t uMmioReg = pDis->param1.base.reg_gen;
1705
1706 /* read */
1707 Assert(pDis->param1.flags == USE_REG_GEN32);
1708
1709 /* Found:
1710 * mov eax, dword [fffe0080] (5 bytes)
1711 * Check if next instruction is:
1712 * shr eax, 4
1713 */
1714 pCtx->rip += cbOp;
1715 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1716 pCtx->rip = oldrip;
1717 if ( rc == VINF_SUCCESS
1718 && pDis->pCurInstr->opcode == OP_SHR
1719 && pDis->param1.flags == USE_REG_GEN32
1720 && pDis->param1.base.reg_gen == uMmioReg
1721 && pDis->param2.flags == USE_IMMEDIATE8
1722 && pDis->param2.parval == 4
1723 && oldcbOp + cbOp < sizeof(pVM->hwaccm.s.aPatches[idx].aOpcode))
1724 {
1725 uint8_t szInstr[15];
1726
1727 /* Replacing two instructions now. */
1728 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, oldcbOp + cbOp);
1729 AssertRC(rc);
1730
1731 pPatch->cbOp = oldcbOp + cbOp;
1732
1733 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1734 szInstr[0] = 0xF0;
1735 szInstr[1] = 0x0F;
1736 szInstr[2] = 0x20;
1737 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
1738 for (unsigned i = 4; i < pPatch->cbOp; i++)
1739 szInstr[i] = 0x90; /* nop */
1740
1741 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, pPatch->cbOp);
1742 AssertRC(rc);
1743
1744 memcpy(pPatch->aNewOpcode, szInstr, pPatch->cbOp);
1745 pPatch->cbNewOp = pPatch->cbOp;
1746
1747 Log(("Acceptable read/shr candidate!\n"));
1748 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1749 }
1750 else
1751 {
1752 pPatch->enmType = HWACCMTPRINSTR_READ;
1753 pPatch->uDstOperand = pDis->param1.base.reg_gen;
1754
1755 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1756 AssertRC(rc);
1757
1758 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1759 pPatch->cbNewOp = sizeof(aVMMCall);
1760 }
1761 }
1762
1763 pPatch->Core.Key = pCtx->eip;
1764 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1765 AssertRC(rc);
1766
1767 pVM->hwaccm.s.cPatches++;
1768 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceSuccess);
1769 return VINF_SUCCESS;
1770 }
1771
1772 /* Save invalid patch, so we will not try again. */
1773 uint32_t idx = pVM->hwaccm.s.cPatches;
1774
1775#ifdef LOG_ENABLED
1776 char szOutput[256];
1777 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1778 if (VBOX_SUCCESS(rc))
1779 Log(("Failed to patch instr: %s\n", szOutput));
1780#endif
1781
1782 pPatch = &pVM->hwaccm.s.aPatches[idx];
1783 pPatch->Core.Key = pCtx->eip;
1784 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1785 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1786 AssertRC(rc);
1787 pVM->hwaccm.s.cPatches++;
1788 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceFailure);
1789 return VINF_SUCCESS;
1790}
1791
1792/**
1793 * Callback to patch a TPR instruction (jump to generated code)
1794 *
1795 * @returns VBox strict status code.
1796 * @param pVM The VM handle.
1797 * @param pVCpu The VMCPU for the EMT we're being called on.
1798 * @param pvUser User specified CPU context
1799 *
1800 */
1801DECLCALLBACK(VBOXSTRICTRC) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1802{
1803 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1804 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1805 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1806 unsigned cbOp;
1807 int rc;
1808#ifdef LOG_ENABLED
1809 RTGCPTR pInstr;
1810 char szOutput[256];
1811#endif
1812
1813 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1814 if (pVCpu->idCpu != idCpu)
1815 return VINF_SUCCESS;
1816
1817 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1818
1819 /* Two or more VCPUs were racing to patch this instruction. */
1820 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1821 if (pPatch)
1822 {
1823 Log(("hwaccmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
1824 return VINF_SUCCESS;
1825 }
1826
1827 Log(("hwaccmR3PatchTprInstr %RGv\n", pCtx->rip));
1828
1829 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1830 AssertRC(rc);
1831 if ( rc == VINF_SUCCESS
1832 && pDis->pCurInstr->opcode == OP_MOV
1833 && cbOp >= 5)
1834 {
1835 uint32_t idx = pVM->hwaccm.s.cPatches;
1836 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[idx];
1837 uint8_t aPatch[64];
1838 uint32_t off = 0;
1839
1840#ifdef LOG_ENABLED
1841 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1842 if (VBOX_SUCCESS(rc))
1843 Log(("Original instr: %s\n", szOutput));
1844#endif
1845
1846 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1847 AssertRC(rc);
1848
1849 pPatch->cbOp = cbOp;
1850 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
1851
1852 if (pDis->param1.flags == USE_DISPLACEMENT32)
1853 {
1854 /*
1855 * TPR write:
1856 *
1857 * push ECX [51]
1858 * push EDX [52]
1859 * push EAX [50]
1860 * xor EDX,EDX [31 D2]
1861 * mov EAX,EAX [89 C0]
1862 * or
1863 * mov EAX,0000000CCh [B8 CC 00 00 00]
1864 * mov ECX,0C0000082h [B9 82 00 00 C0]
1865 * wrmsr [0F 30]
1866 * pop EAX [58]
1867 * pop EDX [5A]
1868 * pop ECX [59]
1869 * jmp return_address [E9 return_address]
1870 *
1871 */
1872 bool fUsesEax = (pDis->param2.flags == USE_REG_GEN32 && pDis->param2.base.reg_gen == USE_REG_EAX);
1873
1874 aPatch[off++] = 0x51; /* push ecx */
1875 aPatch[off++] = 0x52; /* push edx */
1876 if (!fUsesEax)
1877 aPatch[off++] = 0x50; /* push eax */
1878 aPatch[off++] = 0x31; /* xor edx, edx */
1879 aPatch[off++] = 0xD2;
1880 if (pDis->param2.flags == USE_REG_GEN32)
1881 {
1882 if (!fUsesEax)
1883 {
1884 aPatch[off++] = 0x89; /* mov eax, src_reg */
1885 aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, USE_REG_EAX);
1886 }
1887 }
1888 else
1889 {
1890 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1891 aPatch[off++] = 0xB8; /* mov eax, immediate */
1892 *(uint32_t *)&aPatch[off] = pDis->param2.parval;
1893 off += sizeof(uint32_t);
1894 }
1895 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1896 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1897 off += sizeof(uint32_t);
1898
1899 aPatch[off++] = 0x0F; /* wrmsr */
1900 aPatch[off++] = 0x30;
1901 if (!fUsesEax)
1902 aPatch[off++] = 0x58; /* pop eax */
1903 aPatch[off++] = 0x5A; /* pop edx */
1904 aPatch[off++] = 0x59; /* pop ecx */
1905 }
1906 else
1907 {
1908 /*
1909 * TPR read:
1910 *
1911 * push ECX [51]
1912 * push EDX [52]
1913 * push EAX [50]
1914 * mov ECX,0C0000082h [B9 82 00 00 C0]
1915 * rdmsr [0F 32]
1916 * mov EAX,EAX [89 C0]
1917 * pop EAX [58]
1918 * pop EDX [5A]
1919 * pop ECX [59]
1920 * jmp return_address [E9 return_address]
1921 *
1922 */
1923 Assert(pDis->param1.flags == USE_REG_GEN32);
1924
1925 if (pDis->param1.base.reg_gen != USE_REG_ECX)
1926 aPatch[off++] = 0x51; /* push ecx */
1927 if (pDis->param1.base.reg_gen != USE_REG_EDX)
1928 aPatch[off++] = 0x52; /* push edx */
1929 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1930 aPatch[off++] = 0x50; /* push eax */
1931
1932 aPatch[off++] = 0x31; /* xor edx, edx */
1933 aPatch[off++] = 0xD2;
1934
1935 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1936 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1937 off += sizeof(uint32_t);
1938
1939 aPatch[off++] = 0x0F; /* rdmsr */
1940 aPatch[off++] = 0x32;
1941
1942 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1943 {
1944 aPatch[off++] = 0x89; /* mov dst_reg, eax */
1945 aPatch[off++] = MAKE_MODRM(3, USE_REG_EAX, pDis->param1.base.reg_gen);
1946 }
1947
1948 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1949 aPatch[off++] = 0x58; /* pop eax */
1950 if (pDis->param1.base.reg_gen != USE_REG_EDX)
1951 aPatch[off++] = 0x5A; /* pop edx */
1952 if (pDis->param1.base.reg_gen != USE_REG_ECX)
1953 aPatch[off++] = 0x59; /* pop ecx */
1954 }
1955 aPatch[off++] = 0xE9; /* jmp return_address */
1956 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
1957 off += sizeof(RTRCUINTPTR);
1958
1959 if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
1960 {
1961 /* Write new code to the patch buffer. */
1962 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
1963 AssertRC(rc);
1964
1965#ifdef LOG_ENABLED
1966 pInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
1967 while (true)
1968 {
1969 uint32_t cb;
1970
1971 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pInstr, 0, szOutput, sizeof(szOutput), &cb);
1972 if (VBOX_SUCCESS(rc))
1973 Log(("Patch instr %s\n", szOutput));
1974
1975 pInstr += cb;
1976
1977 if (pInstr >= pVM->hwaccm.s.pFreeGuestPatchMem + off)
1978 break;
1979 }
1980#endif
1981
1982 pPatch->aNewOpcode[0] = 0xE9;
1983 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
1984
1985 /* Overwrite the TPR instruction with a jump. */
1986 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
1987 AssertRC(rc);
1988
1989#ifdef LOG_ENABLED
1990 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1991 if (VBOX_SUCCESS(rc))
1992 Log(("Jump: %s\n", szOutput));
1993#endif
1994 pVM->hwaccm.s.pFreeGuestPatchMem += off;
1995 pPatch->cbNewOp = 5;
1996
1997 pPatch->Core.Key = pCtx->eip;
1998 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1999 AssertRC(rc);
2000
2001 pVM->hwaccm.s.cPatches++;
2002 pVM->hwaccm.s.fTPRPatchingActive = true;
2003 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchSuccess);
2004 return VINF_SUCCESS;
2005 }
2006 else
2007 Log(("Ran out of space in our patch buffer!\n"));
2008 }
2009
2010 /* Save invalid patch, so we will not try again. */
2011 uint32_t idx = pVM->hwaccm.s.cPatches;
2012
2013#ifdef LOG_ENABLED
2014 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
2015 if (VBOX_SUCCESS(rc))
2016 Log(("Failed to patch instr: %s\n", szOutput));
2017#endif
2018
2019 pPatch = &pVM->hwaccm.s.aPatches[idx];
2020 pPatch->Core.Key = pCtx->eip;
2021 pPatch->enmType = HWACCMTPRINSTR_INVALID;
2022 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2023 AssertRC(rc);
2024 pVM->hwaccm.s.cPatches++;
2025 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchFailure);
2026 return VINF_SUCCESS;
2027}
2028
2029/**
2030 * Attempt to patch TPR mmio instructions
2031 *
2032 * @returns VBox status code.
2033 * @param pVM The VM to operate on.
2034 * @param pVCpu The VM CPU to operate on.
2035 * @param pCtx CPU context
2036 */
2037VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2038{
2039 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, (pVM->hwaccm.s.pGuestPatchMem) ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr, (void *)pVCpu->idCpu);
2040 AssertRC(rc);
2041 return rc;
2042}
2043
2044/**
2045 * Force execution of the current IO code in the recompiler
2046 *
2047 * @returns VBox status code.
2048 * @param pVM The VM to operate on.
2049 * @param pCtx Partial VM execution context
2050 */
2051VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2052{
2053 PVMCPU pVCpu = VMMGetCpu(pVM);
2054
2055 Assert(pVM->fHWACCMEnabled);
2056 Log(("HWACCMR3EmulateIoBlock\n"));
2057
2058 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2059 if (HWACCMCanEmulateIoBlockEx(pCtx))
2060 {
2061 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
2062 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
2063 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2064 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2065 return VINF_EM_RESCHEDULE_REM;
2066 }
2067 return VINF_SUCCESS;
2068}
2069
2070/**
2071 * Checks if we can currently use hardware accelerated raw mode.
2072 *
2073 * @returns boolean
2074 * @param pVM The VM to operate on.
2075 * @param pCtx Partial VM execution context
2076 */
2077VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2078{
2079 PVMCPU pVCpu = VMMGetCpu(pVM);
2080
2081 Assert(pVM->fHWACCMEnabled);
2082
2083 /* If we're still executing the IO code, then return false. */
2084 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
2085 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2086 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2087 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
2088 return false;
2089
2090 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
2091
2092 /* AMD-V supports real & protected mode with or without paging. */
2093 if (pVM->hwaccm.s.svm.fEnabled)
2094 {
2095 pVCpu->hwaccm.s.fActive = true;
2096 return true;
2097 }
2098
2099 pVCpu->hwaccm.s.fActive = false;
2100
2101 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2102#ifdef HWACCM_VMX_EMULATE_REALMODE
2103 if (pVM->hwaccm.s.vmx.pRealModeTSS)
2104 {
2105 if (CPUMIsGuestInRealModeEx(pCtx))
2106 {
2107 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
2108 * The base must also be equal to (sel << 4).
2109 */
2110 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
2111 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
2112 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
2113 || pCtx->es != (pCtx->esHid.u64Base >> 4)
2114 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
2115 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
2116 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
2117 {
2118 return false;
2119 }
2120 }
2121 else
2122 {
2123 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2124 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
2125 * from real to protected mode. (all sorts of RPL & DPL assumptions)
2126 */
2127 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2128 && enmGuestMode >= PGMMODE_PROTECTED)
2129 {
2130 if ( (pCtx->cs & X86_SEL_RPL)
2131 || (pCtx->ds & X86_SEL_RPL)
2132 || (pCtx->es & X86_SEL_RPL)
2133 || (pCtx->fs & X86_SEL_RPL)
2134 || (pCtx->gs & X86_SEL_RPL)
2135 || (pCtx->ss & X86_SEL_RPL))
2136 {
2137 return false;
2138 }
2139 }
2140 }
2141 }
2142 else
2143#endif /* HWACCM_VMX_EMULATE_REALMODE */
2144 {
2145 if (!CPUMIsGuestInLongModeEx(pCtx))
2146 {
2147 /** @todo This should (probably) be set on every excursion to the REM,
2148 * however it's too risky right now. So, only apply it when we go
2149 * back to REM for real mode execution. (The XP hack below doesn't
2150 * work reliably without this.)
2151 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2152 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2153
2154 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2155 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
2156 return false;
2157
2158 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2159 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2160 * hidden registers (possible recompiler bug; see load_seg_vm) */
2161 if (pCtx->csHid.Attr.n.u1Present == 0)
2162 return false;
2163 if (pCtx->ssHid.Attr.n.u1Present == 0)
2164 return false;
2165
2166 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2167 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2168 /** @todo This check is actually wrong, it doesn't take the direction of the
2169 * stack segment into account. But, it does the job for now. */
2170 if (pCtx->rsp >= pCtx->ssHid.u32Limit)
2171 return false;
2172#if 0
2173 if ( pCtx->cs >= pCtx->gdtr.cbGdt
2174 || pCtx->ss >= pCtx->gdtr.cbGdt
2175 || pCtx->ds >= pCtx->gdtr.cbGdt
2176 || pCtx->es >= pCtx->gdtr.cbGdt
2177 || pCtx->fs >= pCtx->gdtr.cbGdt
2178 || pCtx->gs >= pCtx->gdtr.cbGdt)
2179 return false;
2180#endif
2181 }
2182 }
2183
2184 if (pVM->hwaccm.s.vmx.fEnabled)
2185 {
2186 uint32_t mask;
2187
2188 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2189 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2190 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2191 mask &= ~X86_CR0_NE;
2192
2193#ifdef HWACCM_VMX_EMULATE_REALMODE
2194 if (pVM->hwaccm.s.vmx.pRealModeTSS)
2195 {
2196 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2197 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2198 }
2199 else
2200#endif
2201 {
2202 /* We support protected mode without paging using identity mapping. */
2203 mask &= ~X86_CR0_PG;
2204 }
2205 if ((pCtx->cr0 & mask) != mask)
2206 return false;
2207
2208 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2209 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2210 if ((pCtx->cr0 & mask) != 0)
2211 return false;
2212
2213 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2214 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2215 mask &= ~X86_CR4_VMXE;
2216 if ((pCtx->cr4 & mask) != mask)
2217 return false;
2218
2219 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2220 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2221 if ((pCtx->cr4 & mask) != 0)
2222 return false;
2223
2224 pVCpu->hwaccm.s.fActive = true;
2225 return true;
2226 }
2227
2228 return false;
2229}
2230
2231/**
2232 * Notifcation from EM about a rescheduling into hardware assisted execution
2233 * mode.
2234 *
2235 * @param pVCpu Pointer to the current virtual cpu structure.
2236 */
2237VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2238{
2239 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2240}
2241
2242/**
2243 * Notifcation from EM about returning from instruction emulation (REM / EM).
2244 *
2245 * @param pVCpu Pointer to the current virtual cpu structure.
2246 */
2247VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2248{
2249 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2250}
2251
2252/**
2253 * Checks if we are currently using hardware accelerated raw mode.
2254 *
2255 * @returns boolean
2256 * @param pVCpu The VMCPU to operate on.
2257 */
2258VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2259{
2260 return pVCpu->hwaccm.s.fActive;
2261}
2262
2263/**
2264 * Checks if we are currently using nested paging.
2265 *
2266 * @returns boolean
2267 * @param pVM The VM to operate on.
2268 */
2269VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2270{
2271 return pVM->hwaccm.s.fNestedPaging;
2272}
2273
2274/**
2275 * Checks if we are currently using VPID in VT-x mode.
2276 *
2277 * @returns boolean
2278 * @param pVM The VM to operate on.
2279 */
2280VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2281{
2282 return pVM->hwaccm.s.vmx.fVPID;
2283}
2284
2285
2286/**
2287 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2288 *
2289 * @returns boolean
2290 * @param pVM The VM to operate on.
2291 */
2292VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2293{
2294 return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2295}
2296
2297/**
2298 * Restart an I/O instruction that was refused in ring-0
2299 *
2300 * @returns Strict VBox status code. Informational status codes other than the one documented
2301 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2302 * @retval VINF_SUCCESS Success.
2303 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2304 * status code must be passed on to EM.
2305 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2306 *
2307 * @param pVM The VM to operate on.
2308 * @param pVCpu The VMCPU to operate on.
2309 * @param pCtx VCPU register context
2310 */
2311VMMR3DECL(VBOXSTRICTRC) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2312{
2313 HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2314
2315 pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2316
2317 if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2318 || enmType == HWACCMPENDINGIO_INVALID)
2319 return VERR_NOT_FOUND;
2320
2321 VBOXSTRICTRC rcStrict;
2322 switch (enmType)
2323 {
2324 case HWACCMPENDINGIO_PORT_READ:
2325 {
2326 uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2327 uint32_t u32Val = 0;
2328
2329 rcStrict = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2330 &u32Val,
2331 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2332 if (IOM_SUCCESS(rcStrict))
2333 {
2334 /* Write back to the EAX register. */
2335 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2336 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2337 }
2338 break;
2339 }
2340
2341 case HWACCMPENDINGIO_PORT_WRITE:
2342 rcStrict = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2343 pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2344 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2345 if (IOM_SUCCESS(rcStrict))
2346 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2347 break;
2348
2349 default:
2350 AssertFailed();
2351 return VERR_INTERNAL_ERROR;
2352 }
2353
2354 return rcStrict;
2355}
2356
2357/**
2358 * Inject an NMI into a running VM (only VCPU 0!)
2359 *
2360 * @returns boolean
2361 * @param pVM The VM to operate on.
2362 */
2363VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2364{
2365 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2366 return VINF_SUCCESS;
2367}
2368
2369/**
2370 * Check fatal VT-x/AMD-V error and produce some meaningful
2371 * log release message.
2372 *
2373 * @param pVM The VM to operate on.
2374 * @param iStatusCode VBox status code
2375 */
2376VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2377{
2378 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2379 {
2380 switch(iStatusCode)
2381 {
2382 case VERR_VMX_INVALID_VMCS_FIELD:
2383 break;
2384
2385 case VERR_VMX_INVALID_VMCS_PTR:
2386 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
2387 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2388 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2389 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2390 break;
2391
2392 case VERR_VMX_UNABLE_TO_START_VM:
2393 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2394 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2395#if 0 /* @todo dump the current control fields to the release log */
2396 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2397 {
2398
2399 }
2400#endif
2401 break;
2402
2403 case VERR_VMX_UNABLE_TO_RESUME_VM:
2404 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2405 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2406 break;
2407
2408 case VERR_VMX_INVALID_VMXON_PTR:
2409 break;
2410 }
2411 }
2412}
2413
2414/**
2415 * Execute state save operation.
2416 *
2417 * @returns VBox status code.
2418 * @param pVM VM Handle.
2419 * @param pSSM SSM operation handle.
2420 */
2421static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2422{
2423 int rc;
2424
2425 Log(("hwaccmR3Save:\n"));
2426
2427 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2428 {
2429 /*
2430 * Save the basic bits - fortunately all the other things can be resynced on load.
2431 */
2432 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2433 AssertRCReturn(rc, rc);
2434 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2435 AssertRCReturn(rc, rc);
2436 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2437 AssertRCReturn(rc, rc);
2438
2439 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2440 AssertRCReturn(rc, rc);
2441 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2442 AssertRCReturn(rc, rc);
2443 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2444 AssertRCReturn(rc, rc);
2445 }
2446#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2447 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2448 AssertRCReturn(rc, rc);
2449 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2450 AssertRCReturn(rc, rc);
2451 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2452 AssertRCReturn(rc, rc);
2453
2454 /* Store all the guest patch records too. */
2455 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cPatches);
2456 AssertRCReturn(rc, rc);
2457
2458 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2459 {
2460 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2461
2462 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2463 AssertRCReturn(rc, rc);
2464
2465 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2466 AssertRCReturn(rc, rc);
2467
2468 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2469 AssertRCReturn(rc, rc);
2470
2471 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2472 AssertRCReturn(rc, rc);
2473
2474 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2475 AssertRCReturn(rc, rc);
2476
2477 AssertCompileSize(HWACCMTPRINSTR, 4);
2478 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2479 AssertRCReturn(rc, rc);
2480
2481 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2482 AssertRCReturn(rc, rc);
2483
2484 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2485 AssertRCReturn(rc, rc);
2486
2487 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2488 AssertRCReturn(rc, rc);
2489
2490 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2491 AssertRCReturn(rc, rc);
2492 }
2493#endif
2494 return VINF_SUCCESS;
2495}
2496
2497/**
2498 * Execute state load operation.
2499 *
2500 * @returns VBox status code.
2501 * @param pVM VM Handle.
2502 * @param pSSM SSM operation handle.
2503 * @param uVersion Data layout version.
2504 * @param uPass The data pass.
2505 */
2506static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2507{
2508 int rc;
2509
2510 Log(("hwaccmR3Load:\n"));
2511 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2512
2513 /*
2514 * Validate version.
2515 */
2516 if ( uVersion != HWACCM_SSM_VERSION
2517 && uVersion != HWACCM_SSM_VERSION_NO_PATCHING
2518 && uVersion != HWACCM_SSM_VERSION_2_0_X)
2519 {
2520 AssertMsgFailed(("hwaccmR3Load: Invalid version uVersion=%d!\n", uVersion));
2521 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2522 }
2523 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2524 {
2525 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2526 AssertRCReturn(rc, rc);
2527 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2528 AssertRCReturn(rc, rc);
2529 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2530 AssertRCReturn(rc, rc);
2531
2532 if (uVersion >= HWACCM_SSM_VERSION_NO_PATCHING)
2533 {
2534 uint32_t val;
2535
2536 rc = SSMR3GetU32(pSSM, &val);
2537 AssertRCReturn(rc, rc);
2538 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2539
2540 rc = SSMR3GetU32(pSSM, &val);
2541 AssertRCReturn(rc, rc);
2542 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2543
2544 rc = SSMR3GetU32(pSSM, &val);
2545 AssertRCReturn(rc, rc);
2546 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2547 }
2548 }
2549#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2550 if (uVersion > HWACCM_SSM_VERSION_NO_PATCHING)
2551 {
2552 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2553 AssertRCReturn(rc, rc);
2554 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2555 AssertRCReturn(rc, rc);
2556 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2557 AssertRCReturn(rc, rc);
2558
2559 /* Fetch all TPR patch records. */
2560 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cPatches);
2561 AssertRCReturn(rc, rc);
2562
2563 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2564 {
2565 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2566
2567 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2568 AssertRCReturn(rc, rc);
2569
2570 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2571 AssertRCReturn(rc, rc);
2572
2573 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2574 AssertRCReturn(rc, rc);
2575
2576 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2577 AssertRCReturn(rc, rc);
2578
2579 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2580 AssertRCReturn(rc, rc);
2581
2582 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2583 AssertRCReturn(rc, rc);
2584
2585 if (pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT)
2586 pVM->hwaccm.s.fTPRPatchingActive = true;
2587
2588 Assert(pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT || pVM->hwaccm.s.fTPRPatchingActive == false);
2589
2590 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2591 AssertRCReturn(rc, rc);
2592
2593 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2594 AssertRCReturn(rc, rc);
2595
2596 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2597 AssertRCReturn(rc, rc);
2598
2599 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2600 AssertRCReturn(rc, rc);
2601
2602 Log(("hwaccmR3Load: patch %d\n", i));
2603 Log(("Key = %x\n", pPatch->Core.Key));
2604 Log(("cbOp = %d\n", pPatch->cbOp));
2605 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2606 Log(("type = %d\n", pPatch->enmType));
2607 Log(("srcop = %d\n", pPatch->uSrcOperand));
2608 Log(("dstop = %d\n", pPatch->uDstOperand));
2609 Log(("cFaults = %d\n", pPatch->cFaults));
2610 Log(("target = %x\n", pPatch->pJumpTarget));
2611 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2612 AssertRC(rc);
2613 }
2614 }
2615#endif
2616
2617 /* Recheck all VCPUs if we can go staight into hwaccm execution mode. */
2618 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2619 {
2620 HWACCMR3CanExecuteGuest(pVM, &pVM->aCpus[i]);
2621 }
2622 return VINF_SUCCESS;
2623}
2624
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