VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 25931

Last change on this file since 25931 was 25931, checked in by vboxsync, 15 years ago

Added VBOX_HWVIRTEX_IGNORE_SVM_IN_USE environment variable check to enable hack for disregarding VERR_SVM_IN_USE errors (quite a few BIOSes around that incorrectly set EFER.SVME).
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 127.9 KB
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1/* $Id: HWACCM.cpp 25931 2010-01-20 14:05:01Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/csam.h>
35#include <VBox/selm.h>
36#include <VBox/rem.h>
37#include <VBox/hwacc_vmx.h>
38#include <VBox/hwacc_svm.h>
39#include "HWACCMInternal.h"
40#include <VBox/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/string.h>
48#include <iprt/env.h>
49#include <iprt/thread.h>
50
51/*******************************************************************************
52* Global Variables *
53*******************************************************************************/
54#ifdef VBOX_WITH_STATISTICS
55# define EXIT_REASON(def, val, str) #def " - " #val " - " str
56# define EXIT_REASON_NIL() NULL
57/** Exit reason descriptions for VT-x, used to describe statistics. */
58static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
59{
60 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
61 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
62 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
63 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
64 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
65 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
66 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
67 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
68 EXIT_REASON_NIL(),
69 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
70 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
71 EXIT_REASON_NIL(),
72 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
73 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
74 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
75 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
76 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
77 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
78 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
79 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
80 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
81 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
82 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
83 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
84 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
85 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
86 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
87 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
88 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
89 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
90 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
91 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
92 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
93 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
94 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
95 EXIT_REASON_NIL(),
96 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
97 EXIT_REASON_NIL(),
98 EXIT_REASON_NIL(),
99 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
100 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
101 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
102 EXIT_REASON_NIL(),
103 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
104 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
105 EXIT_REASON_NIL(),
106 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
107 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
108 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
109 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
110 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
111 EXIT_REASON_NIL(),
112 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
113 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
114 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
115 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
116 EXIT_REASON_NIL()
117};
118/** Exit reason descriptions for AMD-V, used to describe statistics. */
119static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
120{
121 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
122 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
123 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
124 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
125 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
126 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
127 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
128 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
129 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
130 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
131 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
132 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
133 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
134 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
135 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
136 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
137 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
153 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
154 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
155 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
156 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
157 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
158 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
159 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
160 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
161 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
162 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
163 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
164 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
165 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
166 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
167 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
168 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
169 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
185 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_INTR , 96, "Physical maskable interrupt."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_NMI , 97, "Physical non-maskable interrupt."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_SMI , 98, "System management interrupt."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_INIT , 99, "Physical INIT signal."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_VINTR ,100, "Visual interrupt."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_IDTR_READ ,102, "Read IDTR"),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_GDTR_READ ,103, "Read GDTR"),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_LDTR_READ ,104, "Read LDTR."),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,105, "Read TR."),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,106, "Write IDTR."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,107, "Write GDTR."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,108, "Write LDTR."),
230 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,109, "Write TR."),
231 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
232 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
233 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
234 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
235 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
236 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
237 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
238 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
239 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
240 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
241 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
242 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
243 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
244 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
245 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
246 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
247 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
248 EXIT_REASON(SVM_EXIT_TASK_SHUTDOWN ,127, "Shutdown."),
249 EXIT_REASON(SVM_EXIT_TASK_VMRUN ,128, "VMRUN instruction."),
250 EXIT_REASON(SVM_EXIT_TASK_VMCALL ,129, "VMCALL instruction."),
251 EXIT_REASON(SVM_EXIT_TASK_VMLOAD ,130, "VMLOAD instruction."),
252 EXIT_REASON(SVM_EXIT_TASK_VMSAVE ,131, "VMSAVE instruction."),
253 EXIT_REASON(SVM_EXIT_TASK_STGI ,132, "STGI instruction."),
254 EXIT_REASON(SVM_EXIT_TASK_CLGI ,133, "CLGI instruction."),
255 EXIT_REASON(SVM_EXIT_TASK_SKINIT ,134, "SKINIT instruction."),
256 EXIT_REASON(SVM_EXIT_TASK_RDTSCP ,135, "RDTSCP instruction."),
257 EXIT_REASON(SVM_EXIT_TASK_ICEBP ,136, "ICEBP instruction."),
258 EXIT_REASON(SVM_EXIT_TASK_WBINVD ,137, "WBINVD instruction."),
259 EXIT_REASON(SVM_EXIT_TASK_MONITOR ,138, "MONITOR instruction."),
260 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
261 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
262 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
263 EXIT_REASON_NIL()
264};
265# undef EXIT_REASON
266# undef EXIT_REASON_NIL
267#endif /* VBOX_WITH_STATISTICS */
268
269/*******************************************************************************
270* Internal Functions *
271*******************************************************************************/
272static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
273static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
274
275
276/**
277 * Initializes the HWACCM.
278 *
279 * @returns VBox status code.
280 * @param pVM The VM to operate on.
281 */
282VMMR3DECL(int) HWACCMR3Init(PVM pVM)
283{
284 LogFlow(("HWACCMR3Init\n"));
285
286 /*
287 * Assert alignment and sizes.
288 */
289 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
290 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
291
292 /* Some structure checks. */
293 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
294 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
295 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
296 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
297
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
300 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
303 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
304 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
305
306
307 /*
308 * Register the saved state data unit.
309 */
310 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
311 NULL, NULL, NULL,
312 NULL, hwaccmR3Save, NULL,
313 NULL, hwaccmR3Load, NULL);
314 if (RT_FAILURE(rc))
315 return rc;
316
317 /* Misc initialisation. */
318 pVM->hwaccm.s.vmx.fSupported = false;
319 pVM->hwaccm.s.svm.fSupported = false;
320 pVM->hwaccm.s.vmx.fEnabled = false;
321 pVM->hwaccm.s.svm.fEnabled = false;
322
323 pVM->hwaccm.s.fNestedPaging = false;
324
325 /* Disabled by default. */
326 pVM->fHWACCMEnabled = false;
327
328 /*
329 * Check CFGM options.
330 */
331 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
332 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
333 /* Nested paging: disabled by default. */
334 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
335 AssertRC(rc);
336
337 /* VT-x VPID: disabled by default. */
338 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
339 AssertRC(rc);
340
341 /* HWACCM support must be explicitely enabled in the configuration file. */
342 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
343 AssertRC(rc);
344
345 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
346 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hwaccm.s.fTRPPatchingAllowed, false);
347 AssertRC(rc);
348
349#ifdef RT_OS_DARWIN
350 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
351#else
352 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
353#endif
354 {
355 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
356 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
357 return VERR_HWACCM_CONFIG_MISMATCH;
358 }
359
360 if (VMMIsHwVirtExtForced(pVM))
361 pVM->fHWACCMEnabled = true;
362
363#if HC_ARCH_BITS == 32
364 /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
365 * (To use the default, don't set 64bitEnabled in CFGM.) */
366 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
367 AssertLogRelRCReturn(rc, rc);
368 if (pVM->hwaccm.s.fAllow64BitGuests)
369 {
370# ifdef RT_OS_DARWIN
371 if (!VMMIsHwVirtExtForced(pVM))
372# else
373 if (!pVM->hwaccm.s.fAllowed)
374# endif
375 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
376 }
377#else
378 /* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
379 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
380 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
381 AssertLogRelRCReturn(rc, rc);
382#endif
383
384
385 /** Determine the init method for AMD-V and VT-x; either one global init for each host CPU
386 * or local init each time we wish to execute guest code.
387 *
388 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
389 */
390 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hwaccm.s.fGlobalInit,
391#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
392 false
393#else
394 true
395#endif
396 );
397
398 /* Max number of resume loops. */
399 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
400 AssertRC(rc);
401
402 return VINF_SUCCESS;
403}
404
405/**
406 * Initializes the per-VCPU HWACCM.
407 *
408 * @returns VBox status code.
409 * @param pVM The VM to operate on.
410 */
411VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
412{
413 LogFlow(("HWACCMR3InitCPU\n"));
414
415 for (VMCPUID i = 0; i < pVM->cCpus; i++)
416 {
417 PVMCPU pVCpu = &pVM->aCpus[i];
418
419 pVCpu->hwaccm.s.fActive = false;
420 }
421
422#ifdef VBOX_WITH_STATISTICS
423 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
424 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
425 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
426 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
427
428 /*
429 * Statistics.
430 */
431 for (VMCPUID i = 0; i < pVM->cCpus; i++)
432 {
433 PVMCPU pVCpu = &pVM->aCpus[i];
434 int rc;
435
436 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of RTMpPokeCpu",
437 "/PROF/HWACCM/CPU%d/Poke", i);
438 AssertRC(rc);
439 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait",
440 "/PROF/HWACCM/CPU%d/PokeWait", i);
441 AssertRC(rc);
442 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait when RTMpPokeCpu fails",
443 "/PROF/HWACCM/CPU%d/PokeWaitFailed", i);
444 AssertRC(rc);
445 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
446 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
447 AssertRC(rc);
448 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
449 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
450 AssertRC(rc);
451 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
452 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
453 AssertRC(rc);
454# if 1 /* temporary for tracking down darwin holdup. */
455 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
456 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
457 AssertRC(rc);
458 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
459 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
460 AssertRC(rc);
461 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
462 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
463 AssertRC(rc);
464# endif
465 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
466 "/PROF/HWACCM/CPU%d/InGC", i);
467 AssertRC(rc);
468
469# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
470 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
471 "/PROF/HWACCM/CPU%d/Switcher3264", i);
472 AssertRC(rc);
473# endif
474
475# define HWACCM_REG_COUNTER(a, b) \
476 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
477 AssertRC(rc);
478
479 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
480 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
481 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
482 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
483 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
484 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
485 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
486 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
487 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
488 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
489 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
490 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
491 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
492 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
493 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
494 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
495 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
496 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
498 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
499 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
503 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
504 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
505 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
506 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
507 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
508 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
509 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
510 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
511 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
512 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
513 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
514 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
515 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
516
517 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
518 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
519
520 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
521 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
522 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
523
524 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPage, "/HWACCM/CPU%d/Flush/Page");
525 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
526 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
527 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLB, "/HWACCM/CPU%d/Flush/TLB");
528 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
529 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
530 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
531 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
532 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
533 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
534 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
535 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
536 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
537
538 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
539 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
540 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow, "/HWACCM/CPU%d/TSC/InterceptOverflow");
541
542 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
543 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
544 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
545
546 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
547 {
548 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
549 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
550 AssertRC(rc);
551 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
552 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
553 AssertRC(rc);
554 }
555
556#undef HWACCM_REG_COUNTER
557
558 pVCpu->hwaccm.s.paStatExitReason = NULL;
559
560 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
561 AssertRC(rc);
562 if (RT_SUCCESS(rc))
563 {
564 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
565 for (int j=0;j<MAX_EXITREASON_STAT;j++)
566 {
567 if (papszDesc[j])
568 {
569 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
570 papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
571 AssertRC(rc);
572 }
573 }
574 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
575 AssertRC(rc);
576 }
577 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
578# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
579 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
580# else
581 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
582# endif
583
584 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
585 AssertRCReturn(rc, rc);
586 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
587# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
588 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
589# else
590 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
591# endif
592 for (unsigned j = 0; j < 255; j++)
593 STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
594 (j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
595
596 }
597#endif /* VBOX_WITH_STATISTICS */
598
599#ifdef VBOX_WITH_CRASHDUMP_MAGIC
600 /* Magic marker for searching in crash dumps. */
601 for (VMCPUID i = 0; i < pVM->cCpus; i++)
602 {
603 PVMCPU pVCpu = &pVM->aCpus[i];
604
605 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
606 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
607 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
608 }
609#endif
610 return VINF_SUCCESS;
611}
612
613/**
614 * Turns off normal raw mode features
615 *
616 * @param pVM The VM to operate on.
617 */
618static void hwaccmR3DisableRawMode(PVM pVM)
619{
620 /* Disable PATM & CSAM. */
621 PATMR3AllowPatching(pVM, false);
622 CSAMDisableScanning(pVM);
623
624 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
625 SELMR3DisableMonitoring(pVM);
626 TRPMR3DisableMonitoring(pVM);
627
628 /* Disable the switcher code (safety precaution). */
629 VMMR3DisableSwitcher(pVM);
630
631 /* Disable mapping of the hypervisor into the shadow page table. */
632 PGMR3MappingsDisable(pVM);
633
634 /* Disable the switcher */
635 VMMR3DisableSwitcher(pVM);
636
637 /* Reinit the paging mode to force the new shadow mode. */
638 for (VMCPUID i = 0; i < pVM->cCpus; i++)
639 {
640 PVMCPU pVCpu = &pVM->aCpus[i];
641
642 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
643 }
644}
645
646/**
647 * Initialize VT-x or AMD-V.
648 *
649 * @returns VBox status code.
650 * @param pVM The VM handle.
651 */
652VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
653{
654 int rc;
655
656 /* Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
657 * is already using AMD-V.
658 */
659 if ( !pVM->hwaccm.s.vmx.fSupported
660 && !pVM->hwaccm.s.svm.fSupported
661 && pVM->hwaccm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
662 && RTEnvGet("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
663 {
664 LogRel(("HWACCM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
665 pVM->hwaccm.s.svm.fSupported = true;
666 pVM->hwaccm.s.svm.fIgnoreInUseError = true;
667 }
668 else
669 if ( !pVM->hwaccm.s.vmx.fSupported
670 && !pVM->hwaccm.s.svm.fSupported)
671 {
672 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
673 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
674
675 if (VMMIsHwVirtExtForced(pVM))
676 {
677 switch (pVM->hwaccm.s.lLastError)
678 {
679 case VERR_VMX_NO_VMX:
680 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
681 case VERR_VMX_IN_VMX_ROOT_MODE:
682 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
683 case VERR_SVM_IN_USE:
684 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
685 case VERR_SVM_NO_SVM:
686 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
687 case VERR_SVM_DISABLED:
688 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
689 default:
690 return pVM->hwaccm.s.lLastError;
691 }
692 }
693 return VINF_SUCCESS;
694 }
695
696 if (pVM->hwaccm.s.vmx.fSupported)
697 {
698 rc = SUPR3QueryVTxSupported();
699 if (RT_FAILURE(rc))
700 {
701#ifdef RT_OS_LINUX
702 LogRel(("HWACCM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
703#else
704 LogRel(("HWACCM: The host kernel does not support VT-x!\n"));
705#endif
706 if ( pVM->cCpus > 1
707 || VMMIsHwVirtExtForced(pVM))
708 return rc;
709
710 /* silently fall back to raw mode */
711 return VINF_SUCCESS;
712 }
713 }
714
715 if (!pVM->hwaccm.s.fAllowed)
716 return VINF_SUCCESS; /* nothing to do */
717
718 /* Enable VT-x or AMD-V on all host CPUs. */
719 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
720 if (RT_FAILURE(rc))
721 {
722 LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
723 return rc;
724 }
725 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
726
727 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
728 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
729 if (!pVM->hwaccm.s.fHasIoApic)
730 {
731 Assert(!pVM->hwaccm.s.fTRPPatchingAllowed); /* paranoia */
732 pVM->hwaccm.s.fTRPPatchingAllowed = false;
733 }
734
735 if (pVM->hwaccm.s.vmx.fSupported)
736 {
737 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
738
739 if ( pVM->hwaccm.s.fInitialized == false
740 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
741 {
742 uint64_t val;
743 RTGCPHYS GCPhys = 0;
744
745 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
746 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
747 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
748 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
749 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
750 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
751 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
752 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
753
754 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
755 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
756 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
757 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
758 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
759 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
760 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
761 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
762 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
763 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
764 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
765 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
766 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
767 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
768 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
769 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
770 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
771 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
772 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
773
774 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
775 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
776 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
777 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
778 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
779 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
780 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
781 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
782 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
783 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
784 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
785 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
786 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
787 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
788 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
789 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
790 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
791 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
792 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
793 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
794 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
795 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
796 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
797 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
798 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
799 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
800 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
801 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
802 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
803 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
804 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
805 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
806 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
807 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
808 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
809 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
810 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
811 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
812 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
813 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
814 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
815 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
816 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
817 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
818
819 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
820 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
821 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
822 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
823 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
824 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
825 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
826 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
827 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
828 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
829 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
830 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
831 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
832 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
833 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
834 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
835 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
836 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
837 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
838 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
839 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
840 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
841 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
842 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
843 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
844 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
845 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
846 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
847 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
848 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
849 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
850 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
851 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
852 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
853 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
854 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
855 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
856 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
857 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
858 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
859 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
860 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
861 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
862
863 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
864 {
865 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
866 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
867 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
868 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
869 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
870 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
871 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
872 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
873 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
874 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT\n"));
875 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
876 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
877 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
878 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
879 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
880 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
881 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
882 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE\n"));
883 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
884 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT\n"));
885
886 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
887 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
888 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
889 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
890 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
891 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
892 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT *must* be set\n"));
893 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
894 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
895 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
896 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
897 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
898 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
899 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
900 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
901 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
902 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE *must* be set\n"));
903 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
904 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT *must* be set\n"));
905 }
906
907 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
908 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
909 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
910 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
911 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
912 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
913 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
914 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
915 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
916 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
917 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
918 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
919 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
920 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
921 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
922 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
923 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
924 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
925 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
926 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
927 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
928 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
929 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
930 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
931 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
932 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
933 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
934 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
935 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
936 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
937 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
938
939 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
940 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
941 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
942 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
943 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
944 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
945 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
946 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
947 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
948 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
949 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
950 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
951 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
952 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
953 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
954 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
955 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
956 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
957 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
958 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
959 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
960 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
961 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
962 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
963 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
964 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
965 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
966 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
967 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
968 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
969 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
970 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
971 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
972 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
973 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
974
975 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
976 {
977 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
978
979 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
980 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
981 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
982 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
983 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
984 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
985 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
986 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
987 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
988 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
989 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
990 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
991 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
992 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
993 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
994 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
995 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
996 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
997 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
998 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
999 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
1000 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
1001 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
1002 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
1003 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
1004 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
1005 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
1006 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
1007 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
1008 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
1009 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
1010 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
1011 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
1012 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
1013 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
1014 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
1015 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
1016 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
1017 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
1018 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
1019 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
1020 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
1021 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
1022 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
1023 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
1024 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
1025 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
1026 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
1027 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
1028 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
1029 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
1030 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
1031 }
1032
1033 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
1034 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1035 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1036 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1037 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1038 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1039
1040 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
1041 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
1042 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
1043 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
1044 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
1045
1046 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
1047
1048 /* Paranoia */
1049 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc) >= 512);
1050
1051 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1052 {
1053 LogRel(("HWACCM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pMSRBitmapPhys));
1054 LogRel(("HWACCM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1055 }
1056
1057#ifdef HWACCM_VTX_WITH_EPT
1058 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1059 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1060#endif /* HWACCM_VTX_WITH_EPT */
1061#ifdef HWACCM_VTX_WITH_VPID
1062 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1063 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
1064 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
1065#endif /* HWACCM_VTX_WITH_VPID */
1066
1067 /* Unrestricted guest execution relies on EPT. */
1068 if ( pVM->hwaccm.s.fNestedPaging
1069 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE))
1070 {
1071 pVM->hwaccm.s.vmx.fUnrestrictedGuest = true;
1072 }
1073
1074 /* Only try once. */
1075 pVM->hwaccm.s.fInitialized = true;
1076
1077 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1078 {
1079 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1080 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
1081 if (RT_SUCCESS(rc))
1082 {
1083 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1084 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
1085 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
1086 /* Bit set to 0 means redirection enabled. */
1087 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
1088 /* Allow all port IO, so the VT-x IO intercepts do their job. */
1089 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
1090 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
1091
1092 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1093 * real and protected mode without paging with EPT.
1094 */
1095 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1096 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
1097 {
1098 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1099 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
1100 }
1101
1102 /* We convert it here every time as pci regions could be reconfigured. */
1103 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1104 AssertRC(rc);
1105 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1106
1107 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1108 AssertRC(rc);
1109 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1110 }
1111 else
1112 {
1113 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1114 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1115 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1116 }
1117 }
1118
1119 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1120 AssertRC(rc);
1121 if (rc == VINF_SUCCESS)
1122 {
1123 pVM->fHWACCMEnabled = true;
1124 pVM->hwaccm.s.vmx.fEnabled = true;
1125 hwaccmR3DisableRawMode(pVM);
1126
1127 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1128#ifdef VBOX_ENABLE_64_BITS_GUESTS
1129 if (pVM->hwaccm.s.fAllow64BitGuests)
1130 {
1131 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1132 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1133 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1134 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1135 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1136 }
1137 else
1138 /* Turn on NXE if PAE has been enabled. */
1139 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1140 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1141
1142 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1143 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1144 : "HWACCM: 32-bit guests supported.\n"));
1145#else
1146 LogRel(("HWACCM: 32-bit guests supported.\n"));
1147#endif
1148 LogRel(("HWACCM: VMX enabled!\n"));
1149 if (pVM->hwaccm.s.fNestedPaging)
1150 {
1151 LogRel(("HWACCM: Enabled nested paging\n"));
1152 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1153 if (pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1154 LogRel(("HWACCM: Unrestricted guest execution enabled!\n"));
1155 }
1156 else
1157 Assert(!pVM->hwaccm.s.vmx.fUnrestrictedGuest);
1158
1159 if (pVM->hwaccm.s.vmx.fVPID)
1160 LogRel(("HWACCM: Enabled VPID\n"));
1161
1162 if ( pVM->hwaccm.s.fNestedPaging
1163 || pVM->hwaccm.s.vmx.fVPID)
1164 {
1165 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1166 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1167 }
1168
1169 /* TPR patching status logging. */
1170 if (pVM->hwaccm.s.fTRPPatchingAllowed)
1171 {
1172 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1173 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1174 {
1175 pVM->hwaccm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1176 LogRel(("HWACCM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1177 }
1178 else
1179 {
1180 uint32_t u32Eax, u32Dummy;
1181
1182 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1183 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1184 if ( u32Eax < 0x80000001
1185 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1186 {
1187 pVM->hwaccm.s.fTRPPatchingAllowed = false;
1188 LogRel(("HWACCM: TPR patching disabled (long mode not supported).\n"));
1189 }
1190 }
1191 }
1192 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1193 }
1194 else
1195 {
1196 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1197 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1198 pVM->fHWACCMEnabled = false;
1199 }
1200 }
1201 }
1202 else
1203 if (pVM->hwaccm.s.svm.fSupported)
1204 {
1205 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1206
1207 if (pVM->hwaccm.s.fInitialized == false)
1208 {
1209 /* Erratum 170 which requires a forced TLB flush for each world switch:
1210 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1211 *
1212 * All BH-G1/2 and DH-G1/2 models include a fix:
1213 * Athlon X2: 0x6b 1/2
1214 * 0x68 1/2
1215 * Athlon 64: 0x7f 1
1216 * 0x6f 2
1217 * Sempron: 0x7f 1/2
1218 * 0x6f 2
1219 * 0x6c 2
1220 * 0x7c 2
1221 * Turion 64: 0x68 2
1222 *
1223 */
1224 uint32_t u32Dummy;
1225 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1226 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1227 u32BaseFamily= (u32Version >> 8) & 0xf;
1228 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1229 u32Model = ((u32Version >> 4) & 0xf);
1230 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1231 u32Stepping = u32Version & 0xf;
1232 if ( u32Family == 0xf
1233 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1234 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1235 {
1236 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1237 }
1238
1239 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1240 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1241 LogRel(("HWACCM: AMD HWCR MSR = %RX64\n", pVM->hwaccm.s.svm.msrHWCR));
1242 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1243 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1244 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1245
1246 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1247 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
1248 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
1249 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
1250 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
1251 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
1252 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
1253 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
1254 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
1255 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
1256 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER)
1257 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER\n"));
1258
1259 /* Only try once. */
1260 pVM->hwaccm.s.fInitialized = true;
1261
1262 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1263 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1264
1265 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1266 AssertRC(rc);
1267 if (rc == VINF_SUCCESS)
1268 {
1269 pVM->fHWACCMEnabled = true;
1270 pVM->hwaccm.s.svm.fEnabled = true;
1271
1272 if (pVM->hwaccm.s.fNestedPaging)
1273 LogRel(("HWACCM: Enabled nested paging\n"));
1274
1275 hwaccmR3DisableRawMode(pVM);
1276 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1277 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1278 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1279#ifdef VBOX_ENABLE_64_BITS_GUESTS
1280 if (pVM->hwaccm.s.fAllow64BitGuests)
1281 {
1282 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1283 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1284 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1285 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1286 }
1287 else
1288 /* Turn on NXE if PAE has been enabled. */
1289 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1290 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1291#endif
1292
1293 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1294 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1295 : "HWACCM: 32-bit guest supported.\n"));
1296
1297 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1298 }
1299 else
1300 {
1301 pVM->fHWACCMEnabled = false;
1302 }
1303 }
1304 }
1305 if (pVM->fHWACCMEnabled)
1306 LogRel(("HWACCM: VT-x/AMD-V init method: %s\n", (pVM->hwaccm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1307 return VINF_SUCCESS;
1308}
1309
1310/**
1311 * Applies relocations to data and code managed by this
1312 * component. This function will be called at init and
1313 * whenever the VMM need to relocate it self inside the GC.
1314 *
1315 * @param pVM The VM.
1316 */
1317VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1318{
1319 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1320
1321 /* Fetch the current paging mode during the relocate callback during state loading. */
1322 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1323 {
1324 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1325 {
1326 PVMCPU pVCpu = &pVM->aCpus[i];
1327
1328 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1329 Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1330 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1331 }
1332 }
1333#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1334 if (pVM->fHWACCMEnabled)
1335 {
1336 int rc;
1337
1338 switch(PGMGetHostMode(pVM))
1339 {
1340 case PGMMODE_32_BIT:
1341 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1342 break;
1343
1344 case PGMMODE_PAE:
1345 case PGMMODE_PAE_NX:
1346 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1347 break;
1348
1349 default:
1350 AssertFailed();
1351 break;
1352 }
1353 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1354 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1355
1356 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1357 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1358
1359 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1360 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1361
1362 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1363 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1364
1365# ifdef DEBUG
1366 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1367 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1368# endif
1369 }
1370#endif
1371 return;
1372}
1373
1374/**
1375 * Checks hardware accelerated raw mode is allowed.
1376 *
1377 * @returns boolean
1378 * @param pVM The VM to operate on.
1379 */
1380VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1381{
1382 return pVM->hwaccm.s.fAllowed;
1383}
1384
1385/**
1386 * Notification callback which is called whenever there is a chance that a CR3
1387 * value might have changed.
1388 *
1389 * This is called by PGM.
1390 *
1391 * @param pVM The VM to operate on.
1392 * @param pVCpu The VMCPU to operate on.
1393 * @param enmShadowMode New shadow paging mode.
1394 * @param enmGuestMode New guest paging mode.
1395 */
1396VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1397{
1398 /* Ignore page mode changes during state loading. */
1399 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1400 return;
1401
1402 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1403
1404 if ( pVM->hwaccm.s.vmx.fEnabled
1405 && pVM->fHWACCMEnabled)
1406 {
1407 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1408 && enmGuestMode >= PGMMODE_PROTECTED)
1409 {
1410 PCPUMCTX pCtx;
1411
1412 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1413
1414 /* After a real mode switch to protected mode we must force
1415 * CPL to 0. Our real mode emulation had to set it to 3.
1416 */
1417 pCtx->ssHid.Attr.n.u2Dpl = 0;
1418 }
1419 }
1420
1421 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1422 {
1423 /* Keep track of paging mode changes. */
1424 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1425 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1426
1427 /* Did we miss a change, because all code was executed in the recompiler? */
1428 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1429 {
1430 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1431 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1432 }
1433 }
1434
1435 /* Reset the contents of the read cache. */
1436 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1437 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1438 pCache->Read.aFieldVal[j] = 0;
1439}
1440
1441/**
1442 * Terminates the HWACCM.
1443 *
1444 * Termination means cleaning up and freeing all resources,
1445 * the VM it self is at this point powered off or suspended.
1446 *
1447 * @returns VBox status code.
1448 * @param pVM The VM to operate on.
1449 */
1450VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1451{
1452 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1453 {
1454 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1455 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1456 }
1457 HWACCMR3TermCPU(pVM);
1458 return 0;
1459}
1460
1461/**
1462 * Terminates the per-VCPU HWACCM.
1463 *
1464 * Termination means cleaning up and freeing all resources,
1465 * the VM it self is at this point powered off or suspended.
1466 *
1467 * @returns VBox status code.
1468 * @param pVM The VM to operate on.
1469 */
1470VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1471{
1472 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1473 {
1474 PVMCPU pVCpu = &pVM->aCpus[i];
1475
1476#ifdef VBOX_WITH_STATISTICS
1477 if (pVCpu->hwaccm.s.paStatExitReason)
1478 {
1479 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1480 pVCpu->hwaccm.s.paStatExitReason = NULL;
1481 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1482 }
1483 if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1484 {
1485 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1486 pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1487 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1488 }
1489#endif
1490
1491#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1492 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1493 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1494 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1495#endif
1496 }
1497 return 0;
1498}
1499
1500/**
1501 * Resets a virtual CPU.
1502 *
1503 * Used by HWACCMR3Reset and CPU hot plugging.
1504 *
1505 * @param pVCpu The CPU to reset.
1506 */
1507VMMR3DECL(void) HWACCMR3ResetCpu(PVMCPU pVCpu)
1508{
1509 /* On first entry we'll sync everything. */
1510 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1511
1512 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1513 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1514
1515 pVCpu->hwaccm.s.fActive = false;
1516 pVCpu->hwaccm.s.Event.fPending = false;
1517
1518 /* Reset state information for real-mode emulation in VT-x. */
1519 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1520 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1521 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1522
1523 /* Reset the contents of the read cache. */
1524 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1525 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1526 pCache->Read.aFieldVal[j] = 0;
1527
1528#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1529 /* Magic marker for searching in crash dumps. */
1530 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1531 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1532#endif
1533}
1534
1535/**
1536 * The VM is being reset.
1537 *
1538 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1539 * needs to be removed.
1540 *
1541 * @param pVM VM handle.
1542 */
1543VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1544{
1545 LogFlow(("HWACCMR3Reset:\n"));
1546
1547 if (pVM->fHWACCMEnabled)
1548 hwaccmR3DisableRawMode(pVM);
1549
1550 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1551 {
1552 PVMCPU pVCpu = &pVM->aCpus[i];
1553
1554 HWACCMR3ResetCpu(pVCpu);
1555 }
1556
1557 /* Clear all patch information. */
1558 pVM->hwaccm.s.pGuestPatchMem = 0;
1559 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1560 pVM->hwaccm.s.cbGuestPatchMem = 0;
1561 pVM->hwaccm.s.cPatches = 0;
1562 pVM->hwaccm.s.PatchTree = 0;
1563 pVM->hwaccm.s.fTPRPatchingActive = false;
1564 ASMMemZero32(pVM->hwaccm.s.aPatches, sizeof(pVM->hwaccm.s.aPatches));
1565}
1566
1567/**
1568 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1569 *
1570 * @returns VBox strict status code.
1571 * @param pVM The VM handle.
1572 * @param pVCpu The VMCPU for the EMT we're being called on.
1573 * @param pvUser Unused
1574 *
1575 */
1576DECLCALLBACK(VBOXSTRICTRC) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1577{
1578 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1579
1580 /* Only execute the handler on the VCPU the original patch request was issued. */
1581 if (pVCpu->idCpu != idCpu)
1582 return VINF_SUCCESS;
1583
1584 Log(("hwaccmR3RemovePatches\n"));
1585 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
1586 {
1587 uint8_t szInstr[15];
1588 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
1589 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1590 int rc;
1591
1592#ifdef LOG_ENABLED
1593 char szOutput[256];
1594
1595 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1596 if (VBOX_SUCCESS(rc))
1597 Log(("Patched instr: %s\n", szOutput));
1598#endif
1599
1600 /* Check if the instruction is still the same. */
1601 rc = PGMPhysSimpleReadGCPtr(pVCpu, szInstr, pInstrGC, pPatch->cbNewOp);
1602 if (rc != VINF_SUCCESS)
1603 {
1604 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1605 continue; /* swapped out or otherwise removed; skip it. */
1606 }
1607
1608 if (memcmp(szInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1609 {
1610 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1611 continue; /* skip it. */
1612 }
1613
1614 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1615 AssertRC(rc);
1616
1617#ifdef LOG_ENABLED
1618 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1619 if (VBOX_SUCCESS(rc))
1620 Log(("Original instr: %s\n", szOutput));
1621#endif
1622 }
1623 pVM->hwaccm.s.cPatches = 0;
1624 pVM->hwaccm.s.PatchTree = 0;
1625 pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1626 pVM->hwaccm.s.fTPRPatchingActive = false;
1627 return VINF_SUCCESS;
1628}
1629
1630/**
1631 * Enable patching in a VT-x/AMD-V guest
1632 *
1633 * @returns VBox status code.
1634 * @param pVM The VM to operate on.
1635 * @param idCpu VCPU to execute hwaccmR3RemovePatches on
1636 * @param pPatchMem Patch memory range
1637 * @param cbPatchMem Size of the memory range
1638 */
1639int hwaccmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1640{
1641 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)idCpu);
1642 AssertRC(rc);
1643
1644 pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1645 pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1646 pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1647 return VINF_SUCCESS;
1648}
1649
1650/**
1651 * Enable patching in a VT-x/AMD-V guest
1652 *
1653 * @returns VBox status code.
1654 * @param pVM The VM to operate on.
1655 * @param pPatchMem Patch memory range
1656 * @param cbPatchMem Size of the memory range
1657 */
1658VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1659{
1660 Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1661 if (pVM->cCpus > 1)
1662 {
1663 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1664 int rc = VMR3ReqCallNoWaitU(pVM->pUVM, VMCPUID_ANY_QUEUE,
1665 (PFNRT)hwaccmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1666 AssertRC(rc);
1667 return rc;
1668 }
1669 return hwaccmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1670}
1671
1672/**
1673 * Disable patching in a VT-x/AMD-V guest
1674 *
1675 * @returns VBox status code.
1676 * @param pVM The VM to operate on.
1677 * @param pPatchMem Patch memory range
1678 * @param cbPatchMem Size of the memory range
1679 */
1680VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1681{
1682 Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1683
1684 Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1685 Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1686
1687 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1688 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)VMMGetCpuId(pVM));
1689 AssertRC(rc);
1690
1691 pVM->hwaccm.s.pGuestPatchMem = 0;
1692 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1693 pVM->hwaccm.s.cbGuestPatchMem = 0;
1694 pVM->hwaccm.s.fTPRPatchingActive = false;
1695 return VINF_SUCCESS;
1696}
1697
1698
1699/**
1700 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1701 *
1702 * @returns VBox strict status code.
1703 * @param pVM The VM handle.
1704 * @param pVCpu The VMCPU for the EMT we're being called on.
1705 * @param pvUser User specified CPU context
1706 *
1707 */
1708DECLCALLBACK(VBOXSTRICTRC) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1709{
1710 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1711 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1712 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1713 unsigned cbOp;
1714
1715 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1716 if (pVCpu->idCpu != idCpu)
1717 return VINF_SUCCESS;
1718
1719 Log(("hwaccmR3ReplaceTprInstr: %RGv\n", pCtx->rip));
1720
1721 /* Two or more VCPUs were racing to patch this instruction. */
1722 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1723 if (pPatch)
1724 return VINF_SUCCESS;
1725
1726 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1727
1728 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1729 AssertRC(rc);
1730 if ( rc == VINF_SUCCESS
1731 && pDis->pCurInstr->opcode == OP_MOV
1732 && cbOp >= 3)
1733 {
1734 uint8_t aVMMCall[3] = { 0xf, 0x1, 0xd9};
1735 uint32_t idx = pVM->hwaccm.s.cPatches;
1736
1737 pPatch = &pVM->hwaccm.s.aPatches[idx];
1738
1739 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1740 AssertRC(rc);
1741
1742 pPatch->cbOp = cbOp;
1743
1744 if (pDis->param1.flags == USE_DISPLACEMENT32)
1745 {
1746 /* write. */
1747 if (pDis->param2.flags == USE_REG_GEN32)
1748 {
1749 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1750 pPatch->uSrcOperand = pDis->param2.base.reg_gen;
1751 }
1752 else
1753 {
1754 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1755 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1756 pPatch->uSrcOperand = pDis->param2.parval;
1757 }
1758 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1759 AssertRC(rc);
1760
1761 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1762 pPatch->cbNewOp = sizeof(aVMMCall);
1763 }
1764 else
1765 {
1766 RTGCPTR oldrip = pCtx->rip;
1767 uint32_t oldcbOp = cbOp;
1768 uint32_t uMmioReg = pDis->param1.base.reg_gen;
1769
1770 /* read */
1771 Assert(pDis->param1.flags == USE_REG_GEN32);
1772
1773 /* Found:
1774 * mov eax, dword [fffe0080] (5 bytes)
1775 * Check if next instruction is:
1776 * shr eax, 4
1777 */
1778 pCtx->rip += cbOp;
1779 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1780 pCtx->rip = oldrip;
1781 if ( rc == VINF_SUCCESS
1782 && pDis->pCurInstr->opcode == OP_SHR
1783 && pDis->param1.flags == USE_REG_GEN32
1784 && pDis->param1.base.reg_gen == uMmioReg
1785 && pDis->param2.flags == USE_IMMEDIATE8
1786 && pDis->param2.parval == 4
1787 && oldcbOp + cbOp < sizeof(pVM->hwaccm.s.aPatches[idx].aOpcode))
1788 {
1789 uint8_t szInstr[15];
1790
1791 /* Replacing two instructions now. */
1792 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, oldcbOp + cbOp);
1793 AssertRC(rc);
1794
1795 pPatch->cbOp = oldcbOp + cbOp;
1796
1797 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1798 szInstr[0] = 0xF0;
1799 szInstr[1] = 0x0F;
1800 szInstr[2] = 0x20;
1801 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
1802 for (unsigned i = 4; i < pPatch->cbOp; i++)
1803 szInstr[i] = 0x90; /* nop */
1804
1805 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, pPatch->cbOp);
1806 AssertRC(rc);
1807
1808 memcpy(pPatch->aNewOpcode, szInstr, pPatch->cbOp);
1809 pPatch->cbNewOp = pPatch->cbOp;
1810
1811 Log(("Acceptable read/shr candidate!\n"));
1812 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1813 }
1814 else
1815 {
1816 pPatch->enmType = HWACCMTPRINSTR_READ;
1817 pPatch->uDstOperand = pDis->param1.base.reg_gen;
1818
1819 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1820 AssertRC(rc);
1821
1822 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1823 pPatch->cbNewOp = sizeof(aVMMCall);
1824 }
1825 }
1826
1827 pPatch->Core.Key = pCtx->eip;
1828 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1829 AssertRC(rc);
1830
1831 pVM->hwaccm.s.cPatches++;
1832 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceSuccess);
1833 return VINF_SUCCESS;
1834 }
1835
1836 /* Save invalid patch, so we will not try again. */
1837 uint32_t idx = pVM->hwaccm.s.cPatches;
1838
1839#ifdef LOG_ENABLED
1840 char szOutput[256];
1841 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1842 if (VBOX_SUCCESS(rc))
1843 Log(("Failed to patch instr: %s\n", szOutput));
1844#endif
1845
1846 pPatch = &pVM->hwaccm.s.aPatches[idx];
1847 pPatch->Core.Key = pCtx->eip;
1848 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1849 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1850 AssertRC(rc);
1851 pVM->hwaccm.s.cPatches++;
1852 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceFailure);
1853 return VINF_SUCCESS;
1854}
1855
1856/**
1857 * Callback to patch a TPR instruction (jump to generated code)
1858 *
1859 * @returns VBox strict status code.
1860 * @param pVM The VM handle.
1861 * @param pVCpu The VMCPU for the EMT we're being called on.
1862 * @param pvUser User specified CPU context
1863 *
1864 */
1865DECLCALLBACK(VBOXSTRICTRC) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1866{
1867 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1868 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1869 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1870 unsigned cbOp;
1871 int rc;
1872#ifdef LOG_ENABLED
1873 RTGCPTR pInstr;
1874 char szOutput[256];
1875#endif
1876
1877 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1878 if (pVCpu->idCpu != idCpu)
1879 return VINF_SUCCESS;
1880
1881 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1882
1883 /* Two or more VCPUs were racing to patch this instruction. */
1884 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1885 if (pPatch)
1886 {
1887 Log(("hwaccmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
1888 return VINF_SUCCESS;
1889 }
1890
1891 Log(("hwaccmR3PatchTprInstr %RGv\n", pCtx->rip));
1892
1893 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1894 AssertRC(rc);
1895 if ( rc == VINF_SUCCESS
1896 && pDis->pCurInstr->opcode == OP_MOV
1897 && cbOp >= 5)
1898 {
1899 uint32_t idx = pVM->hwaccm.s.cPatches;
1900 uint8_t aPatch[64];
1901 uint32_t off = 0;
1902
1903 pPatch = &pVM->hwaccm.s.aPatches[idx];
1904
1905#ifdef LOG_ENABLED
1906 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1907 if (VBOX_SUCCESS(rc))
1908 Log(("Original instr: %s\n", szOutput));
1909#endif
1910
1911 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1912 AssertRC(rc);
1913
1914 pPatch->cbOp = cbOp;
1915 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
1916
1917 if (pDis->param1.flags == USE_DISPLACEMENT32)
1918 {
1919 /*
1920 * TPR write:
1921 *
1922 * push ECX [51]
1923 * push EDX [52]
1924 * push EAX [50]
1925 * xor EDX,EDX [31 D2]
1926 * mov EAX,EAX [89 C0]
1927 * or
1928 * mov EAX,0000000CCh [B8 CC 00 00 00]
1929 * mov ECX,0C0000082h [B9 82 00 00 C0]
1930 * wrmsr [0F 30]
1931 * pop EAX [58]
1932 * pop EDX [5A]
1933 * pop ECX [59]
1934 * jmp return_address [E9 return_address]
1935 *
1936 */
1937 bool fUsesEax = (pDis->param2.flags == USE_REG_GEN32 && pDis->param2.base.reg_gen == USE_REG_EAX);
1938
1939 aPatch[off++] = 0x51; /* push ecx */
1940 aPatch[off++] = 0x52; /* push edx */
1941 if (!fUsesEax)
1942 aPatch[off++] = 0x50; /* push eax */
1943 aPatch[off++] = 0x31; /* xor edx, edx */
1944 aPatch[off++] = 0xD2;
1945 if (pDis->param2.flags == USE_REG_GEN32)
1946 {
1947 if (!fUsesEax)
1948 {
1949 aPatch[off++] = 0x89; /* mov eax, src_reg */
1950 aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, USE_REG_EAX);
1951 }
1952 }
1953 else
1954 {
1955 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1956 aPatch[off++] = 0xB8; /* mov eax, immediate */
1957 *(uint32_t *)&aPatch[off] = pDis->param2.parval;
1958 off += sizeof(uint32_t);
1959 }
1960 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1961 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1962 off += sizeof(uint32_t);
1963
1964 aPatch[off++] = 0x0F; /* wrmsr */
1965 aPatch[off++] = 0x30;
1966 if (!fUsesEax)
1967 aPatch[off++] = 0x58; /* pop eax */
1968 aPatch[off++] = 0x5A; /* pop edx */
1969 aPatch[off++] = 0x59; /* pop ecx */
1970 }
1971 else
1972 {
1973 /*
1974 * TPR read:
1975 *
1976 * push ECX [51]
1977 * push EDX [52]
1978 * push EAX [50]
1979 * mov ECX,0C0000082h [B9 82 00 00 C0]
1980 * rdmsr [0F 32]
1981 * mov EAX,EAX [89 C0]
1982 * pop EAX [58]
1983 * pop EDX [5A]
1984 * pop ECX [59]
1985 * jmp return_address [E9 return_address]
1986 *
1987 */
1988 Assert(pDis->param1.flags == USE_REG_GEN32);
1989
1990 if (pDis->param1.base.reg_gen != USE_REG_ECX)
1991 aPatch[off++] = 0x51; /* push ecx */
1992 if (pDis->param1.base.reg_gen != USE_REG_EDX)
1993 aPatch[off++] = 0x52; /* push edx */
1994 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1995 aPatch[off++] = 0x50; /* push eax */
1996
1997 aPatch[off++] = 0x31; /* xor edx, edx */
1998 aPatch[off++] = 0xD2;
1999
2000 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2001 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2002 off += sizeof(uint32_t);
2003
2004 aPatch[off++] = 0x0F; /* rdmsr */
2005 aPatch[off++] = 0x32;
2006
2007 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2008 {
2009 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2010 aPatch[off++] = MAKE_MODRM(3, USE_REG_EAX, pDis->param1.base.reg_gen);
2011 }
2012
2013 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2014 aPatch[off++] = 0x58; /* pop eax */
2015 if (pDis->param1.base.reg_gen != USE_REG_EDX)
2016 aPatch[off++] = 0x5A; /* pop edx */
2017 if (pDis->param1.base.reg_gen != USE_REG_ECX)
2018 aPatch[off++] = 0x59; /* pop ecx */
2019 }
2020 aPatch[off++] = 0xE9; /* jmp return_address */
2021 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
2022 off += sizeof(RTRCUINTPTR);
2023
2024 if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
2025 {
2026 /* Write new code to the patch buffer. */
2027 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
2028 AssertRC(rc);
2029
2030#ifdef LOG_ENABLED
2031 pInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
2032 while (true)
2033 {
2034 uint32_t cb;
2035
2036 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pInstr, 0, szOutput, sizeof(szOutput), &cb);
2037 if (VBOX_SUCCESS(rc))
2038 Log(("Patch instr %s\n", szOutput));
2039
2040 pInstr += cb;
2041
2042 if (pInstr >= pVM->hwaccm.s.pFreeGuestPatchMem + off)
2043 break;
2044 }
2045#endif
2046
2047 pPatch->aNewOpcode[0] = 0xE9;
2048 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2049
2050 /* Overwrite the TPR instruction with a jump. */
2051 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2052 AssertRC(rc);
2053
2054#ifdef LOG_ENABLED
2055 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
2056 if (VBOX_SUCCESS(rc))
2057 Log(("Jump: %s\n", szOutput));
2058#endif
2059 pVM->hwaccm.s.pFreeGuestPatchMem += off;
2060 pPatch->cbNewOp = 5;
2061
2062 pPatch->Core.Key = pCtx->eip;
2063 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2064 AssertRC(rc);
2065
2066 pVM->hwaccm.s.cPatches++;
2067 pVM->hwaccm.s.fTPRPatchingActive = true;
2068 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchSuccess);
2069 return VINF_SUCCESS;
2070 }
2071 else
2072 Log(("Ran out of space in our patch buffer!\n"));
2073 }
2074
2075 /* Save invalid patch, so we will not try again. */
2076 uint32_t idx = pVM->hwaccm.s.cPatches;
2077
2078#ifdef LOG_ENABLED
2079 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
2080 if (VBOX_SUCCESS(rc))
2081 Log(("Failed to patch instr: %s\n", szOutput));
2082#endif
2083
2084 pPatch = &pVM->hwaccm.s.aPatches[idx];
2085 pPatch->Core.Key = pCtx->eip;
2086 pPatch->enmType = HWACCMTPRINSTR_INVALID;
2087 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2088 AssertRC(rc);
2089 pVM->hwaccm.s.cPatches++;
2090 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchFailure);
2091 return VINF_SUCCESS;
2092}
2093
2094/**
2095 * Attempt to patch TPR mmio instructions
2096 *
2097 * @returns VBox status code.
2098 * @param pVM The VM to operate on.
2099 * @param pVCpu The VM CPU to operate on.
2100 * @param pCtx CPU context
2101 */
2102VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2103{
2104 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, (pVM->hwaccm.s.pGuestPatchMem) ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr, (void *)pVCpu->idCpu);
2105 AssertRC(rc);
2106 return rc;
2107}
2108
2109/**
2110 * Force execution of the current IO code in the recompiler
2111 *
2112 * @returns VBox status code.
2113 * @param pVM The VM to operate on.
2114 * @param pCtx Partial VM execution context
2115 */
2116VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2117{
2118 PVMCPU pVCpu = VMMGetCpu(pVM);
2119
2120 Assert(pVM->fHWACCMEnabled);
2121 Log(("HWACCMR3EmulateIoBlock\n"));
2122
2123 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2124 if (HWACCMCanEmulateIoBlockEx(pCtx))
2125 {
2126 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
2127 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
2128 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2129 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2130 return VINF_EM_RESCHEDULE_REM;
2131 }
2132 return VINF_SUCCESS;
2133}
2134
2135/**
2136 * Checks if we can currently use hardware accelerated raw mode.
2137 *
2138 * @returns boolean
2139 * @param pVM The VM to operate on.
2140 * @param pCtx Partial VM execution context
2141 */
2142VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2143{
2144 PVMCPU pVCpu = VMMGetCpu(pVM);
2145
2146 Assert(pVM->fHWACCMEnabled);
2147
2148 /* If we're still executing the IO code, then return false. */
2149 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
2150 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2151 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2152 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
2153 return false;
2154
2155 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
2156
2157 /* AMD-V supports real & protected mode with or without paging. */
2158 if (pVM->hwaccm.s.svm.fEnabled)
2159 {
2160 pVCpu->hwaccm.s.fActive = true;
2161 return true;
2162 }
2163
2164 pVCpu->hwaccm.s.fActive = false;
2165
2166 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2167#ifdef HWACCM_VMX_EMULATE_REALMODE
2168 Assert((pVM->hwaccm.s.vmx.fUnrestrictedGuest && !pVM->hwaccm.s.vmx.pRealModeTSS) || (!pVM->hwaccm.s.vmx.fUnrestrictedGuest && pVM->hwaccm.s.vmx.pRealModeTSS));
2169
2170 if (pVM->hwaccm.s.vmx.pRealModeTSS)
2171 {
2172 if (CPUMIsGuestInRealModeEx(pCtx))
2173 {
2174 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
2175 * The base must also be equal to (sel << 4).
2176 */
2177 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
2178 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
2179 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
2180 || pCtx->es != (pCtx->esHid.u64Base >> 4)
2181 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
2182 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
2183 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
2184 {
2185 return false;
2186 }
2187 }
2188 else
2189 {
2190 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2191 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
2192 * from real to protected mode. (all sorts of RPL & DPL assumptions)
2193 */
2194 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2195 && enmGuestMode >= PGMMODE_PROTECTED)
2196 {
2197 if ( (pCtx->cs & X86_SEL_RPL)
2198 || (pCtx->ds & X86_SEL_RPL)
2199 || (pCtx->es & X86_SEL_RPL)
2200 || (pCtx->fs & X86_SEL_RPL)
2201 || (pCtx->gs & X86_SEL_RPL)
2202 || (pCtx->ss & X86_SEL_RPL))
2203 {
2204 return false;
2205 }
2206 }
2207 }
2208 }
2209 else
2210#endif /* HWACCM_VMX_EMULATE_REALMODE */
2211 {
2212 if ( !CPUMIsGuestInLongModeEx(pCtx)
2213 && !pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2214 {
2215 /** @todo This should (probably) be set on every excursion to the REM,
2216 * however it's too risky right now. So, only apply it when we go
2217 * back to REM for real mode execution. (The XP hack below doesn't
2218 * work reliably without this.)
2219 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2220 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2221
2222 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2223 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
2224 return false;
2225
2226 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2227 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2228 * hidden registers (possible recompiler bug; see load_seg_vm) */
2229 if (pCtx->csHid.Attr.n.u1Present == 0)
2230 return false;
2231 if (pCtx->ssHid.Attr.n.u1Present == 0)
2232 return false;
2233
2234 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2235 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2236 /** @todo This check is actually wrong, it doesn't take the direction of the
2237 * stack segment into account. But, it does the job for now. */
2238 if (pCtx->rsp >= pCtx->ssHid.u32Limit)
2239 return false;
2240#if 0
2241 if ( pCtx->cs >= pCtx->gdtr.cbGdt
2242 || pCtx->ss >= pCtx->gdtr.cbGdt
2243 || pCtx->ds >= pCtx->gdtr.cbGdt
2244 || pCtx->es >= pCtx->gdtr.cbGdt
2245 || pCtx->fs >= pCtx->gdtr.cbGdt
2246 || pCtx->gs >= pCtx->gdtr.cbGdt)
2247 return false;
2248#endif
2249 }
2250 }
2251
2252 if (pVM->hwaccm.s.vmx.fEnabled)
2253 {
2254 uint32_t mask;
2255
2256 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2257 {
2258 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2259 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2260 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2261 mask &= ~X86_CR0_NE;
2262
2263#ifdef HWACCM_VMX_EMULATE_REALMODE
2264 if (pVM->hwaccm.s.vmx.pRealModeTSS)
2265 {
2266 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2267 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2268 }
2269 else
2270#endif
2271 {
2272 /* We support protected mode without paging using identity mapping. */
2273 mask &= ~X86_CR0_PG;
2274 }
2275 if ((pCtx->cr0 & mask) != mask)
2276 return false;
2277
2278 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2279 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2280 if ((pCtx->cr0 & mask) != 0)
2281 return false;
2282 }
2283
2284 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2285 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2286 mask &= ~X86_CR4_VMXE;
2287 if ((pCtx->cr4 & mask) != mask)
2288 return false;
2289
2290 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2291 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2292 if ((pCtx->cr4 & mask) != 0)
2293 return false;
2294
2295 pVCpu->hwaccm.s.fActive = true;
2296 return true;
2297 }
2298
2299 return false;
2300}
2301
2302/**
2303 * Notifcation from EM about a rescheduling into hardware assisted execution
2304 * mode.
2305 *
2306 * @param pVCpu Pointer to the current virtual cpu structure.
2307 */
2308VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2309{
2310 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2311}
2312
2313/**
2314 * Notifcation from EM about returning from instruction emulation (REM / EM).
2315 *
2316 * @param pVCpu Pointer to the current virtual cpu structure.
2317 */
2318VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2319{
2320 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2321}
2322
2323/**
2324 * Checks if we are currently using hardware accelerated raw mode.
2325 *
2326 * @returns boolean
2327 * @param pVCpu The VMCPU to operate on.
2328 */
2329VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2330{
2331 return pVCpu->hwaccm.s.fActive;
2332}
2333
2334/**
2335 * Checks if we are currently using nested paging.
2336 *
2337 * @returns boolean
2338 * @param pVM The VM to operate on.
2339 */
2340VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2341{
2342 return pVM->hwaccm.s.fNestedPaging;
2343}
2344
2345/**
2346 * Checks if we are currently using VPID in VT-x mode.
2347 *
2348 * @returns boolean
2349 * @param pVM The VM to operate on.
2350 */
2351VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2352{
2353 return pVM->hwaccm.s.vmx.fVPID;
2354}
2355
2356
2357/**
2358 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2359 *
2360 * @returns boolean
2361 * @param pVM The VM to operate on.
2362 */
2363VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2364{
2365 return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2366}
2367
2368/**
2369 * Restart an I/O instruction that was refused in ring-0
2370 *
2371 * @returns Strict VBox status code. Informational status codes other than the one documented
2372 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2373 * @retval VINF_SUCCESS Success.
2374 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2375 * status code must be passed on to EM.
2376 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2377 *
2378 * @param pVM The VM to operate on.
2379 * @param pVCpu The VMCPU to operate on.
2380 * @param pCtx VCPU register context
2381 */
2382VMMR3DECL(VBOXSTRICTRC) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2383{
2384 HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2385
2386 pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2387
2388 if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2389 || enmType == HWACCMPENDINGIO_INVALID)
2390 return VERR_NOT_FOUND;
2391
2392 VBOXSTRICTRC rcStrict;
2393 switch (enmType)
2394 {
2395 case HWACCMPENDINGIO_PORT_READ:
2396 {
2397 uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2398 uint32_t u32Val = 0;
2399
2400 rcStrict = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2401 &u32Val,
2402 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2403 if (IOM_SUCCESS(rcStrict))
2404 {
2405 /* Write back to the EAX register. */
2406 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2407 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2408 }
2409 break;
2410 }
2411
2412 case HWACCMPENDINGIO_PORT_WRITE:
2413 rcStrict = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2414 pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2415 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2416 if (IOM_SUCCESS(rcStrict))
2417 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2418 break;
2419
2420 default:
2421 AssertFailed();
2422 return VERR_INTERNAL_ERROR;
2423 }
2424
2425 return rcStrict;
2426}
2427
2428/**
2429 * Inject an NMI into a running VM (only VCPU 0!)
2430 *
2431 * @returns boolean
2432 * @param pVM The VM to operate on.
2433 */
2434VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2435{
2436 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2437 return VINF_SUCCESS;
2438}
2439
2440/**
2441 * Check fatal VT-x/AMD-V error and produce some meaningful
2442 * log release message.
2443 *
2444 * @param pVM The VM to operate on.
2445 * @param iStatusCode VBox status code
2446 */
2447VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2448{
2449 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2450 {
2451 switch(iStatusCode)
2452 {
2453 case VERR_VMX_INVALID_VMCS_FIELD:
2454 break;
2455
2456 case VERR_VMX_INVALID_VMCS_PTR:
2457 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
2458 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2459 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2460 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2461 break;
2462
2463 case VERR_VMX_UNABLE_TO_START_VM:
2464 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2465 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2466#if 0 /* @todo dump the current control fields to the release log */
2467 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2468 {
2469
2470 }
2471#endif
2472 break;
2473
2474 case VERR_VMX_UNABLE_TO_RESUME_VM:
2475 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2476 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2477 break;
2478
2479 case VERR_VMX_INVALID_VMXON_PTR:
2480 break;
2481 }
2482 }
2483}
2484
2485/**
2486 * Execute state save operation.
2487 *
2488 * @returns VBox status code.
2489 * @param pVM VM Handle.
2490 * @param pSSM SSM operation handle.
2491 */
2492static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2493{
2494 int rc;
2495
2496 Log(("hwaccmR3Save:\n"));
2497
2498 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2499 {
2500 /*
2501 * Save the basic bits - fortunately all the other things can be resynced on load.
2502 */
2503 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2504 AssertRCReturn(rc, rc);
2505 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2506 AssertRCReturn(rc, rc);
2507 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2508 AssertRCReturn(rc, rc);
2509
2510 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2511 AssertRCReturn(rc, rc);
2512 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2513 AssertRCReturn(rc, rc);
2514 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2515 AssertRCReturn(rc, rc);
2516 }
2517#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2518 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2519 AssertRCReturn(rc, rc);
2520 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2521 AssertRCReturn(rc, rc);
2522 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2523 AssertRCReturn(rc, rc);
2524
2525 /* Store all the guest patch records too. */
2526 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cPatches);
2527 AssertRCReturn(rc, rc);
2528
2529 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2530 {
2531 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2532
2533 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2534 AssertRCReturn(rc, rc);
2535
2536 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2537 AssertRCReturn(rc, rc);
2538
2539 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2540 AssertRCReturn(rc, rc);
2541
2542 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2543 AssertRCReturn(rc, rc);
2544
2545 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2546 AssertRCReturn(rc, rc);
2547
2548 AssertCompileSize(HWACCMTPRINSTR, 4);
2549 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2550 AssertRCReturn(rc, rc);
2551
2552 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2553 AssertRCReturn(rc, rc);
2554
2555 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2556 AssertRCReturn(rc, rc);
2557
2558 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2559 AssertRCReturn(rc, rc);
2560
2561 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2562 AssertRCReturn(rc, rc);
2563 }
2564#endif
2565 return VINF_SUCCESS;
2566}
2567
2568/**
2569 * Execute state load operation.
2570 *
2571 * @returns VBox status code.
2572 * @param pVM VM Handle.
2573 * @param pSSM SSM operation handle.
2574 * @param uVersion Data layout version.
2575 * @param uPass The data pass.
2576 */
2577static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2578{
2579 int rc;
2580
2581 Log(("hwaccmR3Load:\n"));
2582 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2583
2584 /*
2585 * Validate version.
2586 */
2587 if ( uVersion != HWACCM_SSM_VERSION
2588 && uVersion != HWACCM_SSM_VERSION_NO_PATCHING
2589 && uVersion != HWACCM_SSM_VERSION_2_0_X)
2590 {
2591 AssertMsgFailed(("hwaccmR3Load: Invalid version uVersion=%d!\n", uVersion));
2592 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2593 }
2594 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2595 {
2596 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2597 AssertRCReturn(rc, rc);
2598 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2599 AssertRCReturn(rc, rc);
2600 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2601 AssertRCReturn(rc, rc);
2602
2603 if (uVersion >= HWACCM_SSM_VERSION_NO_PATCHING)
2604 {
2605 uint32_t val;
2606
2607 rc = SSMR3GetU32(pSSM, &val);
2608 AssertRCReturn(rc, rc);
2609 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2610
2611 rc = SSMR3GetU32(pSSM, &val);
2612 AssertRCReturn(rc, rc);
2613 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2614
2615 rc = SSMR3GetU32(pSSM, &val);
2616 AssertRCReturn(rc, rc);
2617 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2618 }
2619 }
2620#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2621 if (uVersion > HWACCM_SSM_VERSION_NO_PATCHING)
2622 {
2623 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2624 AssertRCReturn(rc, rc);
2625 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2626 AssertRCReturn(rc, rc);
2627 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2628 AssertRCReturn(rc, rc);
2629
2630 /* Fetch all TPR patch records. */
2631 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cPatches);
2632 AssertRCReturn(rc, rc);
2633
2634 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2635 {
2636 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2637
2638 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2639 AssertRCReturn(rc, rc);
2640
2641 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2642 AssertRCReturn(rc, rc);
2643
2644 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2645 AssertRCReturn(rc, rc);
2646
2647 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2648 AssertRCReturn(rc, rc);
2649
2650 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2651 AssertRCReturn(rc, rc);
2652
2653 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2654 AssertRCReturn(rc, rc);
2655
2656 if (pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT)
2657 pVM->hwaccm.s.fTPRPatchingActive = true;
2658
2659 Assert(pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT || pVM->hwaccm.s.fTPRPatchingActive == false);
2660
2661 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2662 AssertRCReturn(rc, rc);
2663
2664 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2665 AssertRCReturn(rc, rc);
2666
2667 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2668 AssertRCReturn(rc, rc);
2669
2670 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2671 AssertRCReturn(rc, rc);
2672
2673 Log(("hwaccmR3Load: patch %d\n", i));
2674 Log(("Key = %x\n", pPatch->Core.Key));
2675 Log(("cbOp = %d\n", pPatch->cbOp));
2676 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2677 Log(("type = %d\n", pPatch->enmType));
2678 Log(("srcop = %d\n", pPatch->uSrcOperand));
2679 Log(("dstop = %d\n", pPatch->uDstOperand));
2680 Log(("cFaults = %d\n", pPatch->cFaults));
2681 Log(("target = %x\n", pPatch->pJumpTarget));
2682 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2683 AssertRC(rc);
2684 }
2685 }
2686#endif
2687
2688 /* Recheck all VCPUs if we can go staight into hwaccm execution mode. */
2689 if (HWACCMIsEnabled(pVM))
2690 {
2691 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2692 {
2693 PVMCPU pVCpu = &pVM->aCpus[i];
2694
2695 HWACCMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2696 }
2697 }
2698 return VINF_SUCCESS;
2699}
2700
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