VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 2623

Last change on this file since 2623 was 2555, checked in by vboxsync, 18 years ago

Added intercept code for rdtsc (not yet enabled).

  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 23.8 KB
Line 
1/* $Id: HWACCM.cpp 2555 2007-05-09 12:58:47Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006 InnoTek Systemberatung GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * If you received this file as part of a commercial VirtualBox
18 * distribution, then only the terms of your commercial VirtualBox
19 * license agreement apply instead of the previous paragraph.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/hwacc_vmx.h>
34#include <VBox/hwacc_svm.h>
35#include "HWACCMInternal.h"
36#include <VBox/vm.h>
37#include <VBox/err.h>
38#include <VBox/param.h>
39#include <VBox/patm.h>
40#include <VBox/csam.h>
41#include <VBox/selm.h>
42
43#include <iprt/assert.h>
44#include <VBox/log.h>
45#include <iprt/asm.h>
46#include <iprt/string.h>
47#include <iprt/thread.h>
48#include "x86context.h"
49
50
51/*******************************************************************************
52* Internal Functions *
53*******************************************************************************/
54static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
55static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
56
57
58/**
59 * Initializes the HWACCM.
60 *
61 * @returns VBox status code.
62 * @param pVM The VM to operate on.
63 */
64HWACCMR3DECL(int) HWACCMR3Init(PVM pVM)
65{
66 LogFlow(("HWACCMR3Init\n"));
67
68 /*
69 * Assert alignment and sizes.
70 */
71 AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
72 AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
73
74 /* Some structure checks. */
75 AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
76 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
77 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
78 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
79
80 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
81 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
82 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
83 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
84 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
85 AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
86 AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
87
88
89 /*
90 * Register the saved state data unit.
91 */
92 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
93 NULL, hwaccmR3Save, NULL,
94 NULL, hwaccmR3Load, NULL);
95 if (VBOX_FAILURE(rc))
96 return rc;
97
98 /** @todo Make sure both pages are either not accessible or readonly! */
99 /* Allocate one page for VMXON. */
100 pVM->hwaccm.s.vmx.pVMXON = SUPContAlloc(1, &pVM->hwaccm.s.vmx.pVMXONPhys);
101 if (pVM->hwaccm.s.vmx.pVMXON == 0)
102 {
103 AssertMsgFailed(("SUPContAlloc failed!!\n"));
104 return VERR_NO_MEMORY;
105 }
106 memset(pVM->hwaccm.s.vmx.pVMXON, 0, PAGE_SIZE);
107
108 /* Allocate one page for the VM control structure (VMCS). */
109 pVM->hwaccm.s.vmx.pVMCS = SUPContAlloc(1, &pVM->hwaccm.s.vmx.pVMCSPhys);
110 if (pVM->hwaccm.s.vmx.pVMCS == 0)
111 {
112 AssertMsgFailed(("SUPContAlloc failed!!\n"));
113 return VERR_NO_MEMORY;
114 }
115 memset(pVM->hwaccm.s.vmx.pVMCS, 0, PAGE_SIZE);
116
117 /* Reuse those two pages for AMD SVM. (one is active; never both) */
118 pVM->hwaccm.s.svm.pHState = pVM->hwaccm.s.vmx.pVMXON;
119 pVM->hwaccm.s.svm.pHStatePhys = pVM->hwaccm.s.vmx.pVMXONPhys;
120 pVM->hwaccm.s.svm.pVMCB = pVM->hwaccm.s.vmx.pVMCS;
121 pVM->hwaccm.s.svm.pVMCBPhys = pVM->hwaccm.s.vmx.pVMCSPhys;
122
123 /* Allocate one page for the SVM host control structure (used for vmsave/vmload). */
124 pVM->hwaccm.s.svm.pVMCBHost = SUPContAlloc(1, &pVM->hwaccm.s.svm.pVMCBHostPhys);
125 if (pVM->hwaccm.s.svm.pVMCBHost == 0)
126 {
127 AssertMsgFailed(("SUPContAlloc failed!!\n"));
128 return VERR_NO_MEMORY;
129 }
130 memset(pVM->hwaccm.s.svm.pVMCBHost, 0, PAGE_SIZE);
131
132 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
133 pVM->hwaccm.s.svm.pIOBitmap = SUPContAlloc(3, &pVM->hwaccm.s.svm.pIOBitmapPhys);
134 if (pVM->hwaccm.s.svm.pIOBitmap == 0)
135 {
136 AssertMsgFailed(("SUPContAlloc failed!!\n"));
137 return VERR_NO_MEMORY;
138 }
139 /* Set all bits to intercept all IO accesses. */
140 memset(pVM->hwaccm.s.svm.pIOBitmap, 0xff, PAGE_SIZE*3);
141
142 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
143 pVM->hwaccm.s.svm.pMSRBitmap = SUPContAlloc(2, &pVM->hwaccm.s.svm.pMSRBitmapPhys);
144 if (pVM->hwaccm.s.svm.pMSRBitmap == 0)
145 {
146 AssertMsgFailed(("SUPContAlloc failed!!\n"));
147 return VERR_NO_MEMORY;
148 }
149 /* Set all bits to intercept all MSR accesses. */
150 memset(pVM->hwaccm.s.svm.pMSRBitmap, 0xff, PAGE_SIZE*2);
151
152 /* Misc initialisation. */
153 pVM->hwaccm.s.vmx.fSupported = false;
154 pVM->hwaccm.s.svm.fSupported = false;
155 pVM->hwaccm.s.vmx.fEnabled = false;
156 pVM->hwaccm.s.svm.fEnabled = false;
157
158 pVM->hwaccm.s.fActive = false;
159
160 /* On first entry we'll sync everything. */
161 pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
162
163 pVM->hwaccm.s.vmx.cr0_mask = 0;
164 pVM->hwaccm.s.vmx.cr4_mask = 0;
165
166 /*
167 * Statistics.
168 */
169 STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
170 STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
171 STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
172
173 STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
174 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
175 STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
176 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
177 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
178 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
179 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
180 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
181 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
182 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
183 STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
184 STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
185 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
186 STAM_REG(pVM, &pVM->hwaccm.s.StatExitRdtsc, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Rdtsc", STAMUNIT_OCCURENCES, "Nr of occurances");
187 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
188 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
189 STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
190 STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
191 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
192 STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
193 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
194 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
195 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/WriteString", STAMUNIT_OCCURENCES, "Nr of occurances");
196 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringRead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/ReadString", STAMUNIT_OCCURENCES, "Nr of occurances");
197 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
198
199 STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
200 STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
201
202 STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
203 STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
204 STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
205
206 pVM->hwaccm.s.pStatExitReason = 0;
207
208#ifdef VBOX_WITH_STATISTICS
209 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVM->hwaccm.s.pStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.pStatExitReason);
210 AssertRC(rc);
211 if (VBOX_SUCCESS(rc))
212 {
213 for (int i=0;i<MAX_EXITREASON_STAT;i++)
214 {
215 char szName[64];
216 RTStrPrintf(szName, sizeof(szName), "/HWACCM/Exit/Reason/%02x", i);
217 int rc = STAMR3Register(pVM, &pVM->hwaccm.s.pStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "Exit reason");
218 AssertRC(rc);
219 }
220 }
221#endif
222
223 /* Disabled by default. */
224 pVM->fHWACCMEnabled = false;
225
226 /* HWACCM support must be explicitely enabled in the configuration file. */
227 pVM->hwaccm.s.fAllowed = false;
228 CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed);
229
230 return VINF_SUCCESS;
231}
232
233
234/**
235 * Turns off normal raw mode features
236 *
237 * @param pVM The VM to operate on.
238 */
239static void hwaccmr3DisableRawMode(PVM pVM)
240{
241 /* Disable PATM & CSAM. */
242 PATMR3AllowPatching(pVM, false);
243 CSAMDisableScanning(pVM);
244
245 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
246 SELMR3DisableMonitoring(pVM);
247 TRPMR3DisableMonitoring(pVM);
248
249 /* The hidden selector registers are now valid. */
250 CPUMSetHiddenSelRegsValid(pVM, true);
251
252 /* Disable the switcher code (safety precaution). */
253 VMMR3DisableSwitcher(pVM);
254
255 /* Disable mapping of the hypervisor into the shadow page table. */
256 PGMR3ChangeShwPDMappings(pVM, false);
257
258 /* Disable the switcher */
259 VMMR3DisableSwitcher(pVM);
260}
261
262/**
263 * Applies relocations to data and code managed by this
264 * component. This function will be called at init and
265 * whenever the VMM need to relocate it self inside the GC.
266 *
267 * @param pVM The VM.
268 */
269HWACCMR3DECL(void) HWACCMR3Relocate(PVM pVM)
270{
271#ifdef LOG_ENABLED
272 Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
273#endif
274
275 if (pVM->hwaccm.s.fAllowed == false)
276 return ;
277
278 if (pVM->hwaccm.s.vmx.fSupported)
279 {
280 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
281 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
282 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
283 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
284 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls));
285 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls));
286 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit));
287 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry));
288 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
289 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
290 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
291 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
292 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
293 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
294
295 if (pVM->hwaccm.s.fInitialized == false && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
296 {
297 /* Only try once. */
298 pVM->hwaccm.s.fInitialized = true;
299
300 int rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, NULL);
301 AssertRC(rc);
302 if (rc == VINF_SUCCESS)
303 {
304 hwaccmr3DisableRawMode(pVM);
305
306 pVM->fHWACCMEnabled = true;
307 pVM->hwaccm.s.vmx.fEnabled = true;
308 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
309 LogRel(("HWACCM: VMX enabled!\n"));
310 }
311 else
312 {
313 LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
314 pVM->fHWACCMEnabled = false;
315 }
316 }
317 }
318 else
319 if (pVM->hwaccm.s.svm.fSupported)
320 {
321 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
322 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
323 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
324 LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
325 LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.svm.u32MaxASID));
326
327 if (pVM->hwaccm.s.fInitialized == false)
328 {
329 /* Only try once. */
330 pVM->hwaccm.s.fInitialized = true;
331
332 int rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, NULL);
333 AssertRC(rc);
334 if (rc == VINF_SUCCESS)
335 {
336 hwaccmr3DisableRawMode(pVM);
337 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
338
339 pVM->fHWACCMEnabled = true;
340 pVM->hwaccm.s.svm.fEnabled = true;
341 }
342 else
343 {
344 pVM->fHWACCMEnabled = false;
345 }
346 }
347 }
348
349}
350
351
352/**
353 * Checks hardware accelerated raw mode is allowed.
354 *
355 * @returns boolean
356 * @param pVM The VM to operate on.
357 */
358HWACCMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
359{
360 return pVM->hwaccm.s.fAllowed;
361}
362
363
364/**
365 * Notification callback which is called whenever there is a chance that a CR3
366 * value might have changed.
367 * This is called by PGM.
368 *
369 * @param pVM The VM to operate on.
370 * @param enmShadowMode New paging mode.
371 */
372HWACCMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode)
373{
374 pVM->hwaccm.s.enmShadowMode = enmShadowMode;
375}
376
377/**
378 * Terminates the HWACCM.
379 *
380 * Termination means cleaning up and freeing all resources,
381 * the VM it self is at this point powered off or suspended.
382 *
383 * @returns VBox status code.
384 * @param pVM The VM to operate on.
385 */
386HWACCMR3DECL(int) HWACCMR3Term(PVM pVM)
387{
388 if (pVM->hwaccm.s.pStatExitReason)
389 {
390 MMHyperFree(pVM, pVM->hwaccm.s.pStatExitReason);
391 pVM->hwaccm.s.pStatExitReason = 0;
392 }
393
394 if (pVM->hwaccm.s.vmx.pVMXON)
395 {
396 SUPContFree(pVM->hwaccm.s.vmx.pVMXON, 1);
397 pVM->hwaccm.s.vmx.pVMXON = 0;
398 }
399 if (pVM->hwaccm.s.vmx.pVMCS)
400 {
401 SUPContFree(pVM->hwaccm.s.vmx.pVMCS, 1);
402 pVM->hwaccm.s.vmx.pVMCS = 0;
403 }
404 if (pVM->hwaccm.s.svm.pVMCBHost)
405 {
406 SUPContFree(pVM->hwaccm.s.svm.pVMCBHost, 1);
407 pVM->hwaccm.s.svm.pVMCBHost = 0;
408 }
409 if (pVM->hwaccm.s.svm.pIOBitmap)
410 {
411 SUPContFree(pVM->hwaccm.s.svm.pIOBitmap, 3);
412 pVM->hwaccm.s.svm.pIOBitmap = 0;
413 }
414 if (pVM->hwaccm.s.svm.pMSRBitmap)
415 {
416 SUPContFree(pVM->hwaccm.s.svm.pMSRBitmap, 2);
417 pVM->hwaccm.s.svm.pMSRBitmap = 0;
418 }
419 return 0;
420}
421
422
423/**
424 * The VM is being reset.
425 *
426 * For the HWACCM component this means that any GDT/LDT/TSS monitors
427 * needs to be removed.
428 *
429 * @param pVM VM handle.
430 */
431HWACCMR3DECL(void) HWACCMR3Reset(PVM pVM)
432{
433 LogFlow(("HWACCMR3Reset:\n"));
434
435 if (pVM->fHWACCMEnabled)
436 hwaccmr3DisableRawMode(pVM);
437
438 /* On first entry we'll sync everything. */
439 pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
440
441 pVM->hwaccm.s.vmx.cr0_mask = 0;
442 pVM->hwaccm.s.vmx.cr4_mask = 0;
443
444 pVM->hwaccm.s.Event.fPending = false;
445}
446
447/**
448 * Checks if we can currently use hardware accelerated raw mode.
449 *
450 * @returns boolean
451 * @param pVM The VM to operate on.
452 * @param pCtx Partial VM execution context
453 */
454HWACCMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
455{
456 uint32_t mask;
457
458 Assert(pVM->fHWACCMEnabled);
459
460 /* AMD SVM supports real & protected mode with or without paging. */
461 if (pVM->hwaccm.s.svm.fEnabled)
462 {
463 pVM->hwaccm.s.fActive = true;
464 return true;
465 }
466
467 /* @todo we can support real-mode by using v86 and protected mode without paging with identity mapped pages.
468 * (but do we really care?)
469 */
470
471 pVM->hwaccm.s.fActive = false;
472
473 /** @note The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
474
475 /* Too early for VMX. */
476 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
477 return false;
478
479 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
480 if (pCtx->csHid.Attr.n.u1Present == 0)
481 return false;
482 if (pCtx->ssHid.Attr.n.u1Present == 0)
483 return false;
484
485 /** @todo if we remove this check, then Windows XP install fails during the textmode phase */
486 if (!(pCtx->cr0 & X86_CR0_WRITE_PROTECT))
487 return false;
488
489 if (pVM->hwaccm.s.vmx.fEnabled)
490 {
491 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
492 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
493 /** @note We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
494 mask &= ~X86_CR0_NE;
495
496 if ((pCtx->cr0 & mask) != mask)
497 return false;
498
499 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
500 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
501 if ((pCtx->cr0 & mask) != 0)
502 return false;
503
504 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
505 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
506 mask &= ~X86_CR4_VMXE;
507 if ((pCtx->cr4 & mask) != mask)
508 return false;
509
510 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
511 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
512 if ((pCtx->cr4 & mask) != 0)
513 return false;
514
515 pVM->hwaccm.s.fActive = true;
516 return true;
517 }
518#if 0
519 else
520 if (pVM->hwaccm.s.svm.fEnabled)
521 {
522 pVM->hwaccm.s.fActive = true;
523 return true;
524 }
525#endif
526
527 return false;
528}
529
530/**
531 * Checks if we are currently using hardware accelerated raw mode.
532 *
533 * @returns boolean
534 * @param pVM The VM to operate on.
535 */
536HWACCMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
537{
538 return pVM->hwaccm.s.fActive;
539}
540
541/**
542 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
543 *
544 * @returns boolean
545 * @param pVM The VM to operate on.
546 */
547HWACCMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
548{
549 return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
550}
551
552/**
553 * Execute state save operation.
554 *
555 * @returns VBox status code.
556 * @param pVM VM Handle.
557 * @param pSSM SSM operation handle.
558 */
559static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
560{
561 int rc;
562
563 Log(("hwaccmR3Save:\n"));
564
565 /*
566 * Save the basic bits - fortunately all the other things can be resynced on load.
567 */
568 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
569 AssertRCReturn(rc, rc);
570 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
571 AssertRCReturn(rc, rc);
572 rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
573 AssertRCReturn(rc, rc);
574
575 return VINF_SUCCESS;
576}
577
578
579/**
580 * Execute state load operation.
581 *
582 * @returns VBox status code.
583 * @param pVM VM Handle.
584 * @param pSSM SSM operation handle.
585 * @param u32Version Data layout version.
586 */
587static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
588{
589 int rc;
590
591 Log(("hwaccmR3Load:\n"));
592
593 /*
594 * Validate version.
595 */
596 if (u32Version != HWACCM_SSM_VERSION)
597 {
598 Log(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
599 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
600 }
601 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
602 AssertRCReturn(rc, rc);
603 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
604 AssertRCReturn(rc, rc);
605 rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
606 AssertRCReturn(rc, rc);
607
608 return VINF_SUCCESS;
609}
610
611
612
613
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette