HWACCM.cpp@ 2705

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1	/* $Id: HWACCM.cpp 2699 2007-05-17 15:18:06Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_HWACCM
26	#include <VBox/cpum.h>
27	#include <VBox/stam.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/trpm.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/hwacc_vmx.h>
34	#include <VBox/hwacc_svm.h>
35	#include "HWACCMInternal.h"
36	#include <VBox/vm.h>
37	#include <VBox/err.h>
38	#include <VBox/param.h>
39	#include <VBox/patm.h>
40	#include <VBox/csam.h>
41	#include <VBox/selm.h>
42
43	#include <iprt/assert.h>
44	#include <VBox/log.h>
45	#include <iprt/asm.h>
46	#include <iprt/string.h>
47	#include <iprt/thread.h>
48	#include "x86context.h"
49
50
51	/*******************************************************************************
52	* Internal Functions *
53	*******************************************************************************/
54	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
55	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
56
57
58	/**
59	* Initializes the HWACCM.
60	*
61	* @returns VBox status code.
62	* @param pVM The VM to operate on.
63	*/
64	HWACCMR3DECL(int) HWACCMR3Init(PVM pVM)
65	{
66	LogFlow(("HWACCMR3Init\n"));
67
68	/*
69	* Assert alignment and sizes.
70	*/
71	AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
72	AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
73
74	/* Some structure checks. */
75	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
76	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
77	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
78	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
79
80	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
81	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
82	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
83	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
84	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
85	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
86	AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
87
88
89	/*
90	* Register the saved state data unit.
91	*/
92	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
93	NULL, hwaccmR3Save, NULL,
94	NULL, hwaccmR3Load, NULL);
95	if (VBOX_FAILURE(rc))
96	return rc;
97
98	/** @todo Make sure both pages are either not accessible or readonly! */
99	/* Allocate one page for VMXON. */
100	pVM->hwaccm.s.vmx.pVMXON = SUPContAlloc(1, &pVM->hwaccm.s.vmx.pVMXONPhys);
101	if (pVM->hwaccm.s.vmx.pVMXON == 0)
102	{
103	AssertMsgFailed(("SUPContAlloc failed!!\n"));
104	return VERR_NO_MEMORY;
105	}
106	memset(pVM->hwaccm.s.vmx.pVMXON, 0, PAGE_SIZE);
107
108	/* Allocate one page for the VM control structure (VMCS). */
109	pVM->hwaccm.s.vmx.pVMCS = SUPContAlloc(1, &pVM->hwaccm.s.vmx.pVMCSPhys);
110	if (pVM->hwaccm.s.vmx.pVMCS == 0)
111	{
112	AssertMsgFailed(("SUPContAlloc failed!!\n"));
113	return VERR_NO_MEMORY;
114	}
115	memset(pVM->hwaccm.s.vmx.pVMCS, 0, PAGE_SIZE);
116
117	/* Reuse those two pages for AMD SVM. (one is active; never both) */
118	pVM->hwaccm.s.svm.pHState = pVM->hwaccm.s.vmx.pVMXON;
119	pVM->hwaccm.s.svm.pHStatePhys = pVM->hwaccm.s.vmx.pVMXONPhys;
120	pVM->hwaccm.s.svm.pVMCB = pVM->hwaccm.s.vmx.pVMCS;
121	pVM->hwaccm.s.svm.pVMCBPhys = pVM->hwaccm.s.vmx.pVMCSPhys;
122
123	/* Allocate one page for the SVM host control structure (used for vmsave/vmload). */
124	pVM->hwaccm.s.svm.pVMCBHost = SUPContAlloc(1, &pVM->hwaccm.s.svm.pVMCBHostPhys);
125	if (pVM->hwaccm.s.svm.pVMCBHost == 0)
126	{
127	AssertMsgFailed(("SUPContAlloc failed!!\n"));
128	return VERR_NO_MEMORY;
129	}
130	memset(pVM->hwaccm.s.svm.pVMCBHost, 0, PAGE_SIZE);
131
132	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
133	pVM->hwaccm.s.svm.pIOBitmap = SUPContAlloc(3, &pVM->hwaccm.s.svm.pIOBitmapPhys);
134	if (pVM->hwaccm.s.svm.pIOBitmap == 0)
135	{
136	AssertMsgFailed(("SUPContAlloc failed!!\n"));
137	return VERR_NO_MEMORY;
138	}
139	/* Set all bits to intercept all IO accesses. */
140	memset(pVM->hwaccm.s.svm.pIOBitmap, 0xff, PAGE_SIZE*3);
141
142	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
143	pVM->hwaccm.s.svm.pMSRBitmap = SUPContAlloc(2, &pVM->hwaccm.s.svm.pMSRBitmapPhys);
144	if (pVM->hwaccm.s.svm.pMSRBitmap == 0)
145	{
146	AssertMsgFailed(("SUPContAlloc failed!!\n"));
147	return VERR_NO_MEMORY;
148	}
149	/* Set all bits to intercept all MSR accesses. */
150	memset(pVM->hwaccm.s.svm.pMSRBitmap, 0xff, PAGE_SIZE*2);
151
152	/* Misc initialisation. */
153	pVM->hwaccm.s.vmx.fSupported = false;
154	pVM->hwaccm.s.svm.fSupported = false;
155	pVM->hwaccm.s.vmx.fEnabled = false;
156	pVM->hwaccm.s.svm.fEnabled = false;
157
158	pVM->hwaccm.s.fActive = false;
159
160	/* On first entry we'll sync everything. */
161	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
162
163	pVM->hwaccm.s.vmx.cr0_mask = 0;
164	pVM->hwaccm.s.vmx.cr4_mask = 0;
165
166	/*
167	* Statistics.
168	*/
169	STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
170	STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
171	STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
172
173	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
174	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
175	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
176	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
177	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
178	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
179	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
180	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
181	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
182	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
183	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
184	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
185	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
186	STAM_REG(pVM, &pVM->hwaccm.s.StatExitRdtsc, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Rdtsc", STAMUNIT_OCCURENCES, "Nr of occurances");
187	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
188	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
189	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
190	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
191	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
192	STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
193	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
194	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
195	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/WriteString", STAMUNIT_OCCURENCES, "Nr of occurances");
196	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringRead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/ReadString", STAMUNIT_OCCURENCES, "Nr of occurances");
197	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
198
199	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
200	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
201
202	STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
203	STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
204	STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
205
206	pVM->hwaccm.s.pStatExitReason = 0;
207
208	#ifdef VBOX_WITH_STATISTICS
209	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVM->hwaccm.s.pStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.pStatExitReason);
210	AssertRC(rc);
211	if (VBOX_SUCCESS(rc))
212	{
213	for (int i=0;i<MAX_EXITREASON_STAT;i++)
214	{
215	char szName[64];
216	RTStrPrintf(szName, sizeof(szName), "/HWACCM/Exit/Reason/%02x", i);
217	int rc = STAMR3Register(pVM, &pVM->hwaccm.s.pStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "Exit reason");
218	AssertRC(rc);
219	}
220	}
221	pVM->hwaccm.s.pStatExitReasonR0 = MMHyperR3ToR0(pVM, pVM->hwaccm.s.pStatExitReason);
222	Assert(pVM->hwaccm.s.pStatExitReasonR0);
223	#endif
224
225	/* Disabled by default. */
226	pVM->fHWACCMEnabled = false;
227
228	/* HWACCM support must be explicitely enabled in the configuration file. */
229	pVM->hwaccm.s.fAllowed = false;
230	CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed);
231
232	return VINF_SUCCESS;
233	}
234
235
236	/**
237	* Turns off normal raw mode features
238	*
239	* @param pVM The VM to operate on.
240	*/
241	static void hwaccmr3DisableRawMode(PVM pVM)
242	{
243	/* Disable PATM & CSAM. */
244	PATMR3AllowPatching(pVM, false);
245	CSAMDisableScanning(pVM);
246
247	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
248	SELMR3DisableMonitoring(pVM);
249	TRPMR3DisableMonitoring(pVM);
250
251	/* The hidden selector registers are now valid. */
252	CPUMSetHiddenSelRegsValid(pVM, true);
253
254	/* Disable the switcher code (safety precaution). */
255	VMMR3DisableSwitcher(pVM);
256
257	/* Disable mapping of the hypervisor into the shadow page table. */
258	PGMR3ChangeShwPDMappings(pVM, false);
259
260	/* Disable the switcher */
261	VMMR3DisableSwitcher(pVM);
262	}
263
264	/**
265	* Applies relocations to data and code managed by this
266	* component. This function will be called at init and
267	* whenever the VMM need to relocate it self inside the GC.
268	*
269	* @param pVM The VM.
270	*/
271	HWACCMR3DECL(void) HWACCMR3Relocate(PVM pVM)
272	{
273	#ifdef LOG_ENABLED
274	Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
275	#endif
276
277	if (pVM->hwaccm.s.fAllowed == false)
278	return ;
279
280	if (pVM->hwaccm.s.vmx.fSupported)
281	{
282	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
283	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
284	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
285	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
286	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls));
287	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls));
288	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit));
289	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry));
290	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
291	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
292	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
293	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
294	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
295	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
296
297	if (pVM->hwaccm.s.fInitialized == false && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
298	{
299	/* Only try once. */
300	pVM->hwaccm.s.fInitialized = true;
301
302	int rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, NULL);
303	AssertRC(rc);
304	if (rc == VINF_SUCCESS)
305	{
306	hwaccmr3DisableRawMode(pVM);
307
308	pVM->fHWACCMEnabled = true;
309	pVM->hwaccm.s.vmx.fEnabled = true;
310	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
311	LogRel(("HWACCM: VMX enabled!\n"));
312	}
313	else
314	{
315	LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
316	pVM->fHWACCMEnabled = false;
317	}
318	}
319	}
320	else
321	if (pVM->hwaccm.s.svm.fSupported)
322	{
323	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
324	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
325	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
326	LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
327	LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.svm.u32MaxASID));
328
329	if (pVM->hwaccm.s.fInitialized == false)
330	{
331	/* Only try once. */
332	pVM->hwaccm.s.fInitialized = true;
333
334	int rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, NULL);
335	AssertRC(rc);
336	if (rc == VINF_SUCCESS)
337	{
338	hwaccmr3DisableRawMode(pVM);
339	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
340
341	pVM->fHWACCMEnabled = true;
342	pVM->hwaccm.s.svm.fEnabled = true;
343	}
344	else
345	{
346	pVM->fHWACCMEnabled = false;
347	}
348	}
349	}
350
351	}
352
353
354	/**
355	* Checks hardware accelerated raw mode is allowed.
356	*
357	* @returns boolean
358	* @param pVM The VM to operate on.
359	*/
360	HWACCMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
361	{
362	return pVM->hwaccm.s.fAllowed;
363	}
364
365
366	/**
367	* Notification callback which is called whenever there is a chance that a CR3
368	* value might have changed.
369	* This is called by PGM.
370	*
371	* @param pVM The VM to operate on.
372	* @param enmShadowMode New paging mode.
373	*/
374	HWACCMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode)
375	{
376	pVM->hwaccm.s.enmShadowMode = enmShadowMode;
377	}
378
379	/**
380	* Terminates the HWACCM.
381	*
382	* Termination means cleaning up and freeing all resources,
383	* the VM it self is at this point powered off or suspended.
384	*
385	* @returns VBox status code.
386	* @param pVM The VM to operate on.
387	*/
388	HWACCMR3DECL(int) HWACCMR3Term(PVM pVM)
389	{
390	if (pVM->hwaccm.s.pStatExitReason)
391	{
392	MMHyperFree(pVM, pVM->hwaccm.s.pStatExitReason);
393	pVM->hwaccm.s.pStatExitReason = 0;
394	}
395
396	if (pVM->hwaccm.s.vmx.pVMXON)
397	{
398	SUPContFree(pVM->hwaccm.s.vmx.pVMXON, 1);
399	pVM->hwaccm.s.vmx.pVMXON = 0;
400	}
401	if (pVM->hwaccm.s.vmx.pVMCS)
402	{
403	SUPContFree(pVM->hwaccm.s.vmx.pVMCS, 1);
404	pVM->hwaccm.s.vmx.pVMCS = 0;
405	}
406	if (pVM->hwaccm.s.svm.pVMCBHost)
407	{
408	SUPContFree(pVM->hwaccm.s.svm.pVMCBHost, 1);
409	pVM->hwaccm.s.svm.pVMCBHost = 0;
410	}
411	if (pVM->hwaccm.s.svm.pIOBitmap)
412	{
413	SUPContFree(pVM->hwaccm.s.svm.pIOBitmap, 3);
414	pVM->hwaccm.s.svm.pIOBitmap = 0;
415	}
416	if (pVM->hwaccm.s.svm.pMSRBitmap)
417	{
418	SUPContFree(pVM->hwaccm.s.svm.pMSRBitmap, 2);
419	pVM->hwaccm.s.svm.pMSRBitmap = 0;
420	}
421	return 0;
422	}
423
424
425	/**
426	* The VM is being reset.
427	*
428	* For the HWACCM component this means that any GDT/LDT/TSS monitors
429	* needs to be removed.
430	*
431	* @param pVM VM handle.
432	*/
433	HWACCMR3DECL(void) HWACCMR3Reset(PVM pVM)
434	{
435	LogFlow(("HWACCMR3Reset:\n"));
436
437	if (pVM->fHWACCMEnabled)
438	hwaccmr3DisableRawMode(pVM);
439
440	/* On first entry we'll sync everything. */
441	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
442
443	pVM->hwaccm.s.vmx.cr0_mask = 0;
444	pVM->hwaccm.s.vmx.cr4_mask = 0;
445
446	pVM->hwaccm.s.Event.fPending = false;
447	}
448
449	/**
450	* Checks if we can currently use hardware accelerated raw mode.
451	*
452	* @returns boolean
453	* @param pVM The VM to operate on.
454	* @param pCtx Partial VM execution context
455	*/
456	HWACCMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
457	{
458	uint32_t mask;
459
460	Assert(pVM->fHWACCMEnabled);
461
462	/* AMD SVM supports real & protected mode with or without paging. */
463	if (pVM->hwaccm.s.svm.fEnabled)
464	{
465	pVM->hwaccm.s.fActive = true;
466	return true;
467	}
468
469	/* @todo we can support real-mode by using v86 and protected mode without paging with identity mapped pages.
470	* (but do we really care?)
471	*/
472
473	pVM->hwaccm.s.fActive = false;
474
475	/** @note The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
476
477	/* Too early for VMX. */
478	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
479	return false;
480
481	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
482	if (pCtx->csHid.Attr.n.u1Present == 0)
483	return false;
484	if (pCtx->ssHid.Attr.n.u1Present == 0)
485	return false;
486
487	/** @todo if we remove this check, then Windows XP install fails during the textmode phase */
488	if (!(pCtx->cr0 & X86_CR0_WRITE_PROTECT))
489	return false;
490
491	if (pVM->hwaccm.s.vmx.fEnabled)
492	{
493	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
494	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
495	/** @note We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
496	mask &= ~X86_CR0_NE;
497
498	if ((pCtx->cr0 & mask) != mask)
499	return false;
500
501	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
502	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
503	if ((pCtx->cr0 & mask) != 0)
504	return false;
505
506	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
507	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
508	mask &= ~X86_CR4_VMXE;
509	if ((pCtx->cr4 & mask) != mask)
510	return false;
511
512	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
513	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
514	if ((pCtx->cr4 & mask) != 0)
515	return false;
516
517	pVM->hwaccm.s.fActive = true;
518	return true;
519	}
520	#if 0
521	else
522	if (pVM->hwaccm.s.svm.fEnabled)
523	{
524	pVM->hwaccm.s.fActive = true;
525	return true;
526	}
527	#endif
528
529	return false;
530	}
531
532	/**
533	* Checks if we are currently using hardware accelerated raw mode.
534	*
535	* @returns boolean
536	* @param pVM The VM to operate on.
537	*/
538	HWACCMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
539	{
540	return pVM->hwaccm.s.fActive;
541	}
542
543	/**
544	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
545	*
546	* @returns boolean
547	* @param pVM The VM to operate on.
548	*/
549	HWACCMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
550	{
551	return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
552	}
553
554	/**
555	* Execute state save operation.
556	*
557	* @returns VBox status code.
558	* @param pVM VM Handle.
559	* @param pSSM SSM operation handle.
560	*/
561	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
562	{
563	int rc;
564
565	Log(("hwaccmR3Save:\n"));
566
567	/*
568	* Save the basic bits - fortunately all the other things can be resynced on load.
569	*/
570	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
571	AssertRCReturn(rc, rc);
572	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
573	AssertRCReturn(rc, rc);
574	rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
575	AssertRCReturn(rc, rc);
576
577	return VINF_SUCCESS;
578	}
579
580
581	/**
582	* Execute state load operation.
583	*
584	* @returns VBox status code.
585	* @param pVM VM Handle.
586	* @param pSSM SSM operation handle.
587	* @param u32Version Data layout version.
588	*/
589	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
590	{
591	int rc;
592
593	Log(("hwaccmR3Load:\n"));
594
595	/*
596	* Validate version.
597	*/
598	if (u32Version != HWACCM_SSM_VERSION)
599	{
600	Log(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
601	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
602	}
603	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
604	AssertRCReturn(rc, rc);
605	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
606	AssertRCReturn(rc, rc);
607	rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
608	AssertRCReturn(rc, rc);
609
610	return VINF_SUCCESS;
611	}
612
613
614
615

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source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 2705

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