VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 27169

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1/* $Id: HWACCM.cpp 27169 2010-03-08 14:21:55Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdmapi.h>
30#include <VBox/pgm.h>
31#include <VBox/ssm.h>
32#include <VBox/trpm.h>
33#include <VBox/dbgf.h>
34#include <VBox/iom.h>
35#include <VBox/patm.h>
36#include <VBox/csam.h>
37#include <VBox/selm.h>
38#include <VBox/rem.h>
39#include <VBox/hwacc_vmx.h>
40#include <VBox/hwacc_svm.h>
41#include "HWACCMInternal.h"
42#include <VBox/vm.h>
43#include <VBox/err.h>
44#include <VBox/param.h>
45
46#include <iprt/assert.h>
47#include <VBox/log.h>
48#include <iprt/asm.h>
49#include <iprt/string.h>
50#include <iprt/env.h>
51#include <iprt/thread.h>
52
53/*******************************************************************************
54* Global Variables *
55*******************************************************************************/
56#ifdef VBOX_WITH_STATISTICS
57# define EXIT_REASON(def, val, str) #def " - " #val " - " str
58# define EXIT_REASON_NIL() NULL
59/** Exit reason descriptions for VT-x, used to describe statistics. */
60static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
61{
62 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
63 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
64 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
65 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
66 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
67 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
68 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
69 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
72 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
73 EXIT_REASON_NIL(),
74 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
75 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
76 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
77 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
78 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
79 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
80 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
81 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
82 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
83 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
84 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
85 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
86 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
87 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
88 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
89 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
90 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
91 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
92 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
93 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
94 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
95 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
96 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
99 EXIT_REASON_NIL(),
100 EXIT_REASON_NIL(),
101 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
102 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
103 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
106 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
107 EXIT_REASON_NIL(),
108 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
109 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
110 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
111 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
112 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
113 EXIT_REASON_NIL(),
114 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
115 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
116 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
117 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
118 EXIT_REASON_NIL()
119};
120/** Exit reason descriptions for AMD-V, used to describe statistics. */
121static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
122{
123 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
124 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
125 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
126 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
127 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
128 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
129 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
130 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
131 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
132 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
133 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
134 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
135 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
136 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
137 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
138 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
154 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
155 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
156 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
157 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
158 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
159 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
160 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
161 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
162 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
163 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
164 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
165 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
166 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
167 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
168 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
169 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
170 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
186 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_INTR , 96, "Physical maskable interrupt."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_NMI , 97, "Physical non-maskable interrupt."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_SMI , 98, "System management interrupt."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_INIT , 99, "Physical INIT signal."),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_VINTR ,100, "Visual interrupt."),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_IDTR_READ ,102, "Read IDTR"),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_GDTR_READ ,103, "Read GDTR"),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_LDTR_READ ,104, "Read LDTR."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,105, "Read TR."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,106, "Write IDTR."),
230 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,107, "Write GDTR."),
231 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,108, "Write LDTR."),
232 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,109, "Write TR."),
233 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
234 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
235 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
236 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
237 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
238 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
239 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
240 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
241 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
242 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
243 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
244 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
245 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
246 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
247 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
248 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
249 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
250 EXIT_REASON(SVM_EXIT_TASK_SHUTDOWN ,127, "Shutdown."),
251 EXIT_REASON(SVM_EXIT_TASK_VMRUN ,128, "VMRUN instruction."),
252 EXIT_REASON(SVM_EXIT_TASK_VMCALL ,129, "VMCALL instruction."),
253 EXIT_REASON(SVM_EXIT_TASK_VMLOAD ,130, "VMLOAD instruction."),
254 EXIT_REASON(SVM_EXIT_TASK_VMSAVE ,131, "VMSAVE instruction."),
255 EXIT_REASON(SVM_EXIT_TASK_STGI ,132, "STGI instruction."),
256 EXIT_REASON(SVM_EXIT_TASK_CLGI ,133, "CLGI instruction."),
257 EXIT_REASON(SVM_EXIT_TASK_SKINIT ,134, "SKINIT instruction."),
258 EXIT_REASON(SVM_EXIT_TASK_RDTSCP ,135, "RDTSCP instruction."),
259 EXIT_REASON(SVM_EXIT_TASK_ICEBP ,136, "ICEBP instruction."),
260 EXIT_REASON(SVM_EXIT_TASK_WBINVD ,137, "WBINVD instruction."),
261 EXIT_REASON(SVM_EXIT_TASK_MONITOR ,138, "MONITOR instruction."),
262 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
263 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
264 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
265 EXIT_REASON_NIL()
266};
267# undef EXIT_REASON
268# undef EXIT_REASON_NIL
269#endif /* VBOX_WITH_STATISTICS */
270
271/*******************************************************************************
272* Internal Functions *
273*******************************************************************************/
274static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
275static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
276
277
278/**
279 * Initializes the HWACCM.
280 *
281 * @returns VBox status code.
282 * @param pVM The VM to operate on.
283 */
284VMMR3DECL(int) HWACCMR3Init(PVM pVM)
285{
286 LogFlow(("HWACCMR3Init\n"));
287
288 /*
289 * Assert alignment and sizes.
290 */
291 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
292 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
293
294 /* Some structure checks. */
295 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
296 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
299
300 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
303 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
304 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
305 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
306 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
307
308
309 /*
310 * Register the saved state data unit.
311 */
312 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
313 NULL, NULL, NULL,
314 NULL, hwaccmR3Save, NULL,
315 NULL, hwaccmR3Load, NULL);
316 if (RT_FAILURE(rc))
317 return rc;
318
319 /* Misc initialisation. */
320 pVM->hwaccm.s.vmx.fSupported = false;
321 pVM->hwaccm.s.svm.fSupported = false;
322 pVM->hwaccm.s.vmx.fEnabled = false;
323 pVM->hwaccm.s.svm.fEnabled = false;
324
325 pVM->hwaccm.s.fNestedPaging = false;
326 pVM->hwaccm.s.fLargePages = false;
327
328 /* Disabled by default. */
329 pVM->fHWACCMEnabled = false;
330
331 /*
332 * Check CFGM options.
333 */
334 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
335 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
336 /* Nested paging: disabled by default. */
337 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
338 AssertRC(rc);
339
340 /* Large pages: disabled by default. */
341 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hwaccm.s.fLargePages, false);
342 AssertRC(rc);
343
344 /* VT-x VPID: disabled by default. */
345 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
346 AssertRC(rc);
347
348 /* HWACCM support must be explicitely enabled in the configuration file. */
349 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
350 AssertRC(rc);
351
352 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
353 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hwaccm.s.fTRPPatchingAllowed, false);
354 AssertRC(rc);
355
356#ifdef RT_OS_DARWIN
357 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
358#else
359 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
360#endif
361 {
362 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
363 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
364 return VERR_HWACCM_CONFIG_MISMATCH;
365 }
366
367 if (VMMIsHwVirtExtForced(pVM))
368 pVM->fHWACCMEnabled = true;
369
370#if HC_ARCH_BITS == 32
371 /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
372 * (To use the default, don't set 64bitEnabled in CFGM.) */
373 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
374 AssertLogRelRCReturn(rc, rc);
375 if (pVM->hwaccm.s.fAllow64BitGuests)
376 {
377# ifdef RT_OS_DARWIN
378 if (!VMMIsHwVirtExtForced(pVM))
379# else
380 if (!pVM->hwaccm.s.fAllowed)
381# endif
382 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
383 }
384#else
385 /* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
386 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
387 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
388 AssertLogRelRCReturn(rc, rc);
389#endif
390
391
392 /** Determine the init method for AMD-V and VT-x; either one global init for each host CPU
393 * or local init each time we wish to execute guest code.
394 *
395 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
396 */
397 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hwaccm.s.fGlobalInit,
398#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
399 false
400#else
401 true
402#endif
403 );
404
405 /* Max number of resume loops. */
406 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
407 AssertRC(rc);
408
409 return VINF_SUCCESS;
410}
411
412/**
413 * Initializes the per-VCPU HWACCM.
414 *
415 * @returns VBox status code.
416 * @param pVM The VM to operate on.
417 */
418VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
419{
420 LogFlow(("HWACCMR3InitCPU\n"));
421
422 for (VMCPUID i = 0; i < pVM->cCpus; i++)
423 {
424 PVMCPU pVCpu = &pVM->aCpus[i];
425
426 pVCpu->hwaccm.s.fActive = false;
427 }
428
429#ifdef VBOX_WITH_STATISTICS
430 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
431 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
432 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
433 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
434
435 /*
436 * Statistics.
437 */
438 for (VMCPUID i = 0; i < pVM->cCpus; i++)
439 {
440 PVMCPU pVCpu = &pVM->aCpus[i];
441 int rc;
442
443 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of RTMpPokeCpu",
444 "/PROF/HWACCM/CPU%d/Poke", i);
445 AssertRC(rc);
446 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait",
447 "/PROF/HWACCM/CPU%d/PokeWait", i);
448 AssertRC(rc);
449 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait when RTMpPokeCpu fails",
450 "/PROF/HWACCM/CPU%d/PokeWaitFailed", i);
451 AssertRC(rc);
452 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
453 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
454 AssertRC(rc);
455 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
456 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
457 AssertRC(rc);
458 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
459 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
460 AssertRC(rc);
461# if 1 /* temporary for tracking down darwin holdup. */
462 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
463 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
464 AssertRC(rc);
465 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
466 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
467 AssertRC(rc);
468 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
469 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
470 AssertRC(rc);
471# endif
472 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
473 "/PROF/HWACCM/CPU%d/InGC", i);
474 AssertRC(rc);
475
476# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
477 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
478 "/PROF/HWACCM/CPU%d/Switcher3264", i);
479 AssertRC(rc);
480# endif
481
482# define HWACCM_REG_COUNTER(a, b) \
483 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
484 AssertRC(rc);
485
486 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
487 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
488 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
489 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
490 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
491 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
492 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
493 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
494 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
495 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
496 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
498 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
499 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
503 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
504 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
505 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
506 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
507 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
508 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
509 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
510 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
511 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
512 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
513 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
514 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
515 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
516 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
517 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
518 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
519 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
520 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
521 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
522 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
523
524 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
525 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
526
527 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
528 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
529 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
530
531 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPage, "/HWACCM/CPU%d/Flush/Page");
532 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
533 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
534 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLB, "/HWACCM/CPU%d/Flush/TLB");
535 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
536 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
537 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
538 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
539 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
540 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
541 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
542 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
543 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
544
545 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
546 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
547 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow, "/HWACCM/CPU%d/TSC/InterceptOverflow");
548
549 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
550 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
551 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
552
553 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
554 {
555 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
556 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
557 AssertRC(rc);
558 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
559 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
560 AssertRC(rc);
561 }
562
563#undef HWACCM_REG_COUNTER
564
565 pVCpu->hwaccm.s.paStatExitReason = NULL;
566
567 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
568 AssertRC(rc);
569 if (RT_SUCCESS(rc))
570 {
571 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
572 for (int j=0;j<MAX_EXITREASON_STAT;j++)
573 {
574 if (papszDesc[j])
575 {
576 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
577 papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
578 AssertRC(rc);
579 }
580 }
581 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
582 AssertRC(rc);
583 }
584 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
585# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
586 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
587# else
588 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
589# endif
590
591 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
592 AssertRCReturn(rc, rc);
593 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
594# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
595 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
596# else
597 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
598# endif
599 for (unsigned j = 0; j < 255; j++)
600 STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
601 (j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
602
603 }
604#endif /* VBOX_WITH_STATISTICS */
605
606#ifdef VBOX_WITH_CRASHDUMP_MAGIC
607 /* Magic marker for searching in crash dumps. */
608 for (VMCPUID i = 0; i < pVM->cCpus; i++)
609 {
610 PVMCPU pVCpu = &pVM->aCpus[i];
611
612 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
613 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
614 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
615 }
616#endif
617 return VINF_SUCCESS;
618}
619
620/**
621 * Turns off normal raw mode features
622 *
623 * @param pVM The VM to operate on.
624 */
625static void hwaccmR3DisableRawMode(PVM pVM)
626{
627 /* Disable PATM & CSAM. */
628 PATMR3AllowPatching(pVM, false);
629 CSAMDisableScanning(pVM);
630
631 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
632 SELMR3DisableMonitoring(pVM);
633 TRPMR3DisableMonitoring(pVM);
634
635 /* Disable the switcher code (safety precaution). */
636 VMMR3DisableSwitcher(pVM);
637
638 /* Disable mapping of the hypervisor into the shadow page table. */
639 PGMR3MappingsDisable(pVM);
640
641 /* Disable the switcher */
642 VMMR3DisableSwitcher(pVM);
643
644 /* Reinit the paging mode to force the new shadow mode. */
645 for (VMCPUID i = 0; i < pVM->cCpus; i++)
646 {
647 PVMCPU pVCpu = &pVM->aCpus[i];
648
649 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
650 }
651}
652
653/**
654 * Initialize VT-x or AMD-V.
655 *
656 * @returns VBox status code.
657 * @param pVM The VM handle.
658 */
659VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
660{
661 int rc;
662
663 /* Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
664 * is already using AMD-V.
665 */
666 if ( !pVM->hwaccm.s.vmx.fSupported
667 && !pVM->hwaccm.s.svm.fSupported
668 && pVM->hwaccm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
669 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
670 {
671 LogRel(("HWACCM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
672 pVM->hwaccm.s.svm.fSupported = true;
673 pVM->hwaccm.s.svm.fIgnoreInUseError = true;
674 }
675 else
676 if ( !pVM->hwaccm.s.vmx.fSupported
677 && !pVM->hwaccm.s.svm.fSupported)
678 {
679 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
680 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
681
682 if (VMMIsHwVirtExtForced(pVM))
683 {
684 switch (pVM->hwaccm.s.lLastError)
685 {
686 case VERR_VMX_NO_VMX:
687 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
688 case VERR_VMX_IN_VMX_ROOT_MODE:
689 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
690 case VERR_SVM_IN_USE:
691 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
692 case VERR_SVM_NO_SVM:
693 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
694 case VERR_SVM_DISABLED:
695 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
696 default:
697 return pVM->hwaccm.s.lLastError;
698 }
699 }
700 return VINF_SUCCESS;
701 }
702
703 if (pVM->hwaccm.s.vmx.fSupported)
704 {
705 rc = SUPR3QueryVTxSupported();
706 if (RT_FAILURE(rc))
707 {
708#ifdef RT_OS_LINUX
709 LogRel(("HWACCM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
710#else
711 LogRel(("HWACCM: The host kernel does not support VT-x!\n"));
712#endif
713 if ( pVM->cCpus > 1
714 || VMMIsHwVirtExtForced(pVM))
715 return rc;
716
717 /* silently fall back to raw mode */
718 return VINF_SUCCESS;
719 }
720 }
721
722 if (!pVM->hwaccm.s.fAllowed)
723 return VINF_SUCCESS; /* nothing to do */
724
725 /* Enable VT-x or AMD-V on all host CPUs. */
726 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
727 if (RT_FAILURE(rc))
728 {
729 LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
730 return rc;
731 }
732 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
733
734 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
735 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
736 if (!pVM->hwaccm.s.fHasIoApic)
737 {
738 Assert(!pVM->hwaccm.s.fTRPPatchingAllowed); /* paranoia */
739 pVM->hwaccm.s.fTRPPatchingAllowed = false;
740 }
741
742 if (pVM->hwaccm.s.vmx.fSupported)
743 {
744 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
745
746 if ( pVM->hwaccm.s.fInitialized == false
747 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
748 {
749 uint64_t val;
750 RTGCPHYS GCPhys = 0;
751
752 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
753 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
754 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
755 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
756 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
757 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
758 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
759 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
760
761 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
762 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
763 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
764 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
765 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
766 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
767 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
768 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
769 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
770 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
771 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
772 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
773 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
774 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
775 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
776 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
777 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
778 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
779 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
780
781 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
782 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
783 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
784 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
785 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
786 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
787 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
788 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
789 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
790 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
791 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
792 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
793 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
794 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
795 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
796 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
797 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
798 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
799 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
800 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
801 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
802 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
803 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
804 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
805 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
806 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
807 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
808 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
809 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
810 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
811 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
812 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
813 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
814 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
815 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
816 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
817 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
818 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
819 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
820 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
821 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
822 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
823 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
824 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
825
826 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
827 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
828 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
829 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
830 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
831 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
832 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
833 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
834 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
835 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
836 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
837 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
838 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
839 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
840 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
841 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
842 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
843 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
844 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
845 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
846 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
847 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
848 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
849 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
850 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
851 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
852 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
853 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
854 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
855 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
856 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
857 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
858 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
859 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
860 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
861 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
862 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
863 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
864 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
865 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
866 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
867 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
868 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
869
870 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
871 {
872 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
873 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
874 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
875 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
876 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
877 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
878 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
879 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
880 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
881 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT\n"));
882 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
883 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
884 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
885 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
886 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
887 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
888 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
889 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE\n"));
890 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
891 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT\n"));
892
893 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
894 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
895 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
896 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
897 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
898 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
899 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT *must* be set\n"));
900 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
901 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
902 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
903 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
904 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
905 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
906 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
907 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
908 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
909 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE *must* be set\n"));
910 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
911 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT *must* be set\n"));
912 }
913
914 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
915 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
916 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
917 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
918 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
919 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
920 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
921 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
922 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
923 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
924 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
925 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
926 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
927 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
928 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
929 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
930 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
931 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
932 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
933 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
934 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
935 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
936 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
937 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
938 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
939 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
940 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
941 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
942 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
943 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
944 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
945
946 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
947 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
948 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
949 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
950 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
951 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
952 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
953 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
954 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
955 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
956 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
957 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
958 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
959 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
960 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
961 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
962 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
963 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
964 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
965 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
966 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
967 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
968 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
969 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
970 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
971 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
972 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
973 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
974 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
975 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
976 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
977 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
978 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
979 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
980 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
981
982 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
983 {
984 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
985
986 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
987 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
988 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
989 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
990 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
991 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
992 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
993 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
994 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
995 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
996 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
997 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
998 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
999 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
1000 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
1001 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
1002 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
1003 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
1004 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
1005 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
1006 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
1007 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
1008 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
1009 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
1010 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
1011 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
1012 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
1013 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
1014 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
1015 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
1016 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
1017 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
1018 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
1019 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
1020 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
1021 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
1022 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
1023 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
1024 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
1025 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
1026 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
1027 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
1028 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
1029 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
1030 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
1031 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
1032 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
1033 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
1034 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
1035 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
1036 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
1037 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
1038 }
1039
1040 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
1041 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1042 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1043 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1044 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1045 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1046
1047 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
1048 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
1049 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
1050 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
1051 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
1052
1053 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
1054
1055 /* Paranoia */
1056 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc) >= 512);
1057
1058 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1059 {
1060 LogRel(("HWACCM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pMSRBitmapPhys));
1061 LogRel(("HWACCM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1062 }
1063
1064#ifdef HWACCM_VTX_WITH_EPT
1065 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1066 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1067#endif /* HWACCM_VTX_WITH_EPT */
1068#ifdef HWACCM_VTX_WITH_VPID
1069 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1070 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
1071 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
1072#endif /* HWACCM_VTX_WITH_VPID */
1073
1074 /* Unrestricted guest execution relies on EPT. */
1075 if ( pVM->hwaccm.s.fNestedPaging
1076 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE))
1077 {
1078 pVM->hwaccm.s.vmx.fUnrestrictedGuest = true;
1079 }
1080
1081 /* Only try once. */
1082 pVM->hwaccm.s.fInitialized = true;
1083
1084 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1085 {
1086 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1087 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
1088 if (RT_SUCCESS(rc))
1089 {
1090 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1091 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
1092 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
1093 /* Bit set to 0 means redirection enabled. */
1094 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
1095 /* Allow all port IO, so the VT-x IO intercepts do their job. */
1096 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
1097 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
1098
1099 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1100 * real and protected mode without paging with EPT.
1101 */
1102 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1103 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
1104 {
1105 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1106 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
1107 }
1108
1109 /* We convert it here every time as pci regions could be reconfigured. */
1110 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1111 AssertRC(rc);
1112 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1113
1114 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1115 AssertRC(rc);
1116 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1117 }
1118 else
1119 {
1120 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1121 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1122 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1123 }
1124 }
1125
1126 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1127 AssertRC(rc);
1128 if (rc == VINF_SUCCESS)
1129 {
1130 pVM->fHWACCMEnabled = true;
1131 pVM->hwaccm.s.vmx.fEnabled = true;
1132 hwaccmR3DisableRawMode(pVM);
1133
1134 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1135#ifdef VBOX_ENABLE_64_BITS_GUESTS
1136 if (pVM->hwaccm.s.fAllow64BitGuests)
1137 {
1138 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1139 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1140 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1141 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1142 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1143 }
1144 else
1145 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1146 /* Todo: this needs to be fixed properly!! */
1147 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1148 && (pVM->hwaccm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1149 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1150
1151 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1152 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1153 : "HWACCM: 32-bit guests supported.\n"));
1154#else
1155 LogRel(("HWACCM: 32-bit guests supported.\n"));
1156#endif
1157 LogRel(("HWACCM: VMX enabled!\n"));
1158 if (pVM->hwaccm.s.fNestedPaging)
1159 {
1160 LogRel(("HWACCM: Enabled nested paging\n"));
1161 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1162 if (pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1163 LogRel(("HWACCM: Unrestricted guest execution enabled!\n"));
1164
1165#if HC_ARCH_BITS == 64
1166 if (pVM->hwaccm.s.fLargePages)
1167 {
1168 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1169 PGMSetLargePageUsage(pVM, true);
1170 LogRel(("HWACCM: Large page support enabled!\n"));
1171 }
1172#endif
1173 }
1174 else
1175 Assert(!pVM->hwaccm.s.vmx.fUnrestrictedGuest);
1176
1177 if (pVM->hwaccm.s.vmx.fVPID)
1178 LogRel(("HWACCM: Enabled VPID\n"));
1179
1180 if ( pVM->hwaccm.s.fNestedPaging
1181 || pVM->hwaccm.s.vmx.fVPID)
1182 {
1183 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1184 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1185 }
1186
1187 /* TPR patching status logging. */
1188 if (pVM->hwaccm.s.fTRPPatchingAllowed)
1189 {
1190 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1191 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1192 {
1193 pVM->hwaccm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1194 LogRel(("HWACCM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1195 }
1196 else
1197 {
1198 uint32_t u32Eax, u32Dummy;
1199
1200 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1201 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1202 if ( u32Eax < 0x80000001
1203 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1204 {
1205 pVM->hwaccm.s.fTRPPatchingAllowed = false;
1206 LogRel(("HWACCM: TPR patching disabled (long mode not supported).\n"));
1207 }
1208 }
1209 }
1210 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1211 }
1212 else
1213 {
1214 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1215 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1216 pVM->fHWACCMEnabled = false;
1217 }
1218 }
1219 }
1220 else
1221 if (pVM->hwaccm.s.svm.fSupported)
1222 {
1223 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1224
1225 if (pVM->hwaccm.s.fInitialized == false)
1226 {
1227 /* Erratum 170 which requires a forced TLB flush for each world switch:
1228 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1229 *
1230 * All BH-G1/2 and DH-G1/2 models include a fix:
1231 * Athlon X2: 0x6b 1/2
1232 * 0x68 1/2
1233 * Athlon 64: 0x7f 1
1234 * 0x6f 2
1235 * Sempron: 0x7f 1/2
1236 * 0x6f 2
1237 * 0x6c 2
1238 * 0x7c 2
1239 * Turion 64: 0x68 2
1240 *
1241 */
1242 uint32_t u32Dummy;
1243 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1244 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1245 u32BaseFamily= (u32Version >> 8) & 0xf;
1246 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1247 u32Model = ((u32Version >> 4) & 0xf);
1248 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1249 u32Stepping = u32Version & 0xf;
1250 if ( u32Family == 0xf
1251 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1252 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1253 {
1254 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1255 }
1256
1257 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1258 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1259 LogRel(("HWACCM: AMD HWCR MSR = %RX64\n", pVM->hwaccm.s.svm.msrHWCR));
1260 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1261 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1262 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1263
1264 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1265 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
1266 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
1267 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
1268 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
1269 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
1270 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
1271 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
1272 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
1273 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
1274 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER)
1275 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER\n"));
1276
1277 /* Only try once. */
1278 pVM->hwaccm.s.fInitialized = true;
1279
1280 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1281 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1282
1283 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1284 AssertRC(rc);
1285 if (rc == VINF_SUCCESS)
1286 {
1287 pVM->fHWACCMEnabled = true;
1288 pVM->hwaccm.s.svm.fEnabled = true;
1289
1290 if (pVM->hwaccm.s.fNestedPaging)
1291 {
1292 LogRel(("HWACCM: Enabled nested paging\n"));
1293#if HC_ARCH_BITS == 64
1294 if (pVM->hwaccm.s.fLargePages)
1295 {
1296 /* Use large (2 MB) pages for our nested paging PDEs where possible. */
1297 PGMSetLargePageUsage(pVM, true);
1298 LogRel(("HWACCM: Large page support enabled!\n"));
1299 }
1300#endif
1301 }
1302
1303 hwaccmR3DisableRawMode(pVM);
1304 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1305 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1306 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1307#ifdef VBOX_ENABLE_64_BITS_GUESTS
1308 if (pVM->hwaccm.s.fAllow64BitGuests)
1309 {
1310 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1311 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1312 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1313 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1314 }
1315 else
1316 /* Turn on NXE if PAE has been enabled. */
1317 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1318 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1319#endif
1320
1321 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1322 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1323 : "HWACCM: 32-bit guest supported.\n"));
1324
1325 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1326 }
1327 else
1328 {
1329 pVM->fHWACCMEnabled = false;
1330 }
1331 }
1332 }
1333 if (pVM->fHWACCMEnabled)
1334 LogRel(("HWACCM: VT-x/AMD-V init method: %s\n", (pVM->hwaccm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1335 return VINF_SUCCESS;
1336}
1337
1338/**
1339 * Applies relocations to data and code managed by this
1340 * component. This function will be called at init and
1341 * whenever the VMM need to relocate it self inside the GC.
1342 *
1343 * @param pVM The VM.
1344 */
1345VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1346{
1347 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1348
1349 /* Fetch the current paging mode during the relocate callback during state loading. */
1350 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1351 {
1352 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1353 {
1354 PVMCPU pVCpu = &pVM->aCpus[i];
1355
1356 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1357 Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1358 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1359 }
1360 }
1361#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1362 if (pVM->fHWACCMEnabled)
1363 {
1364 int rc;
1365
1366 switch(PGMGetHostMode(pVM))
1367 {
1368 case PGMMODE_32_BIT:
1369 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1370 break;
1371
1372 case PGMMODE_PAE:
1373 case PGMMODE_PAE_NX:
1374 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1375 break;
1376
1377 default:
1378 AssertFailed();
1379 break;
1380 }
1381 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1382 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1383
1384 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1385 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1386
1387 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1388 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1389
1390 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1391 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1392
1393# ifdef DEBUG
1394 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1395 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1396# endif
1397 }
1398#endif
1399 return;
1400}
1401
1402/**
1403 * Checks hardware accelerated raw mode is allowed.
1404 *
1405 * @returns boolean
1406 * @param pVM The VM to operate on.
1407 */
1408VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1409{
1410 return pVM->hwaccm.s.fAllowed;
1411}
1412
1413/**
1414 * Notification callback which is called whenever there is a chance that a CR3
1415 * value might have changed.
1416 *
1417 * This is called by PGM.
1418 *
1419 * @param pVM The VM to operate on.
1420 * @param pVCpu The VMCPU to operate on.
1421 * @param enmShadowMode New shadow paging mode.
1422 * @param enmGuestMode New guest paging mode.
1423 */
1424VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1425{
1426 /* Ignore page mode changes during state loading. */
1427 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1428 return;
1429
1430 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1431
1432 if ( pVM->hwaccm.s.vmx.fEnabled
1433 && pVM->fHWACCMEnabled)
1434 {
1435 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1436 && enmGuestMode >= PGMMODE_PROTECTED)
1437 {
1438 PCPUMCTX pCtx;
1439
1440 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1441
1442 /* After a real mode switch to protected mode we must force
1443 * CPL to 0. Our real mode emulation had to set it to 3.
1444 */
1445 pCtx->ssHid.Attr.n.u2Dpl = 0;
1446 }
1447 }
1448
1449 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1450 {
1451 /* Keep track of paging mode changes. */
1452 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1453 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1454
1455 /* Did we miss a change, because all code was executed in the recompiler? */
1456 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1457 {
1458 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1459 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1460 }
1461 }
1462
1463 /* Reset the contents of the read cache. */
1464 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1465 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1466 pCache->Read.aFieldVal[j] = 0;
1467}
1468
1469/**
1470 * Terminates the HWACCM.
1471 *
1472 * Termination means cleaning up and freeing all resources,
1473 * the VM it self is at this point powered off or suspended.
1474 *
1475 * @returns VBox status code.
1476 * @param pVM The VM to operate on.
1477 */
1478VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1479{
1480 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1481 {
1482 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1483 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1484 }
1485 HWACCMR3TermCPU(pVM);
1486 return 0;
1487}
1488
1489/**
1490 * Terminates the per-VCPU HWACCM.
1491 *
1492 * Termination means cleaning up and freeing all resources,
1493 * the VM it self is at this point powered off or suspended.
1494 *
1495 * @returns VBox status code.
1496 * @param pVM The VM to operate on.
1497 */
1498VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1499{
1500 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1501 {
1502 PVMCPU pVCpu = &pVM->aCpus[i];
1503
1504#ifdef VBOX_WITH_STATISTICS
1505 if (pVCpu->hwaccm.s.paStatExitReason)
1506 {
1507 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1508 pVCpu->hwaccm.s.paStatExitReason = NULL;
1509 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1510 }
1511 if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1512 {
1513 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1514 pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1515 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1516 }
1517#endif
1518
1519#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1520 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1521 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1522 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1523#endif
1524 }
1525 return 0;
1526}
1527
1528/**
1529 * Resets a virtual CPU.
1530 *
1531 * Used by HWACCMR3Reset and CPU hot plugging.
1532 *
1533 * @param pVCpu The CPU to reset.
1534 */
1535VMMR3DECL(void) HWACCMR3ResetCpu(PVMCPU pVCpu)
1536{
1537 /* On first entry we'll sync everything. */
1538 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1539
1540 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1541 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1542
1543 pVCpu->hwaccm.s.fActive = false;
1544 pVCpu->hwaccm.s.Event.fPending = false;
1545
1546 /* Reset state information for real-mode emulation in VT-x. */
1547 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1548 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1549 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1550
1551 /* Reset the contents of the read cache. */
1552 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1553 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1554 pCache->Read.aFieldVal[j] = 0;
1555
1556#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1557 /* Magic marker for searching in crash dumps. */
1558 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1559 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1560#endif
1561}
1562
1563/**
1564 * The VM is being reset.
1565 *
1566 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1567 * needs to be removed.
1568 *
1569 * @param pVM VM handle.
1570 */
1571VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1572{
1573 LogFlow(("HWACCMR3Reset:\n"));
1574
1575 if (pVM->fHWACCMEnabled)
1576 hwaccmR3DisableRawMode(pVM);
1577
1578 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1579 {
1580 PVMCPU pVCpu = &pVM->aCpus[i];
1581
1582 HWACCMR3ResetCpu(pVCpu);
1583 }
1584
1585 /* Clear all patch information. */
1586 pVM->hwaccm.s.pGuestPatchMem = 0;
1587 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1588 pVM->hwaccm.s.cbGuestPatchMem = 0;
1589 pVM->hwaccm.s.cPatches = 0;
1590 pVM->hwaccm.s.PatchTree = 0;
1591 pVM->hwaccm.s.fTPRPatchingActive = false;
1592 ASMMemZero32(pVM->hwaccm.s.aPatches, sizeof(pVM->hwaccm.s.aPatches));
1593}
1594
1595/**
1596 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1597 *
1598 * @returns VBox strict status code.
1599 * @param pVM The VM handle.
1600 * @param pVCpu The VMCPU for the EMT we're being called on.
1601 * @param pvUser Unused
1602 *
1603 */
1604DECLCALLBACK(VBOXSTRICTRC) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1605{
1606 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1607
1608 /* Only execute the handler on the VCPU the original patch request was issued. */
1609 if (pVCpu->idCpu != idCpu)
1610 return VINF_SUCCESS;
1611
1612 Log(("hwaccmR3RemovePatches\n"));
1613 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
1614 {
1615 uint8_t szInstr[15];
1616 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
1617 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1618 int rc;
1619
1620#ifdef LOG_ENABLED
1621 char szOutput[256];
1622
1623 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1624 if (RT_SUCCESS(rc))
1625 Log(("Patched instr: %s\n", szOutput));
1626#endif
1627
1628 /* Check if the instruction is still the same. */
1629 rc = PGMPhysSimpleReadGCPtr(pVCpu, szInstr, pInstrGC, pPatch->cbNewOp);
1630 if (rc != VINF_SUCCESS)
1631 {
1632 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1633 continue; /* swapped out or otherwise removed; skip it. */
1634 }
1635
1636 if (memcmp(szInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1637 {
1638 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1639 continue; /* skip it. */
1640 }
1641
1642 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1643 AssertRC(rc);
1644
1645#ifdef LOG_ENABLED
1646 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1647 if (RT_SUCCESS(rc))
1648 Log(("Original instr: %s\n", szOutput));
1649#endif
1650 }
1651 pVM->hwaccm.s.cPatches = 0;
1652 pVM->hwaccm.s.PatchTree = 0;
1653 pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1654 pVM->hwaccm.s.fTPRPatchingActive = false;
1655 return VINF_SUCCESS;
1656}
1657
1658/**
1659 * Enable patching in a VT-x/AMD-V guest
1660 *
1661 * @returns VBox status code.
1662 * @param pVM The VM to operate on.
1663 * @param idCpu VCPU to execute hwaccmR3RemovePatches on
1664 * @param pPatchMem Patch memory range
1665 * @param cbPatchMem Size of the memory range
1666 */
1667int hwaccmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1668{
1669 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)idCpu);
1670 AssertRC(rc);
1671
1672 pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1673 pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1674 pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1675 return VINF_SUCCESS;
1676}
1677
1678/**
1679 * Enable patching in a VT-x/AMD-V guest
1680 *
1681 * @returns VBox status code.
1682 * @param pVM The VM to operate on.
1683 * @param pPatchMem Patch memory range
1684 * @param cbPatchMem Size of the memory range
1685 */
1686VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1687{
1688 Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1689 if (pVM->cCpus > 1)
1690 {
1691 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1692 int rc = VMR3ReqCallNoWaitU(pVM->pUVM, VMCPUID_ANY_QUEUE,
1693 (PFNRT)hwaccmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1694 AssertRC(rc);
1695 return rc;
1696 }
1697 return hwaccmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1698}
1699
1700/**
1701 * Disable patching in a VT-x/AMD-V guest
1702 *
1703 * @returns VBox status code.
1704 * @param pVM The VM to operate on.
1705 * @param pPatchMem Patch memory range
1706 * @param cbPatchMem Size of the memory range
1707 */
1708VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1709{
1710 Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1711
1712 Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1713 Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1714
1715 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1716 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)VMMGetCpuId(pVM));
1717 AssertRC(rc);
1718
1719 pVM->hwaccm.s.pGuestPatchMem = 0;
1720 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1721 pVM->hwaccm.s.cbGuestPatchMem = 0;
1722 pVM->hwaccm.s.fTPRPatchingActive = false;
1723 return VINF_SUCCESS;
1724}
1725
1726
1727/**
1728 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1729 *
1730 * @returns VBox strict status code.
1731 * @param pVM The VM handle.
1732 * @param pVCpu The VMCPU for the EMT we're being called on.
1733 * @param pvUser User specified CPU context
1734 *
1735 */
1736DECLCALLBACK(VBOXSTRICTRC) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1737{
1738 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1739 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1740 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1741 unsigned cbOp;
1742
1743 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1744 if (pVCpu->idCpu != idCpu)
1745 return VINF_SUCCESS;
1746
1747 Log(("hwaccmR3ReplaceTprInstr: %RGv\n", pCtx->rip));
1748
1749 /* Two or more VCPUs were racing to patch this instruction. */
1750 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1751 if (pPatch)
1752 return VINF_SUCCESS;
1753
1754 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1755
1756 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1757 AssertRC(rc);
1758 if ( rc == VINF_SUCCESS
1759 && pDis->pCurInstr->opcode == OP_MOV
1760 && cbOp >= 3)
1761 {
1762 uint8_t aVMMCall[3] = { 0xf, 0x1, 0xd9};
1763 uint32_t idx = pVM->hwaccm.s.cPatches;
1764
1765 pPatch = &pVM->hwaccm.s.aPatches[idx];
1766
1767 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1768 AssertRC(rc);
1769
1770 pPatch->cbOp = cbOp;
1771
1772 if (pDis->param1.flags == USE_DISPLACEMENT32)
1773 {
1774 /* write. */
1775 if (pDis->param2.flags == USE_REG_GEN32)
1776 {
1777 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1778 pPatch->uSrcOperand = pDis->param2.base.reg_gen;
1779 }
1780 else
1781 {
1782 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1783 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1784 pPatch->uSrcOperand = pDis->param2.parval;
1785 }
1786 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1787 AssertRC(rc);
1788
1789 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1790 pPatch->cbNewOp = sizeof(aVMMCall);
1791 }
1792 else
1793 {
1794 RTGCPTR oldrip = pCtx->rip;
1795 uint32_t oldcbOp = cbOp;
1796 uint32_t uMmioReg = pDis->param1.base.reg_gen;
1797
1798 /* read */
1799 Assert(pDis->param1.flags == USE_REG_GEN32);
1800
1801 /* Found:
1802 * mov eax, dword [fffe0080] (5 bytes)
1803 * Check if next instruction is:
1804 * shr eax, 4
1805 */
1806 pCtx->rip += cbOp;
1807 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1808 pCtx->rip = oldrip;
1809 if ( rc == VINF_SUCCESS
1810 && pDis->pCurInstr->opcode == OP_SHR
1811 && pDis->param1.flags == USE_REG_GEN32
1812 && pDis->param1.base.reg_gen == uMmioReg
1813 && pDis->param2.flags == USE_IMMEDIATE8
1814 && pDis->param2.parval == 4
1815 && oldcbOp + cbOp < sizeof(pVM->hwaccm.s.aPatches[idx].aOpcode))
1816 {
1817 uint8_t szInstr[15];
1818
1819 /* Replacing two instructions now. */
1820 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, oldcbOp + cbOp);
1821 AssertRC(rc);
1822
1823 pPatch->cbOp = oldcbOp + cbOp;
1824
1825 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1826 szInstr[0] = 0xF0;
1827 szInstr[1] = 0x0F;
1828 szInstr[2] = 0x20;
1829 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
1830 for (unsigned i = 4; i < pPatch->cbOp; i++)
1831 szInstr[i] = 0x90; /* nop */
1832
1833 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, pPatch->cbOp);
1834 AssertRC(rc);
1835
1836 memcpy(pPatch->aNewOpcode, szInstr, pPatch->cbOp);
1837 pPatch->cbNewOp = pPatch->cbOp;
1838
1839 Log(("Acceptable read/shr candidate!\n"));
1840 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1841 }
1842 else
1843 {
1844 pPatch->enmType = HWACCMTPRINSTR_READ;
1845 pPatch->uDstOperand = pDis->param1.base.reg_gen;
1846
1847 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1848 AssertRC(rc);
1849
1850 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1851 pPatch->cbNewOp = sizeof(aVMMCall);
1852 }
1853 }
1854
1855 pPatch->Core.Key = pCtx->eip;
1856 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1857 AssertRC(rc);
1858
1859 pVM->hwaccm.s.cPatches++;
1860 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceSuccess);
1861 return VINF_SUCCESS;
1862 }
1863
1864 /* Save invalid patch, so we will not try again. */
1865 uint32_t idx = pVM->hwaccm.s.cPatches;
1866
1867#ifdef LOG_ENABLED
1868 char szOutput[256];
1869 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1870 if (RT_SUCCESS(rc))
1871 Log(("Failed to patch instr: %s\n", szOutput));
1872#endif
1873
1874 pPatch = &pVM->hwaccm.s.aPatches[idx];
1875 pPatch->Core.Key = pCtx->eip;
1876 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1877 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1878 AssertRC(rc);
1879 pVM->hwaccm.s.cPatches++;
1880 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceFailure);
1881 return VINF_SUCCESS;
1882}
1883
1884/**
1885 * Callback to patch a TPR instruction (jump to generated code)
1886 *
1887 * @returns VBox strict status code.
1888 * @param pVM The VM handle.
1889 * @param pVCpu The VMCPU for the EMT we're being called on.
1890 * @param pvUser User specified CPU context
1891 *
1892 */
1893DECLCALLBACK(VBOXSTRICTRC) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1894{
1895 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1896 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1897 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1898 unsigned cbOp;
1899 int rc;
1900#ifdef LOG_ENABLED
1901 RTGCPTR pInstr;
1902 char szOutput[256];
1903#endif
1904
1905 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1906 if (pVCpu->idCpu != idCpu)
1907 return VINF_SUCCESS;
1908
1909 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1910
1911 /* Two or more VCPUs were racing to patch this instruction. */
1912 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1913 if (pPatch)
1914 {
1915 Log(("hwaccmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
1916 return VINF_SUCCESS;
1917 }
1918
1919 Log(("hwaccmR3PatchTprInstr %RGv\n", pCtx->rip));
1920
1921 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1922 AssertRC(rc);
1923 if ( rc == VINF_SUCCESS
1924 && pDis->pCurInstr->opcode == OP_MOV
1925 && cbOp >= 5)
1926 {
1927 uint32_t idx = pVM->hwaccm.s.cPatches;
1928 uint8_t aPatch[64];
1929 uint32_t off = 0;
1930
1931 pPatch = &pVM->hwaccm.s.aPatches[idx];
1932
1933#ifdef LOG_ENABLED
1934 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1935 if (RT_SUCCESS(rc))
1936 Log(("Original instr: %s\n", szOutput));
1937#endif
1938
1939 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1940 AssertRC(rc);
1941
1942 pPatch->cbOp = cbOp;
1943 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
1944
1945 if (pDis->param1.flags == USE_DISPLACEMENT32)
1946 {
1947 /*
1948 * TPR write:
1949 *
1950 * push ECX [51]
1951 * push EDX [52]
1952 * push EAX [50]
1953 * xor EDX,EDX [31 D2]
1954 * mov EAX,EAX [89 C0]
1955 * or
1956 * mov EAX,0000000CCh [B8 CC 00 00 00]
1957 * mov ECX,0C0000082h [B9 82 00 00 C0]
1958 * wrmsr [0F 30]
1959 * pop EAX [58]
1960 * pop EDX [5A]
1961 * pop ECX [59]
1962 * jmp return_address [E9 return_address]
1963 *
1964 */
1965 bool fUsesEax = (pDis->param2.flags == USE_REG_GEN32 && pDis->param2.base.reg_gen == USE_REG_EAX);
1966
1967 aPatch[off++] = 0x51; /* push ecx */
1968 aPatch[off++] = 0x52; /* push edx */
1969 if (!fUsesEax)
1970 aPatch[off++] = 0x50; /* push eax */
1971 aPatch[off++] = 0x31; /* xor edx, edx */
1972 aPatch[off++] = 0xD2;
1973 if (pDis->param2.flags == USE_REG_GEN32)
1974 {
1975 if (!fUsesEax)
1976 {
1977 aPatch[off++] = 0x89; /* mov eax, src_reg */
1978 aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, USE_REG_EAX);
1979 }
1980 }
1981 else
1982 {
1983 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1984 aPatch[off++] = 0xB8; /* mov eax, immediate */
1985 *(uint32_t *)&aPatch[off] = pDis->param2.parval;
1986 off += sizeof(uint32_t);
1987 }
1988 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1989 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1990 off += sizeof(uint32_t);
1991
1992 aPatch[off++] = 0x0F; /* wrmsr */
1993 aPatch[off++] = 0x30;
1994 if (!fUsesEax)
1995 aPatch[off++] = 0x58; /* pop eax */
1996 aPatch[off++] = 0x5A; /* pop edx */
1997 aPatch[off++] = 0x59; /* pop ecx */
1998 }
1999 else
2000 {
2001 /*
2002 * TPR read:
2003 *
2004 * push ECX [51]
2005 * push EDX [52]
2006 * push EAX [50]
2007 * mov ECX,0C0000082h [B9 82 00 00 C0]
2008 * rdmsr [0F 32]
2009 * mov EAX,EAX [89 C0]
2010 * pop EAX [58]
2011 * pop EDX [5A]
2012 * pop ECX [59]
2013 * jmp return_address [E9 return_address]
2014 *
2015 */
2016 Assert(pDis->param1.flags == USE_REG_GEN32);
2017
2018 if (pDis->param1.base.reg_gen != USE_REG_ECX)
2019 aPatch[off++] = 0x51; /* push ecx */
2020 if (pDis->param1.base.reg_gen != USE_REG_EDX)
2021 aPatch[off++] = 0x52; /* push edx */
2022 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2023 aPatch[off++] = 0x50; /* push eax */
2024
2025 aPatch[off++] = 0x31; /* xor edx, edx */
2026 aPatch[off++] = 0xD2;
2027
2028 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2029 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2030 off += sizeof(uint32_t);
2031
2032 aPatch[off++] = 0x0F; /* rdmsr */
2033 aPatch[off++] = 0x32;
2034
2035 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2036 {
2037 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2038 aPatch[off++] = MAKE_MODRM(3, USE_REG_EAX, pDis->param1.base.reg_gen);
2039 }
2040
2041 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2042 aPatch[off++] = 0x58; /* pop eax */
2043 if (pDis->param1.base.reg_gen != USE_REG_EDX)
2044 aPatch[off++] = 0x5A; /* pop edx */
2045 if (pDis->param1.base.reg_gen != USE_REG_ECX)
2046 aPatch[off++] = 0x59; /* pop ecx */
2047 }
2048 aPatch[off++] = 0xE9; /* jmp return_address */
2049 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
2050 off += sizeof(RTRCUINTPTR);
2051
2052 if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
2053 {
2054 /* Write new code to the patch buffer. */
2055 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
2056 AssertRC(rc);
2057
2058#ifdef LOG_ENABLED
2059 pInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
2060 while (true)
2061 {
2062 uint32_t cb;
2063
2064 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pInstr, 0, szOutput, sizeof(szOutput), &cb);
2065 if (RT_SUCCESS(rc))
2066 Log(("Patch instr %s\n", szOutput));
2067
2068 pInstr += cb;
2069
2070 if (pInstr >= pVM->hwaccm.s.pFreeGuestPatchMem + off)
2071 break;
2072 }
2073#endif
2074
2075 pPatch->aNewOpcode[0] = 0xE9;
2076 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2077
2078 /* Overwrite the TPR instruction with a jump. */
2079 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2080 AssertRC(rc);
2081
2082#ifdef LOG_ENABLED
2083 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
2084 if (RT_SUCCESS(rc))
2085 Log(("Jump: %s\n", szOutput));
2086#endif
2087 pVM->hwaccm.s.pFreeGuestPatchMem += off;
2088 pPatch->cbNewOp = 5;
2089
2090 pPatch->Core.Key = pCtx->eip;
2091 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2092 AssertRC(rc);
2093
2094 pVM->hwaccm.s.cPatches++;
2095 pVM->hwaccm.s.fTPRPatchingActive = true;
2096 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchSuccess);
2097 return VINF_SUCCESS;
2098 }
2099 else
2100 Log(("Ran out of space in our patch buffer!\n"));
2101 }
2102
2103 /* Save invalid patch, so we will not try again. */
2104 uint32_t idx = pVM->hwaccm.s.cPatches;
2105
2106#ifdef LOG_ENABLED
2107 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
2108 if (RT_SUCCESS(rc))
2109 Log(("Failed to patch instr: %s\n", szOutput));
2110#endif
2111
2112 pPatch = &pVM->hwaccm.s.aPatches[idx];
2113 pPatch->Core.Key = pCtx->eip;
2114 pPatch->enmType = HWACCMTPRINSTR_INVALID;
2115 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2116 AssertRC(rc);
2117 pVM->hwaccm.s.cPatches++;
2118 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchFailure);
2119 return VINF_SUCCESS;
2120}
2121
2122/**
2123 * Attempt to patch TPR mmio instructions
2124 *
2125 * @returns VBox status code.
2126 * @param pVM The VM to operate on.
2127 * @param pVCpu The VM CPU to operate on.
2128 * @param pCtx CPU context
2129 */
2130VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2131{
2132 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, (pVM->hwaccm.s.pGuestPatchMem) ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr, (void *)pVCpu->idCpu);
2133 AssertRC(rc);
2134 return rc;
2135}
2136
2137/**
2138 * Force execution of the current IO code in the recompiler
2139 *
2140 * @returns VBox status code.
2141 * @param pVM The VM to operate on.
2142 * @param pCtx Partial VM execution context
2143 */
2144VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2145{
2146 PVMCPU pVCpu = VMMGetCpu(pVM);
2147
2148 Assert(pVM->fHWACCMEnabled);
2149 Log(("HWACCMR3EmulateIoBlock\n"));
2150
2151 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2152 if (HWACCMCanEmulateIoBlockEx(pCtx))
2153 {
2154 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
2155 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
2156 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2157 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2158 return VINF_EM_RESCHEDULE_REM;
2159 }
2160 return VINF_SUCCESS;
2161}
2162
2163/**
2164 * Checks if we can currently use hardware accelerated raw mode.
2165 *
2166 * @returns boolean
2167 * @param pVM The VM to operate on.
2168 * @param pCtx Partial VM execution context
2169 */
2170VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2171{
2172 PVMCPU pVCpu = VMMGetCpu(pVM);
2173
2174 Assert(pVM->fHWACCMEnabled);
2175
2176 /* If we're still executing the IO code, then return false. */
2177 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
2178 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2179 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2180 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
2181 return false;
2182
2183 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
2184
2185 /* AMD-V supports real & protected mode with or without paging. */
2186 if (pVM->hwaccm.s.svm.fEnabled)
2187 {
2188 pVCpu->hwaccm.s.fActive = true;
2189 return true;
2190 }
2191
2192 pVCpu->hwaccm.s.fActive = false;
2193
2194 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2195#ifdef HWACCM_VMX_EMULATE_REALMODE
2196 bool fVMMDeviceHeapEnabled = PDMVMMDevHeapIsEnabled(pVM);
2197
2198 Assert((pVM->hwaccm.s.vmx.fUnrestrictedGuest && !pVM->hwaccm.s.vmx.pRealModeTSS) || (!pVM->hwaccm.s.vmx.fUnrestrictedGuest && pVM->hwaccm.s.vmx.pRealModeTSS));
2199
2200 /** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. */
2201 if (fVMMDeviceHeapEnabled)
2202 {
2203 if (CPUMIsGuestInRealModeEx(pCtx))
2204 {
2205 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
2206 * The base must also be equal to (sel << 4).
2207 */
2208 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
2209 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
2210 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
2211 || pCtx->es != (pCtx->esHid.u64Base >> 4)
2212 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
2213 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
2214 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
2215 {
2216 return false;
2217 }
2218 }
2219 else
2220 {
2221 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2222 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
2223 * from real to protected mode. (all sorts of RPL & DPL assumptions)
2224 */
2225 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2226 && enmGuestMode >= PGMMODE_PROTECTED)
2227 {
2228 if ( (pCtx->cs & X86_SEL_RPL)
2229 || (pCtx->ds & X86_SEL_RPL)
2230 || (pCtx->es & X86_SEL_RPL)
2231 || (pCtx->fs & X86_SEL_RPL)
2232 || (pCtx->gs & X86_SEL_RPL)
2233 || (pCtx->ss & X86_SEL_RPL))
2234 {
2235 return false;
2236 }
2237 }
2238 }
2239 }
2240 else
2241#endif /* HWACCM_VMX_EMULATE_REALMODE */
2242 {
2243 if ( !CPUMIsGuestInLongModeEx(pCtx)
2244 && !pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2245 {
2246 /** @todo This should (probably) be set on every excursion to the REM,
2247 * however it's too risky right now. So, only apply it when we go
2248 * back to REM for real mode execution. (The XP hack below doesn't
2249 * work reliably without this.)
2250 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2251 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2252
2253 if ( !pVM->hwaccm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap*/
2254 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2255 return false;
2256
2257 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2258 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
2259 return false;
2260
2261 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2262 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2263 * hidden registers (possible recompiler bug; see load_seg_vm) */
2264 if (pCtx->csHid.Attr.n.u1Present == 0)
2265 return false;
2266 if (pCtx->ssHid.Attr.n.u1Present == 0)
2267 return false;
2268
2269 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2270 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2271 /** @todo This check is actually wrong, it doesn't take the direction of the
2272 * stack segment into account. But, it does the job for now. */
2273 if (pCtx->rsp >= pCtx->ssHid.u32Limit)
2274 return false;
2275#if 0
2276 if ( pCtx->cs >= pCtx->gdtr.cbGdt
2277 || pCtx->ss >= pCtx->gdtr.cbGdt
2278 || pCtx->ds >= pCtx->gdtr.cbGdt
2279 || pCtx->es >= pCtx->gdtr.cbGdt
2280 || pCtx->fs >= pCtx->gdtr.cbGdt
2281 || pCtx->gs >= pCtx->gdtr.cbGdt)
2282 return false;
2283#endif
2284 }
2285 }
2286
2287 if (pVM->hwaccm.s.vmx.fEnabled)
2288 {
2289 uint32_t mask;
2290
2291 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2292 {
2293 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2294 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2295 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2296 mask &= ~X86_CR0_NE;
2297
2298#ifdef HWACCM_VMX_EMULATE_REALMODE
2299 if (fVMMDeviceHeapEnabled)
2300 {
2301 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2302 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2303 }
2304 else
2305#endif
2306 {
2307 /* We support protected mode without paging using identity mapping. */
2308 mask &= ~X86_CR0_PG;
2309 }
2310 if ((pCtx->cr0 & mask) != mask)
2311 return false;
2312
2313 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2314 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2315 if ((pCtx->cr0 & mask) != 0)
2316 return false;
2317 }
2318
2319 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2320 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2321 mask &= ~X86_CR4_VMXE;
2322 if ((pCtx->cr4 & mask) != mask)
2323 return false;
2324
2325 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2326 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2327 if ((pCtx->cr4 & mask) != 0)
2328 return false;
2329
2330 pVCpu->hwaccm.s.fActive = true;
2331 return true;
2332 }
2333
2334 return false;
2335}
2336
2337/**
2338 * Checks if we need to reschedule due to VMM device heap changes
2339 *
2340 * @returns boolean
2341 * @param pVM The VM to operate on.
2342 * @param pCtx VM execution context
2343 */
2344VMMR3DECL(bool) HWACCMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2345{
2346 /** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. (VT-x only) */
2347 if ( pVM->hwaccm.s.vmx.fEnabled
2348 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2349 && !PDMVMMDevHeapIsEnabled(pVM)
2350 && (pVM->hwaccm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2351 return true;
2352
2353 return false;
2354}
2355
2356
2357/**
2358 * Notifcation from EM about a rescheduling into hardware assisted execution
2359 * mode.
2360 *
2361 * @param pVCpu Pointer to the current virtual cpu structure.
2362 */
2363VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2364{
2365 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2366}
2367
2368/**
2369 * Notifcation from EM about returning from instruction emulation (REM / EM).
2370 *
2371 * @param pVCpu Pointer to the current virtual cpu structure.
2372 */
2373VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2374{
2375 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2376}
2377
2378/**
2379 * Checks if we are currently using hardware accelerated raw mode.
2380 *
2381 * @returns boolean
2382 * @param pVCpu The VMCPU to operate on.
2383 */
2384VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2385{
2386 return pVCpu->hwaccm.s.fActive;
2387}
2388
2389/**
2390 * Checks if we are currently using nested paging.
2391 *
2392 * @returns boolean
2393 * @param pVM The VM to operate on.
2394 */
2395VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2396{
2397 return pVM->hwaccm.s.fNestedPaging;
2398}
2399
2400/**
2401 * Checks if we are currently using VPID in VT-x mode.
2402 *
2403 * @returns boolean
2404 * @param pVM The VM to operate on.
2405 */
2406VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2407{
2408 return pVM->hwaccm.s.vmx.fVPID;
2409}
2410
2411
2412/**
2413 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2414 *
2415 * @returns boolean
2416 * @param pVM The VM to operate on.
2417 */
2418VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2419{
2420 return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2421}
2422
2423/**
2424 * Restart an I/O instruction that was refused in ring-0
2425 *
2426 * @returns Strict VBox status code. Informational status codes other than the one documented
2427 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2428 * @retval VINF_SUCCESS Success.
2429 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2430 * status code must be passed on to EM.
2431 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2432 *
2433 * @param pVM The VM to operate on.
2434 * @param pVCpu The VMCPU to operate on.
2435 * @param pCtx VCPU register context
2436 */
2437VMMR3DECL(VBOXSTRICTRC) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2438{
2439 HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2440
2441 pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2442
2443 if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2444 || enmType == HWACCMPENDINGIO_INVALID)
2445 return VERR_NOT_FOUND;
2446
2447 VBOXSTRICTRC rcStrict;
2448 switch (enmType)
2449 {
2450 case HWACCMPENDINGIO_PORT_READ:
2451 {
2452 uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2453 uint32_t u32Val = 0;
2454
2455 rcStrict = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2456 &u32Val,
2457 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2458 if (IOM_SUCCESS(rcStrict))
2459 {
2460 /* Write back to the EAX register. */
2461 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2462 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2463 }
2464 break;
2465 }
2466
2467 case HWACCMPENDINGIO_PORT_WRITE:
2468 rcStrict = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2469 pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2470 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2471 if (IOM_SUCCESS(rcStrict))
2472 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2473 break;
2474
2475 default:
2476 AssertFailed();
2477 return VERR_INTERNAL_ERROR;
2478 }
2479
2480 return rcStrict;
2481}
2482
2483/**
2484 * Inject an NMI into a running VM (only VCPU 0!)
2485 *
2486 * @returns boolean
2487 * @param pVM The VM to operate on.
2488 */
2489VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2490{
2491 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2492 return VINF_SUCCESS;
2493}
2494
2495/**
2496 * Check fatal VT-x/AMD-V error and produce some meaningful
2497 * log release message.
2498 *
2499 * @param pVM The VM to operate on.
2500 * @param iStatusCode VBox status code
2501 */
2502VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2503{
2504 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2505 {
2506 switch(iStatusCode)
2507 {
2508 case VERR_VMX_INVALID_VMCS_FIELD:
2509 break;
2510
2511 case VERR_VMX_INVALID_VMCS_PTR:
2512 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
2513 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2514 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2515 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2516 break;
2517
2518 case VERR_VMX_UNABLE_TO_START_VM:
2519 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2520 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2521#if 0 /* @todo dump the current control fields to the release log */
2522 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2523 {
2524
2525 }
2526#endif
2527 break;
2528
2529 case VERR_VMX_UNABLE_TO_RESUME_VM:
2530 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2531 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2532 break;
2533
2534 case VERR_VMX_INVALID_VMXON_PTR:
2535 break;
2536 }
2537 }
2538}
2539
2540/**
2541 * Execute state save operation.
2542 *
2543 * @returns VBox status code.
2544 * @param pVM VM Handle.
2545 * @param pSSM SSM operation handle.
2546 */
2547static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2548{
2549 int rc;
2550
2551 Log(("hwaccmR3Save:\n"));
2552
2553 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2554 {
2555 /*
2556 * Save the basic bits - fortunately all the other things can be resynced on load.
2557 */
2558 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2559 AssertRCReturn(rc, rc);
2560 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2561 AssertRCReturn(rc, rc);
2562 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2563 AssertRCReturn(rc, rc);
2564
2565 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2566 AssertRCReturn(rc, rc);
2567 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2568 AssertRCReturn(rc, rc);
2569 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2570 AssertRCReturn(rc, rc);
2571 }
2572#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2573 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2574 AssertRCReturn(rc, rc);
2575 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2576 AssertRCReturn(rc, rc);
2577 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2578 AssertRCReturn(rc, rc);
2579
2580 /* Store all the guest patch records too. */
2581 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cPatches);
2582 AssertRCReturn(rc, rc);
2583
2584 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2585 {
2586 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2587
2588 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2589 AssertRCReturn(rc, rc);
2590
2591 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2592 AssertRCReturn(rc, rc);
2593
2594 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2595 AssertRCReturn(rc, rc);
2596
2597 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2598 AssertRCReturn(rc, rc);
2599
2600 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2601 AssertRCReturn(rc, rc);
2602
2603 AssertCompileSize(HWACCMTPRINSTR, 4);
2604 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2605 AssertRCReturn(rc, rc);
2606
2607 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2608 AssertRCReturn(rc, rc);
2609
2610 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2611 AssertRCReturn(rc, rc);
2612
2613 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2614 AssertRCReturn(rc, rc);
2615
2616 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2617 AssertRCReturn(rc, rc);
2618 }
2619#endif
2620 return VINF_SUCCESS;
2621}
2622
2623/**
2624 * Execute state load operation.
2625 *
2626 * @returns VBox status code.
2627 * @param pVM VM Handle.
2628 * @param pSSM SSM operation handle.
2629 * @param uVersion Data layout version.
2630 * @param uPass The data pass.
2631 */
2632static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2633{
2634 int rc;
2635
2636 Log(("hwaccmR3Load:\n"));
2637 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2638
2639 /*
2640 * Validate version.
2641 */
2642 if ( uVersion != HWACCM_SSM_VERSION
2643 && uVersion != HWACCM_SSM_VERSION_NO_PATCHING
2644 && uVersion != HWACCM_SSM_VERSION_2_0_X)
2645 {
2646 AssertMsgFailed(("hwaccmR3Load: Invalid version uVersion=%d!\n", uVersion));
2647 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2648 }
2649 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2650 {
2651 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2652 AssertRCReturn(rc, rc);
2653 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2654 AssertRCReturn(rc, rc);
2655 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2656 AssertRCReturn(rc, rc);
2657
2658 if (uVersion >= HWACCM_SSM_VERSION_NO_PATCHING)
2659 {
2660 uint32_t val;
2661
2662 rc = SSMR3GetU32(pSSM, &val);
2663 AssertRCReturn(rc, rc);
2664 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2665
2666 rc = SSMR3GetU32(pSSM, &val);
2667 AssertRCReturn(rc, rc);
2668 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2669
2670 rc = SSMR3GetU32(pSSM, &val);
2671 AssertRCReturn(rc, rc);
2672 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2673 }
2674 }
2675#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2676 if (uVersion > HWACCM_SSM_VERSION_NO_PATCHING)
2677 {
2678 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2679 AssertRCReturn(rc, rc);
2680 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2681 AssertRCReturn(rc, rc);
2682 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2683 AssertRCReturn(rc, rc);
2684
2685 /* Fetch all TPR patch records. */
2686 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cPatches);
2687 AssertRCReturn(rc, rc);
2688
2689 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2690 {
2691 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2692
2693 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2694 AssertRCReturn(rc, rc);
2695
2696 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2697 AssertRCReturn(rc, rc);
2698
2699 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2700 AssertRCReturn(rc, rc);
2701
2702 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2703 AssertRCReturn(rc, rc);
2704
2705 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2706 AssertRCReturn(rc, rc);
2707
2708 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2709 AssertRCReturn(rc, rc);
2710
2711 if (pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT)
2712 pVM->hwaccm.s.fTPRPatchingActive = true;
2713
2714 Assert(pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT || pVM->hwaccm.s.fTPRPatchingActive == false);
2715
2716 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2717 AssertRCReturn(rc, rc);
2718
2719 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2720 AssertRCReturn(rc, rc);
2721
2722 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2723 AssertRCReturn(rc, rc);
2724
2725 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2726 AssertRCReturn(rc, rc);
2727
2728 Log(("hwaccmR3Load: patch %d\n", i));
2729 Log(("Key = %x\n", pPatch->Core.Key));
2730 Log(("cbOp = %d\n", pPatch->cbOp));
2731 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2732 Log(("type = %d\n", pPatch->enmType));
2733 Log(("srcop = %d\n", pPatch->uSrcOperand));
2734 Log(("dstop = %d\n", pPatch->uDstOperand));
2735 Log(("cFaults = %d\n", pPatch->cFaults));
2736 Log(("target = %x\n", pPatch->pJumpTarget));
2737 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2738 AssertRC(rc);
2739 }
2740 }
2741#endif
2742
2743 /* Recheck all VCPUs if we can go staight into hwaccm execution mode. */
2744 if (HWACCMIsEnabled(pVM))
2745 {
2746 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2747 {
2748 PVMCPU pVCpu = &pVM->aCpus[i];
2749
2750 HWACCMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2751 }
2752 }
2753 return VINF_SUCCESS;
2754}
2755
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