VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 28134

Last change on this file since 28134 was 27253, checked in by vboxsync, 15 years ago

Missing stat registration
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 130.3 KB
Line 
1/* $Id: HWACCM.cpp 27253 2010-03-10 14:53:56Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdmapi.h>
30#include <VBox/pgm.h>
31#include <VBox/ssm.h>
32#include <VBox/trpm.h>
33#include <VBox/dbgf.h>
34#include <VBox/iom.h>
35#include <VBox/patm.h>
36#include <VBox/csam.h>
37#include <VBox/selm.h>
38#include <VBox/rem.h>
39#include <VBox/hwacc_vmx.h>
40#include <VBox/hwacc_svm.h>
41#include "HWACCMInternal.h"
42#include <VBox/vm.h>
43#include <VBox/err.h>
44#include <VBox/param.h>
45
46#include <iprt/assert.h>
47#include <VBox/log.h>
48#include <iprt/asm.h>
49#include <iprt/string.h>
50#include <iprt/env.h>
51#include <iprt/thread.h>
52
53/*******************************************************************************
54* Global Variables *
55*******************************************************************************/
56#ifdef VBOX_WITH_STATISTICS
57# define EXIT_REASON(def, val, str) #def " - " #val " - " str
58# define EXIT_REASON_NIL() NULL
59/** Exit reason descriptions for VT-x, used to describe statistics. */
60static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
61{
62 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
63 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
64 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
65 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
66 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
67 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
68 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
69 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
72 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
73 EXIT_REASON_NIL(),
74 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
75 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
76 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
77 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
78 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
79 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
80 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
81 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
82 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
83 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
84 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
85 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
86 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
87 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
88 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
89 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
90 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
91 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
92 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
93 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
94 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
95 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
96 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
99 EXIT_REASON_NIL(),
100 EXIT_REASON_NIL(),
101 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
102 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
103 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
106 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
107 EXIT_REASON_NIL(),
108 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
109 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
110 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
111 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
112 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
113 EXIT_REASON_NIL(),
114 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
115 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
116 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
117 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
118 EXIT_REASON_NIL()
119};
120/** Exit reason descriptions for AMD-V, used to describe statistics. */
121static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
122{
123 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
124 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
125 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
126 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
127 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
128 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
129 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
130 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
131 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
132 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
133 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
134 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
135 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
136 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
137 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
138 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
154 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
155 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
156 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
157 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
158 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
159 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
160 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
161 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
162 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
163 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
164 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
165 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
166 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
167 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
168 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
169 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
170 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
186 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_INTR , 96, "Physical maskable interrupt."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_NMI , 97, "Physical non-maskable interrupt."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_SMI , 98, "System management interrupt."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_INIT , 99, "Physical INIT signal."),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_VINTR ,100, "Visual interrupt."),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_IDTR_READ ,102, "Read IDTR"),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_GDTR_READ ,103, "Read GDTR"),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_LDTR_READ ,104, "Read LDTR."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,105, "Read TR."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,106, "Write IDTR."),
230 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,107, "Write GDTR."),
231 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,108, "Write LDTR."),
232 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,109, "Write TR."),
233 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
234 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
235 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
236 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
237 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
238 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
239 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
240 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
241 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
242 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
243 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
244 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
245 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
246 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
247 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
248 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
249 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
250 EXIT_REASON(SVM_EXIT_TASK_SHUTDOWN ,127, "Shutdown."),
251 EXIT_REASON(SVM_EXIT_TASK_VMRUN ,128, "VMRUN instruction."),
252 EXIT_REASON(SVM_EXIT_TASK_VMCALL ,129, "VMCALL instruction."),
253 EXIT_REASON(SVM_EXIT_TASK_VMLOAD ,130, "VMLOAD instruction."),
254 EXIT_REASON(SVM_EXIT_TASK_VMSAVE ,131, "VMSAVE instruction."),
255 EXIT_REASON(SVM_EXIT_TASK_STGI ,132, "STGI instruction."),
256 EXIT_REASON(SVM_EXIT_TASK_CLGI ,133, "CLGI instruction."),
257 EXIT_REASON(SVM_EXIT_TASK_SKINIT ,134, "SKINIT instruction."),
258 EXIT_REASON(SVM_EXIT_TASK_RDTSCP ,135, "RDTSCP instruction."),
259 EXIT_REASON(SVM_EXIT_TASK_ICEBP ,136, "ICEBP instruction."),
260 EXIT_REASON(SVM_EXIT_TASK_WBINVD ,137, "WBINVD instruction."),
261 EXIT_REASON(SVM_EXIT_TASK_MONITOR ,138, "MONITOR instruction."),
262 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
263 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
264 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
265 EXIT_REASON_NIL()
266};
267# undef EXIT_REASON
268# undef EXIT_REASON_NIL
269#endif /* VBOX_WITH_STATISTICS */
270
271/*******************************************************************************
272* Internal Functions *
273*******************************************************************************/
274static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
275static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
276
277
278/**
279 * Initializes the HWACCM.
280 *
281 * @returns VBox status code.
282 * @param pVM The VM to operate on.
283 */
284VMMR3DECL(int) HWACCMR3Init(PVM pVM)
285{
286 LogFlow(("HWACCMR3Init\n"));
287
288 /*
289 * Assert alignment and sizes.
290 */
291 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
292 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
293
294 /* Some structure checks. */
295 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
296 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
299
300 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
303 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
304 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
305 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
306 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
307
308
309 /*
310 * Register the saved state data unit.
311 */
312 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
313 NULL, NULL, NULL,
314 NULL, hwaccmR3Save, NULL,
315 NULL, hwaccmR3Load, NULL);
316 if (RT_FAILURE(rc))
317 return rc;
318
319 /* Misc initialisation. */
320 pVM->hwaccm.s.vmx.fSupported = false;
321 pVM->hwaccm.s.svm.fSupported = false;
322 pVM->hwaccm.s.vmx.fEnabled = false;
323 pVM->hwaccm.s.svm.fEnabled = false;
324
325 pVM->hwaccm.s.fNestedPaging = false;
326 pVM->hwaccm.s.fLargePages = false;
327
328 /* Disabled by default. */
329 pVM->fHWACCMEnabled = false;
330
331 /*
332 * Check CFGM options.
333 */
334 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
335 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
336 /* Nested paging: disabled by default. */
337 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
338 AssertRC(rc);
339
340 /* Large pages: disabled by default. */
341 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hwaccm.s.fLargePages, false);
342 AssertRC(rc);
343
344 /* VT-x VPID: disabled by default. */
345 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
346 AssertRC(rc);
347
348 /* HWACCM support must be explicitely enabled in the configuration file. */
349 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
350 AssertRC(rc);
351
352 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
353 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hwaccm.s.fTRPPatchingAllowed, false);
354 AssertRC(rc);
355
356#ifdef RT_OS_DARWIN
357 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
358#else
359 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
360#endif
361 {
362 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
363 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
364 return VERR_HWACCM_CONFIG_MISMATCH;
365 }
366
367 if (VMMIsHwVirtExtForced(pVM))
368 pVM->fHWACCMEnabled = true;
369
370#if HC_ARCH_BITS == 32
371 /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
372 * (To use the default, don't set 64bitEnabled in CFGM.) */
373 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
374 AssertLogRelRCReturn(rc, rc);
375 if (pVM->hwaccm.s.fAllow64BitGuests)
376 {
377# ifdef RT_OS_DARWIN
378 if (!VMMIsHwVirtExtForced(pVM))
379# else
380 if (!pVM->hwaccm.s.fAllowed)
381# endif
382 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
383 }
384#else
385 /* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
386 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
387 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
388 AssertLogRelRCReturn(rc, rc);
389#endif
390
391
392 /** Determine the init method for AMD-V and VT-x; either one global init for each host CPU
393 * or local init each time we wish to execute guest code.
394 *
395 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
396 */
397 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hwaccm.s.fGlobalInit,
398#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
399 false
400#else
401 true
402#endif
403 );
404
405 /* Max number of resume loops. */
406 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
407 AssertRC(rc);
408
409 return VINF_SUCCESS;
410}
411
412/**
413 * Initializes the per-VCPU HWACCM.
414 *
415 * @returns VBox status code.
416 * @param pVM The VM to operate on.
417 */
418VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
419{
420 LogFlow(("HWACCMR3InitCPU\n"));
421
422 for (VMCPUID i = 0; i < pVM->cCpus; i++)
423 {
424 PVMCPU pVCpu = &pVM->aCpus[i];
425
426 pVCpu->hwaccm.s.fActive = false;
427 }
428
429#ifdef VBOX_WITH_STATISTICS
430 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
431 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
432 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
433 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
434
435 /*
436 * Statistics.
437 */
438 for (VMCPUID i = 0; i < pVM->cCpus; i++)
439 {
440 PVMCPU pVCpu = &pVM->aCpus[i];
441 int rc;
442
443 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of RTMpPokeCpu",
444 "/PROF/HWACCM/CPU%d/Poke", i);
445 AssertRC(rc);
446 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait",
447 "/PROF/HWACCM/CPU%d/PokeWait", i);
448 AssertRC(rc);
449 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait when RTMpPokeCpu fails",
450 "/PROF/HWACCM/CPU%d/PokeWaitFailed", i);
451 AssertRC(rc);
452 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
453 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
454 AssertRC(rc);
455 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
456 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
457 AssertRC(rc);
458 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
459 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
460 AssertRC(rc);
461# if 1 /* temporary for tracking down darwin holdup. */
462 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
463 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
464 AssertRC(rc);
465 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
466 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
467 AssertRC(rc);
468 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
469 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
470 AssertRC(rc);
471# endif
472 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
473 "/PROF/HWACCM/CPU%d/InGC", i);
474 AssertRC(rc);
475
476# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
477 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
478 "/PROF/HWACCM/CPU%d/Switcher3264", i);
479 AssertRC(rc);
480# endif
481
482# define HWACCM_REG_COUNTER(a, b) \
483 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
484 AssertRC(rc);
485
486 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
487 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
488 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
489 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
490 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
491 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
492 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
493 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
494 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
495 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
496 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
498 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
499 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
503 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
504 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
505 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMonitor, "/HWACCM/CPU%d/Exit/Instr/Monitor");
506 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
507 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
508 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
509 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
510 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
511 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
512 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
513 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
514 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
515 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
516 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
517 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
518 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
519 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
520 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
521 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
522 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
523 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
524
525 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
526 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
527
528 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
529 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
530 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
531
532 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPage, "/HWACCM/CPU%d/Flush/Page");
533 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
534 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
535 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLB, "/HWACCM/CPU%d/Flush/TLB");
536 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
537 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
538 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
539 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
540 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
541 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
542 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
543 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
544 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
545
546 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
547 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
548 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow, "/HWACCM/CPU%d/TSC/InterceptOverflow");
549
550 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
551 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
552 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
553
554 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
555 {
556 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
557 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
558 AssertRC(rc);
559 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
560 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
561 AssertRC(rc);
562 }
563
564#undef HWACCM_REG_COUNTER
565
566 pVCpu->hwaccm.s.paStatExitReason = NULL;
567
568 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
569 AssertRC(rc);
570 if (RT_SUCCESS(rc))
571 {
572 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
573 for (int j=0;j<MAX_EXITREASON_STAT;j++)
574 {
575 if (papszDesc[j])
576 {
577 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
578 papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
579 AssertRC(rc);
580 }
581 }
582 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
583 AssertRC(rc);
584 }
585 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
586# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
587 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
588# else
589 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
590# endif
591
592 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
593 AssertRCReturn(rc, rc);
594 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
595# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
596 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
597# else
598 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
599# endif
600 for (unsigned j = 0; j < 255; j++)
601 STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
602 (j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
603
604 }
605#endif /* VBOX_WITH_STATISTICS */
606
607#ifdef VBOX_WITH_CRASHDUMP_MAGIC
608 /* Magic marker for searching in crash dumps. */
609 for (VMCPUID i = 0; i < pVM->cCpus; i++)
610 {
611 PVMCPU pVCpu = &pVM->aCpus[i];
612
613 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
614 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
615 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
616 }
617#endif
618 return VINF_SUCCESS;
619}
620
621/**
622 * Turns off normal raw mode features
623 *
624 * @param pVM The VM to operate on.
625 */
626static void hwaccmR3DisableRawMode(PVM pVM)
627{
628 /* Disable PATM & CSAM. */
629 PATMR3AllowPatching(pVM, false);
630 CSAMDisableScanning(pVM);
631
632 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
633 SELMR3DisableMonitoring(pVM);
634 TRPMR3DisableMonitoring(pVM);
635
636 /* Disable the switcher code (safety precaution). */
637 VMMR3DisableSwitcher(pVM);
638
639 /* Disable mapping of the hypervisor into the shadow page table. */
640 PGMR3MappingsDisable(pVM);
641
642 /* Disable the switcher */
643 VMMR3DisableSwitcher(pVM);
644
645 /* Reinit the paging mode to force the new shadow mode. */
646 for (VMCPUID i = 0; i < pVM->cCpus; i++)
647 {
648 PVMCPU pVCpu = &pVM->aCpus[i];
649
650 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
651 }
652}
653
654/**
655 * Initialize VT-x or AMD-V.
656 *
657 * @returns VBox status code.
658 * @param pVM The VM handle.
659 */
660VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
661{
662 int rc;
663
664 /* Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
665 * is already using AMD-V.
666 */
667 if ( !pVM->hwaccm.s.vmx.fSupported
668 && !pVM->hwaccm.s.svm.fSupported
669 && pVM->hwaccm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
670 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
671 {
672 LogRel(("HWACCM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
673 pVM->hwaccm.s.svm.fSupported = true;
674 pVM->hwaccm.s.svm.fIgnoreInUseError = true;
675 }
676 else
677 if ( !pVM->hwaccm.s.vmx.fSupported
678 && !pVM->hwaccm.s.svm.fSupported)
679 {
680 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
681 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
682
683 if (VMMIsHwVirtExtForced(pVM))
684 {
685 switch (pVM->hwaccm.s.lLastError)
686 {
687 case VERR_VMX_NO_VMX:
688 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
689 case VERR_VMX_IN_VMX_ROOT_MODE:
690 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
691 case VERR_SVM_IN_USE:
692 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
693 case VERR_SVM_NO_SVM:
694 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
695 case VERR_SVM_DISABLED:
696 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
697 default:
698 return pVM->hwaccm.s.lLastError;
699 }
700 }
701 return VINF_SUCCESS;
702 }
703
704 if (pVM->hwaccm.s.vmx.fSupported)
705 {
706 rc = SUPR3QueryVTxSupported();
707 if (RT_FAILURE(rc))
708 {
709#ifdef RT_OS_LINUX
710 LogRel(("HWACCM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
711#else
712 LogRel(("HWACCM: The host kernel does not support VT-x!\n"));
713#endif
714 if ( pVM->cCpus > 1
715 || VMMIsHwVirtExtForced(pVM))
716 return rc;
717
718 /* silently fall back to raw mode */
719 return VINF_SUCCESS;
720 }
721 }
722
723 if (!pVM->hwaccm.s.fAllowed)
724 return VINF_SUCCESS; /* nothing to do */
725
726 /* Enable VT-x or AMD-V on all host CPUs. */
727 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
728 if (RT_FAILURE(rc))
729 {
730 LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
731 return rc;
732 }
733 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
734
735 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
736 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
737 if (!pVM->hwaccm.s.fHasIoApic)
738 {
739 Assert(!pVM->hwaccm.s.fTRPPatchingAllowed); /* paranoia */
740 pVM->hwaccm.s.fTRPPatchingAllowed = false;
741 }
742
743 if (pVM->hwaccm.s.vmx.fSupported)
744 {
745 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
746
747 if ( pVM->hwaccm.s.fInitialized == false
748 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
749 {
750 uint64_t val;
751 RTGCPHYS GCPhys = 0;
752
753 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
754 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
755 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
756 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
757 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
758 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
759 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
760 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
761
762 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
763 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
764 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
765 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
766 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
767 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
768 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
769 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
770 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
771 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
772 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
773 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
774 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
775 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
776 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
777 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
778 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
779 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
780 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
781
782 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
783 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
784 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
785 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
786 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
787 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
788 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
789 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
790 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
791 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
792 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
793 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
794 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
795 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
796 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
797 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
798 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
799 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
800 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
801 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
802 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
803 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
804 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
805 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
806 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
807 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
808 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
809 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
810 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
811 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
812 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
813 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
814 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
815 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
816 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
817 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
818 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
819 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
820 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
821 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
822 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
823 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
824 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
825 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
826
827 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
828 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
829 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
830 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
831 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
832 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
833 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
834 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
835 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
836 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
837 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
838 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
839 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
840 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
841 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
842 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
843 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
844 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
845 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
846 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
847 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
848 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
849 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
850 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
851 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
852 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
853 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
854 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
855 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
856 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
857 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
858 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
859 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
860 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
861 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
862 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
863 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
864 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
865 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
866 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
867 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
868 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
869 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
870
871 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
872 {
873 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
874 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
875 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
876 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
877 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
878 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
879 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
880 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
881 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
882 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT\n"));
883 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
884 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
885 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
886 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
887 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
888 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
889 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
890 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE\n"));
891 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
892 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT\n"));
893
894 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
895 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
896 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
897 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
898 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
899 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
900 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT *must* be set\n"));
901 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
902 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
903 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
904 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
905 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
906 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
907 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
908 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
909 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
910 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE *must* be set\n"));
911 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
912 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT *must* be set\n"));
913 }
914
915 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
916 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
917 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
918 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
919 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
920 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
921 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
922 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
923 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
924 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
925 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
926 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
927 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
928 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
929 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
930 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
931 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
932 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
933 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
934 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
935 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
936 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
937 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
938 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
939 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
940 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
941 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
942 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
943 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
944 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
945 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
946
947 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
948 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
949 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
950 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
951 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
952 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
953 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
954 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
955 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
956 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
957 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
958 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
959 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
960 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
961 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
962 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
963 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
964 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
965 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
966 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
967 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
968 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
969 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
970 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
971 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
972 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
973 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
974 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
975 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
976 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
977 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
978 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
979 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
980 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
981 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
982
983 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
984 {
985 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
986
987 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
988 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
989 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
990 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
991 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
992 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
993 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
994 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
995 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
996 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
997 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
998 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
999 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
1000 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
1001 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
1002 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
1003 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
1004 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
1005 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
1006 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
1007 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
1008 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
1009 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
1010 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
1011 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
1012 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
1013 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
1014 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
1015 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
1016 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
1017 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
1018 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
1019 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
1020 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
1021 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
1022 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
1023 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
1024 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
1025 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
1026 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
1027 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
1028 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
1029 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
1030 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
1031 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
1032 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
1033 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
1034 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
1035 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
1036 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
1037 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
1038 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
1039 }
1040
1041 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
1042 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1043 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1044 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1045 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1046 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1047
1048 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
1049 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
1050 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
1051 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
1052 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
1053
1054 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
1055
1056 /* Paranoia */
1057 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc) >= 512);
1058
1059 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1060 {
1061 LogRel(("HWACCM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pMSRBitmapPhys));
1062 LogRel(("HWACCM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1063 }
1064
1065#ifdef HWACCM_VTX_WITH_EPT
1066 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1067 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1068#endif /* HWACCM_VTX_WITH_EPT */
1069#ifdef HWACCM_VTX_WITH_VPID
1070 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1071 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
1072 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
1073#endif /* HWACCM_VTX_WITH_VPID */
1074
1075 /* Unrestricted guest execution relies on EPT. */
1076 if ( pVM->hwaccm.s.fNestedPaging
1077 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE))
1078 {
1079 pVM->hwaccm.s.vmx.fUnrestrictedGuest = true;
1080 }
1081
1082 /* Only try once. */
1083 pVM->hwaccm.s.fInitialized = true;
1084
1085 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1086 {
1087 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1088 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
1089 if (RT_SUCCESS(rc))
1090 {
1091 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1092 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
1093 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
1094 /* Bit set to 0 means redirection enabled. */
1095 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
1096 /* Allow all port IO, so the VT-x IO intercepts do their job. */
1097 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
1098 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
1099
1100 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1101 * real and protected mode without paging with EPT.
1102 */
1103 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1104 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
1105 {
1106 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1107 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
1108 }
1109
1110 /* We convert it here every time as pci regions could be reconfigured. */
1111 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1112 AssertRC(rc);
1113 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1114
1115 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1116 AssertRC(rc);
1117 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1118 }
1119 else
1120 {
1121 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1122 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1123 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1124 }
1125 }
1126
1127 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1128 AssertRC(rc);
1129 if (rc == VINF_SUCCESS)
1130 {
1131 pVM->fHWACCMEnabled = true;
1132 pVM->hwaccm.s.vmx.fEnabled = true;
1133 hwaccmR3DisableRawMode(pVM);
1134
1135 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1136#ifdef VBOX_ENABLE_64_BITS_GUESTS
1137 if (pVM->hwaccm.s.fAllow64BitGuests)
1138 {
1139 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1140 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1141 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1142 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1143 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1144 }
1145 else
1146 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1147 /* Todo: this needs to be fixed properly!! */
1148 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1149 && (pVM->hwaccm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1150 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1151
1152 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1153 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1154 : "HWACCM: 32-bit guests supported.\n"));
1155#else
1156 LogRel(("HWACCM: 32-bit guests supported.\n"));
1157#endif
1158 LogRel(("HWACCM: VMX enabled!\n"));
1159 if (pVM->hwaccm.s.fNestedPaging)
1160 {
1161 LogRel(("HWACCM: Enabled nested paging\n"));
1162 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1163 if (pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1164 LogRel(("HWACCM: Unrestricted guest execution enabled!\n"));
1165
1166#if HC_ARCH_BITS == 64
1167 if (pVM->hwaccm.s.fLargePages)
1168 {
1169 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1170 PGMSetLargePageUsage(pVM, true);
1171 LogRel(("HWACCM: Large page support enabled!\n"));
1172 }
1173#endif
1174 }
1175 else
1176 Assert(!pVM->hwaccm.s.vmx.fUnrestrictedGuest);
1177
1178 if (pVM->hwaccm.s.vmx.fVPID)
1179 LogRel(("HWACCM: Enabled VPID\n"));
1180
1181 if ( pVM->hwaccm.s.fNestedPaging
1182 || pVM->hwaccm.s.vmx.fVPID)
1183 {
1184 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1185 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1186 }
1187
1188 /* TPR patching status logging. */
1189 if (pVM->hwaccm.s.fTRPPatchingAllowed)
1190 {
1191 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1192 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1193 {
1194 pVM->hwaccm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1195 LogRel(("HWACCM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1196 }
1197 else
1198 {
1199 uint32_t u32Eax, u32Dummy;
1200
1201 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1202 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1203 if ( u32Eax < 0x80000001
1204 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1205 {
1206 pVM->hwaccm.s.fTRPPatchingAllowed = false;
1207 LogRel(("HWACCM: TPR patching disabled (long mode not supported).\n"));
1208 }
1209 }
1210 }
1211 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1212 }
1213 else
1214 {
1215 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1216 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1217 pVM->fHWACCMEnabled = false;
1218 }
1219 }
1220 }
1221 else
1222 if (pVM->hwaccm.s.svm.fSupported)
1223 {
1224 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1225
1226 if (pVM->hwaccm.s.fInitialized == false)
1227 {
1228 /* Erratum 170 which requires a forced TLB flush for each world switch:
1229 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1230 *
1231 * All BH-G1/2 and DH-G1/2 models include a fix:
1232 * Athlon X2: 0x6b 1/2
1233 * 0x68 1/2
1234 * Athlon 64: 0x7f 1
1235 * 0x6f 2
1236 * Sempron: 0x7f 1/2
1237 * 0x6f 2
1238 * 0x6c 2
1239 * 0x7c 2
1240 * Turion 64: 0x68 2
1241 *
1242 */
1243 uint32_t u32Dummy;
1244 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1245 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1246 u32BaseFamily= (u32Version >> 8) & 0xf;
1247 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1248 u32Model = ((u32Version >> 4) & 0xf);
1249 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1250 u32Stepping = u32Version & 0xf;
1251 if ( u32Family == 0xf
1252 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1253 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1254 {
1255 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1256 }
1257
1258 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1259 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1260 LogRel(("HWACCM: AMD HWCR MSR = %RX64\n", pVM->hwaccm.s.svm.msrHWCR));
1261 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1262 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1263 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1264
1265 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1266 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
1267 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
1268 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
1269 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
1270 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
1271 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
1272 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
1273 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
1274 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
1275 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER)
1276 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER\n"));
1277
1278 /* Only try once. */
1279 pVM->hwaccm.s.fInitialized = true;
1280
1281 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1282 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1283
1284 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1285 AssertRC(rc);
1286 if (rc == VINF_SUCCESS)
1287 {
1288 pVM->fHWACCMEnabled = true;
1289 pVM->hwaccm.s.svm.fEnabled = true;
1290
1291 if (pVM->hwaccm.s.fNestedPaging)
1292 {
1293 LogRel(("HWACCM: Enabled nested paging\n"));
1294#if HC_ARCH_BITS == 64
1295 if (pVM->hwaccm.s.fLargePages)
1296 {
1297 /* Use large (2 MB) pages for our nested paging PDEs where possible. */
1298 PGMSetLargePageUsage(pVM, true);
1299 LogRel(("HWACCM: Large page support enabled!\n"));
1300 }
1301#endif
1302 }
1303
1304 hwaccmR3DisableRawMode(pVM);
1305 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1306 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1307 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1308#ifdef VBOX_ENABLE_64_BITS_GUESTS
1309 if (pVM->hwaccm.s.fAllow64BitGuests)
1310 {
1311 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1312 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1313 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1314 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1315 }
1316 else
1317 /* Turn on NXE if PAE has been enabled. */
1318 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1319 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1320#endif
1321
1322 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1323 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1324 : "HWACCM: 32-bit guest supported.\n"));
1325
1326 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1327 }
1328 else
1329 {
1330 pVM->fHWACCMEnabled = false;
1331 }
1332 }
1333 }
1334 if (pVM->fHWACCMEnabled)
1335 LogRel(("HWACCM: VT-x/AMD-V init method: %s\n", (pVM->hwaccm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1336 return VINF_SUCCESS;
1337}
1338
1339/**
1340 * Applies relocations to data and code managed by this
1341 * component. This function will be called at init and
1342 * whenever the VMM need to relocate it self inside the GC.
1343 *
1344 * @param pVM The VM.
1345 */
1346VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1347{
1348 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1349
1350 /* Fetch the current paging mode during the relocate callback during state loading. */
1351 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1352 {
1353 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1354 {
1355 PVMCPU pVCpu = &pVM->aCpus[i];
1356
1357 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1358 Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1359 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1360 }
1361 }
1362#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1363 if (pVM->fHWACCMEnabled)
1364 {
1365 int rc;
1366
1367 switch(PGMGetHostMode(pVM))
1368 {
1369 case PGMMODE_32_BIT:
1370 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1371 break;
1372
1373 case PGMMODE_PAE:
1374 case PGMMODE_PAE_NX:
1375 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1376 break;
1377
1378 default:
1379 AssertFailed();
1380 break;
1381 }
1382 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1383 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1384
1385 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1386 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1387
1388 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1389 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1390
1391 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1392 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1393
1394# ifdef DEBUG
1395 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1396 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1397# endif
1398 }
1399#endif
1400 return;
1401}
1402
1403/**
1404 * Checks hardware accelerated raw mode is allowed.
1405 *
1406 * @returns boolean
1407 * @param pVM The VM to operate on.
1408 */
1409VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1410{
1411 return pVM->hwaccm.s.fAllowed;
1412}
1413
1414/**
1415 * Notification callback which is called whenever there is a chance that a CR3
1416 * value might have changed.
1417 *
1418 * This is called by PGM.
1419 *
1420 * @param pVM The VM to operate on.
1421 * @param pVCpu The VMCPU to operate on.
1422 * @param enmShadowMode New shadow paging mode.
1423 * @param enmGuestMode New guest paging mode.
1424 */
1425VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1426{
1427 /* Ignore page mode changes during state loading. */
1428 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1429 return;
1430
1431 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1432
1433 if ( pVM->hwaccm.s.vmx.fEnabled
1434 && pVM->fHWACCMEnabled)
1435 {
1436 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1437 && enmGuestMode >= PGMMODE_PROTECTED)
1438 {
1439 PCPUMCTX pCtx;
1440
1441 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1442
1443 /* After a real mode switch to protected mode we must force
1444 * CPL to 0. Our real mode emulation had to set it to 3.
1445 */
1446 pCtx->ssHid.Attr.n.u2Dpl = 0;
1447 }
1448 }
1449
1450 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1451 {
1452 /* Keep track of paging mode changes. */
1453 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1454 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1455
1456 /* Did we miss a change, because all code was executed in the recompiler? */
1457 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1458 {
1459 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1460 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1461 }
1462 }
1463
1464 /* Reset the contents of the read cache. */
1465 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1466 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1467 pCache->Read.aFieldVal[j] = 0;
1468}
1469
1470/**
1471 * Terminates the HWACCM.
1472 *
1473 * Termination means cleaning up and freeing all resources,
1474 * the VM it self is at this point powered off or suspended.
1475 *
1476 * @returns VBox status code.
1477 * @param pVM The VM to operate on.
1478 */
1479VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1480{
1481 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1482 {
1483 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1484 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1485 }
1486 HWACCMR3TermCPU(pVM);
1487 return 0;
1488}
1489
1490/**
1491 * Terminates the per-VCPU HWACCM.
1492 *
1493 * Termination means cleaning up and freeing all resources,
1494 * the VM it self is at this point powered off or suspended.
1495 *
1496 * @returns VBox status code.
1497 * @param pVM The VM to operate on.
1498 */
1499VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1500{
1501 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1502 {
1503 PVMCPU pVCpu = &pVM->aCpus[i];
1504
1505#ifdef VBOX_WITH_STATISTICS
1506 if (pVCpu->hwaccm.s.paStatExitReason)
1507 {
1508 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1509 pVCpu->hwaccm.s.paStatExitReason = NULL;
1510 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1511 }
1512 if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1513 {
1514 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1515 pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1516 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1517 }
1518#endif
1519
1520#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1521 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1522 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1523 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1524#endif
1525 }
1526 return 0;
1527}
1528
1529/**
1530 * Resets a virtual CPU.
1531 *
1532 * Used by HWACCMR3Reset and CPU hot plugging.
1533 *
1534 * @param pVCpu The CPU to reset.
1535 */
1536VMMR3DECL(void) HWACCMR3ResetCpu(PVMCPU pVCpu)
1537{
1538 /* On first entry we'll sync everything. */
1539 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1540
1541 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1542 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1543
1544 pVCpu->hwaccm.s.fActive = false;
1545 pVCpu->hwaccm.s.Event.fPending = false;
1546
1547 /* Reset state information for real-mode emulation in VT-x. */
1548 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1549 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1550 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1551
1552 /* Reset the contents of the read cache. */
1553 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1554 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1555 pCache->Read.aFieldVal[j] = 0;
1556
1557#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1558 /* Magic marker for searching in crash dumps. */
1559 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1560 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1561#endif
1562}
1563
1564/**
1565 * The VM is being reset.
1566 *
1567 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1568 * needs to be removed.
1569 *
1570 * @param pVM VM handle.
1571 */
1572VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1573{
1574 LogFlow(("HWACCMR3Reset:\n"));
1575
1576 if (pVM->fHWACCMEnabled)
1577 hwaccmR3DisableRawMode(pVM);
1578
1579 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1580 {
1581 PVMCPU pVCpu = &pVM->aCpus[i];
1582
1583 HWACCMR3ResetCpu(pVCpu);
1584 }
1585
1586 /* Clear all patch information. */
1587 pVM->hwaccm.s.pGuestPatchMem = 0;
1588 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1589 pVM->hwaccm.s.cbGuestPatchMem = 0;
1590 pVM->hwaccm.s.cPatches = 0;
1591 pVM->hwaccm.s.PatchTree = 0;
1592 pVM->hwaccm.s.fTPRPatchingActive = false;
1593 ASMMemZero32(pVM->hwaccm.s.aPatches, sizeof(pVM->hwaccm.s.aPatches));
1594}
1595
1596/**
1597 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1598 *
1599 * @returns VBox strict status code.
1600 * @param pVM The VM handle.
1601 * @param pVCpu The VMCPU for the EMT we're being called on.
1602 * @param pvUser Unused
1603 *
1604 */
1605DECLCALLBACK(VBOXSTRICTRC) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1606{
1607 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1608
1609 /* Only execute the handler on the VCPU the original patch request was issued. */
1610 if (pVCpu->idCpu != idCpu)
1611 return VINF_SUCCESS;
1612
1613 Log(("hwaccmR3RemovePatches\n"));
1614 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
1615 {
1616 uint8_t szInstr[15];
1617 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
1618 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1619 int rc;
1620
1621#ifdef LOG_ENABLED
1622 char szOutput[256];
1623
1624 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1625 if (RT_SUCCESS(rc))
1626 Log(("Patched instr: %s\n", szOutput));
1627#endif
1628
1629 /* Check if the instruction is still the same. */
1630 rc = PGMPhysSimpleReadGCPtr(pVCpu, szInstr, pInstrGC, pPatch->cbNewOp);
1631 if (rc != VINF_SUCCESS)
1632 {
1633 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1634 continue; /* swapped out or otherwise removed; skip it. */
1635 }
1636
1637 if (memcmp(szInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1638 {
1639 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1640 continue; /* skip it. */
1641 }
1642
1643 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1644 AssertRC(rc);
1645
1646#ifdef LOG_ENABLED
1647 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1648 if (RT_SUCCESS(rc))
1649 Log(("Original instr: %s\n", szOutput));
1650#endif
1651 }
1652 pVM->hwaccm.s.cPatches = 0;
1653 pVM->hwaccm.s.PatchTree = 0;
1654 pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1655 pVM->hwaccm.s.fTPRPatchingActive = false;
1656 return VINF_SUCCESS;
1657}
1658
1659/**
1660 * Enable patching in a VT-x/AMD-V guest
1661 *
1662 * @returns VBox status code.
1663 * @param pVM The VM to operate on.
1664 * @param idCpu VCPU to execute hwaccmR3RemovePatches on
1665 * @param pPatchMem Patch memory range
1666 * @param cbPatchMem Size of the memory range
1667 */
1668int hwaccmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1669{
1670 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)idCpu);
1671 AssertRC(rc);
1672
1673 pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1674 pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1675 pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1676 return VINF_SUCCESS;
1677}
1678
1679/**
1680 * Enable patching in a VT-x/AMD-V guest
1681 *
1682 * @returns VBox status code.
1683 * @param pVM The VM to operate on.
1684 * @param pPatchMem Patch memory range
1685 * @param cbPatchMem Size of the memory range
1686 */
1687VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1688{
1689 Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1690 if (pVM->cCpus > 1)
1691 {
1692 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1693 int rc = VMR3ReqCallNoWaitU(pVM->pUVM, VMCPUID_ANY_QUEUE,
1694 (PFNRT)hwaccmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1695 AssertRC(rc);
1696 return rc;
1697 }
1698 return hwaccmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1699}
1700
1701/**
1702 * Disable patching in a VT-x/AMD-V guest
1703 *
1704 * @returns VBox status code.
1705 * @param pVM The VM to operate on.
1706 * @param pPatchMem Patch memory range
1707 * @param cbPatchMem Size of the memory range
1708 */
1709VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1710{
1711 Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1712
1713 Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1714 Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1715
1716 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1717 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)VMMGetCpuId(pVM));
1718 AssertRC(rc);
1719
1720 pVM->hwaccm.s.pGuestPatchMem = 0;
1721 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1722 pVM->hwaccm.s.cbGuestPatchMem = 0;
1723 pVM->hwaccm.s.fTPRPatchingActive = false;
1724 return VINF_SUCCESS;
1725}
1726
1727
1728/**
1729 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1730 *
1731 * @returns VBox strict status code.
1732 * @param pVM The VM handle.
1733 * @param pVCpu The VMCPU for the EMT we're being called on.
1734 * @param pvUser User specified CPU context
1735 *
1736 */
1737DECLCALLBACK(VBOXSTRICTRC) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1738{
1739 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1740 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1741 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1742 unsigned cbOp;
1743
1744 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1745 if (pVCpu->idCpu != idCpu)
1746 return VINF_SUCCESS;
1747
1748 Log(("hwaccmR3ReplaceTprInstr: %RGv\n", pCtx->rip));
1749
1750 /* Two or more VCPUs were racing to patch this instruction. */
1751 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1752 if (pPatch)
1753 return VINF_SUCCESS;
1754
1755 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1756
1757 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1758 AssertRC(rc);
1759 if ( rc == VINF_SUCCESS
1760 && pDis->pCurInstr->opcode == OP_MOV
1761 && cbOp >= 3)
1762 {
1763 uint8_t aVMMCall[3] = { 0xf, 0x1, 0xd9};
1764 uint32_t idx = pVM->hwaccm.s.cPatches;
1765
1766 pPatch = &pVM->hwaccm.s.aPatches[idx];
1767
1768 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1769 AssertRC(rc);
1770
1771 pPatch->cbOp = cbOp;
1772
1773 if (pDis->param1.flags == USE_DISPLACEMENT32)
1774 {
1775 /* write. */
1776 if (pDis->param2.flags == USE_REG_GEN32)
1777 {
1778 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1779 pPatch->uSrcOperand = pDis->param2.base.reg_gen;
1780 }
1781 else
1782 {
1783 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1784 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1785 pPatch->uSrcOperand = pDis->param2.parval;
1786 }
1787 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1788 AssertRC(rc);
1789
1790 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1791 pPatch->cbNewOp = sizeof(aVMMCall);
1792 }
1793 else
1794 {
1795 RTGCPTR oldrip = pCtx->rip;
1796 uint32_t oldcbOp = cbOp;
1797 uint32_t uMmioReg = pDis->param1.base.reg_gen;
1798
1799 /* read */
1800 Assert(pDis->param1.flags == USE_REG_GEN32);
1801
1802 /* Found:
1803 * mov eax, dword [fffe0080] (5 bytes)
1804 * Check if next instruction is:
1805 * shr eax, 4
1806 */
1807 pCtx->rip += cbOp;
1808 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1809 pCtx->rip = oldrip;
1810 if ( rc == VINF_SUCCESS
1811 && pDis->pCurInstr->opcode == OP_SHR
1812 && pDis->param1.flags == USE_REG_GEN32
1813 && pDis->param1.base.reg_gen == uMmioReg
1814 && pDis->param2.flags == USE_IMMEDIATE8
1815 && pDis->param2.parval == 4
1816 && oldcbOp + cbOp < sizeof(pVM->hwaccm.s.aPatches[idx].aOpcode))
1817 {
1818 uint8_t szInstr[15];
1819
1820 /* Replacing two instructions now. */
1821 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, oldcbOp + cbOp);
1822 AssertRC(rc);
1823
1824 pPatch->cbOp = oldcbOp + cbOp;
1825
1826 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1827 szInstr[0] = 0xF0;
1828 szInstr[1] = 0x0F;
1829 szInstr[2] = 0x20;
1830 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
1831 for (unsigned i = 4; i < pPatch->cbOp; i++)
1832 szInstr[i] = 0x90; /* nop */
1833
1834 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, pPatch->cbOp);
1835 AssertRC(rc);
1836
1837 memcpy(pPatch->aNewOpcode, szInstr, pPatch->cbOp);
1838 pPatch->cbNewOp = pPatch->cbOp;
1839
1840 Log(("Acceptable read/shr candidate!\n"));
1841 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1842 }
1843 else
1844 {
1845 pPatch->enmType = HWACCMTPRINSTR_READ;
1846 pPatch->uDstOperand = pDis->param1.base.reg_gen;
1847
1848 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1849 AssertRC(rc);
1850
1851 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1852 pPatch->cbNewOp = sizeof(aVMMCall);
1853 }
1854 }
1855
1856 pPatch->Core.Key = pCtx->eip;
1857 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1858 AssertRC(rc);
1859
1860 pVM->hwaccm.s.cPatches++;
1861 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceSuccess);
1862 return VINF_SUCCESS;
1863 }
1864
1865 /* Save invalid patch, so we will not try again. */
1866 uint32_t idx = pVM->hwaccm.s.cPatches;
1867
1868#ifdef LOG_ENABLED
1869 char szOutput[256];
1870 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1871 if (RT_SUCCESS(rc))
1872 Log(("Failed to patch instr: %s\n", szOutput));
1873#endif
1874
1875 pPatch = &pVM->hwaccm.s.aPatches[idx];
1876 pPatch->Core.Key = pCtx->eip;
1877 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1878 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1879 AssertRC(rc);
1880 pVM->hwaccm.s.cPatches++;
1881 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceFailure);
1882 return VINF_SUCCESS;
1883}
1884
1885/**
1886 * Callback to patch a TPR instruction (jump to generated code)
1887 *
1888 * @returns VBox strict status code.
1889 * @param pVM The VM handle.
1890 * @param pVCpu The VMCPU for the EMT we're being called on.
1891 * @param pvUser User specified CPU context
1892 *
1893 */
1894DECLCALLBACK(VBOXSTRICTRC) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1895{
1896 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1897 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1898 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1899 unsigned cbOp;
1900 int rc;
1901#ifdef LOG_ENABLED
1902 RTGCPTR pInstr;
1903 char szOutput[256];
1904#endif
1905
1906 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1907 if (pVCpu->idCpu != idCpu)
1908 return VINF_SUCCESS;
1909
1910 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1911
1912 /* Two or more VCPUs were racing to patch this instruction. */
1913 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1914 if (pPatch)
1915 {
1916 Log(("hwaccmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
1917 return VINF_SUCCESS;
1918 }
1919
1920 Log(("hwaccmR3PatchTprInstr %RGv\n", pCtx->rip));
1921
1922 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1923 AssertRC(rc);
1924 if ( rc == VINF_SUCCESS
1925 && pDis->pCurInstr->opcode == OP_MOV
1926 && cbOp >= 5)
1927 {
1928 uint32_t idx = pVM->hwaccm.s.cPatches;
1929 uint8_t aPatch[64];
1930 uint32_t off = 0;
1931
1932 pPatch = &pVM->hwaccm.s.aPatches[idx];
1933
1934#ifdef LOG_ENABLED
1935 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1936 if (RT_SUCCESS(rc))
1937 Log(("Original instr: %s\n", szOutput));
1938#endif
1939
1940 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1941 AssertRC(rc);
1942
1943 pPatch->cbOp = cbOp;
1944 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
1945
1946 if (pDis->param1.flags == USE_DISPLACEMENT32)
1947 {
1948 /*
1949 * TPR write:
1950 *
1951 * push ECX [51]
1952 * push EDX [52]
1953 * push EAX [50]
1954 * xor EDX,EDX [31 D2]
1955 * mov EAX,EAX [89 C0]
1956 * or
1957 * mov EAX,0000000CCh [B8 CC 00 00 00]
1958 * mov ECX,0C0000082h [B9 82 00 00 C0]
1959 * wrmsr [0F 30]
1960 * pop EAX [58]
1961 * pop EDX [5A]
1962 * pop ECX [59]
1963 * jmp return_address [E9 return_address]
1964 *
1965 */
1966 bool fUsesEax = (pDis->param2.flags == USE_REG_GEN32 && pDis->param2.base.reg_gen == USE_REG_EAX);
1967
1968 aPatch[off++] = 0x51; /* push ecx */
1969 aPatch[off++] = 0x52; /* push edx */
1970 if (!fUsesEax)
1971 aPatch[off++] = 0x50; /* push eax */
1972 aPatch[off++] = 0x31; /* xor edx, edx */
1973 aPatch[off++] = 0xD2;
1974 if (pDis->param2.flags == USE_REG_GEN32)
1975 {
1976 if (!fUsesEax)
1977 {
1978 aPatch[off++] = 0x89; /* mov eax, src_reg */
1979 aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, USE_REG_EAX);
1980 }
1981 }
1982 else
1983 {
1984 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1985 aPatch[off++] = 0xB8; /* mov eax, immediate */
1986 *(uint32_t *)&aPatch[off] = pDis->param2.parval;
1987 off += sizeof(uint32_t);
1988 }
1989 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1990 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1991 off += sizeof(uint32_t);
1992
1993 aPatch[off++] = 0x0F; /* wrmsr */
1994 aPatch[off++] = 0x30;
1995 if (!fUsesEax)
1996 aPatch[off++] = 0x58; /* pop eax */
1997 aPatch[off++] = 0x5A; /* pop edx */
1998 aPatch[off++] = 0x59; /* pop ecx */
1999 }
2000 else
2001 {
2002 /*
2003 * TPR read:
2004 *
2005 * push ECX [51]
2006 * push EDX [52]
2007 * push EAX [50]
2008 * mov ECX,0C0000082h [B9 82 00 00 C0]
2009 * rdmsr [0F 32]
2010 * mov EAX,EAX [89 C0]
2011 * pop EAX [58]
2012 * pop EDX [5A]
2013 * pop ECX [59]
2014 * jmp return_address [E9 return_address]
2015 *
2016 */
2017 Assert(pDis->param1.flags == USE_REG_GEN32);
2018
2019 if (pDis->param1.base.reg_gen != USE_REG_ECX)
2020 aPatch[off++] = 0x51; /* push ecx */
2021 if (pDis->param1.base.reg_gen != USE_REG_EDX)
2022 aPatch[off++] = 0x52; /* push edx */
2023 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2024 aPatch[off++] = 0x50; /* push eax */
2025
2026 aPatch[off++] = 0x31; /* xor edx, edx */
2027 aPatch[off++] = 0xD2;
2028
2029 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2030 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2031 off += sizeof(uint32_t);
2032
2033 aPatch[off++] = 0x0F; /* rdmsr */
2034 aPatch[off++] = 0x32;
2035
2036 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2037 {
2038 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2039 aPatch[off++] = MAKE_MODRM(3, USE_REG_EAX, pDis->param1.base.reg_gen);
2040 }
2041
2042 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2043 aPatch[off++] = 0x58; /* pop eax */
2044 if (pDis->param1.base.reg_gen != USE_REG_EDX)
2045 aPatch[off++] = 0x5A; /* pop edx */
2046 if (pDis->param1.base.reg_gen != USE_REG_ECX)
2047 aPatch[off++] = 0x59; /* pop ecx */
2048 }
2049 aPatch[off++] = 0xE9; /* jmp return_address */
2050 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
2051 off += sizeof(RTRCUINTPTR);
2052
2053 if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
2054 {
2055 /* Write new code to the patch buffer. */
2056 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
2057 AssertRC(rc);
2058
2059#ifdef LOG_ENABLED
2060 pInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
2061 while (true)
2062 {
2063 uint32_t cb;
2064
2065 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pInstr, 0, szOutput, sizeof(szOutput), &cb);
2066 if (RT_SUCCESS(rc))
2067 Log(("Patch instr %s\n", szOutput));
2068
2069 pInstr += cb;
2070
2071 if (pInstr >= pVM->hwaccm.s.pFreeGuestPatchMem + off)
2072 break;
2073 }
2074#endif
2075
2076 pPatch->aNewOpcode[0] = 0xE9;
2077 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2078
2079 /* Overwrite the TPR instruction with a jump. */
2080 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2081 AssertRC(rc);
2082
2083#ifdef LOG_ENABLED
2084 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
2085 if (RT_SUCCESS(rc))
2086 Log(("Jump: %s\n", szOutput));
2087#endif
2088 pVM->hwaccm.s.pFreeGuestPatchMem += off;
2089 pPatch->cbNewOp = 5;
2090
2091 pPatch->Core.Key = pCtx->eip;
2092 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2093 AssertRC(rc);
2094
2095 pVM->hwaccm.s.cPatches++;
2096 pVM->hwaccm.s.fTPRPatchingActive = true;
2097 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchSuccess);
2098 return VINF_SUCCESS;
2099 }
2100 else
2101 Log(("Ran out of space in our patch buffer!\n"));
2102 }
2103
2104 /* Save invalid patch, so we will not try again. */
2105 uint32_t idx = pVM->hwaccm.s.cPatches;
2106
2107#ifdef LOG_ENABLED
2108 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
2109 if (RT_SUCCESS(rc))
2110 Log(("Failed to patch instr: %s\n", szOutput));
2111#endif
2112
2113 pPatch = &pVM->hwaccm.s.aPatches[idx];
2114 pPatch->Core.Key = pCtx->eip;
2115 pPatch->enmType = HWACCMTPRINSTR_INVALID;
2116 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2117 AssertRC(rc);
2118 pVM->hwaccm.s.cPatches++;
2119 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchFailure);
2120 return VINF_SUCCESS;
2121}
2122
2123/**
2124 * Attempt to patch TPR mmio instructions
2125 *
2126 * @returns VBox status code.
2127 * @param pVM The VM to operate on.
2128 * @param pVCpu The VM CPU to operate on.
2129 * @param pCtx CPU context
2130 */
2131VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2132{
2133 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, (pVM->hwaccm.s.pGuestPatchMem) ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr, (void *)pVCpu->idCpu);
2134 AssertRC(rc);
2135 return rc;
2136}
2137
2138/**
2139 * Force execution of the current IO code in the recompiler
2140 *
2141 * @returns VBox status code.
2142 * @param pVM The VM to operate on.
2143 * @param pCtx Partial VM execution context
2144 */
2145VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2146{
2147 PVMCPU pVCpu = VMMGetCpu(pVM);
2148
2149 Assert(pVM->fHWACCMEnabled);
2150 Log(("HWACCMR3EmulateIoBlock\n"));
2151
2152 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2153 if (HWACCMCanEmulateIoBlockEx(pCtx))
2154 {
2155 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
2156 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
2157 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2158 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2159 return VINF_EM_RESCHEDULE_REM;
2160 }
2161 return VINF_SUCCESS;
2162}
2163
2164/**
2165 * Checks if we can currently use hardware accelerated raw mode.
2166 *
2167 * @returns boolean
2168 * @param pVM The VM to operate on.
2169 * @param pCtx Partial VM execution context
2170 */
2171VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2172{
2173 PVMCPU pVCpu = VMMGetCpu(pVM);
2174
2175 Assert(pVM->fHWACCMEnabled);
2176
2177 /* If we're still executing the IO code, then return false. */
2178 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
2179 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2180 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2181 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
2182 return false;
2183
2184 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
2185
2186 /* AMD-V supports real & protected mode with or without paging. */
2187 if (pVM->hwaccm.s.svm.fEnabled)
2188 {
2189 pVCpu->hwaccm.s.fActive = true;
2190 return true;
2191 }
2192
2193 pVCpu->hwaccm.s.fActive = false;
2194
2195 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2196#ifdef HWACCM_VMX_EMULATE_REALMODE
2197 bool fVMMDeviceHeapEnabled = PDMVMMDevHeapIsEnabled(pVM);
2198
2199 Assert((pVM->hwaccm.s.vmx.fUnrestrictedGuest && !pVM->hwaccm.s.vmx.pRealModeTSS) || (!pVM->hwaccm.s.vmx.fUnrestrictedGuest && pVM->hwaccm.s.vmx.pRealModeTSS));
2200
2201 /** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. */
2202 if (fVMMDeviceHeapEnabled)
2203 {
2204 if (CPUMIsGuestInRealModeEx(pCtx))
2205 {
2206 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
2207 * The base must also be equal to (sel << 4).
2208 */
2209 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
2210 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
2211 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
2212 || pCtx->es != (pCtx->esHid.u64Base >> 4)
2213 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
2214 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
2215 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
2216 {
2217 return false;
2218 }
2219 }
2220 else
2221 {
2222 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2223 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
2224 * from real to protected mode. (all sorts of RPL & DPL assumptions)
2225 */
2226 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2227 && enmGuestMode >= PGMMODE_PROTECTED)
2228 {
2229 if ( (pCtx->cs & X86_SEL_RPL)
2230 || (pCtx->ds & X86_SEL_RPL)
2231 || (pCtx->es & X86_SEL_RPL)
2232 || (pCtx->fs & X86_SEL_RPL)
2233 || (pCtx->gs & X86_SEL_RPL)
2234 || (pCtx->ss & X86_SEL_RPL))
2235 {
2236 return false;
2237 }
2238 }
2239 }
2240 }
2241 else
2242#endif /* HWACCM_VMX_EMULATE_REALMODE */
2243 {
2244 if ( !CPUMIsGuestInLongModeEx(pCtx)
2245 && !pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2246 {
2247 /** @todo This should (probably) be set on every excursion to the REM,
2248 * however it's too risky right now. So, only apply it when we go
2249 * back to REM for real mode execution. (The XP hack below doesn't
2250 * work reliably without this.)
2251 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2252 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2253
2254 if ( !pVM->hwaccm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap*/
2255 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2256 return false;
2257
2258 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2259 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
2260 return false;
2261
2262 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2263 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2264 * hidden registers (possible recompiler bug; see load_seg_vm) */
2265 if (pCtx->csHid.Attr.n.u1Present == 0)
2266 return false;
2267 if (pCtx->ssHid.Attr.n.u1Present == 0)
2268 return false;
2269
2270 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2271 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2272 /** @todo This check is actually wrong, it doesn't take the direction of the
2273 * stack segment into account. But, it does the job for now. */
2274 if (pCtx->rsp >= pCtx->ssHid.u32Limit)
2275 return false;
2276#if 0
2277 if ( pCtx->cs >= pCtx->gdtr.cbGdt
2278 || pCtx->ss >= pCtx->gdtr.cbGdt
2279 || pCtx->ds >= pCtx->gdtr.cbGdt
2280 || pCtx->es >= pCtx->gdtr.cbGdt
2281 || pCtx->fs >= pCtx->gdtr.cbGdt
2282 || pCtx->gs >= pCtx->gdtr.cbGdt)
2283 return false;
2284#endif
2285 }
2286 }
2287
2288 if (pVM->hwaccm.s.vmx.fEnabled)
2289 {
2290 uint32_t mask;
2291
2292 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2293 {
2294 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2295 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2296 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2297 mask &= ~X86_CR0_NE;
2298
2299#ifdef HWACCM_VMX_EMULATE_REALMODE
2300 if (fVMMDeviceHeapEnabled)
2301 {
2302 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2303 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2304 }
2305 else
2306#endif
2307 {
2308 /* We support protected mode without paging using identity mapping. */
2309 mask &= ~X86_CR0_PG;
2310 }
2311 if ((pCtx->cr0 & mask) != mask)
2312 return false;
2313
2314 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2315 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2316 if ((pCtx->cr0 & mask) != 0)
2317 return false;
2318 }
2319
2320 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2321 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2322 mask &= ~X86_CR4_VMXE;
2323 if ((pCtx->cr4 & mask) != mask)
2324 return false;
2325
2326 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2327 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2328 if ((pCtx->cr4 & mask) != 0)
2329 return false;
2330
2331 pVCpu->hwaccm.s.fActive = true;
2332 return true;
2333 }
2334
2335 return false;
2336}
2337
2338/**
2339 * Checks if we need to reschedule due to VMM device heap changes
2340 *
2341 * @returns boolean
2342 * @param pVM The VM to operate on.
2343 * @param pCtx VM execution context
2344 */
2345VMMR3DECL(bool) HWACCMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2346{
2347 /** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. (VT-x only) */
2348 if ( pVM->hwaccm.s.vmx.fEnabled
2349 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2350 && !PDMVMMDevHeapIsEnabled(pVM)
2351 && (pVM->hwaccm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2352 return true;
2353
2354 return false;
2355}
2356
2357
2358/**
2359 * Notifcation from EM about a rescheduling into hardware assisted execution
2360 * mode.
2361 *
2362 * @param pVCpu Pointer to the current virtual cpu structure.
2363 */
2364VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2365{
2366 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2367}
2368
2369/**
2370 * Notifcation from EM about returning from instruction emulation (REM / EM).
2371 *
2372 * @param pVCpu Pointer to the current virtual cpu structure.
2373 */
2374VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2375{
2376 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2377}
2378
2379/**
2380 * Checks if we are currently using hardware accelerated raw mode.
2381 *
2382 * @returns boolean
2383 * @param pVCpu The VMCPU to operate on.
2384 */
2385VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2386{
2387 return pVCpu->hwaccm.s.fActive;
2388}
2389
2390/**
2391 * Checks if we are currently using nested paging.
2392 *
2393 * @returns boolean
2394 * @param pVM The VM to operate on.
2395 */
2396VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2397{
2398 return pVM->hwaccm.s.fNestedPaging;
2399}
2400
2401/**
2402 * Checks if we are currently using VPID in VT-x mode.
2403 *
2404 * @returns boolean
2405 * @param pVM The VM to operate on.
2406 */
2407VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2408{
2409 return pVM->hwaccm.s.vmx.fVPID;
2410}
2411
2412
2413/**
2414 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2415 *
2416 * @returns boolean
2417 * @param pVM The VM to operate on.
2418 */
2419VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2420{
2421 return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2422}
2423
2424/**
2425 * Restart an I/O instruction that was refused in ring-0
2426 *
2427 * @returns Strict VBox status code. Informational status codes other than the one documented
2428 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2429 * @retval VINF_SUCCESS Success.
2430 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2431 * status code must be passed on to EM.
2432 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2433 *
2434 * @param pVM The VM to operate on.
2435 * @param pVCpu The VMCPU to operate on.
2436 * @param pCtx VCPU register context
2437 */
2438VMMR3DECL(VBOXSTRICTRC) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2439{
2440 HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2441
2442 pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2443
2444 if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2445 || enmType == HWACCMPENDINGIO_INVALID)
2446 return VERR_NOT_FOUND;
2447
2448 VBOXSTRICTRC rcStrict;
2449 switch (enmType)
2450 {
2451 case HWACCMPENDINGIO_PORT_READ:
2452 {
2453 uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2454 uint32_t u32Val = 0;
2455
2456 rcStrict = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2457 &u32Val,
2458 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2459 if (IOM_SUCCESS(rcStrict))
2460 {
2461 /* Write back to the EAX register. */
2462 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2463 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2464 }
2465 break;
2466 }
2467
2468 case HWACCMPENDINGIO_PORT_WRITE:
2469 rcStrict = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2470 pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2471 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2472 if (IOM_SUCCESS(rcStrict))
2473 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2474 break;
2475
2476 default:
2477 AssertFailed();
2478 return VERR_INTERNAL_ERROR;
2479 }
2480
2481 return rcStrict;
2482}
2483
2484/**
2485 * Inject an NMI into a running VM (only VCPU 0!)
2486 *
2487 * @returns boolean
2488 * @param pVM The VM to operate on.
2489 */
2490VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2491{
2492 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2493 return VINF_SUCCESS;
2494}
2495
2496/**
2497 * Check fatal VT-x/AMD-V error and produce some meaningful
2498 * log release message.
2499 *
2500 * @param pVM The VM to operate on.
2501 * @param iStatusCode VBox status code
2502 */
2503VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2504{
2505 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2506 {
2507 switch(iStatusCode)
2508 {
2509 case VERR_VMX_INVALID_VMCS_FIELD:
2510 break;
2511
2512 case VERR_VMX_INVALID_VMCS_PTR:
2513 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
2514 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2515 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2516 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2517 break;
2518
2519 case VERR_VMX_UNABLE_TO_START_VM:
2520 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2521 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2522#if 0 /* @todo dump the current control fields to the release log */
2523 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2524 {
2525
2526 }
2527#endif
2528 break;
2529
2530 case VERR_VMX_UNABLE_TO_RESUME_VM:
2531 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2532 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2533 break;
2534
2535 case VERR_VMX_INVALID_VMXON_PTR:
2536 break;
2537 }
2538 }
2539}
2540
2541/**
2542 * Execute state save operation.
2543 *
2544 * @returns VBox status code.
2545 * @param pVM VM Handle.
2546 * @param pSSM SSM operation handle.
2547 */
2548static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2549{
2550 int rc;
2551
2552 Log(("hwaccmR3Save:\n"));
2553
2554 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2555 {
2556 /*
2557 * Save the basic bits - fortunately all the other things can be resynced on load.
2558 */
2559 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2560 AssertRCReturn(rc, rc);
2561 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2562 AssertRCReturn(rc, rc);
2563 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2564 AssertRCReturn(rc, rc);
2565
2566 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2567 AssertRCReturn(rc, rc);
2568 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2569 AssertRCReturn(rc, rc);
2570 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2571 AssertRCReturn(rc, rc);
2572 }
2573#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2574 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2575 AssertRCReturn(rc, rc);
2576 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2577 AssertRCReturn(rc, rc);
2578 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2579 AssertRCReturn(rc, rc);
2580
2581 /* Store all the guest patch records too. */
2582 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cPatches);
2583 AssertRCReturn(rc, rc);
2584
2585 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2586 {
2587 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2588
2589 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2590 AssertRCReturn(rc, rc);
2591
2592 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2593 AssertRCReturn(rc, rc);
2594
2595 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2596 AssertRCReturn(rc, rc);
2597
2598 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2599 AssertRCReturn(rc, rc);
2600
2601 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2602 AssertRCReturn(rc, rc);
2603
2604 AssertCompileSize(HWACCMTPRINSTR, 4);
2605 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2606 AssertRCReturn(rc, rc);
2607
2608 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2609 AssertRCReturn(rc, rc);
2610
2611 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2612 AssertRCReturn(rc, rc);
2613
2614 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2615 AssertRCReturn(rc, rc);
2616
2617 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2618 AssertRCReturn(rc, rc);
2619 }
2620#endif
2621 return VINF_SUCCESS;
2622}
2623
2624/**
2625 * Execute state load operation.
2626 *
2627 * @returns VBox status code.
2628 * @param pVM VM Handle.
2629 * @param pSSM SSM operation handle.
2630 * @param uVersion Data layout version.
2631 * @param uPass The data pass.
2632 */
2633static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2634{
2635 int rc;
2636
2637 Log(("hwaccmR3Load:\n"));
2638 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2639
2640 /*
2641 * Validate version.
2642 */
2643 if ( uVersion != HWACCM_SSM_VERSION
2644 && uVersion != HWACCM_SSM_VERSION_NO_PATCHING
2645 && uVersion != HWACCM_SSM_VERSION_2_0_X)
2646 {
2647 AssertMsgFailed(("hwaccmR3Load: Invalid version uVersion=%d!\n", uVersion));
2648 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2649 }
2650 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2651 {
2652 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2653 AssertRCReturn(rc, rc);
2654 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2655 AssertRCReturn(rc, rc);
2656 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2657 AssertRCReturn(rc, rc);
2658
2659 if (uVersion >= HWACCM_SSM_VERSION_NO_PATCHING)
2660 {
2661 uint32_t val;
2662
2663 rc = SSMR3GetU32(pSSM, &val);
2664 AssertRCReturn(rc, rc);
2665 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2666
2667 rc = SSMR3GetU32(pSSM, &val);
2668 AssertRCReturn(rc, rc);
2669 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2670
2671 rc = SSMR3GetU32(pSSM, &val);
2672 AssertRCReturn(rc, rc);
2673 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2674 }
2675 }
2676#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2677 if (uVersion > HWACCM_SSM_VERSION_NO_PATCHING)
2678 {
2679 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2680 AssertRCReturn(rc, rc);
2681 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2682 AssertRCReturn(rc, rc);
2683 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2684 AssertRCReturn(rc, rc);
2685
2686 /* Fetch all TPR patch records. */
2687 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cPatches);
2688 AssertRCReturn(rc, rc);
2689
2690 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2691 {
2692 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2693
2694 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2695 AssertRCReturn(rc, rc);
2696
2697 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2698 AssertRCReturn(rc, rc);
2699
2700 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2701 AssertRCReturn(rc, rc);
2702
2703 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2704 AssertRCReturn(rc, rc);
2705
2706 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2707 AssertRCReturn(rc, rc);
2708
2709 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2710 AssertRCReturn(rc, rc);
2711
2712 if (pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT)
2713 pVM->hwaccm.s.fTPRPatchingActive = true;
2714
2715 Assert(pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT || pVM->hwaccm.s.fTPRPatchingActive == false);
2716
2717 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2718 AssertRCReturn(rc, rc);
2719
2720 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2721 AssertRCReturn(rc, rc);
2722
2723 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2724 AssertRCReturn(rc, rc);
2725
2726 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2727 AssertRCReturn(rc, rc);
2728
2729 Log(("hwaccmR3Load: patch %d\n", i));
2730 Log(("Key = %x\n", pPatch->Core.Key));
2731 Log(("cbOp = %d\n", pPatch->cbOp));
2732 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2733 Log(("type = %d\n", pPatch->enmType));
2734 Log(("srcop = %d\n", pPatch->uSrcOperand));
2735 Log(("dstop = %d\n", pPatch->uDstOperand));
2736 Log(("cFaults = %d\n", pPatch->cFaults));
2737 Log(("target = %x\n", pPatch->pJumpTarget));
2738 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2739 AssertRC(rc);
2740 }
2741 }
2742#endif
2743
2744 /* Recheck all VCPUs if we can go staight into hwaccm execution mode. */
2745 if (HWACCMIsEnabled(pVM))
2746 {
2747 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2748 {
2749 PVMCPU pVCpu = &pVM->aCpus[i];
2750
2751 HWACCMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2752 }
2753 }
2754 return VINF_SUCCESS;
2755}
2756
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette