VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 28875

Last change on this file since 28875 was 28812, checked in by vboxsync, 15 years ago

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1/* $Id: HWACCM.cpp 28812 2010-04-27 12:22:05Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HWACCM
22#include <VBox/cpum.h>
23#include <VBox/stam.h>
24#include <VBox/mm.h>
25#include <VBox/pdmapi.h>
26#include <VBox/pgm.h>
27#include <VBox/ssm.h>
28#include <VBox/trpm.h>
29#include <VBox/dbgf.h>
30#include <VBox/iom.h>
31#include <VBox/patm.h>
32#include <VBox/csam.h>
33#include <VBox/selm.h>
34#include <VBox/rem.h>
35#include <VBox/hwacc_vmx.h>
36#include <VBox/hwacc_svm.h>
37#include "HWACCMInternal.h"
38#include <VBox/vm.h>
39#include <VBox/err.h>
40#include <VBox/param.h>
41
42#include <iprt/assert.h>
43#include <VBox/log.h>
44#include <iprt/asm.h>
45#include <iprt/string.h>
46#include <iprt/env.h>
47#include <iprt/thread.h>
48
49/*******************************************************************************
50* Global Variables *
51*******************************************************************************/
52#ifdef VBOX_WITH_STATISTICS
53# define EXIT_REASON(def, val, str) #def " - " #val " - " str
54# define EXIT_REASON_NIL() NULL
55/** Exit reason descriptions for VT-x, used to describe statistics. */
56static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
57{
58 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
59 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
60 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
61 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
62 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
63 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
64 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
65 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
66 EXIT_REASON_NIL(),
67 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
68 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
69 EXIT_REASON_NIL(),
70 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
71 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
72 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
73 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
74 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
75 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
76 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
77 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
78 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
79 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
80 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
81 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
82 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
83 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
84 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
85 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
86 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
87 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
88 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
89 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
90 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
91 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
92 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
93 EXIT_REASON_NIL(),
94 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
95 EXIT_REASON_NIL(),
96 EXIT_REASON_NIL(),
97 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
98 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
99 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
100 EXIT_REASON_NIL(),
101 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
102 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
103 EXIT_REASON_NIL(),
104 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
105 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
106 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
107 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
108 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
109 EXIT_REASON_NIL(),
110 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
111 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
112 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
113 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
114 EXIT_REASON_NIL()
115};
116/** Exit reason descriptions for AMD-V, used to describe statistics. */
117static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
118{
119 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
120 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
121 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
122 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
123 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
124 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
125 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
126 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
127 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
128 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
129 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
130 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
131 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
132 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
133 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
134 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
135 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
136 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
137 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
151 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
152 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
153 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
154 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
155 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
156 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
157 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
158 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
159 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
160 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
161 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
162 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
163 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
164 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
165 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
166 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
167 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
168 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
169 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
183 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
184 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
185 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_INTR , 96, "Physical maskable interrupt."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_NMI , 97, "Physical non-maskable interrupt."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_SMI , 98, "System management interrupt."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_INIT , 99, "Physical INIT signal."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_VINTR ,100, "Visual interrupt."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_IDTR_READ ,102, "Read IDTR"),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_GDTR_READ ,103, "Read GDTR"),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_LDTR_READ ,104, "Read LDTR."),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,105, "Read TR."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,106, "Write IDTR."),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,107, "Write GDTR."),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,108, "Write LDTR."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,109, "Write TR."),
229 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
230 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
231 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
232 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
233 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
234 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
235 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
236 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
237 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
238 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
239 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
240 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
241 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
242 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
243 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
244 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
245 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
246 EXIT_REASON(SVM_EXIT_TASK_SHUTDOWN ,127, "Shutdown."),
247 EXIT_REASON(SVM_EXIT_TASK_VMRUN ,128, "VMRUN instruction."),
248 EXIT_REASON(SVM_EXIT_TASK_VMCALL ,129, "VMCALL instruction."),
249 EXIT_REASON(SVM_EXIT_TASK_VMLOAD ,130, "VMLOAD instruction."),
250 EXIT_REASON(SVM_EXIT_TASK_VMSAVE ,131, "VMSAVE instruction."),
251 EXIT_REASON(SVM_EXIT_TASK_STGI ,132, "STGI instruction."),
252 EXIT_REASON(SVM_EXIT_TASK_CLGI ,133, "CLGI instruction."),
253 EXIT_REASON(SVM_EXIT_TASK_SKINIT ,134, "SKINIT instruction."),
254 EXIT_REASON(SVM_EXIT_TASK_RDTSCP ,135, "RDTSCP instruction."),
255 EXIT_REASON(SVM_EXIT_TASK_ICEBP ,136, "ICEBP instruction."),
256 EXIT_REASON(SVM_EXIT_TASK_WBINVD ,137, "WBINVD instruction."),
257 EXIT_REASON(SVM_EXIT_TASK_MONITOR ,138, "MONITOR instruction."),
258 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
259 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
260 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
261 EXIT_REASON_NIL()
262};
263# undef EXIT_REASON
264# undef EXIT_REASON_NIL
265#endif /* VBOX_WITH_STATISTICS */
266
267/*******************************************************************************
268* Internal Functions *
269*******************************************************************************/
270static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
271static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
272
273
274/**
275 * Initializes the HWACCM.
276 *
277 * @returns VBox status code.
278 * @param pVM The VM to operate on.
279 */
280VMMR3DECL(int) HWACCMR3Init(PVM pVM)
281{
282 LogFlow(("HWACCMR3Init\n"));
283
284 /*
285 * Assert alignment and sizes.
286 */
287 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
288 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
289
290 /* Some structure checks. */
291 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
292 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
293 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
294 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
295
296 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
300 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64GPAT) == 0x668, ("guest.u64GPAT offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64GPAT)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
303 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
304
305
306 /*
307 * Register the saved state data unit.
308 */
309 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
310 NULL, NULL, NULL,
311 NULL, hwaccmR3Save, NULL,
312 NULL, hwaccmR3Load, NULL);
313 if (RT_FAILURE(rc))
314 return rc;
315
316 /* Misc initialisation. */
317 pVM->hwaccm.s.vmx.fSupported = false;
318 pVM->hwaccm.s.svm.fSupported = false;
319 pVM->hwaccm.s.vmx.fEnabled = false;
320 pVM->hwaccm.s.svm.fEnabled = false;
321
322 pVM->hwaccm.s.fNestedPaging = false;
323 pVM->hwaccm.s.fLargePages = false;
324
325 /* Disabled by default. */
326 pVM->fHWACCMEnabled = false;
327
328 /*
329 * Check CFGM options.
330 */
331 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
332 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
333 /* Nested paging: disabled by default. */
334 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
335 AssertRC(rc);
336
337 /* Large pages: disabled by default. */
338 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hwaccm.s.fLargePages, false);
339 AssertRC(rc);
340
341 /* VT-x VPID: disabled by default. */
342 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
343 AssertRC(rc);
344
345 /* HWACCM support must be explicitely enabled in the configuration file. */
346 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
347 AssertRC(rc);
348
349 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
350 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hwaccm.s.fTRPPatchingAllowed, false);
351 AssertRC(rc);
352
353#ifdef RT_OS_DARWIN
354 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
355#else
356 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
357#endif
358 {
359 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
360 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
361 return VERR_HWACCM_CONFIG_MISMATCH;
362 }
363
364 if (VMMIsHwVirtExtForced(pVM))
365 pVM->fHWACCMEnabled = true;
366
367#if HC_ARCH_BITS == 32
368 /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
369 * (To use the default, don't set 64bitEnabled in CFGM.) */
370 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
371 AssertLogRelRCReturn(rc, rc);
372 if (pVM->hwaccm.s.fAllow64BitGuests)
373 {
374# ifdef RT_OS_DARWIN
375 if (!VMMIsHwVirtExtForced(pVM))
376# else
377 if (!pVM->hwaccm.s.fAllowed)
378# endif
379 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
380 }
381#else
382 /* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
383 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
384 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
385 AssertLogRelRCReturn(rc, rc);
386#endif
387
388
389 /** Determine the init method for AMD-V and VT-x; either one global init for each host CPU
390 * or local init each time we wish to execute guest code.
391 *
392 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
393 */
394 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hwaccm.s.fGlobalInit,
395#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
396 false
397#else
398 true
399#endif
400 );
401
402 /* Max number of resume loops. */
403 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
404 AssertRC(rc);
405
406 return VINF_SUCCESS;
407}
408
409/**
410 * Initializes the per-VCPU HWACCM.
411 *
412 * @returns VBox status code.
413 * @param pVM The VM to operate on.
414 */
415VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
416{
417 LogFlow(("HWACCMR3InitCPU\n"));
418
419 for (VMCPUID i = 0; i < pVM->cCpus; i++)
420 {
421 PVMCPU pVCpu = &pVM->aCpus[i];
422
423 pVCpu->hwaccm.s.fActive = false;
424 }
425
426#ifdef VBOX_WITH_STATISTICS
427 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
428 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
429 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
430 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
431
432 /*
433 * Statistics.
434 */
435 for (VMCPUID i = 0; i < pVM->cCpus; i++)
436 {
437 PVMCPU pVCpu = &pVM->aCpus[i];
438 int rc;
439
440 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of RTMpPokeCpu",
441 "/PROF/HWACCM/CPU%d/Poke", i);
442 AssertRC(rc);
443 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait",
444 "/PROF/HWACCM/CPU%d/PokeWait", i);
445 AssertRC(rc);
446 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait when RTMpPokeCpu fails",
447 "/PROF/HWACCM/CPU%d/PokeWaitFailed", i);
448 AssertRC(rc);
449 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
450 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
451 AssertRC(rc);
452 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
453 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
454 AssertRC(rc);
455 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
456 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
457 AssertRC(rc);
458# if 1 /* temporary for tracking down darwin holdup. */
459 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
460 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
461 AssertRC(rc);
462 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
463 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
464 AssertRC(rc);
465 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
466 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
467 AssertRC(rc);
468# endif
469 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
470 "/PROF/HWACCM/CPU%d/InGC", i);
471 AssertRC(rc);
472
473# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
474 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
475 "/PROF/HWACCM/CPU%d/Switcher3264", i);
476 AssertRC(rc);
477# endif
478
479# define HWACCM_REG_COUNTER(a, b) \
480 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
481 AssertRC(rc);
482
483 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
484 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
485 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
486 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
487 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
488 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
489 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
490 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
491 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
492 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
493 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
494 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
495 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
496 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
498 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
499 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMonitor, "/HWACCM/CPU%d/Exit/Instr/Monitor");
503 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
504 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
505 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
506 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
507 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
508 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
509 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
510 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
511 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
512 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
513 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
514 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
515 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
516 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
517 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
518 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
519 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
520 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
521
522 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
523 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
524
525 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
526 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
527 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
528
529 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPage, "/HWACCM/CPU%d/Flush/Page");
530 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
531 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
532 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLB, "/HWACCM/CPU%d/Flush/TLB");
533 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
534 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
535 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
536 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
537 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
538 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
539 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
540 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
541 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
542
543 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
544 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
545 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow, "/HWACCM/CPU%d/TSC/InterceptOverflow");
546
547 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
548 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
549 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
550
551 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
552 {
553 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
554 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
555 AssertRC(rc);
556 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
557 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
558 AssertRC(rc);
559 }
560
561#undef HWACCM_REG_COUNTER
562
563 pVCpu->hwaccm.s.paStatExitReason = NULL;
564
565 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
566 AssertRC(rc);
567 if (RT_SUCCESS(rc))
568 {
569 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
570 for (int j=0;j<MAX_EXITREASON_STAT;j++)
571 {
572 if (papszDesc[j])
573 {
574 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
575 papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
576 AssertRC(rc);
577 }
578 }
579 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
580 AssertRC(rc);
581 }
582 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
583# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
584 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
585# else
586 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
587# endif
588
589 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
590 AssertRCReturn(rc, rc);
591 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
592# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
593 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
594# else
595 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
596# endif
597 for (unsigned j = 0; j < 255; j++)
598 STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
599 (j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
600
601 }
602#endif /* VBOX_WITH_STATISTICS */
603
604#ifdef VBOX_WITH_CRASHDUMP_MAGIC
605 /* Magic marker for searching in crash dumps. */
606 for (VMCPUID i = 0; i < pVM->cCpus; i++)
607 {
608 PVMCPU pVCpu = &pVM->aCpus[i];
609
610 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
611 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
612 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
613 }
614#endif
615 return VINF_SUCCESS;
616}
617
618/**
619 * Turns off normal raw mode features
620 *
621 * @param pVM The VM to operate on.
622 */
623static void hwaccmR3DisableRawMode(PVM pVM)
624{
625 /* Disable PATM & CSAM. */
626 PATMR3AllowPatching(pVM, false);
627 CSAMDisableScanning(pVM);
628
629 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
630 SELMR3DisableMonitoring(pVM);
631 TRPMR3DisableMonitoring(pVM);
632
633 /* Disable the switcher code (safety precaution). */
634 VMMR3DisableSwitcher(pVM);
635
636 /* Disable mapping of the hypervisor into the shadow page table. */
637 PGMR3MappingsDisable(pVM);
638
639 /* Disable the switcher */
640 VMMR3DisableSwitcher(pVM);
641
642 /* Reinit the paging mode to force the new shadow mode. */
643 for (VMCPUID i = 0; i < pVM->cCpus; i++)
644 {
645 PVMCPU pVCpu = &pVM->aCpus[i];
646
647 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
648 }
649}
650
651/**
652 * Initialize VT-x or AMD-V.
653 *
654 * @returns VBox status code.
655 * @param pVM The VM handle.
656 */
657VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
658{
659 int rc;
660
661 /* Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
662 * is already using AMD-V.
663 */
664 if ( !pVM->hwaccm.s.vmx.fSupported
665 && !pVM->hwaccm.s.svm.fSupported
666 && pVM->hwaccm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
667 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
668 {
669 LogRel(("HWACCM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
670 pVM->hwaccm.s.svm.fSupported = true;
671 pVM->hwaccm.s.svm.fIgnoreInUseError = true;
672 }
673 else
674 if ( !pVM->hwaccm.s.vmx.fSupported
675 && !pVM->hwaccm.s.svm.fSupported)
676 {
677 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
678 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
679
680 if (VMMIsHwVirtExtForced(pVM))
681 {
682 switch (pVM->hwaccm.s.lLastError)
683 {
684 case VERR_VMX_NO_VMX:
685 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
686 case VERR_VMX_IN_VMX_ROOT_MODE:
687 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
688 case VERR_SVM_IN_USE:
689 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
690 case VERR_SVM_NO_SVM:
691 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
692 case VERR_SVM_DISABLED:
693 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
694 default:
695 return pVM->hwaccm.s.lLastError;
696 }
697 }
698 return VINF_SUCCESS;
699 }
700
701 if (pVM->hwaccm.s.vmx.fSupported)
702 {
703 rc = SUPR3QueryVTxSupported();
704 if (RT_FAILURE(rc))
705 {
706#ifdef RT_OS_LINUX
707 LogRel(("HWACCM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
708#else
709 LogRel(("HWACCM: The host kernel does not support VT-x!\n"));
710#endif
711 if ( pVM->cCpus > 1
712 || VMMIsHwVirtExtForced(pVM))
713 return rc;
714
715 /* silently fall back to raw mode */
716 return VINF_SUCCESS;
717 }
718 }
719
720 if (!pVM->hwaccm.s.fAllowed)
721 return VINF_SUCCESS; /* nothing to do */
722
723 /* Enable VT-x or AMD-V on all host CPUs. */
724 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
725 if (RT_FAILURE(rc))
726 {
727 LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
728 return rc;
729 }
730 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
731
732 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
733 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
734 if (!pVM->hwaccm.s.fHasIoApic)
735 {
736 Assert(!pVM->hwaccm.s.fTRPPatchingAllowed); /* paranoia */
737 pVM->hwaccm.s.fTRPPatchingAllowed = false;
738 }
739
740 if (pVM->hwaccm.s.vmx.fSupported)
741 {
742 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
743
744 if ( pVM->hwaccm.s.fInitialized == false
745 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
746 {
747 uint64_t val;
748 RTGCPHYS GCPhys = 0;
749
750 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
751 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
752 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
753 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
754 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
755 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
756 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
757 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
758
759 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
760 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
761 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
762 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
763 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
764 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
765 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
766 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
767 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
768 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
769 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
770 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
771 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
772 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
773 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
774 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
775 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
776 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
777 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
778
779 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
780 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
781 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
782 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
783 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
784 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
785 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
786 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
787 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
788 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
789 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
790 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
791 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
792 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
793 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
794 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
795 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
796 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
797 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
798 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
799 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
800 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
801 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
802 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
803 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
804 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
805 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
806 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
807 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
808 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
809 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
810 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
811 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
812 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
813 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
814 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
815 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
816 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
817 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
818 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
819 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
820 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
821 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
822 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
823
824 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
825 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
826 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
827 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
828 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
829 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
830 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
831 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
832 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
833 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
834 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
835 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
836 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
837 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
838 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
839 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
840 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
841 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
842 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
843 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
844 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
845 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
846 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
847 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
848 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
849 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
850 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
851 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
852 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
853 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
854 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
855 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
856 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
857 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
858 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
859 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
860 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
861 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
862 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
863 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
864 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
865 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
866 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
867
868 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
869 {
870 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
871 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
872 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
873 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
874 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
875 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
876 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
877 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
878 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
879 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT\n"));
880 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
881 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
882 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
883 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
884 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
885 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
886 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
887 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE\n"));
888 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
889 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT\n"));
890
891 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
892 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
893 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
894 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
895 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
896 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
897 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT *must* be set\n"));
898 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
899 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
900 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
901 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
902 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
903 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
904 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
905 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
906 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
907 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE *must* be set\n"));
908 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
909 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT *must* be set\n"));
910 }
911
912 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
913 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
914 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
915 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
916 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
917 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
918 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
919 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
920 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
921 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
922 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
923 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
924 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
925 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
926 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
927 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
928 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
929 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
930 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
931 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
932 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
933 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
934 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
935 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
936 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
937 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
938 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
939 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
940 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
941 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
942 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
943
944 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
945 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
946 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
947 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
948 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
949 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
950 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
951 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
952 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
953 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
954 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
955 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
956 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
957 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
958 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
959 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
960 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
961 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
962 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
963 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
964 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
965 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
966 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
967 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
968 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
969 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
970 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
971 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
972 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
973 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
974 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
975 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
976 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
977 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
978 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
979
980 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
981 {
982 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
983
984 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
985 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
986 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
987 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
988 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
989 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
990 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
991 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
992 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
993 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
994 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
995 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
996 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
997 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
998 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
999 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
1000 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
1001 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
1002 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
1003 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
1004 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
1005 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
1006 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
1007 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
1008 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
1009 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
1010 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
1011 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
1012 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
1013 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
1014 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
1015 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
1016 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
1017 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
1018 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
1019 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
1020 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
1021 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
1022 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
1023 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
1024 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
1025 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
1026 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
1027 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
1028 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
1029 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
1030 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
1031 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
1032 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
1033 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
1034 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
1035 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
1036 }
1037
1038 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
1039 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1040 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1041 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1042 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1043 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1044
1045 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
1046 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
1047 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
1048 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
1049 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
1050
1051 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
1052
1053 /* Paranoia */
1054 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc) >= 512);
1055
1056 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1057 {
1058 LogRel(("HWACCM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pMSRBitmapPhys));
1059 LogRel(("HWACCM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1060 }
1061
1062#ifdef HWACCM_VTX_WITH_EPT
1063 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1064 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1065#endif /* HWACCM_VTX_WITH_EPT */
1066#ifdef HWACCM_VTX_WITH_VPID
1067 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1068 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
1069 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
1070#endif /* HWACCM_VTX_WITH_VPID */
1071
1072 /* Unrestricted guest execution relies on EPT. */
1073 if ( pVM->hwaccm.s.fNestedPaging
1074 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE))
1075 {
1076 pVM->hwaccm.s.vmx.fUnrestrictedGuest = true;
1077 }
1078
1079 /* Only try once. */
1080 pVM->hwaccm.s.fInitialized = true;
1081
1082 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1083 {
1084 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1085 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
1086 if (RT_SUCCESS(rc))
1087 {
1088 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1089 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
1090 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
1091 /* Bit set to 0 means redirection enabled. */
1092 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
1093 /* Allow all port IO, so the VT-x IO intercepts do their job. */
1094 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
1095 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
1096
1097 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1098 * real and protected mode without paging with EPT.
1099 */
1100 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1101 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
1102 {
1103 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1104 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
1105 }
1106
1107 /* We convert it here every time as pci regions could be reconfigured. */
1108 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1109 AssertRC(rc);
1110 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1111
1112 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1113 AssertRC(rc);
1114 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1115 }
1116 else
1117 {
1118 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1119 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1120 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1121 }
1122 }
1123
1124 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1125 AssertRC(rc);
1126 if (rc == VINF_SUCCESS)
1127 {
1128 pVM->fHWACCMEnabled = true;
1129 pVM->hwaccm.s.vmx.fEnabled = true;
1130 hwaccmR3DisableRawMode(pVM);
1131
1132 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1133#ifdef VBOX_ENABLE_64_BITS_GUESTS
1134 if (pVM->hwaccm.s.fAllow64BitGuests)
1135 {
1136 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1137 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1138 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1139 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1140 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1141 }
1142 else
1143 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1144 /* Todo: this needs to be fixed properly!! */
1145 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1146 && (pVM->hwaccm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1147 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1148
1149 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1150 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1151 : "HWACCM: 32-bit guests supported.\n"));
1152#else
1153 LogRel(("HWACCM: 32-bit guests supported.\n"));
1154#endif
1155 LogRel(("HWACCM: VMX enabled!\n"));
1156 if (pVM->hwaccm.s.fNestedPaging)
1157 {
1158 LogRel(("HWACCM: Enabled nested paging\n"));
1159 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1160 if (pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1161 LogRel(("HWACCM: Unrestricted guest execution enabled!\n"));
1162
1163#if HC_ARCH_BITS == 64
1164 if (pVM->hwaccm.s.fLargePages)
1165 {
1166 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1167 PGMSetLargePageUsage(pVM, true);
1168 LogRel(("HWACCM: Large page support enabled!\n"));
1169 }
1170#endif
1171 }
1172 else
1173 Assert(!pVM->hwaccm.s.vmx.fUnrestrictedGuest);
1174
1175 if (pVM->hwaccm.s.vmx.fVPID)
1176 LogRel(("HWACCM: Enabled VPID\n"));
1177
1178 if ( pVM->hwaccm.s.fNestedPaging
1179 || pVM->hwaccm.s.vmx.fVPID)
1180 {
1181 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1182 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1183 }
1184
1185 /* TPR patching status logging. */
1186 if (pVM->hwaccm.s.fTRPPatchingAllowed)
1187 {
1188 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1189 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1190 {
1191 pVM->hwaccm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1192 LogRel(("HWACCM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1193 }
1194 else
1195 {
1196 uint32_t u32Eax, u32Dummy;
1197
1198 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1199 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1200 if ( u32Eax < 0x80000001
1201 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1202 {
1203 pVM->hwaccm.s.fTRPPatchingAllowed = false;
1204 LogRel(("HWACCM: TPR patching disabled (long mode not supported).\n"));
1205 }
1206 }
1207 }
1208 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1209 }
1210 else
1211 {
1212 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1213 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1214 pVM->fHWACCMEnabled = false;
1215 }
1216 }
1217 }
1218 else
1219 if (pVM->hwaccm.s.svm.fSupported)
1220 {
1221 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1222
1223 if (pVM->hwaccm.s.fInitialized == false)
1224 {
1225 /* Erratum 170 which requires a forced TLB flush for each world switch:
1226 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1227 *
1228 * All BH-G1/2 and DH-G1/2 models include a fix:
1229 * Athlon X2: 0x6b 1/2
1230 * 0x68 1/2
1231 * Athlon 64: 0x7f 1
1232 * 0x6f 2
1233 * Sempron: 0x7f 1/2
1234 * 0x6f 2
1235 * 0x6c 2
1236 * 0x7c 2
1237 * Turion 64: 0x68 2
1238 *
1239 */
1240 uint32_t u32Dummy;
1241 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1242 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1243 u32BaseFamily= (u32Version >> 8) & 0xf;
1244 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1245 u32Model = ((u32Version >> 4) & 0xf);
1246 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1247 u32Stepping = u32Version & 0xf;
1248 if ( u32Family == 0xf
1249 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1250 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1251 {
1252 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1253 }
1254
1255 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1256 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1257 LogRel(("HWACCM: AMD HWCR MSR = %RX64\n", pVM->hwaccm.s.svm.msrHWCR));
1258 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1259 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1260 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1261
1262 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1263 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
1264 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
1265 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
1266 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
1267 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
1268 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
1269 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
1270 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
1271 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
1272 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER)
1273 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER\n"));
1274
1275 /* Only try once. */
1276 pVM->hwaccm.s.fInitialized = true;
1277
1278 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1279 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1280
1281 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1282 AssertRC(rc);
1283 if (rc == VINF_SUCCESS)
1284 {
1285 pVM->fHWACCMEnabled = true;
1286 pVM->hwaccm.s.svm.fEnabled = true;
1287
1288 if (pVM->hwaccm.s.fNestedPaging)
1289 {
1290 LogRel(("HWACCM: Enabled nested paging\n"));
1291#if HC_ARCH_BITS == 64
1292 if (pVM->hwaccm.s.fLargePages)
1293 {
1294 /* Use large (2 MB) pages for our nested paging PDEs where possible. */
1295 PGMSetLargePageUsage(pVM, true);
1296 LogRel(("HWACCM: Large page support enabled!\n"));
1297 }
1298#endif
1299 }
1300
1301 hwaccmR3DisableRawMode(pVM);
1302 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1303 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1304 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1305#ifdef VBOX_ENABLE_64_BITS_GUESTS
1306 if (pVM->hwaccm.s.fAllow64BitGuests)
1307 {
1308 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1309 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1310 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1311 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1312 }
1313 else
1314 /* Turn on NXE if PAE has been enabled. */
1315 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1316 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1317#endif
1318
1319 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1320 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1321 : "HWACCM: 32-bit guest supported.\n"));
1322
1323 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1324 }
1325 else
1326 {
1327 pVM->fHWACCMEnabled = false;
1328 }
1329 }
1330 }
1331 if (pVM->fHWACCMEnabled)
1332 LogRel(("HWACCM: VT-x/AMD-V init method: %s\n", (pVM->hwaccm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1333 return VINF_SUCCESS;
1334}
1335
1336/**
1337 * Applies relocations to data and code managed by this
1338 * component. This function will be called at init and
1339 * whenever the VMM need to relocate it self inside the GC.
1340 *
1341 * @param pVM The VM.
1342 */
1343VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1344{
1345 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1346
1347 /* Fetch the current paging mode during the relocate callback during state loading. */
1348 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1349 {
1350 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1351 {
1352 PVMCPU pVCpu = &pVM->aCpus[i];
1353
1354 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1355 Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1356 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1357 }
1358 }
1359#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1360 if (pVM->fHWACCMEnabled)
1361 {
1362 int rc;
1363
1364 switch(PGMGetHostMode(pVM))
1365 {
1366 case PGMMODE_32_BIT:
1367 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1368 break;
1369
1370 case PGMMODE_PAE:
1371 case PGMMODE_PAE_NX:
1372 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1373 break;
1374
1375 default:
1376 AssertFailed();
1377 break;
1378 }
1379 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1380 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1381
1382 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1383 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1384
1385 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1386 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1387
1388 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1389 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1390
1391# ifdef DEBUG
1392 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1393 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1394# endif
1395 }
1396#endif
1397 return;
1398}
1399
1400/**
1401 * Checks hardware accelerated raw mode is allowed.
1402 *
1403 * @returns boolean
1404 * @param pVM The VM to operate on.
1405 */
1406VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1407{
1408 return pVM->hwaccm.s.fAllowed;
1409}
1410
1411/**
1412 * Notification callback which is called whenever there is a chance that a CR3
1413 * value might have changed.
1414 *
1415 * This is called by PGM.
1416 *
1417 * @param pVM The VM to operate on.
1418 * @param pVCpu The VMCPU to operate on.
1419 * @param enmShadowMode New shadow paging mode.
1420 * @param enmGuestMode New guest paging mode.
1421 */
1422VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1423{
1424 /* Ignore page mode changes during state loading. */
1425 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1426 return;
1427
1428 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1429
1430 if ( pVM->hwaccm.s.vmx.fEnabled
1431 && pVM->fHWACCMEnabled)
1432 {
1433 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1434 && enmGuestMode >= PGMMODE_PROTECTED)
1435 {
1436 PCPUMCTX pCtx;
1437
1438 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1439
1440 /* After a real mode switch to protected mode we must force
1441 * CPL to 0. Our real mode emulation had to set it to 3.
1442 */
1443 pCtx->ssHid.Attr.n.u2Dpl = 0;
1444 }
1445 }
1446
1447 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1448 {
1449 /* Keep track of paging mode changes. */
1450 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1451 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1452
1453 /* Did we miss a change, because all code was executed in the recompiler? */
1454 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1455 {
1456 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1457 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1458 }
1459 }
1460
1461 /* Reset the contents of the read cache. */
1462 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1463 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1464 pCache->Read.aFieldVal[j] = 0;
1465}
1466
1467/**
1468 * Terminates the HWACCM.
1469 *
1470 * Termination means cleaning up and freeing all resources,
1471 * the VM it self is at this point powered off or suspended.
1472 *
1473 * @returns VBox status code.
1474 * @param pVM The VM to operate on.
1475 */
1476VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1477{
1478 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1479 {
1480 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1481 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1482 }
1483 HWACCMR3TermCPU(pVM);
1484 return 0;
1485}
1486
1487/**
1488 * Terminates the per-VCPU HWACCM.
1489 *
1490 * Termination means cleaning up and freeing all resources,
1491 * the VM it self is at this point powered off or suspended.
1492 *
1493 * @returns VBox status code.
1494 * @param pVM The VM to operate on.
1495 */
1496VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1497{
1498 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1499 {
1500 PVMCPU pVCpu = &pVM->aCpus[i];
1501
1502#ifdef VBOX_WITH_STATISTICS
1503 if (pVCpu->hwaccm.s.paStatExitReason)
1504 {
1505 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1506 pVCpu->hwaccm.s.paStatExitReason = NULL;
1507 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1508 }
1509 if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1510 {
1511 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1512 pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1513 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1514 }
1515#endif
1516
1517#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1518 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1519 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1520 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1521#endif
1522 }
1523 return 0;
1524}
1525
1526/**
1527 * Resets a virtual CPU.
1528 *
1529 * Used by HWACCMR3Reset and CPU hot plugging.
1530 *
1531 * @param pVCpu The CPU to reset.
1532 */
1533VMMR3DECL(void) HWACCMR3ResetCpu(PVMCPU pVCpu)
1534{
1535 /* On first entry we'll sync everything. */
1536 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1537
1538 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1539 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1540
1541 pVCpu->hwaccm.s.fActive = false;
1542 pVCpu->hwaccm.s.Event.fPending = false;
1543
1544 /* Reset state information for real-mode emulation in VT-x. */
1545 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1546 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1547 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1548
1549 /* Reset the contents of the read cache. */
1550 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1551 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1552 pCache->Read.aFieldVal[j] = 0;
1553
1554#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1555 /* Magic marker for searching in crash dumps. */
1556 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1557 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1558#endif
1559}
1560
1561/**
1562 * The VM is being reset.
1563 *
1564 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1565 * needs to be removed.
1566 *
1567 * @param pVM VM handle.
1568 */
1569VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1570{
1571 LogFlow(("HWACCMR3Reset:\n"));
1572
1573 if (pVM->fHWACCMEnabled)
1574 hwaccmR3DisableRawMode(pVM);
1575
1576 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1577 {
1578 PVMCPU pVCpu = &pVM->aCpus[i];
1579
1580 HWACCMR3ResetCpu(pVCpu);
1581 }
1582
1583 /* Clear all patch information. */
1584 pVM->hwaccm.s.pGuestPatchMem = 0;
1585 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1586 pVM->hwaccm.s.cbGuestPatchMem = 0;
1587 pVM->hwaccm.s.cPatches = 0;
1588 pVM->hwaccm.s.PatchTree = 0;
1589 pVM->hwaccm.s.fTPRPatchingActive = false;
1590 ASMMemZero32(pVM->hwaccm.s.aPatches, sizeof(pVM->hwaccm.s.aPatches));
1591}
1592
1593/**
1594 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1595 *
1596 * @returns VBox strict status code.
1597 * @param pVM The VM handle.
1598 * @param pVCpu The VMCPU for the EMT we're being called on.
1599 * @param pvUser Unused
1600 *
1601 */
1602DECLCALLBACK(VBOXSTRICTRC) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1603{
1604 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1605
1606 /* Only execute the handler on the VCPU the original patch request was issued. */
1607 if (pVCpu->idCpu != idCpu)
1608 return VINF_SUCCESS;
1609
1610 Log(("hwaccmR3RemovePatches\n"));
1611 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
1612 {
1613 uint8_t szInstr[15];
1614 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
1615 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1616 int rc;
1617
1618#ifdef LOG_ENABLED
1619 char szOutput[256];
1620
1621 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1622 if (RT_SUCCESS(rc))
1623 Log(("Patched instr: %s\n", szOutput));
1624#endif
1625
1626 /* Check if the instruction is still the same. */
1627 rc = PGMPhysSimpleReadGCPtr(pVCpu, szInstr, pInstrGC, pPatch->cbNewOp);
1628 if (rc != VINF_SUCCESS)
1629 {
1630 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1631 continue; /* swapped out or otherwise removed; skip it. */
1632 }
1633
1634 if (memcmp(szInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1635 {
1636 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1637 continue; /* skip it. */
1638 }
1639
1640 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1641 AssertRC(rc);
1642
1643#ifdef LOG_ENABLED
1644 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1645 if (RT_SUCCESS(rc))
1646 Log(("Original instr: %s\n", szOutput));
1647#endif
1648 }
1649 pVM->hwaccm.s.cPatches = 0;
1650 pVM->hwaccm.s.PatchTree = 0;
1651 pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1652 pVM->hwaccm.s.fTPRPatchingActive = false;
1653 return VINF_SUCCESS;
1654}
1655
1656/**
1657 * Enable patching in a VT-x/AMD-V guest
1658 *
1659 * @returns VBox status code.
1660 * @param pVM The VM to operate on.
1661 * @param idCpu VCPU to execute hwaccmR3RemovePatches on
1662 * @param pPatchMem Patch memory range
1663 * @param cbPatchMem Size of the memory range
1664 */
1665int hwaccmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1666{
1667 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)idCpu);
1668 AssertRC(rc);
1669
1670 pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1671 pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1672 pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1673 return VINF_SUCCESS;
1674}
1675
1676/**
1677 * Enable patching in a VT-x/AMD-V guest
1678 *
1679 * @returns VBox status code.
1680 * @param pVM The VM to operate on.
1681 * @param pPatchMem Patch memory range
1682 * @param cbPatchMem Size of the memory range
1683 */
1684VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1685{
1686 Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1687 if (pVM->cCpus > 1)
1688 {
1689 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1690 int rc = VMR3ReqCallNoWaitU(pVM->pUVM, VMCPUID_ANY_QUEUE,
1691 (PFNRT)hwaccmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1692 AssertRC(rc);
1693 return rc;
1694 }
1695 return hwaccmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1696}
1697
1698/**
1699 * Disable patching in a VT-x/AMD-V guest
1700 *
1701 * @returns VBox status code.
1702 * @param pVM The VM to operate on.
1703 * @param pPatchMem Patch memory range
1704 * @param cbPatchMem Size of the memory range
1705 */
1706VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1707{
1708 Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1709
1710 Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1711 Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1712
1713 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1714 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)VMMGetCpuId(pVM));
1715 AssertRC(rc);
1716
1717 pVM->hwaccm.s.pGuestPatchMem = 0;
1718 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1719 pVM->hwaccm.s.cbGuestPatchMem = 0;
1720 pVM->hwaccm.s.fTPRPatchingActive = false;
1721 return VINF_SUCCESS;
1722}
1723
1724
1725/**
1726 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1727 *
1728 * @returns VBox strict status code.
1729 * @param pVM The VM handle.
1730 * @param pVCpu The VMCPU for the EMT we're being called on.
1731 * @param pvUser User specified CPU context
1732 *
1733 */
1734DECLCALLBACK(VBOXSTRICTRC) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1735{
1736 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1737 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1738 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1739 unsigned cbOp;
1740
1741 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1742 if (pVCpu->idCpu != idCpu)
1743 return VINF_SUCCESS;
1744
1745 Log(("hwaccmR3ReplaceTprInstr: %RGv\n", pCtx->rip));
1746
1747 /* Two or more VCPUs were racing to patch this instruction. */
1748 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1749 if (pPatch)
1750 return VINF_SUCCESS;
1751
1752 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1753
1754 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1755 AssertRC(rc);
1756 if ( rc == VINF_SUCCESS
1757 && pDis->pCurInstr->opcode == OP_MOV
1758 && cbOp >= 3)
1759 {
1760 uint8_t aVMMCall[3] = { 0xf, 0x1, 0xd9};
1761 uint32_t idx = pVM->hwaccm.s.cPatches;
1762
1763 pPatch = &pVM->hwaccm.s.aPatches[idx];
1764
1765 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1766 AssertRC(rc);
1767
1768 pPatch->cbOp = cbOp;
1769
1770 if (pDis->param1.flags == USE_DISPLACEMENT32)
1771 {
1772 /* write. */
1773 if (pDis->param2.flags == USE_REG_GEN32)
1774 {
1775 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1776 pPatch->uSrcOperand = pDis->param2.base.reg_gen;
1777 }
1778 else
1779 {
1780 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1781 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1782 pPatch->uSrcOperand = pDis->param2.parval;
1783 }
1784 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1785 AssertRC(rc);
1786
1787 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1788 pPatch->cbNewOp = sizeof(aVMMCall);
1789 }
1790 else
1791 {
1792 RTGCPTR oldrip = pCtx->rip;
1793 uint32_t oldcbOp = cbOp;
1794 uint32_t uMmioReg = pDis->param1.base.reg_gen;
1795
1796 /* read */
1797 Assert(pDis->param1.flags == USE_REG_GEN32);
1798
1799 /* Found:
1800 * mov eax, dword [fffe0080] (5 bytes)
1801 * Check if next instruction is:
1802 * shr eax, 4
1803 */
1804 pCtx->rip += cbOp;
1805 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1806 pCtx->rip = oldrip;
1807 if ( rc == VINF_SUCCESS
1808 && pDis->pCurInstr->opcode == OP_SHR
1809 && pDis->param1.flags == USE_REG_GEN32
1810 && pDis->param1.base.reg_gen == uMmioReg
1811 && pDis->param2.flags == USE_IMMEDIATE8
1812 && pDis->param2.parval == 4
1813 && oldcbOp + cbOp < sizeof(pVM->hwaccm.s.aPatches[idx].aOpcode))
1814 {
1815 uint8_t szInstr[15];
1816
1817 /* Replacing two instructions now. */
1818 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, oldcbOp + cbOp);
1819 AssertRC(rc);
1820
1821 pPatch->cbOp = oldcbOp + cbOp;
1822
1823 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1824 szInstr[0] = 0xF0;
1825 szInstr[1] = 0x0F;
1826 szInstr[2] = 0x20;
1827 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
1828 for (unsigned i = 4; i < pPatch->cbOp; i++)
1829 szInstr[i] = 0x90; /* nop */
1830
1831 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, pPatch->cbOp);
1832 AssertRC(rc);
1833
1834 memcpy(pPatch->aNewOpcode, szInstr, pPatch->cbOp);
1835 pPatch->cbNewOp = pPatch->cbOp;
1836
1837 Log(("Acceptable read/shr candidate!\n"));
1838 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1839 }
1840 else
1841 {
1842 pPatch->enmType = HWACCMTPRINSTR_READ;
1843 pPatch->uDstOperand = pDis->param1.base.reg_gen;
1844
1845 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1846 AssertRC(rc);
1847
1848 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1849 pPatch->cbNewOp = sizeof(aVMMCall);
1850 }
1851 }
1852
1853 pPatch->Core.Key = pCtx->eip;
1854 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1855 AssertRC(rc);
1856
1857 pVM->hwaccm.s.cPatches++;
1858 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceSuccess);
1859 return VINF_SUCCESS;
1860 }
1861
1862 /* Save invalid patch, so we will not try again. */
1863 uint32_t idx = pVM->hwaccm.s.cPatches;
1864
1865#ifdef LOG_ENABLED
1866 char szOutput[256];
1867 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1868 if (RT_SUCCESS(rc))
1869 Log(("Failed to patch instr: %s\n", szOutput));
1870#endif
1871
1872 pPatch = &pVM->hwaccm.s.aPatches[idx];
1873 pPatch->Core.Key = pCtx->eip;
1874 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1875 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1876 AssertRC(rc);
1877 pVM->hwaccm.s.cPatches++;
1878 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceFailure);
1879 return VINF_SUCCESS;
1880}
1881
1882/**
1883 * Callback to patch a TPR instruction (jump to generated code)
1884 *
1885 * @returns VBox strict status code.
1886 * @param pVM The VM handle.
1887 * @param pVCpu The VMCPU for the EMT we're being called on.
1888 * @param pvUser User specified CPU context
1889 *
1890 */
1891DECLCALLBACK(VBOXSTRICTRC) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1892{
1893 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1894 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1895 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1896 unsigned cbOp;
1897 int rc;
1898#ifdef LOG_ENABLED
1899 RTGCPTR pInstr;
1900 char szOutput[256];
1901#endif
1902
1903 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1904 if (pVCpu->idCpu != idCpu)
1905 return VINF_SUCCESS;
1906
1907 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1908
1909 /* Two or more VCPUs were racing to patch this instruction. */
1910 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1911 if (pPatch)
1912 {
1913 Log(("hwaccmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
1914 return VINF_SUCCESS;
1915 }
1916
1917 Log(("hwaccmR3PatchTprInstr %RGv\n", pCtx->rip));
1918
1919 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1920 AssertRC(rc);
1921 if ( rc == VINF_SUCCESS
1922 && pDis->pCurInstr->opcode == OP_MOV
1923 && cbOp >= 5)
1924 {
1925 uint32_t idx = pVM->hwaccm.s.cPatches;
1926 uint8_t aPatch[64];
1927 uint32_t off = 0;
1928
1929 pPatch = &pVM->hwaccm.s.aPatches[idx];
1930
1931#ifdef LOG_ENABLED
1932 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1933 if (RT_SUCCESS(rc))
1934 Log(("Original instr: %s\n", szOutput));
1935#endif
1936
1937 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1938 AssertRC(rc);
1939
1940 pPatch->cbOp = cbOp;
1941 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
1942
1943 if (pDis->param1.flags == USE_DISPLACEMENT32)
1944 {
1945 /*
1946 * TPR write:
1947 *
1948 * push ECX [51]
1949 * push EDX [52]
1950 * push EAX [50]
1951 * xor EDX,EDX [31 D2]
1952 * mov EAX,EAX [89 C0]
1953 * or
1954 * mov EAX,0000000CCh [B8 CC 00 00 00]
1955 * mov ECX,0C0000082h [B9 82 00 00 C0]
1956 * wrmsr [0F 30]
1957 * pop EAX [58]
1958 * pop EDX [5A]
1959 * pop ECX [59]
1960 * jmp return_address [E9 return_address]
1961 *
1962 */
1963 bool fUsesEax = (pDis->param2.flags == USE_REG_GEN32 && pDis->param2.base.reg_gen == USE_REG_EAX);
1964
1965 aPatch[off++] = 0x51; /* push ecx */
1966 aPatch[off++] = 0x52; /* push edx */
1967 if (!fUsesEax)
1968 aPatch[off++] = 0x50; /* push eax */
1969 aPatch[off++] = 0x31; /* xor edx, edx */
1970 aPatch[off++] = 0xD2;
1971 if (pDis->param2.flags == USE_REG_GEN32)
1972 {
1973 if (!fUsesEax)
1974 {
1975 aPatch[off++] = 0x89; /* mov eax, src_reg */
1976 aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, USE_REG_EAX);
1977 }
1978 }
1979 else
1980 {
1981 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1982 aPatch[off++] = 0xB8; /* mov eax, immediate */
1983 *(uint32_t *)&aPatch[off] = pDis->param2.parval;
1984 off += sizeof(uint32_t);
1985 }
1986 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1987 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1988 off += sizeof(uint32_t);
1989
1990 aPatch[off++] = 0x0F; /* wrmsr */
1991 aPatch[off++] = 0x30;
1992 if (!fUsesEax)
1993 aPatch[off++] = 0x58; /* pop eax */
1994 aPatch[off++] = 0x5A; /* pop edx */
1995 aPatch[off++] = 0x59; /* pop ecx */
1996 }
1997 else
1998 {
1999 /*
2000 * TPR read:
2001 *
2002 * push ECX [51]
2003 * push EDX [52]
2004 * push EAX [50]
2005 * mov ECX,0C0000082h [B9 82 00 00 C0]
2006 * rdmsr [0F 32]
2007 * mov EAX,EAX [89 C0]
2008 * pop EAX [58]
2009 * pop EDX [5A]
2010 * pop ECX [59]
2011 * jmp return_address [E9 return_address]
2012 *
2013 */
2014 Assert(pDis->param1.flags == USE_REG_GEN32);
2015
2016 if (pDis->param1.base.reg_gen != USE_REG_ECX)
2017 aPatch[off++] = 0x51; /* push ecx */
2018 if (pDis->param1.base.reg_gen != USE_REG_EDX)
2019 aPatch[off++] = 0x52; /* push edx */
2020 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2021 aPatch[off++] = 0x50; /* push eax */
2022
2023 aPatch[off++] = 0x31; /* xor edx, edx */
2024 aPatch[off++] = 0xD2;
2025
2026 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2027 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2028 off += sizeof(uint32_t);
2029
2030 aPatch[off++] = 0x0F; /* rdmsr */
2031 aPatch[off++] = 0x32;
2032
2033 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2034 {
2035 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2036 aPatch[off++] = MAKE_MODRM(3, USE_REG_EAX, pDis->param1.base.reg_gen);
2037 }
2038
2039 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2040 aPatch[off++] = 0x58; /* pop eax */
2041 if (pDis->param1.base.reg_gen != USE_REG_EDX)
2042 aPatch[off++] = 0x5A; /* pop edx */
2043 if (pDis->param1.base.reg_gen != USE_REG_ECX)
2044 aPatch[off++] = 0x59; /* pop ecx */
2045 }
2046 aPatch[off++] = 0xE9; /* jmp return_address */
2047 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
2048 off += sizeof(RTRCUINTPTR);
2049
2050 if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
2051 {
2052 /* Write new code to the patch buffer. */
2053 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
2054 AssertRC(rc);
2055
2056#ifdef LOG_ENABLED
2057 pInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
2058 while (true)
2059 {
2060 uint32_t cb;
2061
2062 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pInstr, 0, szOutput, sizeof(szOutput), &cb);
2063 if (RT_SUCCESS(rc))
2064 Log(("Patch instr %s\n", szOutput));
2065
2066 pInstr += cb;
2067
2068 if (pInstr >= pVM->hwaccm.s.pFreeGuestPatchMem + off)
2069 break;
2070 }
2071#endif
2072
2073 pPatch->aNewOpcode[0] = 0xE9;
2074 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2075
2076 /* Overwrite the TPR instruction with a jump. */
2077 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2078 AssertRC(rc);
2079
2080#ifdef LOG_ENABLED
2081 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
2082 if (RT_SUCCESS(rc))
2083 Log(("Jump: %s\n", szOutput));
2084#endif
2085 pVM->hwaccm.s.pFreeGuestPatchMem += off;
2086 pPatch->cbNewOp = 5;
2087
2088 pPatch->Core.Key = pCtx->eip;
2089 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2090 AssertRC(rc);
2091
2092 pVM->hwaccm.s.cPatches++;
2093 pVM->hwaccm.s.fTPRPatchingActive = true;
2094 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchSuccess);
2095 return VINF_SUCCESS;
2096 }
2097 else
2098 Log(("Ran out of space in our patch buffer!\n"));
2099 }
2100
2101 /* Save invalid patch, so we will not try again. */
2102 uint32_t idx = pVM->hwaccm.s.cPatches;
2103
2104#ifdef LOG_ENABLED
2105 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
2106 if (RT_SUCCESS(rc))
2107 Log(("Failed to patch instr: %s\n", szOutput));
2108#endif
2109
2110 pPatch = &pVM->hwaccm.s.aPatches[idx];
2111 pPatch->Core.Key = pCtx->eip;
2112 pPatch->enmType = HWACCMTPRINSTR_INVALID;
2113 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2114 AssertRC(rc);
2115 pVM->hwaccm.s.cPatches++;
2116 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchFailure);
2117 return VINF_SUCCESS;
2118}
2119
2120/**
2121 * Attempt to patch TPR mmio instructions
2122 *
2123 * @returns VBox status code.
2124 * @param pVM The VM to operate on.
2125 * @param pVCpu The VM CPU to operate on.
2126 * @param pCtx CPU context
2127 */
2128VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2129{
2130 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, (pVM->hwaccm.s.pGuestPatchMem) ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr, (void *)pVCpu->idCpu);
2131 AssertRC(rc);
2132 return rc;
2133}
2134
2135/**
2136 * Force execution of the current IO code in the recompiler
2137 *
2138 * @returns VBox status code.
2139 * @param pVM The VM to operate on.
2140 * @param pCtx Partial VM execution context
2141 */
2142VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2143{
2144 PVMCPU pVCpu = VMMGetCpu(pVM);
2145
2146 Assert(pVM->fHWACCMEnabled);
2147 Log(("HWACCMR3EmulateIoBlock\n"));
2148
2149 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2150 if (HWACCMCanEmulateIoBlockEx(pCtx))
2151 {
2152 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
2153 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
2154 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2155 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2156 return VINF_EM_RESCHEDULE_REM;
2157 }
2158 return VINF_SUCCESS;
2159}
2160
2161/**
2162 * Checks if we can currently use hardware accelerated raw mode.
2163 *
2164 * @returns boolean
2165 * @param pVM The VM to operate on.
2166 * @param pCtx Partial VM execution context
2167 */
2168VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2169{
2170 PVMCPU pVCpu = VMMGetCpu(pVM);
2171
2172 Assert(pVM->fHWACCMEnabled);
2173
2174 /* If we're still executing the IO code, then return false. */
2175 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
2176 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2177 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2178 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
2179 return false;
2180
2181 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
2182
2183 /* AMD-V supports real & protected mode with or without paging. */
2184 if (pVM->hwaccm.s.svm.fEnabled)
2185 {
2186 pVCpu->hwaccm.s.fActive = true;
2187 return true;
2188 }
2189
2190 pVCpu->hwaccm.s.fActive = false;
2191
2192 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2193#ifdef HWACCM_VMX_EMULATE_REALMODE
2194 bool fVMMDeviceHeapEnabled = PDMVMMDevHeapIsEnabled(pVM);
2195
2196 Assert((pVM->hwaccm.s.vmx.fUnrestrictedGuest && !pVM->hwaccm.s.vmx.pRealModeTSS) || (!pVM->hwaccm.s.vmx.fUnrestrictedGuest && pVM->hwaccm.s.vmx.pRealModeTSS));
2197
2198 /** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. */
2199 if (fVMMDeviceHeapEnabled)
2200 {
2201 if (CPUMIsGuestInRealModeEx(pCtx))
2202 {
2203 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
2204 * The base must also be equal to (sel << 4).
2205 */
2206 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
2207 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
2208 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
2209 || pCtx->es != (pCtx->esHid.u64Base >> 4)
2210 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
2211 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
2212 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
2213 {
2214 return false;
2215 }
2216 }
2217 else
2218 {
2219 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2220 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
2221 * from real to protected mode. (all sorts of RPL & DPL assumptions)
2222 */
2223 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2224 && enmGuestMode >= PGMMODE_PROTECTED)
2225 {
2226 if ( (pCtx->cs & X86_SEL_RPL)
2227 || (pCtx->ds & X86_SEL_RPL)
2228 || (pCtx->es & X86_SEL_RPL)
2229 || (pCtx->fs & X86_SEL_RPL)
2230 || (pCtx->gs & X86_SEL_RPL)
2231 || (pCtx->ss & X86_SEL_RPL))
2232 {
2233 return false;
2234 }
2235 }
2236 }
2237 }
2238 else
2239#endif /* HWACCM_VMX_EMULATE_REALMODE */
2240 {
2241 if ( !CPUMIsGuestInLongModeEx(pCtx)
2242 && !pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2243 {
2244 /** @todo This should (probably) be set on every excursion to the REM,
2245 * however it's too risky right now. So, only apply it when we go
2246 * back to REM for real mode execution. (The XP hack below doesn't
2247 * work reliably without this.)
2248 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2249 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2250
2251 if ( !pVM->hwaccm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap*/
2252 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2253 return false;
2254
2255 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2256 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
2257 return false;
2258
2259 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2260 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2261 * hidden registers (possible recompiler bug; see load_seg_vm) */
2262 if (pCtx->csHid.Attr.n.u1Present == 0)
2263 return false;
2264 if (pCtx->ssHid.Attr.n.u1Present == 0)
2265 return false;
2266
2267 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2268 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2269 /** @todo This check is actually wrong, it doesn't take the direction of the
2270 * stack segment into account. But, it does the job for now. */
2271 if (pCtx->rsp >= pCtx->ssHid.u32Limit)
2272 return false;
2273#if 0
2274 if ( pCtx->cs >= pCtx->gdtr.cbGdt
2275 || pCtx->ss >= pCtx->gdtr.cbGdt
2276 || pCtx->ds >= pCtx->gdtr.cbGdt
2277 || pCtx->es >= pCtx->gdtr.cbGdt
2278 || pCtx->fs >= pCtx->gdtr.cbGdt
2279 || pCtx->gs >= pCtx->gdtr.cbGdt)
2280 return false;
2281#endif
2282 }
2283 }
2284
2285 if (pVM->hwaccm.s.vmx.fEnabled)
2286 {
2287 uint32_t mask;
2288
2289 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2290 {
2291 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2292 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2293 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2294 mask &= ~X86_CR0_NE;
2295
2296#ifdef HWACCM_VMX_EMULATE_REALMODE
2297 if (fVMMDeviceHeapEnabled)
2298 {
2299 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2300 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2301 }
2302 else
2303#endif
2304 {
2305 /* We support protected mode without paging using identity mapping. */
2306 mask &= ~X86_CR0_PG;
2307 }
2308 if ((pCtx->cr0 & mask) != mask)
2309 return false;
2310
2311 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2312 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2313 if ((pCtx->cr0 & mask) != 0)
2314 return false;
2315 }
2316
2317 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2318 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2319 mask &= ~X86_CR4_VMXE;
2320 if ((pCtx->cr4 & mask) != mask)
2321 return false;
2322
2323 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2324 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2325 if ((pCtx->cr4 & mask) != 0)
2326 return false;
2327
2328 pVCpu->hwaccm.s.fActive = true;
2329 return true;
2330 }
2331
2332 return false;
2333}
2334
2335/**
2336 * Checks if we need to reschedule due to VMM device heap changes
2337 *
2338 * @returns boolean
2339 * @param pVM The VM to operate on.
2340 * @param pCtx VM execution context
2341 */
2342VMMR3DECL(bool) HWACCMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2343{
2344 /** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. (VT-x only) */
2345 if ( pVM->hwaccm.s.vmx.fEnabled
2346 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2347 && !PDMVMMDevHeapIsEnabled(pVM)
2348 && (pVM->hwaccm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2349 return true;
2350
2351 return false;
2352}
2353
2354
2355/**
2356 * Notifcation from EM about a rescheduling into hardware assisted execution
2357 * mode.
2358 *
2359 * @param pVCpu Pointer to the current virtual cpu structure.
2360 */
2361VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2362{
2363 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2364}
2365
2366/**
2367 * Notifcation from EM about returning from instruction emulation (REM / EM).
2368 *
2369 * @param pVCpu Pointer to the current virtual cpu structure.
2370 */
2371VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2372{
2373 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2374}
2375
2376/**
2377 * Checks if we are currently using hardware accelerated raw mode.
2378 *
2379 * @returns boolean
2380 * @param pVCpu The VMCPU to operate on.
2381 */
2382VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2383{
2384 return pVCpu->hwaccm.s.fActive;
2385}
2386
2387/**
2388 * Checks if we are currently using nested paging.
2389 *
2390 * @returns boolean
2391 * @param pVM The VM to operate on.
2392 */
2393VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2394{
2395 return pVM->hwaccm.s.fNestedPaging;
2396}
2397
2398/**
2399 * Checks if we are currently using VPID in VT-x mode.
2400 *
2401 * @returns boolean
2402 * @param pVM The VM to operate on.
2403 */
2404VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2405{
2406 return pVM->hwaccm.s.vmx.fVPID;
2407}
2408
2409
2410/**
2411 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2412 *
2413 * @returns boolean
2414 * @param pVM The VM to operate on.
2415 */
2416VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2417{
2418 return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2419}
2420
2421/**
2422 * Restart an I/O instruction that was refused in ring-0
2423 *
2424 * @returns Strict VBox status code. Informational status codes other than the one documented
2425 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2426 * @retval VINF_SUCCESS Success.
2427 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2428 * status code must be passed on to EM.
2429 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2430 *
2431 * @param pVM The VM to operate on.
2432 * @param pVCpu The VMCPU to operate on.
2433 * @param pCtx VCPU register context
2434 */
2435VMMR3DECL(VBOXSTRICTRC) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2436{
2437 HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2438
2439 pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2440
2441 if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2442 || enmType == HWACCMPENDINGIO_INVALID)
2443 return VERR_NOT_FOUND;
2444
2445 VBOXSTRICTRC rcStrict;
2446 switch (enmType)
2447 {
2448 case HWACCMPENDINGIO_PORT_READ:
2449 {
2450 uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2451 uint32_t u32Val = 0;
2452
2453 rcStrict = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2454 &u32Val,
2455 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2456 if (IOM_SUCCESS(rcStrict))
2457 {
2458 /* Write back to the EAX register. */
2459 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2460 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2461 }
2462 break;
2463 }
2464
2465 case HWACCMPENDINGIO_PORT_WRITE:
2466 rcStrict = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2467 pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2468 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2469 if (IOM_SUCCESS(rcStrict))
2470 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2471 break;
2472
2473 default:
2474 AssertFailed();
2475 return VERR_INTERNAL_ERROR;
2476 }
2477
2478 return rcStrict;
2479}
2480
2481/**
2482 * Inject an NMI into a running VM (only VCPU 0!)
2483 *
2484 * @returns boolean
2485 * @param pVM The VM to operate on.
2486 */
2487VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2488{
2489 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2490 return VINF_SUCCESS;
2491}
2492
2493/**
2494 * Check fatal VT-x/AMD-V error and produce some meaningful
2495 * log release message.
2496 *
2497 * @param pVM The VM to operate on.
2498 * @param iStatusCode VBox status code
2499 */
2500VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2501{
2502 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2503 {
2504 switch(iStatusCode)
2505 {
2506 case VERR_VMX_INVALID_VMCS_FIELD:
2507 break;
2508
2509 case VERR_VMX_INVALID_VMCS_PTR:
2510 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
2511 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2512 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2513 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2514 break;
2515
2516 case VERR_VMX_UNABLE_TO_START_VM:
2517 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2518 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2519#if 0 /* @todo dump the current control fields to the release log */
2520 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2521 {
2522
2523 }
2524#endif
2525 break;
2526
2527 case VERR_VMX_UNABLE_TO_RESUME_VM:
2528 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2529 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2530 break;
2531
2532 case VERR_VMX_INVALID_VMXON_PTR:
2533 break;
2534 }
2535 }
2536}
2537
2538/**
2539 * Execute state save operation.
2540 *
2541 * @returns VBox status code.
2542 * @param pVM VM Handle.
2543 * @param pSSM SSM operation handle.
2544 */
2545static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2546{
2547 int rc;
2548
2549 Log(("hwaccmR3Save:\n"));
2550
2551 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2552 {
2553 /*
2554 * Save the basic bits - fortunately all the other things can be resynced on load.
2555 */
2556 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2557 AssertRCReturn(rc, rc);
2558 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2559 AssertRCReturn(rc, rc);
2560 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2561 AssertRCReturn(rc, rc);
2562
2563 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2564 AssertRCReturn(rc, rc);
2565 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2566 AssertRCReturn(rc, rc);
2567 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2568 AssertRCReturn(rc, rc);
2569 }
2570#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2571 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2572 AssertRCReturn(rc, rc);
2573 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2574 AssertRCReturn(rc, rc);
2575 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2576 AssertRCReturn(rc, rc);
2577
2578 /* Store all the guest patch records too. */
2579 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cPatches);
2580 AssertRCReturn(rc, rc);
2581
2582 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2583 {
2584 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2585
2586 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2587 AssertRCReturn(rc, rc);
2588
2589 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2590 AssertRCReturn(rc, rc);
2591
2592 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2593 AssertRCReturn(rc, rc);
2594
2595 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2596 AssertRCReturn(rc, rc);
2597
2598 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2599 AssertRCReturn(rc, rc);
2600
2601 AssertCompileSize(HWACCMTPRINSTR, 4);
2602 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2603 AssertRCReturn(rc, rc);
2604
2605 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2606 AssertRCReturn(rc, rc);
2607
2608 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2609 AssertRCReturn(rc, rc);
2610
2611 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2612 AssertRCReturn(rc, rc);
2613
2614 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2615 AssertRCReturn(rc, rc);
2616 }
2617#endif
2618 return VINF_SUCCESS;
2619}
2620
2621/**
2622 * Execute state load operation.
2623 *
2624 * @returns VBox status code.
2625 * @param pVM VM Handle.
2626 * @param pSSM SSM operation handle.
2627 * @param uVersion Data layout version.
2628 * @param uPass The data pass.
2629 */
2630static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2631{
2632 int rc;
2633
2634 Log(("hwaccmR3Load:\n"));
2635 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2636
2637 /*
2638 * Validate version.
2639 */
2640 if ( uVersion != HWACCM_SSM_VERSION
2641 && uVersion != HWACCM_SSM_VERSION_NO_PATCHING
2642 && uVersion != HWACCM_SSM_VERSION_2_0_X)
2643 {
2644 AssertMsgFailed(("hwaccmR3Load: Invalid version uVersion=%d!\n", uVersion));
2645 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2646 }
2647 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2648 {
2649 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2650 AssertRCReturn(rc, rc);
2651 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2652 AssertRCReturn(rc, rc);
2653 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2654 AssertRCReturn(rc, rc);
2655
2656 if (uVersion >= HWACCM_SSM_VERSION_NO_PATCHING)
2657 {
2658 uint32_t val;
2659
2660 rc = SSMR3GetU32(pSSM, &val);
2661 AssertRCReturn(rc, rc);
2662 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2663
2664 rc = SSMR3GetU32(pSSM, &val);
2665 AssertRCReturn(rc, rc);
2666 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2667
2668 rc = SSMR3GetU32(pSSM, &val);
2669 AssertRCReturn(rc, rc);
2670 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2671 }
2672 }
2673#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2674 if (uVersion > HWACCM_SSM_VERSION_NO_PATCHING)
2675 {
2676 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2677 AssertRCReturn(rc, rc);
2678 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2679 AssertRCReturn(rc, rc);
2680 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2681 AssertRCReturn(rc, rc);
2682
2683 /* Fetch all TPR patch records. */
2684 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cPatches);
2685 AssertRCReturn(rc, rc);
2686
2687 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2688 {
2689 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2690
2691 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2692 AssertRCReturn(rc, rc);
2693
2694 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2695 AssertRCReturn(rc, rc);
2696
2697 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2698 AssertRCReturn(rc, rc);
2699
2700 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2701 AssertRCReturn(rc, rc);
2702
2703 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2704 AssertRCReturn(rc, rc);
2705
2706 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2707 AssertRCReturn(rc, rc);
2708
2709 if (pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT)
2710 pVM->hwaccm.s.fTPRPatchingActive = true;
2711
2712 Assert(pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT || pVM->hwaccm.s.fTPRPatchingActive == false);
2713
2714 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2715 AssertRCReturn(rc, rc);
2716
2717 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2718 AssertRCReturn(rc, rc);
2719
2720 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2721 AssertRCReturn(rc, rc);
2722
2723 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2724 AssertRCReturn(rc, rc);
2725
2726 Log(("hwaccmR3Load: patch %d\n", i));
2727 Log(("Key = %x\n", pPatch->Core.Key));
2728 Log(("cbOp = %d\n", pPatch->cbOp));
2729 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2730 Log(("type = %d\n", pPatch->enmType));
2731 Log(("srcop = %d\n", pPatch->uSrcOperand));
2732 Log(("dstop = %d\n", pPatch->uDstOperand));
2733 Log(("cFaults = %d\n", pPatch->cFaults));
2734 Log(("target = %x\n", pPatch->pJumpTarget));
2735 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2736 AssertRC(rc);
2737 }
2738 }
2739#endif
2740
2741 /* Recheck all VCPUs if we can go staight into hwaccm execution mode. */
2742 if (HWACCMIsEnabled(pVM))
2743 {
2744 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2745 {
2746 PVMCPU pVCpu = &pVM->aCpus[i];
2747
2748 HWACCMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2749 }
2750 }
2751 return VINF_SUCCESS;
2752}
2753
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