VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 30329

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1/* $Id: HWACCM.cpp 30105 2010-06-09 11:03:37Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HWACCM
22#include <VBox/cpum.h>
23#include <VBox/stam.h>
24#include <VBox/mm.h>
25#include <VBox/pdmapi.h>
26#include <VBox/pgm.h>
27#include <VBox/ssm.h>
28#include <VBox/trpm.h>
29#include <VBox/dbgf.h>
30#include <VBox/iom.h>
31#include <VBox/patm.h>
32#include <VBox/csam.h>
33#include <VBox/selm.h>
34#include <VBox/rem.h>
35#include <VBox/hwacc_vmx.h>
36#include <VBox/hwacc_svm.h>
37#include "HWACCMInternal.h"
38#include <VBox/vm.h>
39#include <VBox/err.h>
40#include <VBox/param.h>
41
42#include <iprt/assert.h>
43#include <VBox/log.h>
44#include <iprt/asm.h>
45#include <iprt/asm-amd64-x86.h>
46#include <iprt/string.h>
47#include <iprt/env.h>
48#include <iprt/thread.h>
49
50/*******************************************************************************
51* Global Variables *
52*******************************************************************************/
53#ifdef VBOX_WITH_STATISTICS
54# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55# define EXIT_REASON_NIL() NULL
56/** Exit reason descriptions for VT-x, used to describe statistics. */
57static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58{
59 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67 EXIT_REASON_NIL(),
68 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94 EXIT_REASON_NIL(),
95 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96 EXIT_REASON_NIL(),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101 EXIT_REASON_NIL(),
102 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110 EXIT_REASON_NIL(),
111 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115 EXIT_REASON_NIL()
116};
117/** Exit reason descriptions for AMD-V, used to describe statistics. */
118static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119{
120 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
121 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
122 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
123 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
124 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
125 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
126 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
127 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
128 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
129 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
130 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
131 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
132 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
133 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
134 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
135 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
136 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
137 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
152 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
153 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
154 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
155 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
156 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
157 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
158 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
159 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
160 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
161 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
162 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
163 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
164 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
165 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
166 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
167 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
168 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
169 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
184 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
185 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_INTR , 96, "Physical maskable interrupt."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_NMI , 97, "Physical non-maskable interrupt."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_SMI , 98, "System management interrupt."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_INIT , 99, "Physical INIT signal."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_VINTR ,100, "Visual interrupt."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_IDTR_READ ,102, "Read IDTR"),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_GDTR_READ ,103, "Read GDTR"),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_LDTR_READ ,104, "Read LDTR."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,105, "Read TR."),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,106, "Write IDTR."),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,107, "Write GDTR."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,108, "Write LDTR."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,109, "Write TR."),
230 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
231 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
232 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
233 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
234 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
235 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
236 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
237 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
238 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
239 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
240 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
241 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
242 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
243 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
244 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
245 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
246 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
247 EXIT_REASON(SVM_EXIT_TASK_SHUTDOWN ,127, "Shutdown."),
248 EXIT_REASON(SVM_EXIT_TASK_VMRUN ,128, "VMRUN instruction."),
249 EXIT_REASON(SVM_EXIT_TASK_VMCALL ,129, "VMCALL instruction."),
250 EXIT_REASON(SVM_EXIT_TASK_VMLOAD ,130, "VMLOAD instruction."),
251 EXIT_REASON(SVM_EXIT_TASK_VMSAVE ,131, "VMSAVE instruction."),
252 EXIT_REASON(SVM_EXIT_TASK_STGI ,132, "STGI instruction."),
253 EXIT_REASON(SVM_EXIT_TASK_CLGI ,133, "CLGI instruction."),
254 EXIT_REASON(SVM_EXIT_TASK_SKINIT ,134, "SKINIT instruction."),
255 EXIT_REASON(SVM_EXIT_TASK_RDTSCP ,135, "RDTSCP instruction."),
256 EXIT_REASON(SVM_EXIT_TASK_ICEBP ,136, "ICEBP instruction."),
257 EXIT_REASON(SVM_EXIT_TASK_WBINVD ,137, "WBINVD instruction."),
258 EXIT_REASON(SVM_EXIT_TASK_MONITOR ,138, "MONITOR instruction."),
259 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
260 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
261 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
262 EXIT_REASON_NIL()
263};
264# undef EXIT_REASON
265# undef EXIT_REASON_NIL
266#endif /* VBOX_WITH_STATISTICS */
267
268/*******************************************************************************
269* Internal Functions *
270*******************************************************************************/
271static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
272static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
273
274
275/**
276 * Initializes the HWACCM.
277 *
278 * @returns VBox status code.
279 * @param pVM The VM to operate on.
280 */
281VMMR3DECL(int) HWACCMR3Init(PVM pVM)
282{
283 LogFlow(("HWACCMR3Init\n"));
284
285 /*
286 * Assert alignment and sizes.
287 */
288 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
289 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
290
291 /* Some structure checks. */
292 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
293 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
294 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
295 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
296
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
300 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64GPAT) == 0x668, ("guest.u64GPAT offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64GPAT)));
303 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
304 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
305
306
307 /*
308 * Register the saved state data unit.
309 */
310 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
311 NULL, NULL, NULL,
312 NULL, hwaccmR3Save, NULL,
313 NULL, hwaccmR3Load, NULL);
314 if (RT_FAILURE(rc))
315 return rc;
316
317 /* Misc initialisation. */
318 pVM->hwaccm.s.vmx.fSupported = false;
319 pVM->hwaccm.s.svm.fSupported = false;
320 pVM->hwaccm.s.vmx.fEnabled = false;
321 pVM->hwaccm.s.svm.fEnabled = false;
322
323 pVM->hwaccm.s.fNestedPaging = false;
324 pVM->hwaccm.s.fLargePages = false;
325
326 /* Disabled by default. */
327 pVM->fHWACCMEnabled = false;
328
329 /*
330 * Check CFGM options.
331 */
332 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
333 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
334 /* Nested paging: disabled by default. */
335 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
336 AssertRC(rc);
337
338 /* Large pages: disabled by default. */
339 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hwaccm.s.fLargePages, false);
340 AssertRC(rc);
341
342 /* VT-x VPID: disabled by default. */
343 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
344 AssertRC(rc);
345
346 /* HWACCM support must be explicitely enabled in the configuration file. */
347 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
348 AssertRC(rc);
349
350 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
351 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hwaccm.s.fTRPPatchingAllowed, false);
352 AssertRC(rc);
353
354#ifdef RT_OS_DARWIN
355 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
356#else
357 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
358#endif
359 {
360 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
361 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
362 return VERR_HWACCM_CONFIG_MISMATCH;
363 }
364
365 if (VMMIsHwVirtExtForced(pVM))
366 pVM->fHWACCMEnabled = true;
367
368#if HC_ARCH_BITS == 32
369 /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
370 * (To use the default, don't set 64bitEnabled in CFGM.) */
371 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
372 AssertLogRelRCReturn(rc, rc);
373 if (pVM->hwaccm.s.fAllow64BitGuests)
374 {
375# ifdef RT_OS_DARWIN
376 if (!VMMIsHwVirtExtForced(pVM))
377# else
378 if (!pVM->hwaccm.s.fAllowed)
379# endif
380 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
381 }
382#else
383 /* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
384 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
385 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
386 AssertLogRelRCReturn(rc, rc);
387#endif
388
389
390 /** Determine the init method for AMD-V and VT-x; either one global init for each host CPU
391 * or local init each time we wish to execute guest code.
392 *
393 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
394 */
395 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hwaccm.s.fGlobalInit,
396#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
397 false
398#else
399 true
400#endif
401 );
402
403 /* Max number of resume loops. */
404 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
405 AssertRC(rc);
406
407 return VINF_SUCCESS;
408}
409
410/**
411 * Initializes the per-VCPU HWACCM.
412 *
413 * @returns VBox status code.
414 * @param pVM The VM to operate on.
415 */
416VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
417{
418 LogFlow(("HWACCMR3InitCPU\n"));
419
420 for (VMCPUID i = 0; i < pVM->cCpus; i++)
421 {
422 PVMCPU pVCpu = &pVM->aCpus[i];
423
424 pVCpu->hwaccm.s.fActive = false;
425 }
426
427#ifdef VBOX_WITH_STATISTICS
428 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
429 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
430 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
431 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
432
433 /*
434 * Statistics.
435 */
436 for (VMCPUID i = 0; i < pVM->cCpus; i++)
437 {
438 PVMCPU pVCpu = &pVM->aCpus[i];
439 int rc;
440
441 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of RTMpPokeCpu",
442 "/PROF/HWACCM/CPU%d/Poke", i);
443 AssertRC(rc);
444 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait",
445 "/PROF/HWACCM/CPU%d/PokeWait", i);
446 AssertRC(rc);
447 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait when RTMpPokeCpu fails",
448 "/PROF/HWACCM/CPU%d/PokeWaitFailed", i);
449 AssertRC(rc);
450 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
451 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
452 AssertRC(rc);
453 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
454 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
455 AssertRC(rc);
456 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
457 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
458 AssertRC(rc);
459# if 1 /* temporary for tracking down darwin holdup. */
460 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
461 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
462 AssertRC(rc);
463 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
464 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
465 AssertRC(rc);
466 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
467 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
468 AssertRC(rc);
469# endif
470 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
471 "/PROF/HWACCM/CPU%d/InGC", i);
472 AssertRC(rc);
473
474# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
475 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
476 "/PROF/HWACCM/CPU%d/Switcher3264", i);
477 AssertRC(rc);
478# endif
479
480# define HWACCM_REG_COUNTER(a, b) \
481 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
482 AssertRC(rc);
483
484 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
485 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
486 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
487 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
488 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
489 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
490 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
491 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
492 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
493 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
494 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
495 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
496 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
498 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
499 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
503 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMonitor, "/HWACCM/CPU%d/Exit/Instr/Monitor");
504 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
505 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
506 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
507 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
508 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
509 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
510 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
511 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
512 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
513 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
514 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
515 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
516 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
517 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
518 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
519 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
520 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
521 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
522
523 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
524 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
525
526 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
527 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
528 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
529
530 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPage, "/HWACCM/CPU%d/Flush/Page");
531 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
532 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
533 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLB, "/HWACCM/CPU%d/Flush/TLB");
534 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
535 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
536 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
537 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
538 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
539 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
540 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
541 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
542 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
543
544 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
545 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
546 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow, "/HWACCM/CPU%d/TSC/InterceptOverflow");
547
548 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
549 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
550 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
551
552#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
553 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFpu64SwitchBack, "/HWACCM/CPU%d/Switch64/Fpu");
554 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDebug64SwitchBack, "/HWACCM/CPU%d/Switch64/Debug");
555#endif
556
557 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
558 {
559 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
560 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
561 AssertRC(rc);
562 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
563 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
564 AssertRC(rc);
565 }
566
567#undef HWACCM_REG_COUNTER
568
569 pVCpu->hwaccm.s.paStatExitReason = NULL;
570
571 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
572 AssertRC(rc);
573 if (RT_SUCCESS(rc))
574 {
575 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
576 for (int j=0;j<MAX_EXITREASON_STAT;j++)
577 {
578 if (papszDesc[j])
579 {
580 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
581 papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
582 AssertRC(rc);
583 }
584 }
585 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
586 AssertRC(rc);
587 }
588 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
589# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
590 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
591# else
592 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
593# endif
594
595 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
596 AssertRCReturn(rc, rc);
597 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
598# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
599 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
600# else
601 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
602# endif
603 for (unsigned j = 0; j < 255; j++)
604 STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
605 (j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
606
607 }
608#endif /* VBOX_WITH_STATISTICS */
609
610#ifdef VBOX_WITH_CRASHDUMP_MAGIC
611 /* Magic marker for searching in crash dumps. */
612 for (VMCPUID i = 0; i < pVM->cCpus; i++)
613 {
614 PVMCPU pVCpu = &pVM->aCpus[i];
615
616 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
617 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
618 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
619 }
620#endif
621 return VINF_SUCCESS;
622}
623
624/**
625 * Turns off normal raw mode features
626 *
627 * @param pVM The VM to operate on.
628 */
629static void hwaccmR3DisableRawMode(PVM pVM)
630{
631 /* Disable PATM & CSAM. */
632 PATMR3AllowPatching(pVM, false);
633 CSAMDisableScanning(pVM);
634
635 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
636 SELMR3DisableMonitoring(pVM);
637 TRPMR3DisableMonitoring(pVM);
638
639 /* Disable the switcher code (safety precaution). */
640 VMMR3DisableSwitcher(pVM);
641
642 /* Disable mapping of the hypervisor into the shadow page table. */
643 PGMR3MappingsDisable(pVM);
644
645 /* Disable the switcher */
646 VMMR3DisableSwitcher(pVM);
647
648 /* Reinit the paging mode to force the new shadow mode. */
649 for (VMCPUID i = 0; i < pVM->cCpus; i++)
650 {
651 PVMCPU pVCpu = &pVM->aCpus[i];
652
653 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
654 }
655}
656
657/**
658 * Initialize VT-x or AMD-V.
659 *
660 * @returns VBox status code.
661 * @param pVM The VM handle.
662 */
663VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
664{
665 int rc;
666
667 /* Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
668 * is already using AMD-V.
669 */
670 if ( !pVM->hwaccm.s.vmx.fSupported
671 && !pVM->hwaccm.s.svm.fSupported
672 && pVM->hwaccm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
673 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
674 {
675 LogRel(("HWACCM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
676 pVM->hwaccm.s.svm.fSupported = true;
677 pVM->hwaccm.s.svm.fIgnoreInUseError = true;
678 }
679 else
680 if ( !pVM->hwaccm.s.vmx.fSupported
681 && !pVM->hwaccm.s.svm.fSupported)
682 {
683 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
684 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
685
686 if (VMMIsHwVirtExtForced(pVM))
687 {
688 switch (pVM->hwaccm.s.lLastError)
689 {
690 case VERR_VMX_NO_VMX:
691 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
692 case VERR_VMX_IN_VMX_ROOT_MODE:
693 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
694 case VERR_SVM_IN_USE:
695 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
696 case VERR_SVM_NO_SVM:
697 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
698 case VERR_SVM_DISABLED:
699 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
700 default:
701 return pVM->hwaccm.s.lLastError;
702 }
703 }
704 return VINF_SUCCESS;
705 }
706
707 if (pVM->hwaccm.s.vmx.fSupported)
708 {
709 rc = SUPR3QueryVTxSupported();
710 if (RT_FAILURE(rc))
711 {
712#ifdef RT_OS_LINUX
713 LogRel(("HWACCM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
714#else
715 LogRel(("HWACCM: The host kernel does not support VT-x!\n"));
716#endif
717 if ( pVM->cCpus > 1
718 || VMMIsHwVirtExtForced(pVM))
719 return rc;
720
721 /* silently fall back to raw mode */
722 return VINF_SUCCESS;
723 }
724 }
725
726 if (!pVM->hwaccm.s.fAllowed)
727 return VINF_SUCCESS; /* nothing to do */
728
729 /* Enable VT-x or AMD-V on all host CPUs. */
730 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
731 if (RT_FAILURE(rc))
732 {
733 LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
734 return rc;
735 }
736 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
737
738 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
739 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
740 if (!pVM->hwaccm.s.fHasIoApic)
741 {
742 Assert(!pVM->hwaccm.s.fTRPPatchingAllowed); /* paranoia */
743 pVM->hwaccm.s.fTRPPatchingAllowed = false;
744 }
745
746 if (pVM->hwaccm.s.vmx.fSupported)
747 {
748 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
749
750 if ( pVM->hwaccm.s.fInitialized == false
751 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
752 {
753 uint64_t val;
754 RTGCPHYS GCPhys = 0;
755
756 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
757 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
758 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
759 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
760 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
761 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
762 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
763 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
764
765 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
766 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
767 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
768 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
769 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
770 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
771 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
772 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
773 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
774 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
775 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
776 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
777 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
778 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
779 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
780 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
781 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
782 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
783 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
784
785 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
786 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
787 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
788 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
789 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
790 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
791 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
792 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
793 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
794 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
795 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
796 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
797 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
798 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
799 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
800 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
801 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
802 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
803 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
804 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
805 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
806 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
807 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
808 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
809 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
810 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
811 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
812 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
813 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
814 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
815 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
816 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
817 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
818 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
819 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
820 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
821 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
822 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
823 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
824 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
825 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
826 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
827 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
828 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
829
830 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
831 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
832 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
833 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
834 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
835 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
836 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
837 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
838 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
839 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
840 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
841 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
842 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
843 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
844 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
845 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
846 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
847 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
848 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
849 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
850 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
851 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
852 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
853 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
854 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
855 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
856 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
857 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
858 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
859 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
860 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
861 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
862 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
863 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
864 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
865 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
866 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
867 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
868 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
869 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
870 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
871 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
872 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
873
874 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
875 {
876 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
877 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
878 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
879 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
880 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
881 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
882 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
883 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
884 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
885 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT\n"));
886 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
887 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
888 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
889 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
890 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
891 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
892 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
893 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE\n"));
894 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
895 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT\n"));
896
897 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
898 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
899 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
900 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
901 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
902 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
903 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT *must* be set\n"));
904 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
905 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
906 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
907 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
908 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
909 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
910 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
911 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
912 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
913 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE *must* be set\n"));
914 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
915 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT *must* be set\n"));
916 }
917
918 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
919 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
920 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
921 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
922 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
923 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
924 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
925 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
926 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
927 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
928 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
929 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
930 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
931 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
932 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
933 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
934 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
935 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
936 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
937 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
938 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
939 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
940 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
941 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
942 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
943 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
944 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
945 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
946 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
947 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
948 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
949
950 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
951 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
952 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
953 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
954 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
955 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
956 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
957 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
958 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
959 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
960 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
961 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
962 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
963 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
964 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
965 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
966 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
967 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
968 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
969 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
970 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
971 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
972 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
973 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
974 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
975 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
976 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
977 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
978 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
979 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
980 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
981 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
982 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
983 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
984 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
985
986 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
987 {
988 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
989
990 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
991 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
992 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
993 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
994 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
995 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
996 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
997 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
998 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
999 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
1000 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
1001 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
1002 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
1003 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
1004 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
1005 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
1006 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
1007 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
1008 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
1009 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
1010 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
1011 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
1012 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
1013 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
1014 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
1015 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
1016 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
1017 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
1018 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
1019 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
1020 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
1021 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
1022 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
1023 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
1024 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
1025 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
1026 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
1027 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
1028 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
1029 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
1030 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
1031 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
1032 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
1033 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
1034 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
1035 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
1036 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
1037 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
1038 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
1039 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
1040 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
1041 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
1042 }
1043
1044 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
1045 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1046 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1047 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1048 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1049 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1050
1051 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
1052 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
1053 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
1054 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
1055 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
1056
1057 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
1058
1059 /* Paranoia */
1060 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc) >= 512);
1061
1062 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1063 {
1064 LogRel(("HWACCM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pMSRBitmapPhys));
1065 LogRel(("HWACCM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1066 }
1067
1068#ifdef HWACCM_VTX_WITH_EPT
1069 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1070 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1071#endif /* HWACCM_VTX_WITH_EPT */
1072#ifdef HWACCM_VTX_WITH_VPID
1073 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1074 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
1075 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
1076#endif /* HWACCM_VTX_WITH_VPID */
1077
1078 /* Unrestricted guest execution relies on EPT. */
1079 if ( pVM->hwaccm.s.fNestedPaging
1080 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE))
1081 {
1082 pVM->hwaccm.s.vmx.fUnrestrictedGuest = true;
1083 }
1084
1085 /* Only try once. */
1086 pVM->hwaccm.s.fInitialized = true;
1087
1088 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1089 {
1090 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1091 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
1092 if (RT_SUCCESS(rc))
1093 {
1094 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1095 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
1096 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
1097 /* Bit set to 0 means redirection enabled. */
1098 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
1099 /* Allow all port IO, so the VT-x IO intercepts do their job. */
1100 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
1101 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
1102
1103 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1104 * real and protected mode without paging with EPT.
1105 */
1106 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1107 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
1108 {
1109 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1110 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
1111 }
1112
1113 /* We convert it here every time as pci regions could be reconfigured. */
1114 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1115 AssertRC(rc);
1116 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1117
1118 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1119 AssertRC(rc);
1120 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1121 }
1122 else
1123 {
1124 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1125 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1126 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1127 }
1128 }
1129
1130 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1131 AssertRC(rc);
1132 if (rc == VINF_SUCCESS)
1133 {
1134 pVM->fHWACCMEnabled = true;
1135 pVM->hwaccm.s.vmx.fEnabled = true;
1136 hwaccmR3DisableRawMode(pVM);
1137
1138 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1139#ifdef VBOX_ENABLE_64_BITS_GUESTS
1140 if (pVM->hwaccm.s.fAllow64BitGuests)
1141 {
1142 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1143 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1144 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1145 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1146 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1147 }
1148 else
1149 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1150 /* Todo: this needs to be fixed properly!! */
1151 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1152 && (pVM->hwaccm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1153 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1154
1155 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1156 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1157 : "HWACCM: 32-bit guests supported.\n"));
1158#else
1159 LogRel(("HWACCM: 32-bit guests supported.\n"));
1160#endif
1161 LogRel(("HWACCM: VMX enabled!\n"));
1162 if (pVM->hwaccm.s.fNestedPaging)
1163 {
1164 LogRel(("HWACCM: Enabled nested paging\n"));
1165 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1166 if (pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1167 LogRel(("HWACCM: Unrestricted guest execution enabled!\n"));
1168
1169#if HC_ARCH_BITS == 64
1170 if (pVM->hwaccm.s.fLargePages)
1171 {
1172 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1173 PGMSetLargePageUsage(pVM, true);
1174 LogRel(("HWACCM: Large page support enabled!\n"));
1175 }
1176#endif
1177 }
1178 else
1179 Assert(!pVM->hwaccm.s.vmx.fUnrestrictedGuest);
1180
1181 if (pVM->hwaccm.s.vmx.fVPID)
1182 LogRel(("HWACCM: Enabled VPID\n"));
1183
1184 if ( pVM->hwaccm.s.fNestedPaging
1185 || pVM->hwaccm.s.vmx.fVPID)
1186 {
1187 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1188 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1189 }
1190
1191 /* TPR patching status logging. */
1192 if (pVM->hwaccm.s.fTRPPatchingAllowed)
1193 {
1194 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1195 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1196 {
1197 pVM->hwaccm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1198 LogRel(("HWACCM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1199 }
1200 else
1201 {
1202 uint32_t u32Eax, u32Dummy;
1203
1204 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1205 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1206 if ( u32Eax < 0x80000001
1207 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1208 {
1209 pVM->hwaccm.s.fTRPPatchingAllowed = false;
1210 LogRel(("HWACCM: TPR patching disabled (long mode not supported).\n"));
1211 }
1212 }
1213 }
1214 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1215 }
1216 else
1217 {
1218 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1219 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1220 pVM->fHWACCMEnabled = false;
1221 }
1222 }
1223 }
1224 else
1225 if (pVM->hwaccm.s.svm.fSupported)
1226 {
1227 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1228
1229 if (pVM->hwaccm.s.fInitialized == false)
1230 {
1231 /* Erratum 170 which requires a forced TLB flush for each world switch:
1232 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1233 *
1234 * All BH-G1/2 and DH-G1/2 models include a fix:
1235 * Athlon X2: 0x6b 1/2
1236 * 0x68 1/2
1237 * Athlon 64: 0x7f 1
1238 * 0x6f 2
1239 * Sempron: 0x7f 1/2
1240 * 0x6f 2
1241 * 0x6c 2
1242 * 0x7c 2
1243 * Turion 64: 0x68 2
1244 *
1245 */
1246 uint32_t u32Dummy;
1247 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1248 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1249 u32BaseFamily= (u32Version >> 8) & 0xf;
1250 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1251 u32Model = ((u32Version >> 4) & 0xf);
1252 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1253 u32Stepping = u32Version & 0xf;
1254 if ( u32Family == 0xf
1255 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1256 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1257 {
1258 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1259 }
1260
1261 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1262 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1263 LogRel(("HWACCM: AMD HWCR MSR = %RX64\n", pVM->hwaccm.s.svm.msrHWCR));
1264 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1265 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1266 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1267
1268 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1269 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
1270 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
1271 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
1272 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
1273 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
1274 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
1275 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
1276 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
1277 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
1278 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER)
1279 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER\n"));
1280
1281 /* Only try once. */
1282 pVM->hwaccm.s.fInitialized = true;
1283
1284 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1285 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1286
1287 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1288 AssertRC(rc);
1289 if (rc == VINF_SUCCESS)
1290 {
1291 pVM->fHWACCMEnabled = true;
1292 pVM->hwaccm.s.svm.fEnabled = true;
1293
1294 if (pVM->hwaccm.s.fNestedPaging)
1295 {
1296 LogRel(("HWACCM: Enabled nested paging\n"));
1297#if HC_ARCH_BITS == 64
1298 if (pVM->hwaccm.s.fLargePages)
1299 {
1300 /* Use large (2 MB) pages for our nested paging PDEs where possible. */
1301 PGMSetLargePageUsage(pVM, true);
1302 LogRel(("HWACCM: Large page support enabled!\n"));
1303 }
1304#endif
1305 }
1306
1307 hwaccmR3DisableRawMode(pVM);
1308 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1309 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1310 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1311#ifdef VBOX_ENABLE_64_BITS_GUESTS
1312 if (pVM->hwaccm.s.fAllow64BitGuests)
1313 {
1314 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1315 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1316 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1317 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1318 }
1319 else
1320 /* Turn on NXE if PAE has been enabled. */
1321 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1322 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1323#endif
1324
1325 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1326 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1327 : "HWACCM: 32-bit guest supported.\n"));
1328
1329 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1330 }
1331 else
1332 {
1333 pVM->fHWACCMEnabled = false;
1334 }
1335 }
1336 }
1337 if (pVM->fHWACCMEnabled)
1338 LogRel(("HWACCM: VT-x/AMD-V init method: %s\n", (pVM->hwaccm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1339 return VINF_SUCCESS;
1340}
1341
1342/**
1343 * Applies relocations to data and code managed by this
1344 * component. This function will be called at init and
1345 * whenever the VMM need to relocate it self inside the GC.
1346 *
1347 * @param pVM The VM.
1348 */
1349VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1350{
1351 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1352
1353 /* Fetch the current paging mode during the relocate callback during state loading. */
1354 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1355 {
1356 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1357 {
1358 PVMCPU pVCpu = &pVM->aCpus[i];
1359
1360 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1361 Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1362 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1363 }
1364 }
1365#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1366 if (pVM->fHWACCMEnabled)
1367 {
1368 int rc;
1369
1370 switch(PGMGetHostMode(pVM))
1371 {
1372 case PGMMODE_32_BIT:
1373 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1374 break;
1375
1376 case PGMMODE_PAE:
1377 case PGMMODE_PAE_NX:
1378 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1379 break;
1380
1381 default:
1382 AssertFailed();
1383 break;
1384 }
1385 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1386 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1387
1388 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1389 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1390
1391 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1392 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1393
1394 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1395 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1396
1397# ifdef DEBUG
1398 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1399 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1400# endif
1401 }
1402#endif
1403 return;
1404}
1405
1406/**
1407 * Checks hardware accelerated raw mode is allowed.
1408 *
1409 * @returns boolean
1410 * @param pVM The VM to operate on.
1411 */
1412VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1413{
1414 return pVM->hwaccm.s.fAllowed;
1415}
1416
1417/**
1418 * Notification callback which is called whenever there is a chance that a CR3
1419 * value might have changed.
1420 *
1421 * This is called by PGM.
1422 *
1423 * @param pVM The VM to operate on.
1424 * @param pVCpu The VMCPU to operate on.
1425 * @param enmShadowMode New shadow paging mode.
1426 * @param enmGuestMode New guest paging mode.
1427 */
1428VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1429{
1430 /* Ignore page mode changes during state loading. */
1431 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1432 return;
1433
1434 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1435
1436 if ( pVM->hwaccm.s.vmx.fEnabled
1437 && pVM->fHWACCMEnabled)
1438 {
1439 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1440 && enmGuestMode >= PGMMODE_PROTECTED)
1441 {
1442 PCPUMCTX pCtx;
1443
1444 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1445
1446 /* After a real mode switch to protected mode we must force
1447 * CPL to 0. Our real mode emulation had to set it to 3.
1448 */
1449 pCtx->ssHid.Attr.n.u2Dpl = 0;
1450 }
1451 }
1452
1453 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1454 {
1455 /* Keep track of paging mode changes. */
1456 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1457 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1458
1459 /* Did we miss a change, because all code was executed in the recompiler? */
1460 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1461 {
1462 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1463 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1464 }
1465 }
1466
1467 /* Reset the contents of the read cache. */
1468 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1469 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1470 pCache->Read.aFieldVal[j] = 0;
1471}
1472
1473/**
1474 * Terminates the HWACCM.
1475 *
1476 * Termination means cleaning up and freeing all resources,
1477 * the VM it self is at this point powered off or suspended.
1478 *
1479 * @returns VBox status code.
1480 * @param pVM The VM to operate on.
1481 */
1482VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1483{
1484 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1485 {
1486 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1487 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1488 }
1489 HWACCMR3TermCPU(pVM);
1490 return 0;
1491}
1492
1493/**
1494 * Terminates the per-VCPU HWACCM.
1495 *
1496 * Termination means cleaning up and freeing all resources,
1497 * the VM it self is at this point powered off or suspended.
1498 *
1499 * @returns VBox status code.
1500 * @param pVM The VM to operate on.
1501 */
1502VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1503{
1504 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1505 {
1506 PVMCPU pVCpu = &pVM->aCpus[i];
1507
1508#ifdef VBOX_WITH_STATISTICS
1509 if (pVCpu->hwaccm.s.paStatExitReason)
1510 {
1511 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1512 pVCpu->hwaccm.s.paStatExitReason = NULL;
1513 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1514 }
1515 if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1516 {
1517 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1518 pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1519 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1520 }
1521#endif
1522
1523#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1524 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1525 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1526 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1527#endif
1528 }
1529 return 0;
1530}
1531
1532/**
1533 * Resets a virtual CPU.
1534 *
1535 * Used by HWACCMR3Reset and CPU hot plugging.
1536 *
1537 * @param pVCpu The CPU to reset.
1538 */
1539VMMR3DECL(void) HWACCMR3ResetCpu(PVMCPU pVCpu)
1540{
1541 /* On first entry we'll sync everything. */
1542 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1543
1544 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1545 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1546
1547 pVCpu->hwaccm.s.fActive = false;
1548 pVCpu->hwaccm.s.Event.fPending = false;
1549
1550 /* Reset state information for real-mode emulation in VT-x. */
1551 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1552 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1553 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1554
1555 /* Reset the contents of the read cache. */
1556 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1557 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1558 pCache->Read.aFieldVal[j] = 0;
1559
1560#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1561 /* Magic marker for searching in crash dumps. */
1562 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1563 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1564#endif
1565}
1566
1567/**
1568 * The VM is being reset.
1569 *
1570 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1571 * needs to be removed.
1572 *
1573 * @param pVM VM handle.
1574 */
1575VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1576{
1577 LogFlow(("HWACCMR3Reset:\n"));
1578
1579 if (pVM->fHWACCMEnabled)
1580 hwaccmR3DisableRawMode(pVM);
1581
1582 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1583 {
1584 PVMCPU pVCpu = &pVM->aCpus[i];
1585
1586 HWACCMR3ResetCpu(pVCpu);
1587 }
1588
1589 /* Clear all patch information. */
1590 pVM->hwaccm.s.pGuestPatchMem = 0;
1591 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1592 pVM->hwaccm.s.cbGuestPatchMem = 0;
1593 pVM->hwaccm.s.cPatches = 0;
1594 pVM->hwaccm.s.PatchTree = 0;
1595 pVM->hwaccm.s.fTPRPatchingActive = false;
1596 ASMMemZero32(pVM->hwaccm.s.aPatches, sizeof(pVM->hwaccm.s.aPatches));
1597}
1598
1599/**
1600 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1601 *
1602 * @returns VBox strict status code.
1603 * @param pVM The VM handle.
1604 * @param pVCpu The VMCPU for the EMT we're being called on.
1605 * @param pvUser Unused
1606 *
1607 */
1608DECLCALLBACK(VBOXSTRICTRC) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1609{
1610 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1611
1612 /* Only execute the handler on the VCPU the original patch request was issued. */
1613 if (pVCpu->idCpu != idCpu)
1614 return VINF_SUCCESS;
1615
1616 Log(("hwaccmR3RemovePatches\n"));
1617 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
1618 {
1619 uint8_t szInstr[15];
1620 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
1621 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1622 int rc;
1623
1624#ifdef LOG_ENABLED
1625 char szOutput[256];
1626
1627 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1628 if (RT_SUCCESS(rc))
1629 Log(("Patched instr: %s\n", szOutput));
1630#endif
1631
1632 /* Check if the instruction is still the same. */
1633 rc = PGMPhysSimpleReadGCPtr(pVCpu, szInstr, pInstrGC, pPatch->cbNewOp);
1634 if (rc != VINF_SUCCESS)
1635 {
1636 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1637 continue; /* swapped out or otherwise removed; skip it. */
1638 }
1639
1640 if (memcmp(szInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1641 {
1642 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1643 continue; /* skip it. */
1644 }
1645
1646 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1647 AssertRC(rc);
1648
1649#ifdef LOG_ENABLED
1650 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1651 if (RT_SUCCESS(rc))
1652 Log(("Original instr: %s\n", szOutput));
1653#endif
1654 }
1655 pVM->hwaccm.s.cPatches = 0;
1656 pVM->hwaccm.s.PatchTree = 0;
1657 pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1658 pVM->hwaccm.s.fTPRPatchingActive = false;
1659 return VINF_SUCCESS;
1660}
1661
1662/**
1663 * Enable patching in a VT-x/AMD-V guest
1664 *
1665 * @returns VBox status code.
1666 * @param pVM The VM to operate on.
1667 * @param idCpu VCPU to execute hwaccmR3RemovePatches on
1668 * @param pPatchMem Patch memory range
1669 * @param cbPatchMem Size of the memory range
1670 */
1671int hwaccmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1672{
1673 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)idCpu);
1674 AssertRC(rc);
1675
1676 pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1677 pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1678 pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1679 return VINF_SUCCESS;
1680}
1681
1682/**
1683 * Enable patching in a VT-x/AMD-V guest
1684 *
1685 * @returns VBox status code.
1686 * @param pVM The VM to operate on.
1687 * @param pPatchMem Patch memory range
1688 * @param cbPatchMem Size of the memory range
1689 */
1690VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1691{
1692 Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1693 if (pVM->cCpus > 1)
1694 {
1695 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1696 int rc = VMR3ReqCallNoWaitU(pVM->pUVM, VMCPUID_ANY_QUEUE,
1697 (PFNRT)hwaccmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1698 AssertRC(rc);
1699 return rc;
1700 }
1701 return hwaccmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1702}
1703
1704/**
1705 * Disable patching in a VT-x/AMD-V guest
1706 *
1707 * @returns VBox status code.
1708 * @param pVM The VM to operate on.
1709 * @param pPatchMem Patch memory range
1710 * @param cbPatchMem Size of the memory range
1711 */
1712VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1713{
1714 Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1715
1716 Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1717 Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1718
1719 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1720 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)VMMGetCpuId(pVM));
1721 AssertRC(rc);
1722
1723 pVM->hwaccm.s.pGuestPatchMem = 0;
1724 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1725 pVM->hwaccm.s.cbGuestPatchMem = 0;
1726 pVM->hwaccm.s.fTPRPatchingActive = false;
1727 return VINF_SUCCESS;
1728}
1729
1730
1731/**
1732 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1733 *
1734 * @returns VBox strict status code.
1735 * @param pVM The VM handle.
1736 * @param pVCpu The VMCPU for the EMT we're being called on.
1737 * @param pvUser User specified CPU context
1738 *
1739 */
1740DECLCALLBACK(VBOXSTRICTRC) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1741{
1742 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1743 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1744 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1745 unsigned cbOp;
1746
1747 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1748 if (pVCpu->idCpu != idCpu)
1749 return VINF_SUCCESS;
1750
1751 Log(("hwaccmR3ReplaceTprInstr: %RGv\n", pCtx->rip));
1752
1753 /* Two or more VCPUs were racing to patch this instruction. */
1754 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1755 if (pPatch)
1756 return VINF_SUCCESS;
1757
1758 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1759
1760 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1761 AssertRC(rc);
1762 if ( rc == VINF_SUCCESS
1763 && pDis->pCurInstr->opcode == OP_MOV
1764 && cbOp >= 3)
1765 {
1766 uint8_t aVMMCall[3] = { 0xf, 0x1, 0xd9};
1767 uint32_t idx = pVM->hwaccm.s.cPatches;
1768
1769 pPatch = &pVM->hwaccm.s.aPatches[idx];
1770
1771 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1772 AssertRC(rc);
1773
1774 pPatch->cbOp = cbOp;
1775
1776 if (pDis->param1.flags == USE_DISPLACEMENT32)
1777 {
1778 /* write. */
1779 if (pDis->param2.flags == USE_REG_GEN32)
1780 {
1781 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1782 pPatch->uSrcOperand = pDis->param2.base.reg_gen;
1783 }
1784 else
1785 {
1786 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1787 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1788 pPatch->uSrcOperand = pDis->param2.parval;
1789 }
1790 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1791 AssertRC(rc);
1792
1793 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1794 pPatch->cbNewOp = sizeof(aVMMCall);
1795 }
1796 else
1797 {
1798 RTGCPTR oldrip = pCtx->rip;
1799 uint32_t oldcbOp = cbOp;
1800 uint32_t uMmioReg = pDis->param1.base.reg_gen;
1801
1802 /* read */
1803 Assert(pDis->param1.flags == USE_REG_GEN32);
1804
1805 /* Found:
1806 * mov eax, dword [fffe0080] (5 bytes)
1807 * Check if next instruction is:
1808 * shr eax, 4
1809 */
1810 pCtx->rip += cbOp;
1811 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1812 pCtx->rip = oldrip;
1813 if ( rc == VINF_SUCCESS
1814 && pDis->pCurInstr->opcode == OP_SHR
1815 && pDis->param1.flags == USE_REG_GEN32
1816 && pDis->param1.base.reg_gen == uMmioReg
1817 && pDis->param2.flags == USE_IMMEDIATE8
1818 && pDis->param2.parval == 4
1819 && oldcbOp + cbOp < sizeof(pVM->hwaccm.s.aPatches[idx].aOpcode))
1820 {
1821 uint8_t szInstr[15];
1822
1823 /* Replacing two instructions now. */
1824 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, oldcbOp + cbOp);
1825 AssertRC(rc);
1826
1827 pPatch->cbOp = oldcbOp + cbOp;
1828
1829 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1830 szInstr[0] = 0xF0;
1831 szInstr[1] = 0x0F;
1832 szInstr[2] = 0x20;
1833 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
1834 for (unsigned i = 4; i < pPatch->cbOp; i++)
1835 szInstr[i] = 0x90; /* nop */
1836
1837 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, pPatch->cbOp);
1838 AssertRC(rc);
1839
1840 memcpy(pPatch->aNewOpcode, szInstr, pPatch->cbOp);
1841 pPatch->cbNewOp = pPatch->cbOp;
1842
1843 Log(("Acceptable read/shr candidate!\n"));
1844 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1845 }
1846 else
1847 {
1848 pPatch->enmType = HWACCMTPRINSTR_READ;
1849 pPatch->uDstOperand = pDis->param1.base.reg_gen;
1850
1851 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1852 AssertRC(rc);
1853
1854 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1855 pPatch->cbNewOp = sizeof(aVMMCall);
1856 }
1857 }
1858
1859 pPatch->Core.Key = pCtx->eip;
1860 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1861 AssertRC(rc);
1862
1863 pVM->hwaccm.s.cPatches++;
1864 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceSuccess);
1865 return VINF_SUCCESS;
1866 }
1867
1868 /* Save invalid patch, so we will not try again. */
1869 uint32_t idx = pVM->hwaccm.s.cPatches;
1870
1871#ifdef LOG_ENABLED
1872 char szOutput[256];
1873 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1874 if (RT_SUCCESS(rc))
1875 Log(("Failed to patch instr: %s\n", szOutput));
1876#endif
1877
1878 pPatch = &pVM->hwaccm.s.aPatches[idx];
1879 pPatch->Core.Key = pCtx->eip;
1880 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1881 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1882 AssertRC(rc);
1883 pVM->hwaccm.s.cPatches++;
1884 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceFailure);
1885 return VINF_SUCCESS;
1886}
1887
1888/**
1889 * Callback to patch a TPR instruction (jump to generated code)
1890 *
1891 * @returns VBox strict status code.
1892 * @param pVM The VM handle.
1893 * @param pVCpu The VMCPU for the EMT we're being called on.
1894 * @param pvUser User specified CPU context
1895 *
1896 */
1897DECLCALLBACK(VBOXSTRICTRC) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1898{
1899 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1900 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1901 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1902 unsigned cbOp;
1903 int rc;
1904#ifdef LOG_ENABLED
1905 RTGCPTR pInstr;
1906 char szOutput[256];
1907#endif
1908
1909 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1910 if (pVCpu->idCpu != idCpu)
1911 return VINF_SUCCESS;
1912
1913 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1914
1915 /* Two or more VCPUs were racing to patch this instruction. */
1916 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1917 if (pPatch)
1918 {
1919 Log(("hwaccmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
1920 return VINF_SUCCESS;
1921 }
1922
1923 Log(("hwaccmR3PatchTprInstr %RGv\n", pCtx->rip));
1924
1925 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1926 AssertRC(rc);
1927 if ( rc == VINF_SUCCESS
1928 && pDis->pCurInstr->opcode == OP_MOV
1929 && cbOp >= 5)
1930 {
1931 uint32_t idx = pVM->hwaccm.s.cPatches;
1932 uint8_t aPatch[64];
1933 uint32_t off = 0;
1934
1935 pPatch = &pVM->hwaccm.s.aPatches[idx];
1936
1937#ifdef LOG_ENABLED
1938 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1939 if (RT_SUCCESS(rc))
1940 Log(("Original instr: %s\n", szOutput));
1941#endif
1942
1943 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1944 AssertRC(rc);
1945
1946 pPatch->cbOp = cbOp;
1947 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
1948
1949 if (pDis->param1.flags == USE_DISPLACEMENT32)
1950 {
1951 /*
1952 * TPR write:
1953 *
1954 * push ECX [51]
1955 * push EDX [52]
1956 * push EAX [50]
1957 * xor EDX,EDX [31 D2]
1958 * mov EAX,EAX [89 C0]
1959 * or
1960 * mov EAX,0000000CCh [B8 CC 00 00 00]
1961 * mov ECX,0C0000082h [B9 82 00 00 C0]
1962 * wrmsr [0F 30]
1963 * pop EAX [58]
1964 * pop EDX [5A]
1965 * pop ECX [59]
1966 * jmp return_address [E9 return_address]
1967 *
1968 */
1969 bool fUsesEax = (pDis->param2.flags == USE_REG_GEN32 && pDis->param2.base.reg_gen == USE_REG_EAX);
1970
1971 aPatch[off++] = 0x51; /* push ecx */
1972 aPatch[off++] = 0x52; /* push edx */
1973 if (!fUsesEax)
1974 aPatch[off++] = 0x50; /* push eax */
1975 aPatch[off++] = 0x31; /* xor edx, edx */
1976 aPatch[off++] = 0xD2;
1977 if (pDis->param2.flags == USE_REG_GEN32)
1978 {
1979 if (!fUsesEax)
1980 {
1981 aPatch[off++] = 0x89; /* mov eax, src_reg */
1982 aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, USE_REG_EAX);
1983 }
1984 }
1985 else
1986 {
1987 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1988 aPatch[off++] = 0xB8; /* mov eax, immediate */
1989 *(uint32_t *)&aPatch[off] = pDis->param2.parval;
1990 off += sizeof(uint32_t);
1991 }
1992 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1993 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1994 off += sizeof(uint32_t);
1995
1996 aPatch[off++] = 0x0F; /* wrmsr */
1997 aPatch[off++] = 0x30;
1998 if (!fUsesEax)
1999 aPatch[off++] = 0x58; /* pop eax */
2000 aPatch[off++] = 0x5A; /* pop edx */
2001 aPatch[off++] = 0x59; /* pop ecx */
2002 }
2003 else
2004 {
2005 /*
2006 * TPR read:
2007 *
2008 * push ECX [51]
2009 * push EDX [52]
2010 * push EAX [50]
2011 * mov ECX,0C0000082h [B9 82 00 00 C0]
2012 * rdmsr [0F 32]
2013 * mov EAX,EAX [89 C0]
2014 * pop EAX [58]
2015 * pop EDX [5A]
2016 * pop ECX [59]
2017 * jmp return_address [E9 return_address]
2018 *
2019 */
2020 Assert(pDis->param1.flags == USE_REG_GEN32);
2021
2022 if (pDis->param1.base.reg_gen != USE_REG_ECX)
2023 aPatch[off++] = 0x51; /* push ecx */
2024 if (pDis->param1.base.reg_gen != USE_REG_EDX)
2025 aPatch[off++] = 0x52; /* push edx */
2026 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2027 aPatch[off++] = 0x50; /* push eax */
2028
2029 aPatch[off++] = 0x31; /* xor edx, edx */
2030 aPatch[off++] = 0xD2;
2031
2032 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2033 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2034 off += sizeof(uint32_t);
2035
2036 aPatch[off++] = 0x0F; /* rdmsr */
2037 aPatch[off++] = 0x32;
2038
2039 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2040 {
2041 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2042 aPatch[off++] = MAKE_MODRM(3, USE_REG_EAX, pDis->param1.base.reg_gen);
2043 }
2044
2045 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2046 aPatch[off++] = 0x58; /* pop eax */
2047 if (pDis->param1.base.reg_gen != USE_REG_EDX)
2048 aPatch[off++] = 0x5A; /* pop edx */
2049 if (pDis->param1.base.reg_gen != USE_REG_ECX)
2050 aPatch[off++] = 0x59; /* pop ecx */
2051 }
2052 aPatch[off++] = 0xE9; /* jmp return_address */
2053 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
2054 off += sizeof(RTRCUINTPTR);
2055
2056 if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
2057 {
2058 /* Write new code to the patch buffer. */
2059 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
2060 AssertRC(rc);
2061
2062#ifdef LOG_ENABLED
2063 pInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
2064 while (true)
2065 {
2066 uint32_t cb;
2067
2068 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pInstr, 0, szOutput, sizeof(szOutput), &cb);
2069 if (RT_SUCCESS(rc))
2070 Log(("Patch instr %s\n", szOutput));
2071
2072 pInstr += cb;
2073
2074 if (pInstr >= pVM->hwaccm.s.pFreeGuestPatchMem + off)
2075 break;
2076 }
2077#endif
2078
2079 pPatch->aNewOpcode[0] = 0xE9;
2080 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2081
2082 /* Overwrite the TPR instruction with a jump. */
2083 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2084 AssertRC(rc);
2085
2086#ifdef LOG_ENABLED
2087 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
2088 if (RT_SUCCESS(rc))
2089 Log(("Jump: %s\n", szOutput));
2090#endif
2091 pVM->hwaccm.s.pFreeGuestPatchMem += off;
2092 pPatch->cbNewOp = 5;
2093
2094 pPatch->Core.Key = pCtx->eip;
2095 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2096 AssertRC(rc);
2097
2098 pVM->hwaccm.s.cPatches++;
2099 pVM->hwaccm.s.fTPRPatchingActive = true;
2100 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchSuccess);
2101 return VINF_SUCCESS;
2102 }
2103 else
2104 Log(("Ran out of space in our patch buffer!\n"));
2105 }
2106
2107 /* Save invalid patch, so we will not try again. */
2108 uint32_t idx = pVM->hwaccm.s.cPatches;
2109
2110#ifdef LOG_ENABLED
2111 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
2112 if (RT_SUCCESS(rc))
2113 Log(("Failed to patch instr: %s\n", szOutput));
2114#endif
2115
2116 pPatch = &pVM->hwaccm.s.aPatches[idx];
2117 pPatch->Core.Key = pCtx->eip;
2118 pPatch->enmType = HWACCMTPRINSTR_INVALID;
2119 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2120 AssertRC(rc);
2121 pVM->hwaccm.s.cPatches++;
2122 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchFailure);
2123 return VINF_SUCCESS;
2124}
2125
2126/**
2127 * Attempt to patch TPR mmio instructions
2128 *
2129 * @returns VBox status code.
2130 * @param pVM The VM to operate on.
2131 * @param pVCpu The VM CPU to operate on.
2132 * @param pCtx CPU context
2133 */
2134VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2135{
2136 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, (pVM->hwaccm.s.pGuestPatchMem) ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr, (void *)pVCpu->idCpu);
2137 AssertRC(rc);
2138 return rc;
2139}
2140
2141/**
2142 * Force execution of the current IO code in the recompiler
2143 *
2144 * @returns VBox status code.
2145 * @param pVM The VM to operate on.
2146 * @param pCtx Partial VM execution context
2147 */
2148VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2149{
2150 PVMCPU pVCpu = VMMGetCpu(pVM);
2151
2152 Assert(pVM->fHWACCMEnabled);
2153 Log(("HWACCMR3EmulateIoBlock\n"));
2154
2155 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2156 if (HWACCMCanEmulateIoBlockEx(pCtx))
2157 {
2158 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
2159 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
2160 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2161 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2162 return VINF_EM_RESCHEDULE_REM;
2163 }
2164 return VINF_SUCCESS;
2165}
2166
2167/**
2168 * Checks if we can currently use hardware accelerated raw mode.
2169 *
2170 * @returns boolean
2171 * @param pVM The VM to operate on.
2172 * @param pCtx Partial VM execution context
2173 */
2174VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2175{
2176 PVMCPU pVCpu = VMMGetCpu(pVM);
2177
2178 Assert(pVM->fHWACCMEnabled);
2179
2180 /* If we're still executing the IO code, then return false. */
2181 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
2182 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2183 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2184 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
2185 return false;
2186
2187 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
2188
2189 /* AMD-V supports real & protected mode with or without paging. */
2190 if (pVM->hwaccm.s.svm.fEnabled)
2191 {
2192 pVCpu->hwaccm.s.fActive = true;
2193 return true;
2194 }
2195
2196 pVCpu->hwaccm.s.fActive = false;
2197
2198 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2199 Assert((pVM->hwaccm.s.vmx.fUnrestrictedGuest && !pVM->hwaccm.s.vmx.pRealModeTSS) || (!pVM->hwaccm.s.vmx.fUnrestrictedGuest && pVM->hwaccm.s.vmx.pRealModeTSS));
2200
2201 bool fSupportsRealMode = pVM->hwaccm.s.vmx.fUnrestrictedGuest || PDMVMMDevHeapIsEnabled(pVM);
2202 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2203 {
2204 /** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. */
2205 if (fSupportsRealMode)
2206 {
2207 if (CPUMIsGuestInRealModeEx(pCtx))
2208 {
2209 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
2210 * The base must also be equal to (sel << 4).
2211 */
2212 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
2213 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
2214 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
2215 || pCtx->es != (pCtx->esHid.u64Base >> 4)
2216 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
2217 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
2218 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
2219 {
2220 return false;
2221 }
2222 }
2223 else
2224 {
2225 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2226 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
2227 * from real to protected mode. (all sorts of RPL & DPL assumptions)
2228 */
2229 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2230 && enmGuestMode >= PGMMODE_PROTECTED)
2231 {
2232 if ( (pCtx->cs & X86_SEL_RPL)
2233 || (pCtx->ds & X86_SEL_RPL)
2234 || (pCtx->es & X86_SEL_RPL)
2235 || (pCtx->fs & X86_SEL_RPL)
2236 || (pCtx->gs & X86_SEL_RPL)
2237 || (pCtx->ss & X86_SEL_RPL))
2238 {
2239 return false;
2240 }
2241 }
2242 }
2243 }
2244 else
2245 {
2246 if ( !CPUMIsGuestInLongModeEx(pCtx)
2247 && !pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2248 {
2249 /** @todo This should (probably) be set on every excursion to the REM,
2250 * however it's too risky right now. So, only apply it when we go
2251 * back to REM for real mode execution. (The XP hack below doesn't
2252 * work reliably without this.)
2253 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2254 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2255
2256 if ( !pVM->hwaccm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap*/
2257 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2258 return false;
2259
2260 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2261 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
2262 return false;
2263
2264 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2265 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2266 * hidden registers (possible recompiler bug; see load_seg_vm) */
2267 if (pCtx->csHid.Attr.n.u1Present == 0)
2268 return false;
2269 if (pCtx->ssHid.Attr.n.u1Present == 0)
2270 return false;
2271
2272 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2273 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2274 /** @todo This check is actually wrong, it doesn't take the direction of the
2275 * stack segment into account. But, it does the job for now. */
2276 if (pCtx->rsp >= pCtx->ssHid.u32Limit)
2277 return false;
2278 #if 0
2279 if ( pCtx->cs >= pCtx->gdtr.cbGdt
2280 || pCtx->ss >= pCtx->gdtr.cbGdt
2281 || pCtx->ds >= pCtx->gdtr.cbGdt
2282 || pCtx->es >= pCtx->gdtr.cbGdt
2283 || pCtx->fs >= pCtx->gdtr.cbGdt
2284 || pCtx->gs >= pCtx->gdtr.cbGdt)
2285 return false;
2286 #endif
2287 }
2288 }
2289 }
2290
2291 if (pVM->hwaccm.s.vmx.fEnabled)
2292 {
2293 uint32_t mask;
2294
2295 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2296 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2297 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2298 mask &= ~X86_CR0_NE;
2299
2300 if (fSupportsRealMode)
2301 {
2302 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2303 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2304 }
2305 else
2306 {
2307 /* We support protected mode without paging using identity mapping. */
2308 mask &= ~X86_CR0_PG;
2309 }
2310 if ((pCtx->cr0 & mask) != mask)
2311 return false;
2312
2313 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2314 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2315 if ((pCtx->cr0 & mask) != 0)
2316 return false;
2317
2318 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2319 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2320 mask &= ~X86_CR4_VMXE;
2321 if ((pCtx->cr4 & mask) != mask)
2322 return false;
2323
2324 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2325 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2326 if ((pCtx->cr4 & mask) != 0)
2327 return false;
2328
2329 pVCpu->hwaccm.s.fActive = true;
2330 return true;
2331 }
2332
2333 return false;
2334}
2335
2336/**
2337 * Checks if we need to reschedule due to VMM device heap changes
2338 *
2339 * @returns boolean
2340 * @param pVM The VM to operate on.
2341 * @param pCtx VM execution context
2342 */
2343VMMR3DECL(bool) HWACCMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2344{
2345 /** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. (VT-x only) */
2346 if ( pVM->hwaccm.s.vmx.fEnabled
2347 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2348 && !PDMVMMDevHeapIsEnabled(pVM)
2349 && (pVM->hwaccm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2350 return true;
2351
2352 return false;
2353}
2354
2355
2356/**
2357 * Notifcation from EM about a rescheduling into hardware assisted execution
2358 * mode.
2359 *
2360 * @param pVCpu Pointer to the current virtual cpu structure.
2361 */
2362VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2363{
2364 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2365}
2366
2367/**
2368 * Notifcation from EM about returning from instruction emulation (REM / EM).
2369 *
2370 * @param pVCpu Pointer to the current virtual cpu structure.
2371 */
2372VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2373{
2374 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2375}
2376
2377/**
2378 * Checks if we are currently using hardware accelerated raw mode.
2379 *
2380 * @returns boolean
2381 * @param pVCpu The VMCPU to operate on.
2382 */
2383VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2384{
2385 return pVCpu->hwaccm.s.fActive;
2386}
2387
2388/**
2389 * Checks if we are currently using nested paging.
2390 *
2391 * @returns boolean
2392 * @param pVM The VM to operate on.
2393 */
2394VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2395{
2396 return pVM->hwaccm.s.fNestedPaging;
2397}
2398
2399/**
2400 * Checks if we are currently using VPID in VT-x mode.
2401 *
2402 * @returns boolean
2403 * @param pVM The VM to operate on.
2404 */
2405VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2406{
2407 return pVM->hwaccm.s.vmx.fVPID;
2408}
2409
2410
2411/**
2412 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2413 *
2414 * @returns boolean
2415 * @param pVM The VM to operate on.
2416 */
2417VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2418{
2419 return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2420}
2421
2422/**
2423 * Restart an I/O instruction that was refused in ring-0
2424 *
2425 * @returns Strict VBox status code. Informational status codes other than the one documented
2426 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2427 * @retval VINF_SUCCESS Success.
2428 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2429 * status code must be passed on to EM.
2430 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2431 *
2432 * @param pVM The VM to operate on.
2433 * @param pVCpu The VMCPU to operate on.
2434 * @param pCtx VCPU register context
2435 */
2436VMMR3DECL(VBOXSTRICTRC) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2437{
2438 HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2439
2440 pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2441
2442 if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2443 || enmType == HWACCMPENDINGIO_INVALID)
2444 return VERR_NOT_FOUND;
2445
2446 VBOXSTRICTRC rcStrict;
2447 switch (enmType)
2448 {
2449 case HWACCMPENDINGIO_PORT_READ:
2450 {
2451 uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2452 uint32_t u32Val = 0;
2453
2454 rcStrict = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2455 &u32Val,
2456 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2457 if (IOM_SUCCESS(rcStrict))
2458 {
2459 /* Write back to the EAX register. */
2460 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2461 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2462 }
2463 break;
2464 }
2465
2466 case HWACCMPENDINGIO_PORT_WRITE:
2467 rcStrict = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2468 pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2469 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2470 if (IOM_SUCCESS(rcStrict))
2471 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2472 break;
2473
2474 default:
2475 AssertFailed();
2476 return VERR_INTERNAL_ERROR;
2477 }
2478
2479 return rcStrict;
2480}
2481
2482/**
2483 * Inject an NMI into a running VM (only VCPU 0!)
2484 *
2485 * @returns boolean
2486 * @param pVM The VM to operate on.
2487 */
2488VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2489{
2490 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2491 return VINF_SUCCESS;
2492}
2493
2494/**
2495 * Check fatal VT-x/AMD-V error and produce some meaningful
2496 * log release message.
2497 *
2498 * @param pVM The VM to operate on.
2499 * @param iStatusCode VBox status code
2500 */
2501VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2502{
2503 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2504 {
2505 switch(iStatusCode)
2506 {
2507 case VERR_VMX_INVALID_VMCS_FIELD:
2508 break;
2509
2510 case VERR_VMX_INVALID_VMCS_PTR:
2511 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
2512 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2513 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2514 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2515 break;
2516
2517 case VERR_VMX_UNABLE_TO_START_VM:
2518 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2519 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2520#if 0 /* @todo dump the current control fields to the release log */
2521 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2522 {
2523
2524 }
2525#endif
2526 break;
2527
2528 case VERR_VMX_UNABLE_TO_RESUME_VM:
2529 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2530 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2531 break;
2532
2533 case VERR_VMX_INVALID_VMXON_PTR:
2534 break;
2535 }
2536 }
2537}
2538
2539/**
2540 * Execute state save operation.
2541 *
2542 * @returns VBox status code.
2543 * @param pVM VM Handle.
2544 * @param pSSM SSM operation handle.
2545 */
2546static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2547{
2548 int rc;
2549
2550 Log(("hwaccmR3Save:\n"));
2551
2552 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2553 {
2554 /*
2555 * Save the basic bits - fortunately all the other things can be resynced on load.
2556 */
2557 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2558 AssertRCReturn(rc, rc);
2559 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2560 AssertRCReturn(rc, rc);
2561 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2562 AssertRCReturn(rc, rc);
2563
2564 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2565 AssertRCReturn(rc, rc);
2566 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2567 AssertRCReturn(rc, rc);
2568 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2569 AssertRCReturn(rc, rc);
2570 }
2571#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2572 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2573 AssertRCReturn(rc, rc);
2574 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2575 AssertRCReturn(rc, rc);
2576 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2577 AssertRCReturn(rc, rc);
2578
2579 /* Store all the guest patch records too. */
2580 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cPatches);
2581 AssertRCReturn(rc, rc);
2582
2583 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2584 {
2585 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2586
2587 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2588 AssertRCReturn(rc, rc);
2589
2590 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2591 AssertRCReturn(rc, rc);
2592
2593 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2594 AssertRCReturn(rc, rc);
2595
2596 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2597 AssertRCReturn(rc, rc);
2598
2599 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2600 AssertRCReturn(rc, rc);
2601
2602 AssertCompileSize(HWACCMTPRINSTR, 4);
2603 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2604 AssertRCReturn(rc, rc);
2605
2606 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2607 AssertRCReturn(rc, rc);
2608
2609 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2610 AssertRCReturn(rc, rc);
2611
2612 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2613 AssertRCReturn(rc, rc);
2614
2615 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2616 AssertRCReturn(rc, rc);
2617 }
2618#endif
2619 return VINF_SUCCESS;
2620}
2621
2622/**
2623 * Execute state load operation.
2624 *
2625 * @returns VBox status code.
2626 * @param pVM VM Handle.
2627 * @param pSSM SSM operation handle.
2628 * @param uVersion Data layout version.
2629 * @param uPass The data pass.
2630 */
2631static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2632{
2633 int rc;
2634
2635 Log(("hwaccmR3Load:\n"));
2636 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2637
2638 /*
2639 * Validate version.
2640 */
2641 if ( uVersion != HWACCM_SSM_VERSION
2642 && uVersion != HWACCM_SSM_VERSION_NO_PATCHING
2643 && uVersion != HWACCM_SSM_VERSION_2_0_X)
2644 {
2645 AssertMsgFailed(("hwaccmR3Load: Invalid version uVersion=%d!\n", uVersion));
2646 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2647 }
2648 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2649 {
2650 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2651 AssertRCReturn(rc, rc);
2652 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2653 AssertRCReturn(rc, rc);
2654 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2655 AssertRCReturn(rc, rc);
2656
2657 if (uVersion >= HWACCM_SSM_VERSION_NO_PATCHING)
2658 {
2659 uint32_t val;
2660
2661 rc = SSMR3GetU32(pSSM, &val);
2662 AssertRCReturn(rc, rc);
2663 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2664
2665 rc = SSMR3GetU32(pSSM, &val);
2666 AssertRCReturn(rc, rc);
2667 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2668
2669 rc = SSMR3GetU32(pSSM, &val);
2670 AssertRCReturn(rc, rc);
2671 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2672 }
2673 }
2674#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2675 if (uVersion > HWACCM_SSM_VERSION_NO_PATCHING)
2676 {
2677 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2678 AssertRCReturn(rc, rc);
2679 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2680 AssertRCReturn(rc, rc);
2681 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2682 AssertRCReturn(rc, rc);
2683
2684 /* Fetch all TPR patch records. */
2685 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cPatches);
2686 AssertRCReturn(rc, rc);
2687
2688 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2689 {
2690 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2691
2692 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2693 AssertRCReturn(rc, rc);
2694
2695 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2696 AssertRCReturn(rc, rc);
2697
2698 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2699 AssertRCReturn(rc, rc);
2700
2701 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2702 AssertRCReturn(rc, rc);
2703
2704 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2705 AssertRCReturn(rc, rc);
2706
2707 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2708 AssertRCReturn(rc, rc);
2709
2710 if (pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT)
2711 pVM->hwaccm.s.fTPRPatchingActive = true;
2712
2713 Assert(pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT || pVM->hwaccm.s.fTPRPatchingActive == false);
2714
2715 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2716 AssertRCReturn(rc, rc);
2717
2718 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2719 AssertRCReturn(rc, rc);
2720
2721 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2722 AssertRCReturn(rc, rc);
2723
2724 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2725 AssertRCReturn(rc, rc);
2726
2727 Log(("hwaccmR3Load: patch %d\n", i));
2728 Log(("Key = %x\n", pPatch->Core.Key));
2729 Log(("cbOp = %d\n", pPatch->cbOp));
2730 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2731 Log(("type = %d\n", pPatch->enmType));
2732 Log(("srcop = %d\n", pPatch->uSrcOperand));
2733 Log(("dstop = %d\n", pPatch->uDstOperand));
2734 Log(("cFaults = %d\n", pPatch->cFaults));
2735 Log(("target = %x\n", pPatch->pJumpTarget));
2736 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2737 AssertRC(rc);
2738 }
2739 }
2740#endif
2741
2742 /* Recheck all VCPUs if we can go staight into hwaccm execution mode. */
2743 if (HWACCMIsEnabled(pVM))
2744 {
2745 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2746 {
2747 PVMCPU pVCpu = &pVM->aCpus[i];
2748
2749 HWACCMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2750 }
2751 }
2752 return VINF_SUCCESS;
2753}
2754
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