VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 34134

Last change on this file since 34134 was 33540, checked in by vboxsync, 14 years ago

*: spelling fixes, thanks Timeless!
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1/* $Id: HWACCM.cpp 33540 2010-10-28 09:27:05Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HWACCM
22#include <VBox/cpum.h>
23#include <VBox/stam.h>
24#include <VBox/mm.h>
25#include <VBox/pdmapi.h>
26#include <VBox/pgm.h>
27#include <VBox/ssm.h>
28#include <VBox/trpm.h>
29#include <VBox/dbgf.h>
30#include <VBox/iom.h>
31#include <VBox/patm.h>
32#include <VBox/csam.h>
33#include <VBox/selm.h>
34#include <VBox/rem.h>
35#include <VBox/hwacc_vmx.h>
36#include <VBox/hwacc_svm.h>
37#include "HWACCMInternal.h"
38#include <VBox/vm.h>
39#include <VBox/err.h>
40#include <VBox/param.h>
41
42#include <iprt/assert.h>
43#include <VBox/log.h>
44#include <iprt/asm.h>
45#include <iprt/asm-amd64-x86.h>
46#include <iprt/string.h>
47#include <iprt/env.h>
48#include <iprt/thread.h>
49
50/*******************************************************************************
51* Global Variables *
52*******************************************************************************/
53#ifdef VBOX_WITH_STATISTICS
54# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55# define EXIT_REASON_NIL() NULL
56/** Exit reason descriptions for VT-x, used to describe statistics. */
57static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58{
59 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67 EXIT_REASON_NIL(),
68 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94 EXIT_REASON_NIL(),
95 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96 EXIT_REASON_NIL(),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101 EXIT_REASON_NIL(),
102 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110 EXIT_REASON_NIL(),
111 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115 EXIT_REASON_NIL()
116};
117/** Exit reason descriptions for AMD-V, used to describe statistics. */
118static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119{
120 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
121 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
122 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
123 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
124 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
125 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
126 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
127 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
128 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
129 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
130 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
131 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
132 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
133 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
134 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
135 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
136 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
137 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
152 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
153 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
154 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
155 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
156 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
157 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
158 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
159 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
160 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
161 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
162 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
163 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
164 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
165 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
166 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
167 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
168 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
169 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
184 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
185 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
216 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt."),
217 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt."),
218 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt."),
219 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal."),
220 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt."),
221 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
222 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
223 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
224 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
225 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
226 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
227 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
228 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
229 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
230 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
231 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
232 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
233 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
234 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
235 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
236 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
237 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
238 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
239 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
240 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
241 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
242 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
243 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
244 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
245 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
246 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
247 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
248 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
249 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
250 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
251 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
252 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
253 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
254 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
255 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
256 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
257 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
258 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
259 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
260 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
261 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
262 EXIT_REASON_NIL()
263};
264# undef EXIT_REASON
265# undef EXIT_REASON_NIL
266#endif /* VBOX_WITH_STATISTICS */
267
268/*******************************************************************************
269* Internal Functions *
270*******************************************************************************/
271static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
272static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
273
274
275/**
276 * Initializes the HWACCM.
277 *
278 * @returns VBox status code.
279 * @param pVM The VM to operate on.
280 */
281VMMR3DECL(int) HWACCMR3Init(PVM pVM)
282{
283 LogFlow(("HWACCMR3Init\n"));
284
285 /*
286 * Assert alignment and sizes.
287 */
288 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
289 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
290
291 /* Some structure checks. */
292 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
293 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
294 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
295
296 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.TR) == 0x490, ("guest.TR offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.TR)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8CPL) == 0x4CB, ("guest.u8CPL offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8CPL)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64EFER) == 0x4D0, ("guest.u64EFER offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64EFER)));
300 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR4) == 0x548, ("guest.u64CR4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR4)));
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RIP) == 0x578, ("guest.u64RIP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RIP)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RSP) == 0x5D8, ("guest.u64RSP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RSP)));
303 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR2) == 0x640, ("guest.u64CR2 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR2)));
304 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64GPAT) == 0x668, ("guest.u64GPAT offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64GPAT)));
305 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO) == 0x690, ("guest.u64LASTEXCPTO offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO)));
306 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
307
308
309 /*
310 * Register the saved state data unit.
311 */
312 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
313 NULL, NULL, NULL,
314 NULL, hwaccmR3Save, NULL,
315 NULL, hwaccmR3Load, NULL);
316 if (RT_FAILURE(rc))
317 return rc;
318
319 /* Misc initialisation. */
320 pVM->hwaccm.s.vmx.fSupported = false;
321 pVM->hwaccm.s.svm.fSupported = false;
322 pVM->hwaccm.s.vmx.fEnabled = false;
323 pVM->hwaccm.s.svm.fEnabled = false;
324
325 pVM->hwaccm.s.fNestedPaging = false;
326 pVM->hwaccm.s.fLargePages = false;
327
328 /* Disabled by default. */
329 pVM->fHWACCMEnabled = false;
330
331 /*
332 * Check CFGM options.
333 */
334 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
335 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
336 /* Nested paging: disabled by default. */
337 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
338 AssertRC(rc);
339
340 /* Large pages: disabled by default. */
341 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hwaccm.s.fLargePages, false);
342 AssertRC(rc);
343
344 /* VT-x VPID: disabled by default. */
345 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
346 AssertRC(rc);
347
348 /* HWACCM support must be explicitely enabled in the configuration file. */
349 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
350 AssertRC(rc);
351
352 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
353 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hwaccm.s.fTRPPatchingAllowed, false);
354 AssertRC(rc);
355
356#ifdef RT_OS_DARWIN
357 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
358#else
359 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
360#endif
361 {
362 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
363 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
364 return VERR_HWACCM_CONFIG_MISMATCH;
365 }
366
367 if (VMMIsHwVirtExtForced(pVM))
368 pVM->fHWACCMEnabled = true;
369
370#if HC_ARCH_BITS == 32
371 /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
372 * (To use the default, don't set 64bitEnabled in CFGM.) */
373 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
374 AssertLogRelRCReturn(rc, rc);
375 if (pVM->hwaccm.s.fAllow64BitGuests)
376 {
377# ifdef RT_OS_DARWIN
378 if (!VMMIsHwVirtExtForced(pVM))
379# else
380 if (!pVM->hwaccm.s.fAllowed)
381# endif
382 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
383 }
384#else
385 /* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
386 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
387 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
388 AssertLogRelRCReturn(rc, rc);
389#endif
390
391
392 /** Determine the init method for AMD-V and VT-x; either one global init for each host CPU
393 * or local init each time we wish to execute guest code.
394 *
395 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
396 */
397 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hwaccm.s.fGlobalInit,
398#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
399 false
400#else
401 true
402#endif
403 );
404
405 /* Max number of resume loops. */
406 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
407 AssertRC(rc);
408
409 return VINF_SUCCESS;
410}
411
412/**
413 * Initializes the per-VCPU HWACCM.
414 *
415 * @returns VBox status code.
416 * @param pVM The VM to operate on.
417 */
418VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
419{
420 LogFlow(("HWACCMR3InitCPU\n"));
421
422 for (VMCPUID i = 0; i < pVM->cCpus; i++)
423 {
424 PVMCPU pVCpu = &pVM->aCpus[i];
425
426 pVCpu->hwaccm.s.fActive = false;
427 }
428
429#ifdef VBOX_WITH_STATISTICS
430 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
431 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
432 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
433 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
434
435 /*
436 * Statistics.
437 */
438 for (VMCPUID i = 0; i < pVM->cCpus; i++)
439 {
440 PVMCPU pVCpu = &pVM->aCpus[i];
441 int rc;
442
443 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of RTMpPokeCpu",
444 "/PROF/HWACCM/CPU%d/Poke", i);
445 AssertRC(rc);
446 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait",
447 "/PROF/HWACCM/CPU%d/PokeWait", i);
448 AssertRC(rc);
449 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait when RTMpPokeCpu fails",
450 "/PROF/HWACCM/CPU%d/PokeWaitFailed", i);
451 AssertRC(rc);
452 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
453 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
454 AssertRC(rc);
455 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
456 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
457 AssertRC(rc);
458 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
459 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
460 AssertRC(rc);
461# if 1 /* temporary for tracking down darwin holdup. */
462 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
463 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
464 AssertRC(rc);
465 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
466 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
467 AssertRC(rc);
468 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
469 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
470 AssertRC(rc);
471# endif
472 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
473 "/PROF/HWACCM/CPU%d/InGC", i);
474 AssertRC(rc);
475
476# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
477 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
478 "/PROF/HWACCM/CPU%d/Switcher3264", i);
479 AssertRC(rc);
480# endif
481
482# define HWACCM_REG_COUNTER(a, b) \
483 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
484 AssertRC(rc);
485
486 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
487 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
488 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
489 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
490 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
491 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
492 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
493 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
494 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
495 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
496 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
498 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
499 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
503 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
504 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
505 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMonitor, "/HWACCM/CPU%d/Exit/Instr/Monitor");
506 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
507 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
508 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
509 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
510 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
511 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
512 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
513 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
514 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
515 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
516 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
517 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
518 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
519 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
520 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
521 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
522 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
523 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
524
525 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
526 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
527
528 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
529 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
530 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
531
532 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPage, "/HWACCM/CPU%d/Flush/Page");
533 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
534 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
535 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLB, "/HWACCM/CPU%d/Flush/TLB");
536 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
537 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
538 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
539 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
540 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
541 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
542 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
543 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
544 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
545
546 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
547 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
548 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow, "/HWACCM/CPU%d/TSC/InterceptOverflow");
549
550 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
551 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
552 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
553
554 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatLoadMinimal, "/HWACCM/CPU%d/Load/Minimal");
555 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatLoadFull, "/HWACCM/CPU%d/Load/Full");
556
557#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
558 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFpu64SwitchBack, "/HWACCM/CPU%d/Switch64/Fpu");
559 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDebug64SwitchBack, "/HWACCM/CPU%d/Switch64/Debug");
560#endif
561
562 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
563 {
564 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
565 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
566 AssertRC(rc);
567 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
568 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
569 AssertRC(rc);
570 }
571
572#undef HWACCM_REG_COUNTER
573
574 pVCpu->hwaccm.s.paStatExitReason = NULL;
575
576 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
577 AssertRC(rc);
578 if (RT_SUCCESS(rc))
579 {
580 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
581 for (int j=0;j<MAX_EXITREASON_STAT;j++)
582 {
583 if (papszDesc[j])
584 {
585 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
586 papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
587 AssertRC(rc);
588 }
589 }
590 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
591 AssertRC(rc);
592 }
593 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
594# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
595 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
596# else
597 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
598# endif
599
600 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
601 AssertRCReturn(rc, rc);
602 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
603# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
604 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
605# else
606 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
607# endif
608 for (unsigned j = 0; j < 255; j++)
609 STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
610 (j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
611
612 }
613#endif /* VBOX_WITH_STATISTICS */
614
615#ifdef VBOX_WITH_CRASHDUMP_MAGIC
616 /* Magic marker for searching in crash dumps. */
617 for (VMCPUID i = 0; i < pVM->cCpus; i++)
618 {
619 PVMCPU pVCpu = &pVM->aCpus[i];
620
621 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
622 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
623 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
624 }
625#endif
626 return VINF_SUCCESS;
627}
628
629/**
630 * Turns off normal raw mode features
631 *
632 * @param pVM The VM to operate on.
633 */
634static void hwaccmR3DisableRawMode(PVM pVM)
635{
636 /* Disable PATM & CSAM. */
637 PATMR3AllowPatching(pVM, false);
638 CSAMDisableScanning(pVM);
639
640 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
641 SELMR3DisableMonitoring(pVM);
642 TRPMR3DisableMonitoring(pVM);
643
644 /* Disable the switcher code (safety precaution). */
645 VMMR3DisableSwitcher(pVM);
646
647 /* Disable mapping of the hypervisor into the shadow page table. */
648 PGMR3MappingsDisable(pVM);
649
650 /* Disable the switcher */
651 VMMR3DisableSwitcher(pVM);
652
653 /* Reinit the paging mode to force the new shadow mode. */
654 for (VMCPUID i = 0; i < pVM->cCpus; i++)
655 {
656 PVMCPU pVCpu = &pVM->aCpus[i];
657
658 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
659 }
660}
661
662/**
663 * Initialize VT-x or AMD-V.
664 *
665 * @returns VBox status code.
666 * @param pVM The VM handle.
667 */
668VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
669{
670 int rc;
671
672 /* Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
673 * is already using AMD-V.
674 */
675 if ( !pVM->hwaccm.s.vmx.fSupported
676 && !pVM->hwaccm.s.svm.fSupported
677 && pVM->hwaccm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
678 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
679 {
680 LogRel(("HWACCM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
681 pVM->hwaccm.s.svm.fSupported = true;
682 pVM->hwaccm.s.svm.fIgnoreInUseError = true;
683 }
684 else
685 if ( !pVM->hwaccm.s.vmx.fSupported
686 && !pVM->hwaccm.s.svm.fSupported)
687 {
688 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
689 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
690
691 if (VMMIsHwVirtExtForced(pVM))
692 {
693 switch (pVM->hwaccm.s.lLastError)
694 {
695 case VERR_VMX_NO_VMX:
696 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
697 case VERR_VMX_IN_VMX_ROOT_MODE:
698 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
699 case VERR_SVM_IN_USE:
700 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
701 case VERR_SVM_NO_SVM:
702 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
703 case VERR_SVM_DISABLED:
704 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
705 default:
706 return pVM->hwaccm.s.lLastError;
707 }
708 }
709 return VINF_SUCCESS;
710 }
711
712 if (pVM->hwaccm.s.vmx.fSupported)
713 {
714 rc = SUPR3QueryVTxSupported();
715 if (RT_FAILURE(rc))
716 {
717#ifdef RT_OS_LINUX
718 LogRel(("HWACCM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
719#else
720 LogRel(("HWACCM: The host kernel does not support VT-x!\n"));
721#endif
722 if ( pVM->cCpus > 1
723 || VMMIsHwVirtExtForced(pVM))
724 return rc;
725
726 /* silently fall back to raw mode */
727 return VINF_SUCCESS;
728 }
729 }
730
731 if (!pVM->hwaccm.s.fAllowed)
732 return VINF_SUCCESS; /* nothing to do */
733
734 /* Enable VT-x or AMD-V on all host CPUs. */
735 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
736 if (RT_FAILURE(rc))
737 {
738 LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
739 return rc;
740 }
741 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
742
743 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
744 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
745 if (!pVM->hwaccm.s.fHasIoApic)
746 {
747 Assert(!pVM->hwaccm.s.fTRPPatchingAllowed); /* paranoia */
748 pVM->hwaccm.s.fTRPPatchingAllowed = false;
749 }
750
751 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
752 if (pVM->hwaccm.s.vmx.fSupported)
753 {
754 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
755
756 if ( pVM->hwaccm.s.fInitialized == false
757 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
758 {
759 uint64_t val;
760 RTGCPHYS GCPhys = 0;
761
762 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
763 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
764 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
765 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
766 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
767 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
768 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
769 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
770
771 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
772 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
773 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
774 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
775 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
776 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
777 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
778 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
779 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
780 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
781 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
782 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
783 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
784 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
785 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
786 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
787 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
788 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
789 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
790
791 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
792 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
793 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
794 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
795 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
796 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
797 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
798 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
799 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
800 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
801 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
802 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
803 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
804 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
805 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
806 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
807 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
808 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
809 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
810 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
811 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
812 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
813 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
814 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
815 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
816 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
817 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
818 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
819 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
820 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
821 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
822 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
823 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
824 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
825 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
826 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
827 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
828 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
829 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
830 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
831 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
832 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
833 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
834 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
835
836 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
837 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
838 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
839 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
840 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
841 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
842 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
843 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
844 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
845 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
846 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
847 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
848 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
849 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
850 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
851 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
852 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
853 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
854 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
855 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
856 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
857 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
858 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
859 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
860 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
861 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
862 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
863 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
864 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
865 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
866 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
867 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
868 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
869 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
870 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
871 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
872 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
873 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
874 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
875 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
876 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
877 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
878 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
879
880 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
881 {
882 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
883 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
884 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
885 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
886 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
887 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
888 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
889 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
890 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
891 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT\n"));
892 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
893 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
894 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
895 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
896 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
897 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
898 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
899 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE\n"));
900 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
901 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT\n"));
902
903 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
904 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
905 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
906 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
907 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
908 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
909 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT *must* be set\n"));
910 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
911 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
912 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
913 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
914 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
915 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
916 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
917 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
918 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
919 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE *must* be set\n"));
920 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
921 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT *must* be set\n"));
922 }
923
924 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
925 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
926 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
927 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
928 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
929 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
930 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
931 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
932 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
933 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
934 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
935 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
936 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
937 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
938 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
939 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
940 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
941 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
942 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
943 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
944 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
945 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
946 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
947 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
948 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
949 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
950 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
951 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
952 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
953 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
954 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
955
956 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
957 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
958 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
959 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
960 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
961 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
962 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
963 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
964 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
965 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
966 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
967 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
968 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
969 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
970 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
971 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
972 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
973 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
974 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
975 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
976 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
977 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
978 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
979 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
980 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
981 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
982 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
983 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
984 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
985 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
986 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
987 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
988 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
989 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
990 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
991
992 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
993 {
994 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
995
996 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
997 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
998 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
999 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
1000 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
1001 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
1002 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
1003 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
1004 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
1005 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
1006 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
1007 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
1008 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
1009 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
1010 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
1011 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
1012 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
1013 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
1014 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
1015 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
1016 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
1017 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
1018 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
1019 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
1020 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
1021 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
1022 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
1023 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
1024 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
1025 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
1026 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
1027 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
1028 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
1029 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
1030 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
1031 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
1032 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
1033 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
1034 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
1035 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
1036 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
1037 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
1038 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
1039 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
1040 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
1041 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
1042 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
1043 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
1044 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
1045 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
1046 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
1047 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
1048 }
1049
1050 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
1051 if ( !pVM->hwaccm.s.vmx.fUsePreemptTimer
1052 || MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc) == pVM->hwaccm.s.vmx.cPreemptTimerShift)
1053 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1054 else
1055 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x - erratum detected, using %x instead\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc), pVM->hwaccm.s.vmx.cPreemptTimerShift));
1056 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1057 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1058 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1059 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1060
1061 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
1062 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
1063 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
1064 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
1065 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
1066
1067 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
1068
1069 /* Paranoia */
1070 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc) >= 512);
1071
1072 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1073 {
1074 LogRel(("HWACCM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pMSRBitmapPhys));
1075 LogRel(("HWACCM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1076 }
1077
1078#ifdef HWACCM_VTX_WITH_EPT
1079 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1080 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1081#endif /* HWACCM_VTX_WITH_EPT */
1082#ifdef HWACCM_VTX_WITH_VPID
1083 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1084 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
1085 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
1086#endif /* HWACCM_VTX_WITH_VPID */
1087
1088 /* Unrestricted guest execution relies on EPT. */
1089 if ( pVM->hwaccm.s.fNestedPaging
1090 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE))
1091 {
1092 pVM->hwaccm.s.vmx.fUnrestrictedGuest = true;
1093 }
1094
1095 /* Only try once. */
1096 pVM->hwaccm.s.fInitialized = true;
1097
1098 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1099 {
1100 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1101 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
1102 if (RT_SUCCESS(rc))
1103 {
1104 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1105 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
1106 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
1107 /* Bit set to 0 means redirection enabled. */
1108 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
1109 /* Allow all port IO, so the VT-x IO intercepts do their job. */
1110 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
1111 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
1112
1113 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1114 * real and protected mode without paging with EPT.
1115 */
1116 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1117 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
1118 {
1119 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1120 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
1121 }
1122
1123 /* We convert it here every time as pci regions could be reconfigured. */
1124 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1125 AssertRC(rc);
1126 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1127
1128 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1129 AssertRC(rc);
1130 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1131 }
1132 else
1133 {
1134 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1135 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1136 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1137 }
1138 }
1139
1140 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1141 AssertRC(rc);
1142 if (rc == VINF_SUCCESS)
1143 {
1144 pVM->fHWACCMEnabled = true;
1145 pVM->hwaccm.s.vmx.fEnabled = true;
1146 hwaccmR3DisableRawMode(pVM);
1147
1148 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1149#ifdef VBOX_ENABLE_64_BITS_GUESTS
1150 if (pVM->hwaccm.s.fAllow64BitGuests)
1151 {
1152 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1153 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1154 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1155 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1156 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1157 }
1158 else
1159 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1160 /* Todo: this needs to be fixed properly!! */
1161 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1162 && (pVM->hwaccm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1163 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1164
1165 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1166 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1167 : "HWACCM: 32-bit guests supported.\n"));
1168#else
1169 LogRel(("HWACCM: 32-bit guests supported.\n"));
1170#endif
1171 LogRel(("HWACCM: VMX enabled!\n"));
1172 if (pVM->hwaccm.s.fNestedPaging)
1173 {
1174 LogRel(("HWACCM: Enabled nested paging\n"));
1175 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1176 if (pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1177 LogRel(("HWACCM: Unrestricted guest execution enabled!\n"));
1178
1179#if HC_ARCH_BITS == 64
1180 if (pVM->hwaccm.s.fLargePages)
1181 {
1182 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1183 PGMSetLargePageUsage(pVM, true);
1184 LogRel(("HWACCM: Large page support enabled!\n"));
1185 }
1186#endif
1187 }
1188 else
1189 Assert(!pVM->hwaccm.s.vmx.fUnrestrictedGuest);
1190
1191 if (pVM->hwaccm.s.vmx.fVPID)
1192 LogRel(("HWACCM: Enabled VPID\n"));
1193
1194 if ( pVM->hwaccm.s.fNestedPaging
1195 || pVM->hwaccm.s.vmx.fVPID)
1196 {
1197 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1198 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1199 }
1200
1201 /* TPR patching status logging. */
1202 if (pVM->hwaccm.s.fTRPPatchingAllowed)
1203 {
1204 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1205 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1206 {
1207 pVM->hwaccm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1208 LogRel(("HWACCM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1209 }
1210 else
1211 {
1212 uint32_t u32Eax, u32Dummy;
1213
1214 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1215 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1216 if ( u32Eax < 0x80000001
1217 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1218 {
1219 pVM->hwaccm.s.fTRPPatchingAllowed = false;
1220 LogRel(("HWACCM: TPR patching disabled (long mode not supported).\n"));
1221 }
1222 }
1223 }
1224 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1225 }
1226 else
1227 {
1228 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1229 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1230 pVM->fHWACCMEnabled = false;
1231 }
1232 }
1233 }
1234 else
1235 if (pVM->hwaccm.s.svm.fSupported)
1236 {
1237 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1238
1239 if (pVM->hwaccm.s.fInitialized == false)
1240 {
1241 /* Erratum 170 which requires a forced TLB flush for each world switch:
1242 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1243 *
1244 * All BH-G1/2 and DH-G1/2 models include a fix:
1245 * Athlon X2: 0x6b 1/2
1246 * 0x68 1/2
1247 * Athlon 64: 0x7f 1
1248 * 0x6f 2
1249 * Sempron: 0x7f 1/2
1250 * 0x6f 2
1251 * 0x6c 2
1252 * 0x7c 2
1253 * Turion 64: 0x68 2
1254 *
1255 */
1256 uint32_t u32Dummy;
1257 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1258 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1259 u32BaseFamily= (u32Version >> 8) & 0xf;
1260 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1261 u32Model = ((u32Version >> 4) & 0xf);
1262 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1263 u32Stepping = u32Version & 0xf;
1264 if ( u32Family == 0xf
1265 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1266 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1267 {
1268 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1269 }
1270
1271 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1272 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1273 LogRel(("HWACCM: AMD HWCR MSR = %RX64\n", pVM->hwaccm.s.svm.msrHWCR));
1274 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1275 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1276 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1277
1278 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1279 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
1280 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
1281 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
1282 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
1283 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
1284 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
1285 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
1286 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
1287 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
1288 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER)
1289 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER\n"));
1290
1291 /* Only try once. */
1292 pVM->hwaccm.s.fInitialized = true;
1293
1294 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1295 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1296
1297 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1298 AssertRC(rc);
1299 if (rc == VINF_SUCCESS)
1300 {
1301 pVM->fHWACCMEnabled = true;
1302 pVM->hwaccm.s.svm.fEnabled = true;
1303
1304 if (pVM->hwaccm.s.fNestedPaging)
1305 {
1306 LogRel(("HWACCM: Enabled nested paging\n"));
1307#if HC_ARCH_BITS == 64
1308 if (pVM->hwaccm.s.fLargePages)
1309 {
1310 /* Use large (2 MB) pages for our nested paging PDEs where possible. */
1311 PGMSetLargePageUsage(pVM, true);
1312 LogRel(("HWACCM: Large page support enabled!\n"));
1313 }
1314#endif
1315 }
1316
1317 hwaccmR3DisableRawMode(pVM);
1318 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1319 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1320 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1321#ifdef VBOX_ENABLE_64_BITS_GUESTS
1322 if (pVM->hwaccm.s.fAllow64BitGuests)
1323 {
1324 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1325 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1326 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1327 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1328 }
1329 else
1330 /* Turn on NXE if PAE has been enabled. */
1331 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1332 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1333#endif
1334
1335 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1336 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1337 : "HWACCM: 32-bit guest supported.\n"));
1338
1339 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1340 }
1341 else
1342 {
1343 pVM->fHWACCMEnabled = false;
1344 }
1345 }
1346 }
1347 if (pVM->fHWACCMEnabled)
1348 LogRel(("HWACCM: VT-x/AMD-V init method: %s\n", (pVM->hwaccm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1349 RTLogRelSetBuffering(fOldBuffered);
1350 return VINF_SUCCESS;
1351}
1352
1353/**
1354 * Applies relocations to data and code managed by this
1355 * component. This function will be called at init and
1356 * whenever the VMM need to relocate it self inside the GC.
1357 *
1358 * @param pVM The VM.
1359 */
1360VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1361{
1362 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1363
1364 /* Fetch the current paging mode during the relocate callback during state loading. */
1365 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1366 {
1367 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1368 {
1369 PVMCPU pVCpu = &pVM->aCpus[i];
1370
1371 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1372 Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1373 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1374 }
1375 }
1376#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1377 if (pVM->fHWACCMEnabled)
1378 {
1379 int rc;
1380
1381 switch(PGMGetHostMode(pVM))
1382 {
1383 case PGMMODE_32_BIT:
1384 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1385 break;
1386
1387 case PGMMODE_PAE:
1388 case PGMMODE_PAE_NX:
1389 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1390 break;
1391
1392 default:
1393 AssertFailed();
1394 break;
1395 }
1396 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1397 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1398
1399 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1400 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1401
1402 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1403 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1404
1405 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1406 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1407
1408# ifdef DEBUG
1409 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1410 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1411# endif
1412 }
1413#endif
1414 return;
1415}
1416
1417/**
1418 * Checks hardware accelerated raw mode is allowed.
1419 *
1420 * @returns boolean
1421 * @param pVM The VM to operate on.
1422 */
1423VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1424{
1425 return pVM->hwaccm.s.fAllowed;
1426}
1427
1428/**
1429 * Notification callback which is called whenever there is a chance that a CR3
1430 * value might have changed.
1431 *
1432 * This is called by PGM.
1433 *
1434 * @param pVM The VM to operate on.
1435 * @param pVCpu The VMCPU to operate on.
1436 * @param enmShadowMode New shadow paging mode.
1437 * @param enmGuestMode New guest paging mode.
1438 */
1439VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1440{
1441 /* Ignore page mode changes during state loading. */
1442 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1443 return;
1444
1445 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1446
1447 if ( pVM->hwaccm.s.vmx.fEnabled
1448 && pVM->fHWACCMEnabled)
1449 {
1450 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1451 && enmGuestMode >= PGMMODE_PROTECTED)
1452 {
1453 PCPUMCTX pCtx;
1454
1455 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1456
1457 /* After a real mode switch to protected mode we must force
1458 * CPL to 0. Our real mode emulation had to set it to 3.
1459 */
1460 pCtx->ssHid.Attr.n.u2Dpl = 0;
1461 }
1462 }
1463
1464 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1465 {
1466 /* Keep track of paging mode changes. */
1467 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1468 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1469
1470 /* Did we miss a change, because all code was executed in the recompiler? */
1471 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1472 {
1473 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1474 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1475 }
1476 }
1477
1478 /* Reset the contents of the read cache. */
1479 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1480 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1481 pCache->Read.aFieldVal[j] = 0;
1482}
1483
1484/**
1485 * Terminates the HWACCM.
1486 *
1487 * Termination means cleaning up and freeing all resources,
1488 * the VM it self is at this point powered off or suspended.
1489 *
1490 * @returns VBox status code.
1491 * @param pVM The VM to operate on.
1492 */
1493VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1494{
1495 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1496 {
1497 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1498 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1499 }
1500 HWACCMR3TermCPU(pVM);
1501 return 0;
1502}
1503
1504/**
1505 * Terminates the per-VCPU HWACCM.
1506 *
1507 * Termination means cleaning up and freeing all resources,
1508 * the VM it self is at this point powered off or suspended.
1509 *
1510 * @returns VBox status code.
1511 * @param pVM The VM to operate on.
1512 */
1513VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1514{
1515 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1516 {
1517 PVMCPU pVCpu = &pVM->aCpus[i];
1518
1519#ifdef VBOX_WITH_STATISTICS
1520 if (pVCpu->hwaccm.s.paStatExitReason)
1521 {
1522 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1523 pVCpu->hwaccm.s.paStatExitReason = NULL;
1524 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1525 }
1526 if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1527 {
1528 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1529 pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1530 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1531 }
1532#endif
1533
1534#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1535 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1536 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1537 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1538#endif
1539 }
1540 return 0;
1541}
1542
1543/**
1544 * Resets a virtual CPU.
1545 *
1546 * Used by HWACCMR3Reset and CPU hot plugging.
1547 *
1548 * @param pVCpu The CPU to reset.
1549 */
1550VMMR3DECL(void) HWACCMR3ResetCpu(PVMCPU pVCpu)
1551{
1552 /* On first entry we'll sync everything. */
1553 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1554
1555 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1556 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1557
1558 pVCpu->hwaccm.s.fActive = false;
1559 pVCpu->hwaccm.s.Event.fPending = false;
1560
1561 /* Reset state information for real-mode emulation in VT-x. */
1562 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1563 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1564 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1565
1566 /* Reset the contents of the read cache. */
1567 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1568 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1569 pCache->Read.aFieldVal[j] = 0;
1570
1571#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1572 /* Magic marker for searching in crash dumps. */
1573 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1574 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1575#endif
1576}
1577
1578/**
1579 * The VM is being reset.
1580 *
1581 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1582 * needs to be removed.
1583 *
1584 * @param pVM VM handle.
1585 */
1586VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1587{
1588 LogFlow(("HWACCMR3Reset:\n"));
1589
1590 if (pVM->fHWACCMEnabled)
1591 hwaccmR3DisableRawMode(pVM);
1592
1593 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1594 {
1595 PVMCPU pVCpu = &pVM->aCpus[i];
1596
1597 HWACCMR3ResetCpu(pVCpu);
1598 }
1599
1600 /* Clear all patch information. */
1601 pVM->hwaccm.s.pGuestPatchMem = 0;
1602 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1603 pVM->hwaccm.s.cbGuestPatchMem = 0;
1604 pVM->hwaccm.s.cPatches = 0;
1605 pVM->hwaccm.s.PatchTree = 0;
1606 pVM->hwaccm.s.fTPRPatchingActive = false;
1607 ASMMemZero32(pVM->hwaccm.s.aPatches, sizeof(pVM->hwaccm.s.aPatches));
1608}
1609
1610/**
1611 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1612 *
1613 * @returns VBox strict status code.
1614 * @param pVM The VM handle.
1615 * @param pVCpu The VMCPU for the EMT we're being called on.
1616 * @param pvUser Unused
1617 *
1618 */
1619DECLCALLBACK(VBOXSTRICTRC) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1620{
1621 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1622
1623 /* Only execute the handler on the VCPU the original patch request was issued. */
1624 if (pVCpu->idCpu != idCpu)
1625 return VINF_SUCCESS;
1626
1627 Log(("hwaccmR3RemovePatches\n"));
1628 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
1629 {
1630 uint8_t szInstr[15];
1631 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
1632 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1633 int rc;
1634
1635#ifdef LOG_ENABLED
1636 char szOutput[256];
1637
1638 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1639 szOutput, sizeof(szOutput), NULL);
1640 if (RT_SUCCESS(rc))
1641 Log(("Patched instr: %s\n", szOutput));
1642#endif
1643
1644 /* Check if the instruction is still the same. */
1645 rc = PGMPhysSimpleReadGCPtr(pVCpu, szInstr, pInstrGC, pPatch->cbNewOp);
1646 if (rc != VINF_SUCCESS)
1647 {
1648 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1649 continue; /* swapped out or otherwise removed; skip it. */
1650 }
1651
1652 if (memcmp(szInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1653 {
1654 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1655 continue; /* skip it. */
1656 }
1657
1658 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1659 AssertRC(rc);
1660
1661#ifdef LOG_ENABLED
1662 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1663 szOutput, sizeof(szOutput), NULL);
1664 if (RT_SUCCESS(rc))
1665 Log(("Original instr: %s\n", szOutput));
1666#endif
1667 }
1668 pVM->hwaccm.s.cPatches = 0;
1669 pVM->hwaccm.s.PatchTree = 0;
1670 pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1671 pVM->hwaccm.s.fTPRPatchingActive = false;
1672 return VINF_SUCCESS;
1673}
1674
1675/**
1676 * Enable patching in a VT-x/AMD-V guest
1677 *
1678 * @returns VBox status code.
1679 * @param pVM The VM to operate on.
1680 * @param idCpu VCPU to execute hwaccmR3RemovePatches on
1681 * @param pPatchMem Patch memory range
1682 * @param cbPatchMem Size of the memory range
1683 */
1684int hwaccmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1685{
1686 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)idCpu);
1687 AssertRC(rc);
1688
1689 pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1690 pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1691 pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1692 return VINF_SUCCESS;
1693}
1694
1695/**
1696 * Enable patching in a VT-x/AMD-V guest
1697 *
1698 * @returns VBox status code.
1699 * @param pVM The VM to operate on.
1700 * @param pPatchMem Patch memory range
1701 * @param cbPatchMem Size of the memory range
1702 */
1703VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1704{
1705 Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1706 if (pVM->cCpus > 1)
1707 {
1708 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1709 int rc = VMR3ReqCallNoWaitU(pVM->pUVM, VMCPUID_ANY_QUEUE,
1710 (PFNRT)hwaccmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1711 AssertRC(rc);
1712 return rc;
1713 }
1714 return hwaccmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1715}
1716
1717/**
1718 * Disable patching in a VT-x/AMD-V guest
1719 *
1720 * @returns VBox status code.
1721 * @param pVM The VM to operate on.
1722 * @param pPatchMem Patch memory range
1723 * @param cbPatchMem Size of the memory range
1724 */
1725VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1726{
1727 Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1728
1729 Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1730 Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1731
1732 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1733 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)VMMGetCpuId(pVM));
1734 AssertRC(rc);
1735
1736 pVM->hwaccm.s.pGuestPatchMem = 0;
1737 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1738 pVM->hwaccm.s.cbGuestPatchMem = 0;
1739 pVM->hwaccm.s.fTPRPatchingActive = false;
1740 return VINF_SUCCESS;
1741}
1742
1743
1744/**
1745 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1746 *
1747 * @returns VBox strict status code.
1748 * @param pVM The VM handle.
1749 * @param pVCpu The VMCPU for the EMT we're being called on.
1750 * @param pvUser User specified CPU context
1751 *
1752 */
1753DECLCALLBACK(VBOXSTRICTRC) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1754{
1755 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1756 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1757 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1758 unsigned cbOp;
1759
1760 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1761 if (pVCpu->idCpu != idCpu)
1762 return VINF_SUCCESS;
1763
1764 Log(("hwaccmR3ReplaceTprInstr: %RGv\n", pCtx->rip));
1765
1766 /* Two or more VCPUs were racing to patch this instruction. */
1767 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1768 if (pPatch)
1769 return VINF_SUCCESS;
1770
1771 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1772
1773 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1774 AssertRC(rc);
1775 if ( rc == VINF_SUCCESS
1776 && pDis->pCurInstr->opcode == OP_MOV
1777 && cbOp >= 3)
1778 {
1779 uint8_t aVMMCall[3] = { 0xf, 0x1, 0xd9};
1780 uint32_t idx = pVM->hwaccm.s.cPatches;
1781
1782 pPatch = &pVM->hwaccm.s.aPatches[idx];
1783
1784 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1785 AssertRC(rc);
1786
1787 pPatch->cbOp = cbOp;
1788
1789 if (pDis->param1.flags == USE_DISPLACEMENT32)
1790 {
1791 /* write. */
1792 if (pDis->param2.flags == USE_REG_GEN32)
1793 {
1794 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1795 pPatch->uSrcOperand = pDis->param2.base.reg_gen;
1796 }
1797 else
1798 {
1799 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1800 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1801 pPatch->uSrcOperand = pDis->param2.parval;
1802 }
1803 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1804 AssertRC(rc);
1805
1806 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1807 pPatch->cbNewOp = sizeof(aVMMCall);
1808 }
1809 else
1810 {
1811 RTGCPTR oldrip = pCtx->rip;
1812 uint32_t oldcbOp = cbOp;
1813 uint32_t uMmioReg = pDis->param1.base.reg_gen;
1814
1815 /* read */
1816 Assert(pDis->param1.flags == USE_REG_GEN32);
1817
1818 /* Found:
1819 * mov eax, dword [fffe0080] (5 bytes)
1820 * Check if next instruction is:
1821 * shr eax, 4
1822 */
1823 pCtx->rip += cbOp;
1824 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1825 pCtx->rip = oldrip;
1826 if ( rc == VINF_SUCCESS
1827 && pDis->pCurInstr->opcode == OP_SHR
1828 && pDis->param1.flags == USE_REG_GEN32
1829 && pDis->param1.base.reg_gen == uMmioReg
1830 && pDis->param2.flags == USE_IMMEDIATE8
1831 && pDis->param2.parval == 4
1832 && oldcbOp + cbOp < sizeof(pVM->hwaccm.s.aPatches[idx].aOpcode))
1833 {
1834 uint8_t szInstr[15];
1835
1836 /* Replacing two instructions now. */
1837 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, oldcbOp + cbOp);
1838 AssertRC(rc);
1839
1840 pPatch->cbOp = oldcbOp + cbOp;
1841
1842 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1843 szInstr[0] = 0xF0;
1844 szInstr[1] = 0x0F;
1845 szInstr[2] = 0x20;
1846 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
1847 for (unsigned i = 4; i < pPatch->cbOp; i++)
1848 szInstr[i] = 0x90; /* nop */
1849
1850 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, pPatch->cbOp);
1851 AssertRC(rc);
1852
1853 memcpy(pPatch->aNewOpcode, szInstr, pPatch->cbOp);
1854 pPatch->cbNewOp = pPatch->cbOp;
1855
1856 Log(("Acceptable read/shr candidate!\n"));
1857 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1858 }
1859 else
1860 {
1861 pPatch->enmType = HWACCMTPRINSTR_READ;
1862 pPatch->uDstOperand = pDis->param1.base.reg_gen;
1863
1864 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1865 AssertRC(rc);
1866
1867 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1868 pPatch->cbNewOp = sizeof(aVMMCall);
1869 }
1870 }
1871
1872 pPatch->Core.Key = pCtx->eip;
1873 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1874 AssertRC(rc);
1875
1876 pVM->hwaccm.s.cPatches++;
1877 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceSuccess);
1878 return VINF_SUCCESS;
1879 }
1880
1881 /* Save invalid patch, so we will not try again. */
1882 uint32_t idx = pVM->hwaccm.s.cPatches;
1883
1884#ifdef LOG_ENABLED
1885 char szOutput[256];
1886 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1887 szOutput, sizeof(szOutput), NULL);
1888 if (RT_SUCCESS(rc))
1889 Log(("Failed to patch instr: %s\n", szOutput));
1890#endif
1891
1892 pPatch = &pVM->hwaccm.s.aPatches[idx];
1893 pPatch->Core.Key = pCtx->eip;
1894 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1895 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1896 AssertRC(rc);
1897 pVM->hwaccm.s.cPatches++;
1898 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceFailure);
1899 return VINF_SUCCESS;
1900}
1901
1902/**
1903 * Callback to patch a TPR instruction (jump to generated code)
1904 *
1905 * @returns VBox strict status code.
1906 * @param pVM The VM handle.
1907 * @param pVCpu The VMCPU for the EMT we're being called on.
1908 * @param pvUser User specified CPU context
1909 *
1910 */
1911DECLCALLBACK(VBOXSTRICTRC) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1912{
1913 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1914 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1915 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1916 unsigned cbOp;
1917 int rc;
1918#ifdef LOG_ENABLED
1919 RTGCPTR pInstr;
1920 char szOutput[256];
1921#endif
1922
1923 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1924 if (pVCpu->idCpu != idCpu)
1925 return VINF_SUCCESS;
1926
1927 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1928
1929 /* Two or more VCPUs were racing to patch this instruction. */
1930 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1931 if (pPatch)
1932 {
1933 Log(("hwaccmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
1934 return VINF_SUCCESS;
1935 }
1936
1937 Log(("hwaccmR3PatchTprInstr %RGv\n", pCtx->rip));
1938
1939 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1940 AssertRC(rc);
1941 if ( rc == VINF_SUCCESS
1942 && pDis->pCurInstr->opcode == OP_MOV
1943 && cbOp >= 5)
1944 {
1945 uint32_t idx = pVM->hwaccm.s.cPatches;
1946 uint8_t aPatch[64];
1947 uint32_t off = 0;
1948
1949 pPatch = &pVM->hwaccm.s.aPatches[idx];
1950
1951#ifdef LOG_ENABLED
1952 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1953 szOutput, sizeof(szOutput), NULL);
1954 if (RT_SUCCESS(rc))
1955 Log(("Original instr: %s\n", szOutput));
1956#endif
1957
1958 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1959 AssertRC(rc);
1960
1961 pPatch->cbOp = cbOp;
1962 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
1963
1964 if (pDis->param1.flags == USE_DISPLACEMENT32)
1965 {
1966 /*
1967 * TPR write:
1968 *
1969 * push ECX [51]
1970 * push EDX [52]
1971 * push EAX [50]
1972 * xor EDX,EDX [31 D2]
1973 * mov EAX,EAX [89 C0]
1974 * or
1975 * mov EAX,0000000CCh [B8 CC 00 00 00]
1976 * mov ECX,0C0000082h [B9 82 00 00 C0]
1977 * wrmsr [0F 30]
1978 * pop EAX [58]
1979 * pop EDX [5A]
1980 * pop ECX [59]
1981 * jmp return_address [E9 return_address]
1982 *
1983 */
1984 bool fUsesEax = (pDis->param2.flags == USE_REG_GEN32 && pDis->param2.base.reg_gen == USE_REG_EAX);
1985
1986 aPatch[off++] = 0x51; /* push ecx */
1987 aPatch[off++] = 0x52; /* push edx */
1988 if (!fUsesEax)
1989 aPatch[off++] = 0x50; /* push eax */
1990 aPatch[off++] = 0x31; /* xor edx, edx */
1991 aPatch[off++] = 0xD2;
1992 if (pDis->param2.flags == USE_REG_GEN32)
1993 {
1994 if (!fUsesEax)
1995 {
1996 aPatch[off++] = 0x89; /* mov eax, src_reg */
1997 aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, USE_REG_EAX);
1998 }
1999 }
2000 else
2001 {
2002 Assert(pDis->param2.flags == USE_IMMEDIATE32);
2003 aPatch[off++] = 0xB8; /* mov eax, immediate */
2004 *(uint32_t *)&aPatch[off] = pDis->param2.parval;
2005 off += sizeof(uint32_t);
2006 }
2007 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2008 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2009 off += sizeof(uint32_t);
2010
2011 aPatch[off++] = 0x0F; /* wrmsr */
2012 aPatch[off++] = 0x30;
2013 if (!fUsesEax)
2014 aPatch[off++] = 0x58; /* pop eax */
2015 aPatch[off++] = 0x5A; /* pop edx */
2016 aPatch[off++] = 0x59; /* pop ecx */
2017 }
2018 else
2019 {
2020 /*
2021 * TPR read:
2022 *
2023 * push ECX [51]
2024 * push EDX [52]
2025 * push EAX [50]
2026 * mov ECX,0C0000082h [B9 82 00 00 C0]
2027 * rdmsr [0F 32]
2028 * mov EAX,EAX [89 C0]
2029 * pop EAX [58]
2030 * pop EDX [5A]
2031 * pop ECX [59]
2032 * jmp return_address [E9 return_address]
2033 *
2034 */
2035 Assert(pDis->param1.flags == USE_REG_GEN32);
2036
2037 if (pDis->param1.base.reg_gen != USE_REG_ECX)
2038 aPatch[off++] = 0x51; /* push ecx */
2039 if (pDis->param1.base.reg_gen != USE_REG_EDX)
2040 aPatch[off++] = 0x52; /* push edx */
2041 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2042 aPatch[off++] = 0x50; /* push eax */
2043
2044 aPatch[off++] = 0x31; /* xor edx, edx */
2045 aPatch[off++] = 0xD2;
2046
2047 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2048 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2049 off += sizeof(uint32_t);
2050
2051 aPatch[off++] = 0x0F; /* rdmsr */
2052 aPatch[off++] = 0x32;
2053
2054 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2055 {
2056 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2057 aPatch[off++] = MAKE_MODRM(3, USE_REG_EAX, pDis->param1.base.reg_gen);
2058 }
2059
2060 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2061 aPatch[off++] = 0x58; /* pop eax */
2062 if (pDis->param1.base.reg_gen != USE_REG_EDX)
2063 aPatch[off++] = 0x5A; /* pop edx */
2064 if (pDis->param1.base.reg_gen != USE_REG_ECX)
2065 aPatch[off++] = 0x59; /* pop ecx */
2066 }
2067 aPatch[off++] = 0xE9; /* jmp return_address */
2068 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
2069 off += sizeof(RTRCUINTPTR);
2070
2071 if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
2072 {
2073 /* Write new code to the patch buffer. */
2074 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
2075 AssertRC(rc);
2076
2077#ifdef LOG_ENABLED
2078 pInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
2079 while (true)
2080 {
2081 uint32_t cb;
2082
2083 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2084 szOutput, sizeof(szOutput), &cb);
2085 if (RT_SUCCESS(rc))
2086 Log(("Patch instr %s\n", szOutput));
2087
2088 pInstr += cb;
2089
2090 if (pInstr >= pVM->hwaccm.s.pFreeGuestPatchMem + off)
2091 break;
2092 }
2093#endif
2094
2095 pPatch->aNewOpcode[0] = 0xE9;
2096 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2097
2098 /* Overwrite the TPR instruction with a jump. */
2099 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2100 AssertRC(rc);
2101
2102#ifdef LOG_ENABLED
2103 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2104 szOutput, sizeof(szOutput), NULL);
2105 if (RT_SUCCESS(rc))
2106 Log(("Jump: %s\n", szOutput));
2107#endif
2108 pVM->hwaccm.s.pFreeGuestPatchMem += off;
2109 pPatch->cbNewOp = 5;
2110
2111 pPatch->Core.Key = pCtx->eip;
2112 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2113 AssertRC(rc);
2114
2115 pVM->hwaccm.s.cPatches++;
2116 pVM->hwaccm.s.fTPRPatchingActive = true;
2117 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchSuccess);
2118 return VINF_SUCCESS;
2119 }
2120 else
2121 Log(("Ran out of space in our patch buffer!\n"));
2122 }
2123
2124 /* Save invalid patch, so we will not try again. */
2125 uint32_t idx = pVM->hwaccm.s.cPatches;
2126
2127#ifdef LOG_ENABLED
2128 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2129 szOutput, sizeof(szOutput), NULL);
2130 if (RT_SUCCESS(rc))
2131 Log(("Failed to patch instr: %s\n", szOutput));
2132#endif
2133
2134 pPatch = &pVM->hwaccm.s.aPatches[idx];
2135 pPatch->Core.Key = pCtx->eip;
2136 pPatch->enmType = HWACCMTPRINSTR_INVALID;
2137 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2138 AssertRC(rc);
2139 pVM->hwaccm.s.cPatches++;
2140 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchFailure);
2141 return VINF_SUCCESS;
2142}
2143
2144/**
2145 * Attempt to patch TPR mmio instructions
2146 *
2147 * @returns VBox status code.
2148 * @param pVM The VM to operate on.
2149 * @param pVCpu The VM CPU to operate on.
2150 * @param pCtx CPU context
2151 */
2152VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2153{
2154 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, (pVM->hwaccm.s.pGuestPatchMem) ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr, (void *)pVCpu->idCpu);
2155 AssertRC(rc);
2156 return rc;
2157}
2158
2159/**
2160 * Force execution of the current IO code in the recompiler
2161 *
2162 * @returns VBox status code.
2163 * @param pVM The VM to operate on.
2164 * @param pCtx Partial VM execution context
2165 */
2166VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2167{
2168 PVMCPU pVCpu = VMMGetCpu(pVM);
2169
2170 Assert(pVM->fHWACCMEnabled);
2171 Log(("HWACCMR3EmulateIoBlock\n"));
2172
2173 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2174 if (HWACCMCanEmulateIoBlockEx(pCtx))
2175 {
2176 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
2177 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
2178 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2179 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2180 return VINF_EM_RESCHEDULE_REM;
2181 }
2182 return VINF_SUCCESS;
2183}
2184
2185/**
2186 * Checks if we can currently use hardware accelerated raw mode.
2187 *
2188 * @returns boolean
2189 * @param pVM The VM to operate on.
2190 * @param pCtx Partial VM execution context
2191 */
2192VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2193{
2194 PVMCPU pVCpu = VMMGetCpu(pVM);
2195
2196 Assert(pVM->fHWACCMEnabled);
2197
2198 /* If we're still executing the IO code, then return false. */
2199 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
2200 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2201 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2202 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
2203 return false;
2204
2205 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
2206
2207 /* AMD-V supports real & protected mode with or without paging. */
2208 if (pVM->hwaccm.s.svm.fEnabled)
2209 {
2210 pVCpu->hwaccm.s.fActive = true;
2211 return true;
2212 }
2213
2214 pVCpu->hwaccm.s.fActive = false;
2215
2216 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2217 Assert((pVM->hwaccm.s.vmx.fUnrestrictedGuest && !pVM->hwaccm.s.vmx.pRealModeTSS) || (!pVM->hwaccm.s.vmx.fUnrestrictedGuest && pVM->hwaccm.s.vmx.pRealModeTSS));
2218
2219 bool fSupportsRealMode = pVM->hwaccm.s.vmx.fUnrestrictedGuest || PDMVMMDevHeapIsEnabled(pVM);
2220 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2221 {
2222 /** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. */
2223 if (fSupportsRealMode)
2224 {
2225 if (CPUMIsGuestInRealModeEx(pCtx))
2226 {
2227 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
2228 * The base must also be equal to (sel << 4).
2229 */
2230 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
2231 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
2232 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
2233 || pCtx->es != (pCtx->esHid.u64Base >> 4)
2234 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
2235 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
2236 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
2237 {
2238 return false;
2239 }
2240 }
2241 else
2242 {
2243 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2244 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
2245 * from real to protected mode. (all sorts of RPL & DPL assumptions)
2246 */
2247 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2248 && enmGuestMode >= PGMMODE_PROTECTED)
2249 {
2250 if ( (pCtx->cs & X86_SEL_RPL)
2251 || (pCtx->ds & X86_SEL_RPL)
2252 || (pCtx->es & X86_SEL_RPL)
2253 || (pCtx->fs & X86_SEL_RPL)
2254 || (pCtx->gs & X86_SEL_RPL)
2255 || (pCtx->ss & X86_SEL_RPL))
2256 {
2257 return false;
2258 }
2259 }
2260 /* VT-x also chokes on invalid tr or ldtr selectors (minix) */
2261 if ( pCtx->gdtr.cbGdt
2262 && ( pCtx->tr > pCtx->gdtr.cbGdt
2263 || pCtx->ldtr > pCtx->gdtr.cbGdt))
2264 {
2265 return false;
2266 }
2267 }
2268 }
2269 else
2270 {
2271 if ( !CPUMIsGuestInLongModeEx(pCtx)
2272 && !pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2273 {
2274 /** @todo This should (probably) be set on every excursion to the REM,
2275 * however it's too risky right now. So, only apply it when we go
2276 * back to REM for real mode execution. (The XP hack below doesn't
2277 * work reliably without this.)
2278 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2279 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2280
2281 if ( !pVM->hwaccm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap*/
2282 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2283 return false;
2284
2285 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2286 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
2287 return false;
2288
2289 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2290 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2291 * hidden registers (possible recompiler bug; see load_seg_vm) */
2292 if (pCtx->csHid.Attr.n.u1Present == 0)
2293 return false;
2294 if (pCtx->ssHid.Attr.n.u1Present == 0)
2295 return false;
2296
2297 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2298 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2299 /** @todo This check is actually wrong, it doesn't take the direction of the
2300 * stack segment into account. But, it does the job for now. */
2301 if (pCtx->rsp >= pCtx->ssHid.u32Limit)
2302 return false;
2303 #if 0
2304 if ( pCtx->cs >= pCtx->gdtr.cbGdt
2305 || pCtx->ss >= pCtx->gdtr.cbGdt
2306 || pCtx->ds >= pCtx->gdtr.cbGdt
2307 || pCtx->es >= pCtx->gdtr.cbGdt
2308 || pCtx->fs >= pCtx->gdtr.cbGdt
2309 || pCtx->gs >= pCtx->gdtr.cbGdt)
2310 return false;
2311 #endif
2312 }
2313 }
2314 }
2315
2316 if (pVM->hwaccm.s.vmx.fEnabled)
2317 {
2318 uint32_t mask;
2319
2320 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2321 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2322 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2323 mask &= ~X86_CR0_NE;
2324
2325 if (fSupportsRealMode)
2326 {
2327 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2328 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2329 }
2330 else
2331 {
2332 /* We support protected mode without paging using identity mapping. */
2333 mask &= ~X86_CR0_PG;
2334 }
2335 if ((pCtx->cr0 & mask) != mask)
2336 return false;
2337
2338 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2339 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2340 if ((pCtx->cr0 & mask) != 0)
2341 return false;
2342
2343 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2344 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2345 mask &= ~X86_CR4_VMXE;
2346 if ((pCtx->cr4 & mask) != mask)
2347 return false;
2348
2349 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2350 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2351 if ((pCtx->cr4 & mask) != 0)
2352 return false;
2353
2354 pVCpu->hwaccm.s.fActive = true;
2355 return true;
2356 }
2357
2358 return false;
2359}
2360
2361/**
2362 * Checks if we need to reschedule due to VMM device heap changes
2363 *
2364 * @returns boolean
2365 * @param pVM The VM to operate on.
2366 * @param pCtx VM execution context
2367 */
2368VMMR3DECL(bool) HWACCMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2369{
2370 /** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. (VT-x only) */
2371 if ( pVM->hwaccm.s.vmx.fEnabled
2372 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2373 && !PDMVMMDevHeapIsEnabled(pVM)
2374 && (pVM->hwaccm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2375 return true;
2376
2377 return false;
2378}
2379
2380
2381/**
2382 * Notification from EM about a rescheduling into hardware assisted execution
2383 * mode.
2384 *
2385 * @param pVCpu Pointer to the current virtual cpu structure.
2386 */
2387VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2388{
2389 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2390}
2391
2392/**
2393 * Notification from EM about returning from instruction emulation (REM / EM).
2394 *
2395 * @param pVCpu Pointer to the current virtual cpu structure.
2396 */
2397VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2398{
2399 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2400}
2401
2402/**
2403 * Checks if we are currently using hardware accelerated raw mode.
2404 *
2405 * @returns boolean
2406 * @param pVCpu The VMCPU to operate on.
2407 */
2408VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2409{
2410 return pVCpu->hwaccm.s.fActive;
2411}
2412
2413/**
2414 * Checks if we are currently using nested paging.
2415 *
2416 * @returns boolean
2417 * @param pVM The VM to operate on.
2418 */
2419VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2420{
2421 return pVM->hwaccm.s.fNestedPaging;
2422}
2423
2424/**
2425 * Checks if we are currently using VPID in VT-x mode.
2426 *
2427 * @returns boolean
2428 * @param pVM The VM to operate on.
2429 */
2430VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2431{
2432 return pVM->hwaccm.s.vmx.fVPID;
2433}
2434
2435
2436/**
2437 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2438 *
2439 * @returns boolean
2440 * @param pVM The VM to operate on.
2441 */
2442VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2443{
2444 return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2445}
2446
2447/**
2448 * Checks if the VMX-preemption timer is being used.
2449 *
2450 * @returns true if it is, false if it isn't.
2451 * @param pVM The VM handle.
2452 */
2453VMMR3DECL(bool) HWACCMR3IsVmxPreemptionTimerUsed(PVM pVM)
2454{
2455 return HWACCMIsEnabled(pVM)
2456 && pVM->hwaccm.s.vmx.fEnabled
2457 && pVM->hwaccm.s.vmx.fUsePreemptTimer;
2458}
2459
2460/**
2461 * Restart an I/O instruction that was refused in ring-0
2462 *
2463 * @returns Strict VBox status code. Informational status codes other than the one documented
2464 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2465 * @retval VINF_SUCCESS Success.
2466 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2467 * status code must be passed on to EM.
2468 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2469 *
2470 * @param pVM The VM to operate on.
2471 * @param pVCpu The VMCPU to operate on.
2472 * @param pCtx VCPU register context
2473 */
2474VMMR3DECL(VBOXSTRICTRC) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2475{
2476 HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2477
2478 pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2479
2480 if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2481 || enmType == HWACCMPENDINGIO_INVALID)
2482 return VERR_NOT_FOUND;
2483
2484 VBOXSTRICTRC rcStrict;
2485 switch (enmType)
2486 {
2487 case HWACCMPENDINGIO_PORT_READ:
2488 {
2489 uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2490 uint32_t u32Val = 0;
2491
2492 rcStrict = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2493 &u32Val,
2494 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2495 if (IOM_SUCCESS(rcStrict))
2496 {
2497 /* Write back to the EAX register. */
2498 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2499 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2500 }
2501 break;
2502 }
2503
2504 case HWACCMPENDINGIO_PORT_WRITE:
2505 rcStrict = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2506 pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2507 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2508 if (IOM_SUCCESS(rcStrict))
2509 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2510 break;
2511
2512 default:
2513 AssertFailed();
2514 return VERR_INTERNAL_ERROR;
2515 }
2516
2517 return rcStrict;
2518}
2519
2520/**
2521 * Inject an NMI into a running VM (only VCPU 0!)
2522 *
2523 * @returns boolean
2524 * @param pVM The VM to operate on.
2525 */
2526VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2527{
2528 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2529 return VINF_SUCCESS;
2530}
2531
2532/**
2533 * Check fatal VT-x/AMD-V error and produce some meaningful
2534 * log release message.
2535 *
2536 * @param pVM The VM to operate on.
2537 * @param iStatusCode VBox status code
2538 */
2539VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2540{
2541 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2542 {
2543 switch(iStatusCode)
2544 {
2545 case VERR_VMX_INVALID_VMCS_FIELD:
2546 break;
2547
2548 case VERR_VMX_INVALID_VMCS_PTR:
2549 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
2550 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2551 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2552 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2553 break;
2554
2555 case VERR_VMX_UNABLE_TO_START_VM:
2556 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2557 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2558#if 0 /* @todo dump the current control fields to the release log */
2559 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2560 {
2561
2562 }
2563#endif
2564 break;
2565
2566 case VERR_VMX_UNABLE_TO_RESUME_VM:
2567 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2568 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2569 break;
2570
2571 case VERR_VMX_INVALID_VMXON_PTR:
2572 break;
2573 }
2574 }
2575}
2576
2577/**
2578 * Execute state save operation.
2579 *
2580 * @returns VBox status code.
2581 * @param pVM VM Handle.
2582 * @param pSSM SSM operation handle.
2583 */
2584static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2585{
2586 int rc;
2587
2588 Log(("hwaccmR3Save:\n"));
2589
2590 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2591 {
2592 /*
2593 * Save the basic bits - fortunately all the other things can be resynced on load.
2594 */
2595 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2596 AssertRCReturn(rc, rc);
2597 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2598 AssertRCReturn(rc, rc);
2599 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2600 AssertRCReturn(rc, rc);
2601
2602 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2603 AssertRCReturn(rc, rc);
2604 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2605 AssertRCReturn(rc, rc);
2606 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2607 AssertRCReturn(rc, rc);
2608 }
2609#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2610 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2611 AssertRCReturn(rc, rc);
2612 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2613 AssertRCReturn(rc, rc);
2614 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2615 AssertRCReturn(rc, rc);
2616
2617 /* Store all the guest patch records too. */
2618 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cPatches);
2619 AssertRCReturn(rc, rc);
2620
2621 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2622 {
2623 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2624
2625 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2626 AssertRCReturn(rc, rc);
2627
2628 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2629 AssertRCReturn(rc, rc);
2630
2631 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2632 AssertRCReturn(rc, rc);
2633
2634 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2635 AssertRCReturn(rc, rc);
2636
2637 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2638 AssertRCReturn(rc, rc);
2639
2640 AssertCompileSize(HWACCMTPRINSTR, 4);
2641 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2642 AssertRCReturn(rc, rc);
2643
2644 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2645 AssertRCReturn(rc, rc);
2646
2647 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2648 AssertRCReturn(rc, rc);
2649
2650 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2651 AssertRCReturn(rc, rc);
2652
2653 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2654 AssertRCReturn(rc, rc);
2655 }
2656#endif
2657 return VINF_SUCCESS;
2658}
2659
2660/**
2661 * Execute state load operation.
2662 *
2663 * @returns VBox status code.
2664 * @param pVM VM Handle.
2665 * @param pSSM SSM operation handle.
2666 * @param uVersion Data layout version.
2667 * @param uPass The data pass.
2668 */
2669static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2670{
2671 int rc;
2672
2673 Log(("hwaccmR3Load:\n"));
2674 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2675
2676 /*
2677 * Validate version.
2678 */
2679 if ( uVersion != HWACCM_SSM_VERSION
2680 && uVersion != HWACCM_SSM_VERSION_NO_PATCHING
2681 && uVersion != HWACCM_SSM_VERSION_2_0_X)
2682 {
2683 AssertMsgFailed(("hwaccmR3Load: Invalid version uVersion=%d!\n", uVersion));
2684 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2685 }
2686 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2687 {
2688 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2689 AssertRCReturn(rc, rc);
2690 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2691 AssertRCReturn(rc, rc);
2692 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2693 AssertRCReturn(rc, rc);
2694
2695 if (uVersion >= HWACCM_SSM_VERSION_NO_PATCHING)
2696 {
2697 uint32_t val;
2698
2699 rc = SSMR3GetU32(pSSM, &val);
2700 AssertRCReturn(rc, rc);
2701 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2702
2703 rc = SSMR3GetU32(pSSM, &val);
2704 AssertRCReturn(rc, rc);
2705 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2706
2707 rc = SSMR3GetU32(pSSM, &val);
2708 AssertRCReturn(rc, rc);
2709 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2710 }
2711 }
2712#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2713 if (uVersion > HWACCM_SSM_VERSION_NO_PATCHING)
2714 {
2715 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2716 AssertRCReturn(rc, rc);
2717 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2718 AssertRCReturn(rc, rc);
2719 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2720 AssertRCReturn(rc, rc);
2721
2722 /* Fetch all TPR patch records. */
2723 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cPatches);
2724 AssertRCReturn(rc, rc);
2725
2726 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2727 {
2728 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2729
2730 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2731 AssertRCReturn(rc, rc);
2732
2733 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2734 AssertRCReturn(rc, rc);
2735
2736 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2737 AssertRCReturn(rc, rc);
2738
2739 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2740 AssertRCReturn(rc, rc);
2741
2742 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2743 AssertRCReturn(rc, rc);
2744
2745 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2746 AssertRCReturn(rc, rc);
2747
2748 if (pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT)
2749 pVM->hwaccm.s.fTPRPatchingActive = true;
2750
2751 Assert(pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT || pVM->hwaccm.s.fTPRPatchingActive == false);
2752
2753 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2754 AssertRCReturn(rc, rc);
2755
2756 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2757 AssertRCReturn(rc, rc);
2758
2759 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2760 AssertRCReturn(rc, rc);
2761
2762 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2763 AssertRCReturn(rc, rc);
2764
2765 Log(("hwaccmR3Load: patch %d\n", i));
2766 Log(("Key = %x\n", pPatch->Core.Key));
2767 Log(("cbOp = %d\n", pPatch->cbOp));
2768 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2769 Log(("type = %d\n", pPatch->enmType));
2770 Log(("srcop = %d\n", pPatch->uSrcOperand));
2771 Log(("dstop = %d\n", pPatch->uDstOperand));
2772 Log(("cFaults = %d\n", pPatch->cFaults));
2773 Log(("target = %x\n", pPatch->pJumpTarget));
2774 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2775 AssertRC(rc);
2776 }
2777 }
2778#endif
2779
2780 /* Recheck all VCPUs if we can go straight into hwaccm execution mode. */
2781 if (HWACCMIsEnabled(pVM))
2782 {
2783 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2784 {
2785 PVMCPU pVCpu = &pVM->aCpus[i];
2786
2787 HWACCMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2788 }
2789 }
2790 return VINF_SUCCESS;
2791}
2792
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