HWACCM.cpp@ 5458

Last change on this file since 5458 was 5073, checked in by vboxsync, 17 years ago
Limit the amount of resume loops
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 34.1 KB

Line
1	/* $Id: HWACCM.cpp 5073 2007-09-27 11:06:28Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HWACCM
22	#include <VBox/cpum.h>
23	#include <VBox/stam.h>
24	#include <VBox/mm.h>
25	#include <VBox/pdm.h>
26	#include <VBox/pgm.h>
27	#include <VBox/trpm.h>
28	#include <VBox/dbgf.h>
29	#include <VBox/hwacc_vmx.h>
30	#include <VBox/hwacc_svm.h>
31	#include "HWACCMInternal.h"
32	#include <VBox/vm.h>
33	#include <VBox/err.h>
34	#include <VBox/param.h>
35	#include <VBox/patm.h>
36	#include <VBox/csam.h>
37	#include <VBox/selm.h>
38
39	#include <iprt/assert.h>
40	#include <VBox/log.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43	#include <iprt/thread.h>
44
45
46	/*******************************************************************************
47	* Internal Functions *
48	*******************************************************************************/
49	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
50	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
51
52
53	/**
54	* Initializes the HWACCM.
55	*
56	* @returns VBox status code.
57	* @param pVM The VM to operate on.
58	*/
59	HWACCMR3DECL(int) HWACCMR3Init(PVM pVM)
60	{
61	LogFlow(("HWACCMR3Init\n"));
62
63	/*
64	* Assert alignment and sizes.
65	*/
66	AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
67	AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
68
69	/* Some structure checks. */
70	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
71	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
72	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
73	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
74
75	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
76	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
77	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
78	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
79	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
80	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
81	AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
82
83
84	/*
85	* Register the saved state data unit.
86	*/
87	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
88	NULL, hwaccmR3Save, NULL,
89	NULL, hwaccmR3Load, NULL);
90	if (VBOX_FAILURE(rc))
91	return rc;
92
93	/** @todo Make sure both pages are either not accessible or readonly! */
94	/* Allocate one page for VMXON. */
95	pVM->hwaccm.s.vmx.pVMXON = SUPContAlloc(1, &pVM->hwaccm.s.vmx.pVMXONPhys);
96	if (pVM->hwaccm.s.vmx.pVMXON == 0)
97	{
98	AssertMsgFailed(("SUPContAlloc failed!!\n"));
99	return VERR_NO_MEMORY;
100	}
101	memset(pVM->hwaccm.s.vmx.pVMXON, 0, PAGE_SIZE);
102
103	/* Allocate one page for the VM control structure (VMCS). */
104	pVM->hwaccm.s.vmx.pVMCS = SUPContAlloc(1, &pVM->hwaccm.s.vmx.pVMCSPhys);
105	if (pVM->hwaccm.s.vmx.pVMCS == 0)
106	{
107	AssertMsgFailed(("SUPContAlloc failed!!\n"));
108	return VERR_NO_MEMORY;
109	}
110	memset(pVM->hwaccm.s.vmx.pVMCS, 0, PAGE_SIZE);
111
112	/* Allocate one page for the TSS we need for real mode emulation. */
113	pVM->hwaccm.s.vmx.pRealModeTSS = (PVBOXTSS)SUPContAlloc(1, &pVM->hwaccm.s.vmx.pRealModeTSSPhys);
114	if (pVM->hwaccm.s.vmx.pRealModeTSS == 0)
115	{
116	AssertMsgFailed(("SUPContAlloc failed!!\n"));
117	return VERR_NO_MEMORY;
118	}
119	/* We initialize it properly later as we can reuse it for SVM */
120	memset(pVM->hwaccm.s.vmx.pRealModeTSS, 0, PAGE_SIZE);
121
122	/* Reuse those three pages for AMD SVM. (one is active; never both) */
123	pVM->hwaccm.s.svm.pHState = pVM->hwaccm.s.vmx.pVMXON;
124	pVM->hwaccm.s.svm.pHStatePhys = pVM->hwaccm.s.vmx.pVMXONPhys;
125	pVM->hwaccm.s.svm.pVMCB = pVM->hwaccm.s.vmx.pVMCS;
126	pVM->hwaccm.s.svm.pVMCBPhys = pVM->hwaccm.s.vmx.pVMCSPhys;
127	pVM->hwaccm.s.svm.pVMCBHost = pVM->hwaccm.s.vmx.pRealModeTSS;
128	pVM->hwaccm.s.svm.pVMCBHostPhys = pVM->hwaccm.s.vmx.pRealModeTSSPhys;
129
130	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
131	pVM->hwaccm.s.svm.pIOBitmap = SUPContAlloc(3, &pVM->hwaccm.s.svm.pIOBitmapPhys);
132	if (pVM->hwaccm.s.svm.pIOBitmap == 0)
133	{
134	AssertMsgFailed(("SUPContAlloc failed!!\n"));
135	return VERR_NO_MEMORY;
136	}
137	/* Set all bits to intercept all IO accesses. */
138	memset(pVM->hwaccm.s.svm.pIOBitmap, 0xff, PAGE_SIZE*3);
139
140	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
141	pVM->hwaccm.s.svm.pMSRBitmap = SUPContAlloc(2, &pVM->hwaccm.s.svm.pMSRBitmapPhys);
142	if (pVM->hwaccm.s.svm.pMSRBitmap == 0)
143	{
144	AssertMsgFailed(("SUPContAlloc failed!!\n"));
145	return VERR_NO_MEMORY;
146	}
147	/* Set all bits to intercept all MSR accesses. */
148	memset(pVM->hwaccm.s.svm.pMSRBitmap, 0xff, PAGE_SIZE*2);
149
150	/* Misc initialisation. */
151	pVM->hwaccm.s.vmx.fSupported = false;
152	pVM->hwaccm.s.svm.fSupported = false;
153	pVM->hwaccm.s.vmx.fEnabled = false;
154	pVM->hwaccm.s.svm.fEnabled = false;
155
156	pVM->hwaccm.s.fActive = false;
157
158	/* On first entry we'll sync everything. */
159	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
160
161	pVM->hwaccm.s.vmx.cr0_mask = 0;
162	pVM->hwaccm.s.vmx.cr4_mask = 0;
163
164	/*
165	* Statistics.
166	*/
167	STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
168	STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
169	STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
170
171	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
172	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
173	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
174	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
175	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
176	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
177	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
178	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
179	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
180	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
181	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
182	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
183	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
184	STAM_REG(pVM, &pVM->hwaccm.s.StatExitRdtsc, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Rdtsc", STAMUNIT_OCCURENCES, "Nr of occurances");
185	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
186	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
187	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
188	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
189	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
190	STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
191	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
192	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
193	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/WriteString", STAMUNIT_OCCURENCES, "Nr of occurances");
194	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringRead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/ReadString", STAMUNIT_OCCURENCES, "Nr of occurances");
195	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
196	STAM_REG(pVM, &pVM->hwaccm.s.StatExitMaxResume, STAMTYPE_COUNTER, "/HWACCM/Exit/Safety/MaxResume", STAMUNIT_OCCURENCES, "Nr of occurances");
197
198	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
199	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
200
201	STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
202	STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
203	STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
204
205	pVM->hwaccm.s.pStatExitReason = 0;
206
207	#ifdef VBOX_WITH_STATISTICS
208	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVM->hwaccm.s.pStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.pStatExitReason);
209	AssertRC(rc);
210	if (VBOX_SUCCESS(rc))
211	{
212	for (int i=0;i<MAX_EXITREASON_STAT;i++)
213	{
214	char szName[64];
215	RTStrPrintf(szName, sizeof(szName), "/HWACCM/Exit/Reason/%02x", i);
216	int rc = STAMR3Register(pVM, &pVM->hwaccm.s.pStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "Exit reason");
217	AssertRC(rc);
218	}
219	}
220	pVM->hwaccm.s.pStatExitReasonR0 = MMHyperR3ToR0(pVM, pVM->hwaccm.s.pStatExitReason);
221	Assert(pVM->hwaccm.s.pStatExitReasonR0);
222	#endif
223
224	/* Disabled by default. */
225	pVM->fHWACCMEnabled = false;
226
227	/* HWACCM support must be explicitely enabled in the configuration file. */
228	pVM->hwaccm.s.fAllowed = false;
229	CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed);
230
231	return VINF_SUCCESS;
232	}
233
234
235	/**
236	* Turns off normal raw mode features
237	*
238	* @param pVM The VM to operate on.
239	*/
240	static void hwaccmr3DisableRawMode(PVM pVM)
241	{
242	/* Disable PATM & CSAM. */
243	PATMR3AllowPatching(pVM, false);
244	CSAMDisableScanning(pVM);
245
246	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
247	SELMR3DisableMonitoring(pVM);
248	TRPMR3DisableMonitoring(pVM);
249
250	/* The hidden selector registers are now valid. */
251	CPUMSetHiddenSelRegsValid(pVM, true);
252
253	/* Disable the switcher code (safety precaution). */
254	VMMR3DisableSwitcher(pVM);
255
256	/* Disable mapping of the hypervisor into the shadow page table. */
257	PGMR3ChangeShwPDMappings(pVM, false);
258
259	/* Disable the switcher */
260	VMMR3DisableSwitcher(pVM);
261	}
262
263	/**
264	* Applies relocations to data and code managed by this
265	* component. This function will be called at init and
266	* whenever the VMM need to relocate it self inside the GC.
267	*
268	* @param pVM The VM.
269	*/
270	HWACCMR3DECL(void) HWACCMR3Relocate(PVM pVM)
271	{
272	#ifdef LOG_ENABLED
273	Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
274	#endif
275
276	if (pVM->hwaccm.s.fAllowed == false)
277	return ;
278
279	if (pVM->hwaccm.s.vmx.fSupported)
280	{
281	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
282
283	if ( pVM->hwaccm.s.fInitialized == false
284	&& pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
285	{
286	uint64_t val;
287
288	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
289	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
290	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
291	LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
292	LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
293	LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
294	LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
295	LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
296
297	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls));
298	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL;
299	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
300	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
301	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
302	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
303	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls;
304	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
305	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT must be set\n"));
306	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
307	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT must be set\n"));
308
309	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls));
310	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL;
311	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
312	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
313	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
314	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
315	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
316	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
317	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
318	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
319	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
320	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
321	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
322	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
323	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
324	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
325	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
326	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
327	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
328	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
329	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
330	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
331	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
332	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
333	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
334	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
335	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
336	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
337	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
338	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
339	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
340	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
341	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
342	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
343	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls;
344	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
345	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT must be set\n"));
346	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
347	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET must be set\n"));
348	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
349	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT must be set\n"));
350	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
351	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT must be set\n"));
352	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
353	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT must be set\n"));
354	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
355	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT must be set\n"));
356	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
357	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT must be set\n"));
358	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
359	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT must be set\n"));
360	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
361	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT must be set\n"));
362	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
363	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW must be set\n"));
364	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
365	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT must be set\n"));
366	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
367	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT must be set\n"));
368	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
369	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS must be set\n"));
370	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
371	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS must be set\n"));
372	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
373	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT must be set\n"));
374	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
375	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT must be set\n"));
376
377	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry));
378	val = pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL;
379	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
380	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
381	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
382	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
383	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
384	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
385	val = pVM->hwaccm.s.vmx.msr.vmx_entry;
386	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
387	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE must be set\n"));
388	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
389	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM must be set\n"));
390	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
391	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON must be set\n"));
392
393	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit));
394	val = pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL;
395	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
396	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
397	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
398	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
399	val = pVM->hwaccm.s.vmx.msr.vmx_exit;
400	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
401	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 must be set\n"));
402	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
403	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ must be set\n"));
404
405	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
406	LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
407	LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
408	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
409	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
410
411	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
412	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
413	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
414	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
415	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
416
417	/* Only try once. */
418	pVM->hwaccm.s.fInitialized = true;
419
420	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
421	* for I/O operations. */
422	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
423	/* Bit set to 0 means redirection enabled. */
424	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
425
426	int rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
427	AssertRC(rc);
428	if (rc == VINF_SUCCESS)
429	{
430	hwaccmr3DisableRawMode(pVM);
431
432	pVM->fHWACCMEnabled = true;
433	pVM->hwaccm.s.vmx.fEnabled = true;
434	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
435	LogRel(("HWACCM: VMX enabled!\n"));
436	}
437	else
438	{
439	LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
440	LogRel(("HWACCM: Last instruction error %x\n", pVM->hwaccm.s.vmx.ulLastInstrError));
441	pVM->fHWACCMEnabled = false;
442	}
443	}
444	}
445	else
446	if (pVM->hwaccm.s.svm.fSupported)
447	{
448	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
449
450	if (pVM->hwaccm.s.fInitialized == false)
451	{
452	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
453	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
454	LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
455	LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.svm.u32MaxASID));
456
457	/* Only try once. */
458	pVM->hwaccm.s.fInitialized = true;
459
460	int rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
461	AssertRC(rc);
462	if (rc == VINF_SUCCESS)
463	{
464	hwaccmr3DisableRawMode(pVM);
465	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
466
467	pVM->fHWACCMEnabled = true;
468	pVM->hwaccm.s.svm.fEnabled = true;
469	}
470	else
471	{
472	pVM->fHWACCMEnabled = false;
473	}
474	}
475	}
476	else
477	if (pVM->hwaccm.s.fHWACCMR0Init)
478	{
479	LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Vrc\n", pVM->hwaccm.s.lLastError));
480	LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
481	}
482
483	}
484
485
486	/**
487	* Checks hardware accelerated raw mode is allowed.
488	*
489	* @returns boolean
490	* @param pVM The VM to operate on.
491	*/
492	HWACCMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
493	{
494	return pVM->hwaccm.s.fAllowed;
495	}
496
497
498	/**
499	* Notification callback which is called whenever there is a chance that a CR3
500	* value might have changed.
501	* This is called by PGM.
502	*
503	* @param pVM The VM to operate on.
504	* @param enmShadowMode New paging mode.
505	*/
506	HWACCMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode)
507	{
508	pVM->hwaccm.s.enmShadowMode = enmShadowMode;
509	}
510
511	/**
512	* Terminates the HWACCM.
513	*
514	* Termination means cleaning up and freeing all resources,
515	* the VM it self is at this point powered off or suspended.
516	*
517	* @returns VBox status code.
518	* @param pVM The VM to operate on.
519	*/
520	HWACCMR3DECL(int) HWACCMR3Term(PVM pVM)
521	{
522	if (pVM->hwaccm.s.pStatExitReason)
523	{
524	MMHyperFree(pVM, pVM->hwaccm.s.pStatExitReason);
525	pVM->hwaccm.s.pStatExitReason = 0;
526	}
527
528	if (pVM->hwaccm.s.vmx.pVMXON)
529	{
530	SUPContFree(pVM->hwaccm.s.vmx.pVMXON, 1);
531	pVM->hwaccm.s.vmx.pVMXON = 0;
532	}
533	if (pVM->hwaccm.s.vmx.pVMCS)
534	{
535	SUPContFree(pVM->hwaccm.s.vmx.pVMCS, 1);
536	pVM->hwaccm.s.vmx.pVMCS = 0;
537	}
538	if (pVM->hwaccm.s.vmx.pRealModeTSS)
539	{
540	SUPContFree(pVM->hwaccm.s.vmx.pRealModeTSS, 1);
541	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
542	}
543	if (pVM->hwaccm.s.svm.pIOBitmap)
544	{
545	SUPContFree(pVM->hwaccm.s.svm.pIOBitmap, 3);
546	pVM->hwaccm.s.svm.pIOBitmap = 0;
547	}
548	if (pVM->hwaccm.s.svm.pMSRBitmap)
549	{
550	SUPContFree(pVM->hwaccm.s.svm.pMSRBitmap, 2);
551	pVM->hwaccm.s.svm.pMSRBitmap = 0;
552	}
553	return 0;
554	}
555
556
557	/**
558	* The VM is being reset.
559	*
560	* For the HWACCM component this means that any GDT/LDT/TSS monitors
561	* needs to be removed.
562	*
563	* @param pVM VM handle.
564	*/
565	HWACCMR3DECL(void) HWACCMR3Reset(PVM pVM)
566	{
567	LogFlow(("HWACCMR3Reset:\n"));
568
569	if (pVM->fHWACCMEnabled)
570	hwaccmr3DisableRawMode(pVM);
571
572	/* On first entry we'll sync everything. */
573	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
574
575	pVM->hwaccm.s.vmx.cr0_mask = 0;
576	pVM->hwaccm.s.vmx.cr4_mask = 0;
577
578	pVM->hwaccm.s.Event.fPending = false;
579	}
580
581	/**
582	* Checks if we can currently use hardware accelerated raw mode.
583	*
584	* @returns boolean
585	* @param pVM The VM to operate on.
586	* @param pCtx Partial VM execution context
587	*/
588	HWACCMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
589	{
590	uint32_t mask;
591
592	Assert(pVM->fHWACCMEnabled);
593
594	/* AMD SVM supports real & protected mode with or without paging. */
595	if (pVM->hwaccm.s.svm.fEnabled)
596	{
597	pVM->hwaccm.s.fActive = true;
598	return true;
599	}
600
601	/* @todo we can support real-mode by using v86 and protected mode without paging with identity mapped pages.
602	* (but do we really care?)
603	*/
604
605	pVM->hwaccm.s.fActive = false;
606
607	/** @note The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
608
609	#ifndef HWACCM_VMX_EMULATE_ALL
610	/* Too early for VMX. */
611	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
612	return false;
613
614	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
615	if (pCtx->csHid.Attr.n.u1Present == 0)
616	return false;
617	if (pCtx->ssHid.Attr.n.u1Present == 0)
618	return false;
619
620	/** @todo if we remove this check, then Windows XP install fails during the textmode phase */
621	if (!(pCtx->cr0 & X86_CR0_WRITE_PROTECT))
622	return false;
623	#endif
624
625	if (pVM->hwaccm.s.vmx.fEnabled)
626	{
627	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
628	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
629	/* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
630	mask &= ~X86_CR0_NE;
631	#ifdef HWACCM_VMX_EMULATE_ALL
632	/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
633	mask &= ~(X86_CR0_PG\|X86_CR0_PE);
634	#endif
635	if ((pCtx->cr0 & mask) != mask)
636	return false;
637
638	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
639	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
640	if ((pCtx->cr0 & mask) != 0)
641	return false;
642
643	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
644	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
645	mask &= ~X86_CR4_VMXE;
646	if ((pCtx->cr4 & mask) != mask)
647	return false;
648
649	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
650	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
651	if ((pCtx->cr4 & mask) != 0)
652	return false;
653
654	pVM->hwaccm.s.fActive = true;
655	return true;
656	}
657
658	return false;
659	}
660
661	/**
662	* Checks if we are currently using hardware accelerated raw mode.
663	*
664	* @returns boolean
665	* @param pVM The VM to operate on.
666	*/
667	HWACCMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
668	{
669	return pVM->hwaccm.s.fActive;
670	}
671
672	/**
673	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
674	*
675	* @returns boolean
676	* @param pVM The VM to operate on.
677	*/
678	HWACCMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
679	{
680	return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
681	}
682
683	/**
684	* Execute state save operation.
685	*
686	* @returns VBox status code.
687	* @param pVM VM Handle.
688	* @param pSSM SSM operation handle.
689	*/
690	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
691	{
692	int rc;
693
694	Log(("hwaccmR3Save:\n"));
695
696	/*
697	* Save the basic bits - fortunately all the other things can be resynced on load.
698	*/
699	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
700	AssertRCReturn(rc, rc);
701	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
702	AssertRCReturn(rc, rc);
703	rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
704	AssertRCReturn(rc, rc);
705
706	return VINF_SUCCESS;
707	}
708
709
710	/**
711	* Execute state load operation.
712	*
713	* @returns VBox status code.
714	* @param pVM VM Handle.
715	* @param pSSM SSM operation handle.
716	* @param u32Version Data layout version.
717	*/
718	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
719	{
720	int rc;
721
722	Log(("hwaccmR3Load:\n"));
723
724	/*
725	* Validate version.
726	*/
727	if (u32Version != HWACCM_SSM_VERSION)
728	{
729	Log(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
730	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
731	}
732	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
733	AssertRCReturn(rc, rc);
734	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
735	AssertRCReturn(rc, rc);
736	rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
737	AssertRCReturn(rc, rc);
738
739	return VINF_SUCCESS;
740	}
741
742
743
744

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source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 5458

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