VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 8841

Last change on this file since 8841 was 8816, checked in by vboxsync, 17 years ago

Added a release log statement about erratum 170
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1/* $Id: HWACCM.cpp 8816 2008-05-14 14:49:10Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/hwacc_vmx.h>
34#include <VBox/hwacc_svm.h>
35#include "HWACCMInternal.h"
36#include <VBox/vm.h>
37#include <VBox/err.h>
38#include <VBox/param.h>
39#include <VBox/patm.h>
40#include <VBox/csam.h>
41#include <VBox/selm.h>
42
43#include <iprt/assert.h>
44#include <VBox/log.h>
45#include <iprt/asm.h>
46#include <iprt/string.h>
47#include <iprt/thread.h>
48
49
50/*******************************************************************************
51* Internal Functions *
52*******************************************************************************/
53static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
54static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
55
56
57/**
58 * Initializes the HWACCM.
59 *
60 * @returns VBox status code.
61 * @param pVM The VM to operate on.
62 */
63HWACCMR3DECL(int) HWACCMR3Init(PVM pVM)
64{
65 LogFlow(("HWACCMR3Init\n"));
66
67 /*
68 * Assert alignment and sizes.
69 */
70 AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
71 AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
72
73 /* Some structure checks. */
74 AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
75 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
76 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
77 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
78
79 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
80 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
81 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
82 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
83 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
84 AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
85 AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
86
87
88 /*
89 * Register the saved state data unit.
90 */
91 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
92 NULL, hwaccmR3Save, NULL,
93 NULL, hwaccmR3Load, NULL);
94 if (VBOX_FAILURE(rc))
95 return rc;
96
97 /* Misc initialisation. */
98 pVM->hwaccm.s.vmx.fSupported = false;
99 pVM->hwaccm.s.svm.fSupported = false;
100 pVM->hwaccm.s.vmx.fEnabled = false;
101 pVM->hwaccm.s.svm.fEnabled = false;
102
103 pVM->hwaccm.s.fActive = false;
104
105 /* On first entry we'll sync everything. */
106 pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
107
108 pVM->hwaccm.s.vmx.cr0_mask = 0;
109 pVM->hwaccm.s.vmx.cr4_mask = 0;
110
111 /*
112 * Statistics.
113 */
114 STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
115 STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
116 STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
117
118 STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
119 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
120 STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
121 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
122 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
123 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
124 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
125 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
126 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
127 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
128 STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
129 STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
130 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
131 STAM_REG(pVM, &pVM->hwaccm.s.StatExitRdtsc, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Rdtsc", STAMUNIT_OCCURENCES, "Nr of occurances");
132 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
133 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
134 STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
135 STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
136 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
137 STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
138 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
139 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
140 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/WriteString", STAMUNIT_OCCURENCES, "Nr of occurances");
141 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringRead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/ReadString", STAMUNIT_OCCURENCES, "Nr of occurances");
142 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
143 STAM_REG(pVM, &pVM->hwaccm.s.StatExitMaxResume, STAMTYPE_COUNTER, "/HWACCM/Exit/Safety/MaxResume", STAMUNIT_OCCURENCES, "Nr of occurances");
144
145 STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
146 STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
147
148 STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
149 STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
150 STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
151
152 pVM->hwaccm.s.pStatExitReason = 0;
153
154#ifdef VBOX_WITH_STATISTICS
155 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVM->hwaccm.s.pStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.pStatExitReason);
156 AssertRC(rc);
157 if (VBOX_SUCCESS(rc))
158 {
159 for (int i=0;i<MAX_EXITREASON_STAT;i++)
160 {
161 char szName[64];
162 RTStrPrintf(szName, sizeof(szName), "/HWACCM/Exit/Reason/%02x", i);
163 int rc = STAMR3Register(pVM, &pVM->hwaccm.s.pStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "Exit reason");
164 AssertRC(rc);
165 }
166 }
167 pVM->hwaccm.s.pStatExitReasonR0 = MMHyperR3ToR0(pVM, pVM->hwaccm.s.pStatExitReason);
168 Assert(pVM->hwaccm.s.pStatExitReasonR0);
169#endif
170
171 /* Disabled by default. */
172 pVM->fHWACCMEnabled = false;
173
174 /* HWACCM support must be explicitely enabled in the configuration file. */
175 pVM->hwaccm.s.fAllowed = false;
176 CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed);
177
178 return VINF_SUCCESS;
179}
180
181
182/**
183 * Turns off normal raw mode features
184 *
185 * @param pVM The VM to operate on.
186 */
187static void hwaccmr3DisableRawMode(PVM pVM)
188{
189 /* Disable PATM & CSAM. */
190 PATMR3AllowPatching(pVM, false);
191 CSAMDisableScanning(pVM);
192
193 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
194 SELMR3DisableMonitoring(pVM);
195 TRPMR3DisableMonitoring(pVM);
196
197 /* The hidden selector registers are now valid. */
198 CPUMSetHiddenSelRegsValid(pVM, true);
199
200 /* Disable the switcher code (safety precaution). */
201 VMMR3DisableSwitcher(pVM);
202
203 /* Disable mapping of the hypervisor into the shadow page table. */
204 PGMR3ChangeShwPDMappings(pVM, false);
205
206 /* Disable the switcher */
207 VMMR3DisableSwitcher(pVM);
208}
209
210/**
211 * Initialize VT-x or AMD-V.
212 *
213 * @returns VBox status code.
214 * @param pVM The VM handle.
215 */
216HWACCMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
217{
218 int rc;
219
220 if ( !pVM->hwaccm.s.vmx.fSupported
221 && !pVM->hwaccm.s.svm.fSupported)
222 {
223 LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Vrc\n", pVM->hwaccm.s.lLastError));
224 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
225 return VINF_SUCCESS;
226 }
227
228 /*
229 * Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
230 * because it turns off paging, which is not allowed in VMX root mode.
231 *
232 * To simplify matters we'll just force all running VMs to either use raw or hwaccm mode. No mixing allowed.
233 *
234 */
235 /* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
236 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
237 if (VBOX_FAILURE(rc))
238 {
239 LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Vrc\n", rc));
240 LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
241 /* Invert the selection */
242 pVM->hwaccm.s.fAllowed ^= 1;
243 LogRel(("HWACCMR3InitFinalize: new HWACCM status = %s\n", pVM->hwaccm.s.fAllowed ? "enabled" : "disabled"));
244
245 if (pVM->hwaccm.s.fAllowed)
246 {
247 if (pVM->hwaccm.s.vmx.fSupported)
248 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses Intel VT-x hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using VT-x as well.\n");
249 else
250 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses AMD-V hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using AMD-V as well.\n");
251 }
252 else
253 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses software virtualization. It is not allowed to simultaneously use VT-x or AMD-V, therefore this VM will be run using software virtualization as well.\n");
254 }
255
256 if (pVM->hwaccm.s.fAllowed == false)
257 return VINF_SUCCESS; /* disabled */
258
259 Assert(!pVM->fHWACCMEnabled);
260
261 if (pVM->hwaccm.s.vmx.fSupported)
262 {
263 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
264
265 if ( pVM->hwaccm.s.fInitialized == false
266 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
267 {
268 uint64_t val;
269
270 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
271 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
272 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
273 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
274 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
275 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
276 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
277 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
278
279 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls));
280 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL;
281 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
282 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
283 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
284 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
285 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls;
286 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
287 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
288 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
289 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
290
291 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls));
292 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL;
293 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
294 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
295 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
296 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
297 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
298 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
299 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
300 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
301 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
302 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
303 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
304 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
305 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
306 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
307 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
308 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
309 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
310 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
311 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
312 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
313 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
314 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
315 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
316 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
317 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
318 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
319 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
320 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
321 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
322 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
323 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
324 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
325 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls;
326 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
327 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
328 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
329 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
330 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
331 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
332 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
333 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
334 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
335 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
336 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
337 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
338 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
339 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
340 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
341 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
342 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
343 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
344 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
345 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
346 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
347 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
348 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
349 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
350 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
351 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
352 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
353 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
354 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
355 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
356 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
357 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
358
359 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry));
360 val = pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL;
361 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
362 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
363 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
364 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
365 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
366 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
367 val = pVM->hwaccm.s.vmx.msr.vmx_entry;
368 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
369 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
370 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
371 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
372 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
373 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
374
375 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit));
376 val = pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL;
377 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
378 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
379 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
380 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
381 val = pVM->hwaccm.s.vmx.msr.vmx_exit;
382 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
383 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
384 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
385 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
386
387 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
388 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
389 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
390 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
391 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
392
393 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
394 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
395 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
396 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
397 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
398
399 /* Only try once. */
400 pVM->hwaccm.s.fInitialized = true;
401
402 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
403 AssertRC(rc);
404 if (rc == VINF_SUCCESS)
405 {
406 hwaccmr3DisableRawMode(pVM);
407
408 pVM->fHWACCMEnabled = true;
409 pVM->hwaccm.s.vmx.fEnabled = true;
410 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
411 LogRel(("HWACCM: VMX enabled!\n"));
412 }
413 else
414 {
415 LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
416 LogRel(("HWACCM: Last instruction error %x\n", pVM->hwaccm.s.vmx.ulLastInstrError));
417 pVM->fHWACCMEnabled = false;
418 }
419 }
420 }
421 else
422 if (pVM->hwaccm.s.svm.fSupported)
423 {
424 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
425
426 if (pVM->hwaccm.s.fInitialized == false)
427 {
428 /* Erratum 170 which requires a forced TLB flush for each world switch:
429 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
430 *
431 * All BH-G1/2 and DH-G1/2 models include a fix:
432 * Athlon X2: 0x6b 1/2
433 * 0x68 1/2
434 * Athlon 64: 0x7f 1
435 * 0x6f 2
436 * Sempron: 0x7f 1/2
437 * 0x6f 2
438 * 0x6c 2
439 * 0x7c 2
440 * Turion 64: 0x68 2
441 *
442 */
443 uint32_t u32Dummy;
444 uint32_t u32Version, u32Family, u32Model, u32Stepping;
445 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
446 u32Family = ((u32Version >> 8) & 0xf) + (((u32Version >> 8) & 0xf) == 0xf ? (u32Version >> 20) & 0x7f : 0);
447 u32Model = ((u32Version >> 4) & 0xf);
448 u32Model = u32Model | ((u32Model == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
449 u32Stepping = u32Version & 0xf;
450 if ( u32Family == 0xf
451 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
452 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
453 {
454 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
455 }
456
457 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
458 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
459 LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
460 LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.svm.u32MaxASID));
461
462 /* Only try once. */
463 pVM->hwaccm.s.fInitialized = true;
464
465 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
466 AssertRC(rc);
467 if (rc == VINF_SUCCESS)
468 {
469 hwaccmr3DisableRawMode(pVM);
470 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
471#if 0 /* not yet */
472 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
473#endif
474
475 pVM->fHWACCMEnabled = true;
476 pVM->hwaccm.s.svm.fEnabled = true;
477 }
478 else
479 {
480 pVM->fHWACCMEnabled = false;
481 }
482 }
483 }
484 return VINF_SUCCESS;
485}
486
487/**
488 * Applies relocations to data and code managed by this
489 * component. This function will be called at init and
490 * whenever the VMM need to relocate it self inside the GC.
491 *
492 * @param pVM The VM.
493 */
494HWACCMR3DECL(void) HWACCMR3Relocate(PVM pVM)
495{
496 Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
497 return;
498}
499
500
501/**
502 * Checks hardware accelerated raw mode is allowed.
503 *
504 * @returns boolean
505 * @param pVM The VM to operate on.
506 */
507HWACCMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
508{
509 return pVM->hwaccm.s.fAllowed;
510}
511
512
513/**
514 * Notification callback which is called whenever there is a chance that a CR3
515 * value might have changed.
516 * This is called by PGM.
517 *
518 * @param pVM The VM to operate on.
519 * @param enmShadowMode New paging mode.
520 */
521HWACCMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode)
522{
523 pVM->hwaccm.s.enmShadowMode = enmShadowMode;
524}
525
526/**
527 * Terminates the HWACCM.
528 *
529 * Termination means cleaning up and freeing all resources,
530 * the VM it self is at this point powered off or suspended.
531 *
532 * @returns VBox status code.
533 * @param pVM The VM to operate on.
534 */
535HWACCMR3DECL(int) HWACCMR3Term(PVM pVM)
536{
537 if (pVM->hwaccm.s.pStatExitReason)
538 {
539 MMHyperFree(pVM, pVM->hwaccm.s.pStatExitReason);
540 pVM->hwaccm.s.pStatExitReason = 0;
541 }
542 return 0;
543}
544
545
546/**
547 * The VM is being reset.
548 *
549 * For the HWACCM component this means that any GDT/LDT/TSS monitors
550 * needs to be removed.
551 *
552 * @param pVM VM handle.
553 */
554HWACCMR3DECL(void) HWACCMR3Reset(PVM pVM)
555{
556 LogFlow(("HWACCMR3Reset:\n"));
557
558 if (pVM->fHWACCMEnabled)
559 hwaccmr3DisableRawMode(pVM);
560
561 /* On first entry we'll sync everything. */
562 pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
563
564 pVM->hwaccm.s.vmx.cr0_mask = 0;
565 pVM->hwaccm.s.vmx.cr4_mask = 0;
566
567 pVM->hwaccm.s.Event.fPending = false;
568}
569
570/**
571 * Checks if we can currently use hardware accelerated raw mode.
572 *
573 * @returns boolean
574 * @param pVM The VM to operate on.
575 * @param pCtx Partial VM execution context
576 */
577HWACCMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
578{
579 Assert(pVM->fHWACCMEnabled);
580
581 /* AMD SVM supports real & protected mode with or without paging. */
582 if (pVM->hwaccm.s.svm.fEnabled)
583 {
584 pVM->hwaccm.s.fActive = true;
585 return true;
586 }
587
588 /* @todo we can support real-mode by using v86 and protected mode without paging with identity mapped pages.
589 * (but do we really care?)
590 */
591
592 pVM->hwaccm.s.fActive = false;
593
594 /** @note The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
595
596#ifndef HWACCM_VMX_EMULATE_ALL
597 /* Too early for VMX. */
598 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
599 return false;
600
601 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
602 if (pCtx->csHid.Attr.n.u1Present == 0)
603 return false;
604 if (pCtx->ssHid.Attr.n.u1Present == 0)
605 return false;
606#endif
607
608 if (pVM->hwaccm.s.vmx.fEnabled)
609 {
610 uint32_t mask;
611
612 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
613 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
614 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
615 mask &= ~X86_CR0_NE;
616#ifdef HWACCM_VMX_EMULATE_ALL
617 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
618 mask &= ~(X86_CR0_PG|X86_CR0_PE);
619#endif
620 if ((pCtx->cr0 & mask) != mask)
621 return false;
622
623 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
624 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
625 if ((pCtx->cr0 & mask) != 0)
626 return false;
627
628 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
629 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
630 mask &= ~X86_CR4_VMXE;
631 if ((pCtx->cr4 & mask) != mask)
632 return false;
633
634 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
635 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
636 if ((pCtx->cr4 & mask) != 0)
637 return false;
638
639 pVM->hwaccm.s.fActive = true;
640 return true;
641 }
642
643 return false;
644}
645
646/**
647 * Checks if we are currently using hardware accelerated raw mode.
648 *
649 * @returns boolean
650 * @param pVM The VM to operate on.
651 */
652HWACCMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
653{
654 return pVM->hwaccm.s.fActive;
655}
656
657/**
658 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
659 *
660 * @returns boolean
661 * @param pVM The VM to operate on.
662 */
663HWACCMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
664{
665 return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
666}
667
668/**
669 * Execute state save operation.
670 *
671 * @returns VBox status code.
672 * @param pVM VM Handle.
673 * @param pSSM SSM operation handle.
674 */
675static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
676{
677 int rc;
678
679 Log(("hwaccmR3Save:\n"));
680
681 /*
682 * Save the basic bits - fortunately all the other things can be resynced on load.
683 */
684 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
685 AssertRCReturn(rc, rc);
686 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
687 AssertRCReturn(rc, rc);
688 rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
689 AssertRCReturn(rc, rc);
690
691 return VINF_SUCCESS;
692}
693
694
695/**
696 * Execute state load operation.
697 *
698 * @returns VBox status code.
699 * @param pVM VM Handle.
700 * @param pSSM SSM operation handle.
701 * @param u32Version Data layout version.
702 */
703static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
704{
705 int rc;
706
707 Log(("hwaccmR3Load:\n"));
708
709 /*
710 * Validate version.
711 */
712 if (u32Version != HWACCM_SSM_VERSION)
713 {
714 Log(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
715 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
716 }
717 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
718 AssertRCReturn(rc, rc);
719 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
720 AssertRCReturn(rc, rc);
721 rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
722 AssertRCReturn(rc, rc);
723
724 return VINF_SUCCESS;
725}
726
727
728
729
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