VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 9016

Last change on this file since 9016 was 8943, checked in by vboxsync, 17 years ago

AMD-V: flush TLB when the flush count for the cpu has changed
AMD-V: Some preparational work for nested paging.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 36.3 KB
Line 
1/* $Id: HWACCM.cpp 8943 2008-05-20 09:15:53Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/hwacc_vmx.h>
34#include <VBox/hwacc_svm.h>
35#include "HWACCMInternal.h"
36#include <VBox/vm.h>
37#include <VBox/err.h>
38#include <VBox/param.h>
39#include <VBox/patm.h>
40#include <VBox/csam.h>
41#include <VBox/selm.h>
42
43#include <iprt/assert.h>
44#include <VBox/log.h>
45#include <iprt/asm.h>
46#include <iprt/string.h>
47#include <iprt/thread.h>
48
49
50/*******************************************************************************
51* Internal Functions *
52*******************************************************************************/
53static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
54static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
55
56
57/**
58 * Initializes the HWACCM.
59 *
60 * @returns VBox status code.
61 * @param pVM The VM to operate on.
62 */
63HWACCMR3DECL(int) HWACCMR3Init(PVM pVM)
64{
65 LogFlow(("HWACCMR3Init\n"));
66
67 /*
68 * Assert alignment and sizes.
69 */
70 AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
71 AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
72
73 /* Some structure checks. */
74 AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
75 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
76 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
77 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
78
79 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
80 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
81 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
82 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
83 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
84 AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
85 AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
86
87
88 /*
89 * Register the saved state data unit.
90 */
91 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
92 NULL, hwaccmR3Save, NULL,
93 NULL, hwaccmR3Load, NULL);
94 if (VBOX_FAILURE(rc))
95 return rc;
96
97 /* Misc initialisation. */
98 pVM->hwaccm.s.vmx.fSupported = false;
99 pVM->hwaccm.s.svm.fSupported = false;
100 pVM->hwaccm.s.vmx.fEnabled = false;
101 pVM->hwaccm.s.svm.fEnabled = false;
102
103 pVM->hwaccm.s.fActive = false;
104
105 /* On first entry we'll sync everything. */
106 pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
107
108 pVM->hwaccm.s.vmx.cr0_mask = 0;
109 pVM->hwaccm.s.vmx.cr4_mask = 0;
110
111 /*
112 * Statistics.
113 */
114 STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
115 STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
116 STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
117
118 STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
119 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
120 STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
121 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
122 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
123 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
124 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
125 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
126 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
127 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
128 STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
129 STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
130 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
131 STAM_REG(pVM, &pVM->hwaccm.s.StatExitRdtsc, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Rdtsc", STAMUNIT_OCCURENCES, "Nr of occurances");
132 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
133 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
134 STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
135 STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
136 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
137 STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
138 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
139 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
140 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/WriteString", STAMUNIT_OCCURENCES, "Nr of occurances");
141 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringRead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/ReadString", STAMUNIT_OCCURENCES, "Nr of occurances");
142 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
143 STAM_REG(pVM, &pVM->hwaccm.s.StatExitMaxResume, STAMTYPE_COUNTER, "/HWACCM/Exit/Safety/MaxResume", STAMUNIT_OCCURENCES, "Nr of occurances");
144
145 STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
146 STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
147
148 STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
149 STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
150 STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
151
152 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageManual, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
153 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBManual, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
154 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBCRxChange, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/CRx", STAMUNIT_OCCURENCES, "Nr of occurances");
155 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageInvlpg, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
156 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Switch", STAMUNIT_OCCURENCES, "Nr of occurances");
157 STAM_REG(pVM, &pVM->hwaccm.s.StatNoFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Skipped", STAMUNIT_OCCURENCES, "Nr of occurances");
158 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushASID, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/ASID", STAMUNIT_OCCURENCES, "Nr of occurances");
159
160 pVM->hwaccm.s.pStatExitReason = 0;
161
162#ifdef VBOX_WITH_STATISTICS
163 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVM->hwaccm.s.pStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.pStatExitReason);
164 AssertRC(rc);
165 if (VBOX_SUCCESS(rc))
166 {
167 for (int i=0;i<MAX_EXITREASON_STAT;i++)
168 {
169 char szName[64];
170 RTStrPrintf(szName, sizeof(szName), "/HWACCM/Exit/Reason/%02x", i);
171 int rc = STAMR3Register(pVM, &pVM->hwaccm.s.pStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "Exit reason");
172 AssertRC(rc);
173 }
174 }
175 pVM->hwaccm.s.pStatExitReasonR0 = MMHyperR3ToR0(pVM, pVM->hwaccm.s.pStatExitReason);
176 Assert(pVM->hwaccm.s.pStatExitReasonR0);
177#endif
178
179 /* Disabled by default. */
180 pVM->fHWACCMEnabled = false;
181
182 /* HWACCM support must be explicitely enabled in the configuration file. */
183 pVM->hwaccm.s.fAllowed = false;
184 CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed);
185
186 return VINF_SUCCESS;
187}
188
189
190/**
191 * Turns off normal raw mode features
192 *
193 * @param pVM The VM to operate on.
194 */
195static void hwaccmr3DisableRawMode(PVM pVM)
196{
197 /* Disable PATM & CSAM. */
198 PATMR3AllowPatching(pVM, false);
199 CSAMDisableScanning(pVM);
200
201 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
202 SELMR3DisableMonitoring(pVM);
203 TRPMR3DisableMonitoring(pVM);
204
205 /* The hidden selector registers are now valid. */
206 CPUMSetHiddenSelRegsValid(pVM, true);
207
208 /* Disable the switcher code (safety precaution). */
209 VMMR3DisableSwitcher(pVM);
210
211 /* Disable mapping of the hypervisor into the shadow page table. */
212 PGMR3ChangeShwPDMappings(pVM, false);
213
214 /* Disable the switcher */
215 VMMR3DisableSwitcher(pVM);
216}
217
218/**
219 * Initialize VT-x or AMD-V.
220 *
221 * @returns VBox status code.
222 * @param pVM The VM handle.
223 */
224HWACCMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
225{
226 int rc;
227
228 if ( !pVM->hwaccm.s.vmx.fSupported
229 && !pVM->hwaccm.s.svm.fSupported)
230 {
231 LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Vrc\n", pVM->hwaccm.s.lLastError));
232 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
233 return VINF_SUCCESS;
234 }
235
236 /*
237 * Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
238 * because it turns off paging, which is not allowed in VMX root mode.
239 *
240 * To simplify matters we'll just force all running VMs to either use raw or hwaccm mode. No mixing allowed.
241 *
242 */
243 /* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
244 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
245 if (VBOX_FAILURE(rc))
246 {
247 LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Vrc\n", rc));
248 LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
249 /* Invert the selection */
250 pVM->hwaccm.s.fAllowed ^= 1;
251 LogRel(("HWACCMR3InitFinalize: new HWACCM status = %s\n", pVM->hwaccm.s.fAllowed ? "enabled" : "disabled"));
252
253 if (pVM->hwaccm.s.fAllowed)
254 {
255 if (pVM->hwaccm.s.vmx.fSupported)
256 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses Intel VT-x hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using VT-x as well.\n");
257 else
258 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses AMD-V hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using AMD-V as well.\n");
259 }
260 else
261 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses software virtualization. It is not allowed to simultaneously use VT-x or AMD-V, therefore this VM will be run using software virtualization as well.\n");
262 }
263
264 if (pVM->hwaccm.s.fAllowed == false)
265 return VINF_SUCCESS; /* disabled */
266
267 Assert(!pVM->fHWACCMEnabled);
268
269 if (pVM->hwaccm.s.vmx.fSupported)
270 {
271 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
272
273 if ( pVM->hwaccm.s.fInitialized == false
274 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
275 {
276 uint64_t val;
277
278 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
279 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
280 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
281 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
282 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
283 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
284 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
285 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
286
287 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls));
288 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL;
289 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
290 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
291 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
292 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
293 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls;
294 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
295 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
296 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
297 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
298
299 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls));
300 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL;
301 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
302 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
303 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
304 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
305 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
306 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
307 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
308 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
309 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
310 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
311 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
312 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
313 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
314 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
315 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
316 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
317 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
318 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
319 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
320 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
321 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
322 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
323 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
324 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
325 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
326 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
327 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
328 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
329 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
330 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
331 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
332 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
333 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls;
334 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
335 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
336 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
337 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
338 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
339 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
340 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
341 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
342 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
343 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
344 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
345 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
346 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
347 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
348 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
349 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
350 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
351 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
352 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
353 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
354 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
355 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
356 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
357 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
358 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
359 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
360 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
361 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
362 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
363 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
364 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
365 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
366
367 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry));
368 val = pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL;
369 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
370 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
371 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
372 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
373 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
374 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
375 val = pVM->hwaccm.s.vmx.msr.vmx_entry;
376 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
377 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
378 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
379 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
380 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
381 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
382
383 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit));
384 val = pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL;
385 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
386 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
387 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
388 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
389 val = pVM->hwaccm.s.vmx.msr.vmx_exit;
390 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
391 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
392 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
393 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
394
395 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
396 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
397 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
398 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
399 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
400
401 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
402 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
403 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
404 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
405 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
406
407 /* Only try once. */
408 pVM->hwaccm.s.fInitialized = true;
409
410 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
411 AssertRC(rc);
412 if (rc == VINF_SUCCESS)
413 {
414 hwaccmr3DisableRawMode(pVM);
415
416 pVM->fHWACCMEnabled = true;
417 pVM->hwaccm.s.vmx.fEnabled = true;
418 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
419 LogRel(("HWACCM: VMX enabled!\n"));
420 }
421 else
422 {
423 LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
424 LogRel(("HWACCM: Last instruction error %x\n", pVM->hwaccm.s.vmx.ulLastInstrError));
425 pVM->fHWACCMEnabled = false;
426 }
427 }
428 }
429 else
430 if (pVM->hwaccm.s.svm.fSupported)
431 {
432 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
433
434 if (pVM->hwaccm.s.fInitialized == false)
435 {
436 /* Erratum 170 which requires a forced TLB flush for each world switch:
437 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
438 *
439 * All BH-G1/2 and DH-G1/2 models include a fix:
440 * Athlon X2: 0x6b 1/2
441 * 0x68 1/2
442 * Athlon 64: 0x7f 1
443 * 0x6f 2
444 * Sempron: 0x7f 1/2
445 * 0x6f 2
446 * 0x6c 2
447 * 0x7c 2
448 * Turion 64: 0x68 2
449 *
450 */
451 uint32_t u32Dummy;
452 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
453 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
454 u32BaseFamily= (u32Version >> 8) & 0xf;
455 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
456 u32Model = ((u32Version >> 4) & 0xf);
457 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
458 u32Stepping = u32Version & 0xf;
459 if ( u32Family == 0xf
460 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
461 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
462 {
463 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
464 }
465
466 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
467 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
468 LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
469 LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.svm.u32MaxASID));
470 LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
471
472 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
473 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
474 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
475 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
476 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
477 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
478 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
479 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
480 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
481 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
482
483 /* Only try once. */
484 pVM->hwaccm.s.fInitialized = true;
485
486 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
487 AssertRC(rc);
488 if (rc == VINF_SUCCESS)
489 {
490 hwaccmr3DisableRawMode(pVM);
491 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
492#if 0 /* not yet */
493 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
494#endif
495
496 pVM->fHWACCMEnabled = true;
497 pVM->hwaccm.s.svm.fEnabled = true;
498 }
499 else
500 {
501 pVM->fHWACCMEnabled = false;
502 }
503 }
504 }
505 return VINF_SUCCESS;
506}
507
508/**
509 * Applies relocations to data and code managed by this
510 * component. This function will be called at init and
511 * whenever the VMM need to relocate it self inside the GC.
512 *
513 * @param pVM The VM.
514 */
515HWACCMR3DECL(void) HWACCMR3Relocate(PVM pVM)
516{
517 Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
518 return;
519}
520
521
522/**
523 * Checks hardware accelerated raw mode is allowed.
524 *
525 * @returns boolean
526 * @param pVM The VM to operate on.
527 */
528HWACCMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
529{
530 return pVM->hwaccm.s.fAllowed;
531}
532
533
534/**
535 * Notification callback which is called whenever there is a chance that a CR3
536 * value might have changed.
537 * This is called by PGM.
538 *
539 * @param pVM The VM to operate on.
540 * @param enmShadowMode New paging mode.
541 */
542HWACCMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode)
543{
544 pVM->hwaccm.s.enmShadowMode = enmShadowMode;
545}
546
547/**
548 * Terminates the HWACCM.
549 *
550 * Termination means cleaning up and freeing all resources,
551 * the VM it self is at this point powered off or suspended.
552 *
553 * @returns VBox status code.
554 * @param pVM The VM to operate on.
555 */
556HWACCMR3DECL(int) HWACCMR3Term(PVM pVM)
557{
558 if (pVM->hwaccm.s.pStatExitReason)
559 {
560 MMHyperFree(pVM, pVM->hwaccm.s.pStatExitReason);
561 pVM->hwaccm.s.pStatExitReason = 0;
562 }
563 return 0;
564}
565
566
567/**
568 * The VM is being reset.
569 *
570 * For the HWACCM component this means that any GDT/LDT/TSS monitors
571 * needs to be removed.
572 *
573 * @param pVM VM handle.
574 */
575HWACCMR3DECL(void) HWACCMR3Reset(PVM pVM)
576{
577 LogFlow(("HWACCMR3Reset:\n"));
578
579 if (pVM->fHWACCMEnabled)
580 hwaccmr3DisableRawMode(pVM);
581
582 /* On first entry we'll sync everything. */
583 pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
584
585 pVM->hwaccm.s.vmx.cr0_mask = 0;
586 pVM->hwaccm.s.vmx.cr4_mask = 0;
587
588 pVM->hwaccm.s.Event.fPending = false;
589}
590
591/**
592 * Checks if we can currently use hardware accelerated raw mode.
593 *
594 * @returns boolean
595 * @param pVM The VM to operate on.
596 * @param pCtx Partial VM execution context
597 */
598HWACCMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
599{
600 Assert(pVM->fHWACCMEnabled);
601
602 /* AMD SVM supports real & protected mode with or without paging. */
603 if (pVM->hwaccm.s.svm.fEnabled)
604 {
605 pVM->hwaccm.s.fActive = true;
606 return true;
607 }
608
609 /* @todo we can support real-mode by using v86 and protected mode without paging with identity mapped pages.
610 * (but do we really care?)
611 */
612
613 pVM->hwaccm.s.fActive = false;
614
615 /** @note The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
616
617#ifndef HWACCM_VMX_EMULATE_ALL
618 /* Too early for VMX. */
619 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
620 return false;
621
622 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
623 if (pCtx->csHid.Attr.n.u1Present == 0)
624 return false;
625 if (pCtx->ssHid.Attr.n.u1Present == 0)
626 return false;
627#endif
628
629 if (pVM->hwaccm.s.vmx.fEnabled)
630 {
631 uint32_t mask;
632
633 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
634 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
635 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
636 mask &= ~X86_CR0_NE;
637#ifdef HWACCM_VMX_EMULATE_ALL
638 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
639 mask &= ~(X86_CR0_PG|X86_CR0_PE);
640#endif
641 if ((pCtx->cr0 & mask) != mask)
642 return false;
643
644 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
645 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
646 if ((pCtx->cr0 & mask) != 0)
647 return false;
648
649 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
650 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
651 mask &= ~X86_CR4_VMXE;
652 if ((pCtx->cr4 & mask) != mask)
653 return false;
654
655 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
656 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
657 if ((pCtx->cr4 & mask) != 0)
658 return false;
659
660 pVM->hwaccm.s.fActive = true;
661 return true;
662 }
663
664 return false;
665}
666
667/**
668 * Checks if we are currently using hardware accelerated raw mode.
669 *
670 * @returns boolean
671 * @param pVM The VM to operate on.
672 */
673HWACCMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
674{
675 return pVM->hwaccm.s.fActive;
676}
677
678/**
679 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
680 *
681 * @returns boolean
682 * @param pVM The VM to operate on.
683 */
684HWACCMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
685{
686 return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
687}
688
689/**
690 * Execute state save operation.
691 *
692 * @returns VBox status code.
693 * @param pVM VM Handle.
694 * @param pSSM SSM operation handle.
695 */
696static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
697{
698 int rc;
699
700 Log(("hwaccmR3Save:\n"));
701
702 /*
703 * Save the basic bits - fortunately all the other things can be resynced on load.
704 */
705 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
706 AssertRCReturn(rc, rc);
707 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
708 AssertRCReturn(rc, rc);
709 rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
710 AssertRCReturn(rc, rc);
711
712 return VINF_SUCCESS;
713}
714
715
716/**
717 * Execute state load operation.
718 *
719 * @returns VBox status code.
720 * @param pVM VM Handle.
721 * @param pSSM SSM operation handle.
722 * @param u32Version Data layout version.
723 */
724static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
725{
726 int rc;
727
728 Log(("hwaccmR3Load:\n"));
729
730 /*
731 * Validate version.
732 */
733 if (u32Version != HWACCM_SSM_VERSION)
734 {
735 Log(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
736 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
737 }
738 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
739 AssertRCReturn(rc, rc);
740 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
741 AssertRCReturn(rc, rc);
742 rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
743 AssertRCReturn(rc, rc);
744
745 return VINF_SUCCESS;
746}
747
748
749
750
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