HWACCM.cpp@ 9449

Last change on this file since 9449 was 9383, checked in by vboxsync, 17 years ago
VT-x/AMD-V updates for 64 bits guests
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1	/* $Id: HWACCM.cpp 9383 2008-06-04 12:22:45Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_HWACCM
26	#include <VBox/cpum.h>
27	#include <VBox/stam.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/trpm.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/hwacc_vmx.h>
34	#include <VBox/hwacc_svm.h>
35	#include "HWACCMInternal.h"
36	#include <VBox/vm.h>
37	#include <VBox/err.h>
38	#include <VBox/param.h>
39	#include <VBox/patm.h>
40	#include <VBox/csam.h>
41	#include <VBox/selm.h>
42
43	#include <iprt/assert.h>
44	#include <VBox/log.h>
45	#include <iprt/asm.h>
46	#include <iprt/string.h>
47	#include <iprt/thread.h>
48
49	/*******************************************************************************
50	* Internal Functions *
51	*******************************************************************************/
52	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
53	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
54
55
56	/**
57	* Initializes the HWACCM.
58	*
59	* @returns VBox status code.
60	* @param pVM The VM to operate on.
61	*/
62	HWACCMR3DECL(int) HWACCMR3Init(PVM pVM)
63	{
64	LogFlow(("HWACCMR3Init\n"));
65
66	/*
67	* Assert alignment and sizes.
68	*/
69	AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
70	AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
71
72	/* Some structure checks. */
73	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
74	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
75	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
76	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
77
78	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
79	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
80	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
81	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
82	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
83	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
84	AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
85
86
87	/*
88	* Register the saved state data unit.
89	*/
90	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
91	NULL, hwaccmR3Save, NULL,
92	NULL, hwaccmR3Load, NULL);
93	if (VBOX_FAILURE(rc))
94	return rc;
95
96	/* Misc initialisation. */
97	pVM->hwaccm.s.vmx.fSupported = false;
98	pVM->hwaccm.s.svm.fSupported = false;
99	pVM->hwaccm.s.vmx.fEnabled = false;
100	pVM->hwaccm.s.svm.fEnabled = false;
101
102	pVM->hwaccm.s.fActive = false;
103	pVM->hwaccm.s.fNestedPaging = false;
104
105	/* On first entry we'll sync everything. */
106	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
107
108	pVM->hwaccm.s.vmx.cr0_mask = 0;
109	pVM->hwaccm.s.vmx.cr4_mask = 0;
110
111	/*
112	* Statistics.
113	*/
114	STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
115	STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
116	STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
117
118	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
119	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
120	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
121	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
122	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
123	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
124	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
125	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
126	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
127	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
128	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
129	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
130	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
131	STAM_REG(pVM, &pVM->hwaccm.s.StatExitRdtsc, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Rdtsc", STAMUNIT_OCCURENCES, "Nr of occurances");
132	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
133	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
134	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
135	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
136	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
137	STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
138	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
139	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
140	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/WriteString", STAMUNIT_OCCURENCES, "Nr of occurances");
141	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringRead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/ReadString", STAMUNIT_OCCURENCES, "Nr of occurances");
142	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
143	STAM_REG(pVM, &pVM->hwaccm.s.StatExitMaxResume, STAMTYPE_COUNTER, "/HWACCM/Exit/Safety/MaxResume", STAMUNIT_OCCURENCES, "Nr of occurances");
144
145	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
146	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
147
148	STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
149	STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
150	STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
151
152	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageManual, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Virt/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
153	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPhysPageManual, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Phys/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
154	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBManual, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
155	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBCRxChange, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/CRx", STAMUNIT_OCCURENCES, "Nr of occurances");
156	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageInvlpg, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
157	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Switch", STAMUNIT_OCCURENCES, "Nr of occurances");
158	STAM_REG(pVM, &pVM->hwaccm.s.StatNoFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Skipped", STAMUNIT_OCCURENCES, "Nr of occurances");
159	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushASID, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/ASID", STAMUNIT_OCCURENCES, "Nr of occurances");
160
161	STAM_REG(pVM, &pVM->hwaccm.s.StatTSCOffset, STAMTYPE_COUNTER, "/HWACCM/TSC/Offset", STAMUNIT_OCCURENCES, "Nr of occurances");
162	STAM_REG(pVM, &pVM->hwaccm.s.StatTSCIntercept, STAMTYPE_COUNTER, "/HWACCM/TSC/Intercept", STAMUNIT_OCCURENCES, "Nr of occurances");
163
164	pVM->hwaccm.s.pStatExitReason = 0;
165
166	#ifdef VBOX_WITH_STATISTICS
167	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVM->hwaccm.s.pStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.pStatExitReason);
168	AssertRC(rc);
169	if (VBOX_SUCCESS(rc))
170	{
171	for (int i=0;i<MAX_EXITREASON_STAT;i++)
172	{
173	char szName[64];
174	RTStrPrintf(szName, sizeof(szName), "/HWACCM/Exit/Reason/%02x", i);
175	int rc = STAMR3Register(pVM, &pVM->hwaccm.s.pStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "Exit reason");
176	AssertRC(rc);
177	}
178	int rc = STAMR3Register(pVM, &pVM->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, "/HWACCM/Exit/Reason/#NPF", STAMUNIT_OCCURENCES, "Exit reason");
179	AssertRC(rc);
180	}
181	pVM->hwaccm.s.pStatExitReasonR0 = MMHyperR3ToR0(pVM, pVM->hwaccm.s.pStatExitReason);
182	Assert(pVM->hwaccm.s.pStatExitReasonR0);
183	#endif
184
185	/* Disabled by default. */
186	pVM->fHWACCMEnabled = false;
187
188	/* HWACCM support must be explicitely enabled in the configuration file. */
189	pVM->hwaccm.s.fAllowed = false;
190	CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed);
191
192	return VINF_SUCCESS;
193	}
194
195
196	/**
197	* Turns off normal raw mode features
198	*
199	* @param pVM The VM to operate on.
200	*/
201	static void hwaccmr3DisableRawMode(PVM pVM)
202	{
203	/* Disable PATM & CSAM. */
204	PATMR3AllowPatching(pVM, false);
205	CSAMDisableScanning(pVM);
206
207	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
208	SELMR3DisableMonitoring(pVM);
209	TRPMR3DisableMonitoring(pVM);
210
211	/* The hidden selector registers are now valid. */
212	CPUMSetHiddenSelRegsValid(pVM, true);
213
214	/* Disable the switcher code (safety precaution). */
215	VMMR3DisableSwitcher(pVM);
216
217	/* Disable mapping of the hypervisor into the shadow page table. */
218	PGMR3ChangeShwPDMappings(pVM, false);
219
220	/* Disable the switcher */
221	VMMR3DisableSwitcher(pVM);
222
223	if (pVM->hwaccm.s.fNestedPaging)
224	{
225	/* Reinit the paging mode to force the new shadow mode. */
226	PGMR3ChangeMode(pVM, PGMMODE_REAL);
227	}
228	}
229
230	/**
231	* Initialize VT-x or AMD-V.
232	*
233	* @returns VBox status code.
234	* @param pVM The VM handle.
235	*/
236	HWACCMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
237	{
238	int rc;
239
240	if ( !pVM->hwaccm.s.vmx.fSupported
241	&& !pVM->hwaccm.s.svm.fSupported)
242	{
243	LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Vrc\n", pVM->hwaccm.s.lLastError));
244	LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
245	return VINF_SUCCESS;
246	}
247
248	/*
249	* Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
250	* because it turns off paging, which is not allowed in VMX root mode.
251	*
252	* To simplify matters we'll just force all running VMs to either use raw or hwaccm mode. No mixing allowed.
253	*
254	*/
255	/* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
256	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
257	if (VBOX_FAILURE(rc))
258	{
259	LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Vrc\n", rc));
260	LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
261	/* Invert the selection */
262	pVM->hwaccm.s.fAllowed ^= 1;
263	LogRel(("HWACCMR3InitFinalize: new HWACCM status = %s\n", pVM->hwaccm.s.fAllowed ? "enabled" : "disabled"));
264
265	if (pVM->hwaccm.s.fAllowed)
266	{
267	if (pVM->hwaccm.s.vmx.fSupported)
268	VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses Intel VT-x hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using VT-x as well.\n");
269	else
270	VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses AMD-V hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using AMD-V as well.\n");
271	}
272	else
273	VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses software virtualization. It is not allowed to simultaneously use VT-x or AMD-V, therefore this VM will be run using software virtualization as well.\n");
274	}
275
276	if (pVM->hwaccm.s.fAllowed == false)
277	return VINF_SUCCESS; /* disabled */
278
279	Assert(!pVM->fHWACCMEnabled);
280
281	if (pVM->hwaccm.s.vmx.fSupported)
282	{
283	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
284
285	if ( pVM->hwaccm.s.fInitialized == false
286	&& pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
287	{
288	uint64_t val;
289
290	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
291	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
292	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
293	LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
294	LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
295	LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
296	LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
297	LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
298
299	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls));
300	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL;
301	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
302	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
303	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
304	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
305	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls;
306	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
307	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT must be set\n"));
308	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
309	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT must be set\n"));
310
311	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls));
312	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL;
313	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
314	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
315	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
316	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
317	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
318	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
319	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
320	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
321	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
322	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
323	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
324	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
325	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
326	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
327	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
328	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
329	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
330	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
331	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
332	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
333	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
334	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
335	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
336	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
337	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
338	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
339	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
340	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
341	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
342	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
343	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
344	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
345	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls;
346	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
347	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT must be set\n"));
348	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
349	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET must be set\n"));
350	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
351	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT must be set\n"));
352	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
353	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT must be set\n"));
354	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
355	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT must be set\n"));
356	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
357	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT must be set\n"));
358	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
359	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT must be set\n"));
360	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
361	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT must be set\n"));
362	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
363	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT must be set\n"));
364	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
365	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW must be set\n"));
366	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
367	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT must be set\n"));
368	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
369	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT must be set\n"));
370	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
371	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS must be set\n"));
372	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
373	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS must be set\n"));
374	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
375	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT must be set\n"));
376	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
377	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT must be set\n"));
378
379	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry));
380	val = pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL;
381	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
382	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
383	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
384	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
385	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
386	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
387	val = pVM->hwaccm.s.vmx.msr.vmx_entry;
388	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
389	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE must be set\n"));
390	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
391	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM must be set\n"));
392	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
393	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON must be set\n"));
394
395	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit));
396	val = pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL;
397	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
398	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
399	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
400	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
401	val = pVM->hwaccm.s.vmx.msr.vmx_exit;
402	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
403	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 must be set\n"));
404	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
405	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ must be set\n"));
406
407	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
408	LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
409	LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
410	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
411	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
412
413	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
414	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
415	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
416	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
417	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
418
419	/* Only try once. */
420	pVM->hwaccm.s.fInitialized = true;
421
422	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
423	AssertRC(rc);
424	if (rc == VINF_SUCCESS)
425	{
426	pVM->fHWACCMEnabled = true;
427	pVM->hwaccm.s.vmx.fEnabled = true;
428	hwaccmr3DisableRawMode(pVM);
429
430	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
431	#ifdef VBOX_ENABLE_64_BITS_GUESTS
432	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
433	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
434	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
435	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
436	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
437	#endif
438	LogRel(("HWACCM: VMX enabled!\n"));
439	}
440	else
441	{
442	LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
443	LogRel(("HWACCM: Last instruction error %x\n", pVM->hwaccm.s.vmx.ulLastInstrError));
444	pVM->fHWACCMEnabled = false;
445	}
446	}
447	}
448	else
449	if (pVM->hwaccm.s.svm.fSupported)
450	{
451	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
452
453	if (pVM->hwaccm.s.fInitialized == false)
454	{
455	/* Erratum 170 which requires a forced TLB flush for each world switch:
456	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
457	*
458	* All BH-G1/2 and DH-G1/2 models include a fix:
459	* Athlon X2: 0x6b 1/2
460	* 0x68 1/2
461	* Athlon 64: 0x7f 1
462	* 0x6f 2
463	* Sempron: 0x7f 1/2
464	* 0x6f 2
465	* 0x6c 2
466	* 0x7c 2
467	* Turion 64: 0x68 2
468	*
469	*/
470	uint32_t u32Dummy;
471	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
472	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
473	u32BaseFamily= (u32Version >> 8) & 0xf;
474	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
475	u32Model = ((u32Version >> 4) & 0xf);
476	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
477	u32Stepping = u32Version & 0xf;
478	if ( u32Family == 0xf
479	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
480	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
481	{
482	LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
483	}
484
485	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
486	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
487	LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
488	LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.svm.u32MaxASID));
489	LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
490
491	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
492	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
493	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
494	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
495	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
496	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
497	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
498	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
499	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
500	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
501
502	/* Only try once. */
503	pVM->hwaccm.s.fInitialized = true;
504
505	#ifdef VBOX_WITH_NESTED_PAGING
506	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
507	pVM->hwaccm.s.fNestedPaging = true;
508	#endif
509
510	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
511	AssertRC(rc);
512	if (rc == VINF_SUCCESS)
513	{
514	pVM->fHWACCMEnabled = true;
515	pVM->hwaccm.s.svm.fEnabled = true;
516
517	hwaccmr3DisableRawMode(pVM);
518	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
519	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
520	#ifdef VBOX_ENABLE_64_BITS_GUESTS
521	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
522	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
523	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
524	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
525	#endif
526	}
527	else
528	{
529	pVM->fHWACCMEnabled = false;
530	}
531	}
532	}
533	return VINF_SUCCESS;
534	}
535
536	/**
537	* Applies relocations to data and code managed by this
538	* component. This function will be called at init and
539	* whenever the VMM need to relocate it self inside the GC.
540	*
541	* @param pVM The VM.
542	*/
543	HWACCMR3DECL(void) HWACCMR3Relocate(PVM pVM)
544	{
545	Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
546	return;
547	}
548
549
550	/**
551	* Checks hardware accelerated raw mode is allowed.
552	*
553	* @returns boolean
554	* @param pVM The VM to operate on.
555	*/
556	HWACCMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
557	{
558	return pVM->hwaccm.s.fAllowed;
559	}
560
561
562	/**
563	* Notification callback which is called whenever there is a chance that a CR3
564	* value might have changed.
565	* This is called by PGM.
566	*
567	* @param pVM The VM to operate on.
568	* @param enmShadowMode New paging mode.
569	*/
570	HWACCMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode)
571	{
572	pVM->hwaccm.s.enmShadowMode = enmShadowMode;
573	}
574
575	/**
576	* Terminates the HWACCM.
577	*
578	* Termination means cleaning up and freeing all resources,
579	* the VM it self is at this point powered off or suspended.
580	*
581	* @returns VBox status code.
582	* @param pVM The VM to operate on.
583	*/
584	HWACCMR3DECL(int) HWACCMR3Term(PVM pVM)
585	{
586	if (pVM->hwaccm.s.pStatExitReason)
587	{
588	MMHyperFree(pVM, pVM->hwaccm.s.pStatExitReason);
589	pVM->hwaccm.s.pStatExitReason = 0;
590	}
591	return 0;
592	}
593
594
595	/**
596	* The VM is being reset.
597	*
598	* For the HWACCM component this means that any GDT/LDT/TSS monitors
599	* needs to be removed.
600	*
601	* @param pVM VM handle.
602	*/
603	HWACCMR3DECL(void) HWACCMR3Reset(PVM pVM)
604	{
605	LogFlow(("HWACCMR3Reset:\n"));
606
607	if (pVM->fHWACCMEnabled)
608	hwaccmr3DisableRawMode(pVM);
609
610	/* On first entry we'll sync everything. */
611	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
612
613	pVM->hwaccm.s.vmx.cr0_mask = 0;
614	pVM->hwaccm.s.vmx.cr4_mask = 0;
615
616	pVM->hwaccm.s.Event.fPending = false;
617	}
618
619	/**
620	* Checks if we can currently use hardware accelerated raw mode.
621	*
622	* @returns boolean
623	* @param pVM The VM to operate on.
624	* @param pCtx Partial VM execution context
625	*/
626	HWACCMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
627	{
628	Assert(pVM->fHWACCMEnabled);
629
630	/* AMD SVM supports real & protected mode with or without paging. */
631	if (pVM->hwaccm.s.svm.fEnabled)
632	{
633	pVM->hwaccm.s.fActive = true;
634	return true;
635	}
636
637	/* @todo we can support real-mode by using v86 and protected mode without paging with identity mapped pages.
638	* (but do we really care?)
639	*/
640
641	pVM->hwaccm.s.fActive = false;
642
643	/** @note The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
644
645	#ifndef HWACCM_VMX_EMULATE_ALL
646	/* Too early for VMX. */
647	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
648	return false;
649
650	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
651	if (pCtx->csHid.Attr.n.u1Present == 0)
652	return false;
653	if (pCtx->ssHid.Attr.n.u1Present == 0)
654	return false;
655	#endif
656
657	if (pVM->hwaccm.s.vmx.fEnabled)
658	{
659	uint32_t mask;
660
661	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
662	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
663	/* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
664	mask &= ~X86_CR0_NE;
665	#ifdef HWACCM_VMX_EMULATE_ALL
666	/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
667	mask &= ~(X86_CR0_PG\|X86_CR0_PE);
668	#endif
669	if ((pCtx->cr0 & mask) != mask)
670	return false;
671
672	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
673	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
674	if ((pCtx->cr0 & mask) != 0)
675	return false;
676
677	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
678	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
679	mask &= ~X86_CR4_VMXE;
680	if ((pCtx->cr4 & mask) != mask)
681	return false;
682
683	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
684	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
685	if ((pCtx->cr4 & mask) != 0)
686	return false;
687
688	pVM->hwaccm.s.fActive = true;
689	return true;
690	}
691
692	return false;
693	}
694
695	/**
696	* Checks if we are currently using hardware accelerated raw mode.
697	*
698	* @returns boolean
699	* @param pVM The VM to operate on.
700	*/
701	HWACCMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
702	{
703	return pVM->hwaccm.s.fActive;
704	}
705
706	/**
707	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
708	*
709	* @returns boolean
710	* @param pVM The VM to operate on.
711	*/
712	HWACCMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
713	{
714	return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
715	}
716
717	/**
718	* Execute state save operation.
719	*
720	* @returns VBox status code.
721	* @param pVM VM Handle.
722	* @param pSSM SSM operation handle.
723	*/
724	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
725	{
726	int rc;
727
728	Log(("hwaccmR3Save:\n"));
729
730	/*
731	* Save the basic bits - fortunately all the other things can be resynced on load.
732	*/
733	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
734	AssertRCReturn(rc, rc);
735	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
736	AssertRCReturn(rc, rc);
737	rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
738	AssertRCReturn(rc, rc);
739
740	return VINF_SUCCESS;
741	}
742
743
744	/**
745	* Execute state load operation.
746	*
747	* @returns VBox status code.
748	* @param pVM VM Handle.
749	* @param pSSM SSM operation handle.
750	* @param u32Version Data layout version.
751	*/
752	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
753	{
754	int rc;
755
756	Log(("hwaccmR3Load:\n"));
757
758	/*
759	* Validate version.
760	*/
761	if (u32Version != HWACCM_SSM_VERSION)
762	{
763	Log(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
764	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
765	}
766	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
767	AssertRCReturn(rc, rc);
768	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
769	AssertRCReturn(rc, rc);
770	rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
771	AssertRCReturn(rc, rc);
772
773	return VINF_SUCCESS;
774	}
775
776
777
778

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source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 9449

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