VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 10502

Last change on this file since 10502 was 10502, checked in by vboxsync, 16 years ago

Take precautions for being rescheduled to a different cpu due to long jumps to ring 3. (affects AMD-V only)
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1/* $Id: HWACCMInternal.h 10502 2008-07-11 09:31:15Z vboxsync $ */
2/** @file
3 * HWACCM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___HWACCMInternal_h
23#define ___HWACCMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/em.h>
28#include <VBox/stam.h>
29#include <VBox/dis.h>
30#include <VBox/hwaccm.h>
31#include <VBox/pgm.h>
32#include <iprt/memobj.h>
33#include <iprt/cpuset.h>
34#include <iprt/mp.h>
35
36/* Uncomment to enable experimental nested paging. */
37/////#define VBOX_WITH_NESTED_PAGING
38#if HC_ARCH_BITS == 64
39/* Enable 64 bits guest support. */
40# define VBOX_ENABLE_64_BITS_GUESTS
41#endif
42
43__BEGIN_DECLS
44
45
46/** @defgroup grp_hwaccm_int Internal
47 * @ingroup grp_hwaccm
48 * @internal
49 * @{
50 */
51
52
53/**
54 * Converts a HWACCM pointer into a VM pointer.
55 * @returns Pointer to the VM structure the EM is part of.
56 * @param pHWACCM Pointer to HWACCM instance data.
57 */
58#define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
59
60/** Maximum number of exit reason statistics counters. */
61#define MAX_EXITREASON_STAT 0x100
62#define MASK_EXITREASON_STAT 0xff
63
64/** @name Changed flags
65 * These flags are used to keep track of which important registers that
66 * have been changed since last they were reset.
67 * @{
68 */
69#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
70#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
71#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
72#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
73#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
74#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
75#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
76#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
77#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
78#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
79#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
80#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
81
82#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
83 | HWACCM_CHANGED_GUEST_CR0 \
84 | HWACCM_CHANGED_GUEST_CR3 \
85 | HWACCM_CHANGED_GUEST_CR4 \
86 | HWACCM_CHANGED_GUEST_GDTR \
87 | HWACCM_CHANGED_GUEST_IDTR \
88 | HWACCM_CHANGED_GUEST_LDTR \
89 | HWACCM_CHANGED_GUEST_TR \
90 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
91 | HWACCM_CHANGED_GUEST_FPU \
92 | HWACCM_CHANGED_GUEST_DEBUG \
93 | HWACCM_CHANGED_HOST_CONTEXT)
94
95#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
96 | HWACCM_CHANGED_GUEST_CR0 \
97 | HWACCM_CHANGED_GUEST_CR3 \
98 | HWACCM_CHANGED_GUEST_CR4 \
99 | HWACCM_CHANGED_GUEST_GDTR \
100 | HWACCM_CHANGED_GUEST_IDTR \
101 | HWACCM_CHANGED_GUEST_LDTR \
102 | HWACCM_CHANGED_GUEST_TR \
103 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
104 | HWACCM_CHANGED_GUEST_DEBUG \
105 | HWACCM_CHANGED_GUEST_FPU)
106
107/** @} */
108
109/** @name Intercepted traps
110 * Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
111 * Currently #NM and #PF only
112 */
113#ifdef VBOX_STRICT
114#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF)
115#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
116#else
117#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
118#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
119#endif
120/** @} */
121
122
123/** Maxium resume loops allowed in ring 0 (safety precaution) */
124#define HWACCM_MAX_RESUME_LOOPS 1024
125
126/** HWACCM SSM version
127 */
128#define HWACCM_SSM_VERSION 3
129
130/* Per-cpu information. */
131typedef struct
132{
133 RTCPUID idCpu;
134
135 RTR0MEMOBJ pMemObj;
136 /* Current ASID (AMD-V only) */
137 uint32_t uCurrentASID;
138 /* TLB flush count */
139 uint32_t cTLBFlushes;
140
141 /* Set the first time a cpu is used to make sure we start with a clean TLB. */
142 bool fFlushTLB;
143
144 bool fConfigured;
145} HWACCM_CPUINFO;
146typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
147
148/* VT-x capability qword. */
149typedef union
150{
151 struct
152 {
153 uint32_t disallowed0;
154 uint32_t allowed1;
155 } n;
156 uint64_t u;
157} VMX_CAPABILITY;
158
159/**
160 * HWACCM VM Instance data.
161 * Changes to this must checked against the padding of the cfgm union in VM!
162 */
163typedef struct HWACCM
164{
165 /** Offset to the VM structure.
166 * See HWACCM2VM(). */
167 RTUINT offVM;
168
169 /** Set when we've initialized VMX or SVM. */
170 bool fInitialized;
171 /** Set when we're using VMX/SVN at that moment. */
172 bool fActive;
173
174 /** Set when hardware acceleration is allowed. */
175 bool fAllowed;
176
177 /** Set if nested paging is enabled. */
178 bool fNestedPaging;
179
180 /** HWACCM_CHANGED_* flags. */
181 uint32_t fContextUseFlags;
182
183 /** Old style FPU reporting trap mask override performed (optimization) */
184 uint32_t fFPUOldStyleOverride;
185
186 /** And mask for copying register contents. */
187 uint64_t u64RegisterMask;
188 struct
189 {
190 /** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
191 bool fSupported;
192
193 /** Set when we've enabled VMX. */
194 bool fEnabled;
195
196 /** Set if we can use VMXResume to execute guest code. */
197 bool fResumeVM;
198
199 /** R0 memory object for the VM control structure (VMCS). */
200 RTR0MEMOBJ pMemObjVMCS;
201 /** Physical address of the VM control structure (VMCS). */
202 RTHCPHYS pVMCSPhys;
203 /** Virtual address of the VM control structure (VMCS). */
204 R0PTRTYPE(void *) pVMCS;
205
206 /** R0 memory object for the TSS page used for real mode emulation. */
207 RTR0MEMOBJ pMemObjRealModeTSS;
208 /** Physical address of the TSS page used for real mode emulation. */
209 RTHCPHYS pRealModeTSSPhys;
210 /** Virtual address of the TSS page used for real mode emulation. */
211 R0PTRTYPE(PVBOXTSS) pRealModeTSS;
212
213 /** R0 memory object for the virtual APIC mmio cache. */
214 RTR0MEMOBJ pMemObjAPIC;
215 /** Physical address of the virtual APIC mmio cache. */
216 RTHCPHYS pAPICPhys;
217 /** Virtual address of the virtual APIC mmio cache. */
218 R0PTRTYPE(uint8_t *) pAPIC;
219
220 /** Ring 0 handlers for VT-x. */
221 DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx));
222
223 /** Host CR4 value (set by ring-0 VMX init) */
224 uint64_t hostCR4;
225
226 /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
227 uint64_t proc_ctls;
228
229 /** Current CR0 mask. */
230 uint64_t cr0_mask;
231 /** Current CR4 mask. */
232 uint64_t cr4_mask;
233
234 /** VMX MSR values */
235 struct
236 {
237 uint64_t feature_ctrl;
238 uint64_t vmx_basic_info;
239 VMX_CAPABILITY vmx_pin_ctls;
240 VMX_CAPABILITY vmx_proc_ctls;
241 VMX_CAPABILITY vmx_exit;
242 VMX_CAPABILITY vmx_entry;
243 uint64_t vmx_misc;
244 uint64_t vmx_cr0_fixed0;
245 uint64_t vmx_cr0_fixed1;
246 uint64_t vmx_cr4_fixed0;
247 uint64_t vmx_cr4_fixed1;
248 uint64_t vmx_vmcs_enum;
249 } msr;
250
251 /* Last instruction error */
252 uint32_t ulLastInstrError;
253 } vmx;
254
255 struct
256 {
257 /** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
258 bool fSupported;
259 /** Set when we've enabled SVM. */
260 bool fEnabled;
261 /** Set if we don't have to flush the TLB on VM entry. */
262 bool fResumeVM;
263 /** Set if erratum 170 affects the AMD cpu. */
264 bool fAlwaysFlushTLB;
265 /** Set if we need to flush the TLB during the world switch. */
266 bool fForceTLBFlush;
267
268 /* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
269 RTCPUID idLastCpu;
270
271 /* TLB flush count */
272 uint32_t cTLBFlushes;
273
274 /** R0 memory object for the VM control block (VMCB). */
275 RTR0MEMOBJ pMemObjVMCB;
276 /** Physical address of the VM control block (VMCB). */
277 RTHCPHYS pVMCBPhys;
278 /** Virtual address of the VM control block (VMCB). */
279 R0PTRTYPE(void *) pVMCB;
280
281 /** R0 memory object for the host VM control block (VMCB). */
282 RTR0MEMOBJ pMemObjVMCBHost;
283 /** Physical address of the host VM control block (VMCB). */
284 RTHCPHYS pVMCBHostPhys;
285 /** Virtual address of the host VM control block (VMCB). */
286 R0PTRTYPE(void *) pVMCBHost;
287
288 /** R0 memory object for the IO bitmap (12kb). */
289 RTR0MEMOBJ pMemObjIOBitmap;
290 /** Physical address of the IO bitmap (12kb). */
291 RTHCPHYS pIOBitmapPhys;
292 /** Virtual address of the IO bitmap. */
293 R0PTRTYPE(void *) pIOBitmap;
294
295 /** R0 memory object for the MSR bitmap (8kb). */
296 RTR0MEMOBJ pMemObjMSRBitmap;
297 /** Physical address of the MSR bitmap (8kb). */
298 RTHCPHYS pMSRBitmapPhys;
299 /** Virtual address of the MSR bitmap. */
300 R0PTRTYPE(void *) pMSRBitmap;
301
302 /** Ring 0 handlers for VT-x. */
303 DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx));
304
305 /** SVM revision. */
306 uint32_t u32Rev;
307
308 /** Maximum ASID allowed. */
309 uint32_t u32MaxASID;
310
311 /** SVM feature bits from cpuid 0x8000000a */
312 uint32_t u32Features;
313 } svm;
314
315 struct
316 {
317 uint32_t u32AMDFeatureECX;
318 uint32_t u32AMDFeatureEDX;
319 } cpuid;
320
321 /* Event injection state. */
322 struct
323 {
324 uint32_t fPending;
325 uint32_t errCode;
326 uint64_t intInfo;
327 } Event;
328
329 /** Saved error from detection */
330 int32_t lLastError;
331
332 /** HWACCMR0Init was run */
333 bool fHWACCMR0Init;
334
335 /** Currenty shadow paging mode. */
336 PGMMODE enmShadowMode;
337
338 STAMPROFILEADV StatEntry;
339 STAMPROFILEADV StatExit;
340 STAMPROFILEADV StatInGC;
341
342 STAMCOUNTER StatIntInject;
343
344 STAMCOUNTER StatExitShadowNM;
345 STAMCOUNTER StatExitGuestNM;
346 STAMCOUNTER StatExitShadowPF;
347 STAMCOUNTER StatExitGuestPF;
348 STAMCOUNTER StatExitGuestUD;
349 STAMCOUNTER StatExitGuestSS;
350 STAMCOUNTER StatExitGuestNP;
351 STAMCOUNTER StatExitGuestGP;
352 STAMCOUNTER StatExitGuestDE;
353 STAMCOUNTER StatExitGuestMF;
354 STAMCOUNTER StatExitInvpg;
355 STAMCOUNTER StatExitInvd;
356 STAMCOUNTER StatExitCpuid;
357 STAMCOUNTER StatExitRdtsc;
358 STAMCOUNTER StatExitCRxWrite;
359 STAMCOUNTER StatExitCRxRead;
360 STAMCOUNTER StatExitDRxWrite;
361 STAMCOUNTER StatExitDRxRead;
362 STAMCOUNTER StatExitCLTS;
363 STAMCOUNTER StatExitLMSW;
364 STAMCOUNTER StatExitIOWrite;
365 STAMCOUNTER StatExitIORead;
366 STAMCOUNTER StatExitIOStringWrite;
367 STAMCOUNTER StatExitIOStringRead;
368 STAMCOUNTER StatExitIrqWindow;
369 STAMCOUNTER StatExitMaxResume;
370 STAMCOUNTER StatIntReinject;
371 STAMCOUNTER StatPendingHostIrq;
372
373 STAMCOUNTER StatFlushPageManual;
374 STAMCOUNTER StatFlushPhysPageManual;
375 STAMCOUNTER StatFlushTLBManual;
376 STAMCOUNTER StatFlushPageInvlpg;
377 STAMCOUNTER StatFlushTLBWorldSwitch;
378 STAMCOUNTER StatNoFlushTLBWorldSwitch;
379 STAMCOUNTER StatFlushTLBCRxChange;
380 STAMCOUNTER StatFlushASID;
381
382 STAMCOUNTER StatSwitchGuestIrq;
383 STAMCOUNTER StatSwitchToR3;
384
385 STAMCOUNTER StatTSCOffset;
386 STAMCOUNTER StatTSCIntercept;
387
388 STAMCOUNTER StatExitReasonNPF;
389 R3PTRTYPE(PSTAMCOUNTER) pStatExitReason;
390 R0PTRTYPE(PSTAMCOUNTER) pStatExitReasonR0;
391} HWACCM;
392/** Pointer to HWACCM VM instance data. */
393typedef HWACCM *PHWACCM;
394
395#ifdef IN_RING0
396
397#ifdef VBOX_STRICT
398/**
399 * Returns the cpu structure for the current cpu.
400 * Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
401 *
402 * @returns cpu structure pointer
403 * @param pVM The VM to operate on.
404 */
405HWACCMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
406
407HWACCMR0DECL(void) HWACCMDumpRegs(PCPUMCTX pCtx);
408HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
409#else
410#define HWACCMDumpRegs(a) do { } while (0)
411#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
412#endif
413
414/* Dummy callback handlers. */
415HWACCMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu);
416HWACCMR0DECL(int) HWACCMR0DummyLeave(PVM pVM);
417HWACCMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
418HWACCMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
419HWACCMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
420HWACCMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
421HWACCMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
422HWACCMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx);
423HWACCMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM);
424HWACCMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx);
425
426#endif
427
428/** @} */
429
430__END_DECLS
431
432#endif
433
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