HWACCMInternal.h@ 12624

Last change on this file since 12624 was 12610, checked in by vboxsync, 17 years ago
Extra statistics for IO debug breakpoint checking.
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1	/* $Id: HWACCMInternal.h 12610 2008-09-19 16:42:31Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <iprt/memobj.h>
33	#include <iprt/cpuset.h>
34	#include <iprt/mp.h>
35
36	#if HC_ARCH_BITS == 64
37	/* Enable 64 bits guest support. */
38	# define VBOX_ENABLE_64_BITS_GUESTS
39	#endif
40
41	__BEGIN_DECLS
42
43
44	/** @defgroup grp_hwaccm_int Internal
45	* @ingroup grp_hwaccm
46	* @internal
47	* @{
48	*/
49
50
51	/**
52	* Converts a HWACCM pointer into a VM pointer.
53	* @returns Pointer to the VM structure the EM is part of.
54	* @param pHWACCM Pointer to HWACCM instance data.
55	*/
56	#define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
57
58	/** Maximum number of exit reason statistics counters. */
59	#define MAX_EXITREASON_STAT 0x100
60	#define MASK_EXITREASON_STAT 0xff
61
62	/** @name Changed flags
63	* These flags are used to keep track of which important registers that
64	* have been changed since last they were reset.
65	* @{
66	*/
67	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
68	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
69	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
70	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
71	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
72	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
73	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
74	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
75	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
76	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
77	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
78	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
79
80	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
81	\| HWACCM_CHANGED_GUEST_CR0 \
82	\| HWACCM_CHANGED_GUEST_CR3 \
83	\| HWACCM_CHANGED_GUEST_CR4 \
84	\| HWACCM_CHANGED_GUEST_GDTR \
85	\| HWACCM_CHANGED_GUEST_IDTR \
86	\| HWACCM_CHANGED_GUEST_LDTR \
87	\| HWACCM_CHANGED_GUEST_TR \
88	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
89	\| HWACCM_CHANGED_GUEST_FPU \
90	\| HWACCM_CHANGED_GUEST_DEBUG \
91	\| HWACCM_CHANGED_HOST_CONTEXT)
92
93	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
94	\| HWACCM_CHANGED_GUEST_CR0 \
95	\| HWACCM_CHANGED_GUEST_CR3 \
96	\| HWACCM_CHANGED_GUEST_CR4 \
97	\| HWACCM_CHANGED_GUEST_GDTR \
98	\| HWACCM_CHANGED_GUEST_IDTR \
99	\| HWACCM_CHANGED_GUEST_LDTR \
100	\| HWACCM_CHANGED_GUEST_TR \
101	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
102	\| HWACCM_CHANGED_GUEST_DEBUG \
103	\| HWACCM_CHANGED_GUEST_FPU)
104
105	/** @} */
106
107	/** @name Intercepted traps
108	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
109	* Currently #NM and #PF only
110	*/
111	#ifdef VBOX_STRICT
112	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
113	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
114	#else
115	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
116	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
117	#endif
118	/** @} */
119
120
121	/** Maxium resume loops allowed in ring 0 (safety precaution) */
122	#define HWACCM_MAX_RESUME_LOOPS 1024
123
124	/** HWACCM SSM version
125	*/
126	#define HWACCM_SSM_VERSION 3
127
128	/* Per-cpu information. */
129	typedef struct
130	{
131	RTCPUID idCpu;
132
133	RTR0MEMOBJ pMemObj;
134	/* Current ASID (AMD-V only) */
135	uint32_t uCurrentASID;
136	/* TLB flush count */
137	uint32_t cTLBFlushes;
138
139	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
140	bool fFlushTLB;
141
142	bool fConfigured;
143	} HWACCM_CPUINFO;
144	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
145
146	/* VT-x capability qword. */
147	typedef union
148	{
149	struct
150	{
151	uint32_t disallowed0;
152	uint32_t allowed1;
153	} n;
154	uint64_t u;
155	} VMX_CAPABILITY;
156
157	/**
158	* HWACCM VM Instance data.
159	* Changes to this must checked against the padding of the cfgm union in VM!
160	*/
161	typedef struct HWACCM
162	{
163	/** Offset to the VM structure.
164	* See HWACCM2VM(). */
165	RTUINT offVM;
166
167	/** Set when we've initialized VMX or SVM. */
168	bool fInitialized;
169	/** Set when we're using VMX/SVN at that moment. */
170	bool fActive;
171
172	/** Set when hardware acceleration is allowed. */
173	bool fAllowed;
174
175	/** Set if nested paging is enabled. */
176	bool fNestedPaging;
177
178	/** Set if nested paging is allowed. */
179	bool fAllowNestedPaging;
180
181	/** HWACCM_CHANGED_* flags. */
182	uint32_t fContextUseFlags;
183
184	/** Old style FPU reporting trap mask override performed (optimization) */
185	uint32_t fFPUOldStyleOverride;
186
187	/** And mask for copying register contents. */
188	uint64_t u64RegisterMask;
189	struct
190	{
191	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
192	bool fSupported;
193
194	/** Set when we've enabled VMX. */
195	bool fEnabled;
196
197	/** Set if we can use VMXResume to execute guest code. */
198	bool fResumeVM;
199
200	/** R0 memory object for the VM control structure (VMCS). */
201	RTR0MEMOBJ pMemObjVMCS;
202	/** Physical address of the VM control structure (VMCS). */
203	RTHCPHYS pVMCSPhys;
204	/** Virtual address of the VM control structure (VMCS). */
205	R0PTRTYPE(void *) pVMCS;
206
207	/** R0 memory object for the TSS page used for real mode emulation. */
208	RTR0MEMOBJ pMemObjRealModeTSS;
209	/** Physical address of the TSS page used for real mode emulation. */
210	RTHCPHYS pRealModeTSSPhys;
211	/** Virtual address of the TSS page used for real mode emulation. */
212	R0PTRTYPE(PVBOXTSS) pRealModeTSS;
213
214	/** R0 memory object for the virtual APIC mmio cache. */
215	RTR0MEMOBJ pMemObjAPIC;
216	/** Physical address of the virtual APIC mmio cache. */
217	RTHCPHYS pAPICPhys;
218	/** Virtual address of the virtual APIC mmio cache. */
219	R0PTRTYPE(uint8_t *) pAPIC;
220
221	/** R0 memory object for the MSR bitmap (1 page). */
222	RTR0MEMOBJ pMemObjMSRBitmap;
223	/** Physical address of the MSR bitmap (1 page). */
224	RTHCPHYS pMSRBitmapPhys;
225	/** Virtual address of the MSR bitmap (1 page). */
226	R0PTRTYPE(uint8_t *) pMSRBitmap;
227
228	/** R0 memory object for the MSR entry load page (guest MSRs). */
229	RTR0MEMOBJ pMemObjMSREntryLoad;
230	/** Physical address of the MSR entry load page (guest MSRs). */
231	RTHCPHYS pMSREntryLoadPhys;
232	/** Virtual address of the MSR entry load page (guest MSRs). */
233	R0PTRTYPE(uint8_t *) pMSREntryLoad;
234
235	/** R0 memory object for the MSR exit store page (guest MSRs). */
236	RTR0MEMOBJ pMemObjMSRExitStore;
237	/** Physical address of the MSR exit store page (guest MSRs). */
238	RTHCPHYS pMSRExitStorePhys;
239	/** Virtual address of the MSR exit store page (guest MSRs). */
240	R0PTRTYPE(uint8_t *) pMSRExitStore;
241
242	/** R0 memory object for the MSR exit load page (host MSRs). */
243	RTR0MEMOBJ pMemObjMSRExitLoad;
244	/** Physical address of the MSR exit load page (host MSRs). */
245	RTHCPHYS pMSRExitLoadPhys;
246	/** Virtual address of the MSR exit load page (host MSRs). */
247	R0PTRTYPE(uint8_t *) pMSRExitLoad;
248
249	/** Ring 0 handlers for VT-x. */
250	DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx));
251
252	/** Host CR4 value (set by ring-0 VMX init) */
253	uint64_t hostCR4;
254
255	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
256	uint64_t proc_ctls;
257
258	/** Current CR0 mask. */
259	uint64_t cr0_mask;
260	/** Current CR4 mask. */
261	uint64_t cr4_mask;
262
263	/** VMX MSR values */
264	struct
265	{
266	uint64_t feature_ctrl;
267	uint64_t vmx_basic_info;
268	VMX_CAPABILITY vmx_pin_ctls;
269	VMX_CAPABILITY vmx_proc_ctls;
270	VMX_CAPABILITY vmx_proc_ctls2;
271	VMX_CAPABILITY vmx_exit;
272	VMX_CAPABILITY vmx_entry;
273	uint64_t vmx_misc;
274	uint64_t vmx_cr0_fixed0;
275	uint64_t vmx_cr0_fixed1;
276	uint64_t vmx_cr4_fixed0;
277	uint64_t vmx_cr4_fixed1;
278	uint64_t vmx_vmcs_enum;
279	uint64_t vmx_eptcaps;
280	} msr;
281
282	/* Last instruction error */
283	uint32_t ulLastInstrError;
284
285	/** Current trap mask. */
286	uint32_t u32TrapMask;
287
288	struct
289	{
290	uint64_t u64VMCSPhys;
291	uint32_t ulVMCSRevision;
292	} lasterror;
293	} vmx;
294
295	struct
296	{
297	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
298	bool fSupported;
299	/** Set when we've enabled SVM. */
300	bool fEnabled;
301	/** Set if we don't have to flush the TLB on VM entry. */
302	bool fResumeVM;
303	/** Set if erratum 170 affects the AMD cpu. */
304	bool fAlwaysFlushTLB;
305	/** Set if we need to flush the TLB during the world switch. */
306	bool fForceTLBFlush;
307
308	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
309	RTCPUID idLastCpu;
310
311	/* TLB flush count */
312	uint32_t cTLBFlushes;
313
314	/* Current ASID in use by the VM */
315	uint32_t uCurrentASID;
316
317	/** R0 memory object for the VM control block (VMCB). */
318	RTR0MEMOBJ pMemObjVMCB;
319	/** Physical address of the VM control block (VMCB). */
320	RTHCPHYS pVMCBPhys;
321	/** Virtual address of the VM control block (VMCB). */
322	R0PTRTYPE(void *) pVMCB;
323
324	/** R0 memory object for the host VM control block (VMCB). */
325	RTR0MEMOBJ pMemObjVMCBHost;
326	/** Physical address of the host VM control block (VMCB). */
327	RTHCPHYS pVMCBHostPhys;
328	/** Virtual address of the host VM control block (VMCB). */
329	R0PTRTYPE(void *) pVMCBHost;
330
331	/** R0 memory object for the IO bitmap (12kb). */
332	RTR0MEMOBJ pMemObjIOBitmap;
333	/** Physical address of the IO bitmap (12kb). */
334	RTHCPHYS pIOBitmapPhys;
335	/** Virtual address of the IO bitmap. */
336	R0PTRTYPE(void *) pIOBitmap;
337
338	/** R0 memory object for the MSR bitmap (8kb). */
339	RTR0MEMOBJ pMemObjMSRBitmap;
340	/** Physical address of the MSR bitmap (8kb). */
341	RTHCPHYS pMSRBitmapPhys;
342	/** Virtual address of the MSR bitmap. */
343	R0PTRTYPE(void *) pMSRBitmap;
344
345	/** Ring 0 handlers for VT-x. */
346	DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx));
347
348	/** SVM revision. */
349	uint32_t u32Rev;
350
351	/** Maximum ASID allowed. */
352	uint32_t u32MaxASID;
353
354	/** SVM feature bits from cpuid 0x8000000a */
355	uint32_t u32Features;
356	} svm;
357
358	struct
359	{
360	uint32_t u32AMDFeatureECX;
361	uint32_t u32AMDFeatureEDX;
362	} cpuid;
363
364	/* Event injection state. */
365	struct
366	{
367	uint32_t fPending;
368	uint32_t errCode;
369	uint64_t intInfo;
370	} Event;
371
372	/** Saved error from detection */
373	int32_t lLastError;
374
375	/** HWACCMR0Init was run */
376	bool fHWACCMR0Init;
377
378	/** Currenty shadow paging mode. */
379	PGMMODE enmShadowMode;
380
381	#ifdef VBOX_STRICT
382	/** The CPU ID of the CPU currently owning the VMCS. Set in
383	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
384	RTCPUID idEnteredCpu;
385	# if HC_ARCH_BITS == 32
386	RTCPUID Alignment0;
387	# endif
388	#endif
389
390	STAMPROFILEADV StatEntry;
391	STAMPROFILEADV StatExit;
392	STAMPROFILEADV StatInGC;
393
394	STAMCOUNTER StatIntInject;
395
396	STAMCOUNTER StatExitShadowNM;
397	STAMCOUNTER StatExitGuestNM;
398	STAMCOUNTER StatExitShadowPF;
399	STAMCOUNTER StatExitGuestPF;
400	STAMCOUNTER StatExitGuestUD;
401	STAMCOUNTER StatExitGuestSS;
402	STAMCOUNTER StatExitGuestNP;
403	STAMCOUNTER StatExitGuestGP;
404	STAMCOUNTER StatExitGuestDE;
405	STAMCOUNTER StatExitGuestDB;
406	STAMCOUNTER StatExitGuestMF;
407	STAMCOUNTER StatExitInvpg;
408	STAMCOUNTER StatExitInvd;
409	STAMCOUNTER StatExitCpuid;
410	STAMCOUNTER StatExitRdtsc;
411	STAMCOUNTER StatExitCRxWrite;
412	STAMCOUNTER StatExitCRxRead;
413	STAMCOUNTER StatExitDRxWrite;
414	STAMCOUNTER StatExitDRxRead;
415	STAMCOUNTER StatExitCLTS;
416	STAMCOUNTER StatExitLMSW;
417	STAMCOUNTER StatExitIOWrite;
418	STAMCOUNTER StatExitIORead;
419	STAMCOUNTER StatExitIOStringWrite;
420	STAMCOUNTER StatExitIOStringRead;
421	STAMCOUNTER StatExitIrqWindow;
422	STAMCOUNTER StatExitMaxResume;
423	STAMCOUNTER StatIntReinject;
424	STAMCOUNTER StatPendingHostIrq;
425
426	STAMCOUNTER StatFlushPageManual;
427	STAMCOUNTER StatFlushPhysPageManual;
428	STAMCOUNTER StatFlushTLBManual;
429	STAMCOUNTER StatFlushPageInvlpg;
430	STAMCOUNTER StatFlushTLBWorldSwitch;
431	STAMCOUNTER StatNoFlushTLBWorldSwitch;
432	STAMCOUNTER StatFlushTLBCRxChange;
433	STAMCOUNTER StatFlushASID;
434
435	STAMCOUNTER StatSwitchGuestIrq;
436	STAMCOUNTER StatSwitchToR3;
437
438	STAMCOUNTER StatTSCOffset;
439	STAMCOUNTER StatTSCIntercept;
440
441	STAMCOUNTER StatExitReasonNPF;
442	STAMCOUNTER StatDRxArmed;
443	STAMCOUNTER StatDRxContextSwitch;
444	STAMCOUNTER StatDRxIOCheck;
445
446
447	R3PTRTYPE(PSTAMCOUNTER) pStatExitReason;
448	R0PTRTYPE(PSTAMCOUNTER) pStatExitReasonR0;
449	} HWACCM;
450	/** Pointer to HWACCM VM instance data. */
451	typedef HWACCM *PHWACCM;
452
453	#ifdef IN_RING0
454
455	/**
456	* Returns the cpu structure for the current cpu.
457	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
458	*
459	* @returns cpu structure pointer
460	* @param pVM The VM to operate on.
461	*/
462	HWACCMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
463
464	#ifdef VBOX_STRICT
465	HWACCMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx);
466	HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
467	#else
468	#define HWACCMDumpRegs(a, b) do { } while (0)
469	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
470	#endif
471
472	/* Dummy callback handlers. */
473	HWACCMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu);
474	HWACCMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, CPUMCTX *pCtx);
475	HWACCMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
476	HWACCMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
477	HWACCMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
478	HWACCMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
479	HWACCMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
480	HWACCMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx);
481	HWACCMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM);
482	HWACCMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx);
483
484	#endif
485
486	/** @} */
487
488	__END_DECLS
489
490	#endif
491

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 12624

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