HWACCMInternal.h@ 32217

Last change on this file since 32217 was 30789, checked in by vboxsync, 14 years ago
include,Config.kmk: Made the headers syntax check cleanly on linux.amd64 w/ gcc v4.3.4.
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1	/* $Id: HWACCMInternal.h 30789 2010-07-12 11:21:21Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___HWACCMInternal_h
19	#define ___HWACCMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/em.h>
24	#include <VBox/stam.h>
25	#include <VBox/dis.h>
26	#include <VBox/hwaccm.h>
27	#include <VBox/hwacc_vmx.h>
28	#include <VBox/pgm.h>
29	#include <VBox/cpum.h>
30	#include <iprt/memobj.h>
31	#include <iprt/cpuset.h>
32	#include <iprt/mp.h>
33	#include <iprt/avl.h>
34
35	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined (VBOX_WITH_64_BITS_GUESTS)
36	/* Enable 64 bits guest support. */
37	# define VBOX_ENABLE_64_BITS_GUESTS
38	#endif
39
40	#define VMX_USE_CACHED_VMCS_ACCESSES
41	#define HWACCM_VMX_EMULATE_REALMODE
42	#define HWACCM_VTX_WITH_EPT
43	#define HWACCM_VTX_WITH_VPID
44
45
46	#if 0
47	/* Seeing somewhat random behaviour on my Nehalem system with auto-save of guest MSRs;
48	* for some strange reason the CPU doesn't save the MSRs during the VM-exit.
49	* Clearly visible with a dual VCPU configured OpenSolaris 200906 live cd VM.
50	*
51	* Note: change the assembly files when enabling this! (remove the manual auto load/save)
52	*/
53	#define VBOX_WITH_AUTO_MSR_LOAD_RESTORE
54	#endif
55
56	RT_C_DECLS_BEGIN
57
58
59	/** @defgroup grp_hwaccm_int Internal
60	* @ingroup grp_hwaccm
61	* @internal
62	* @{
63	*/
64
65
66	/** Maximum number of exit reason statistics counters. */
67	#define MAX_EXITREASON_STAT 0x100
68	#define MASK_EXITREASON_STAT 0xff
69	#define MASK_INJECT_IRQ_STAT 0xff
70
71	/** @name Changed flags
72	* These flags are used to keep track of which important registers that
73	* have been changed since last they were reset.
74	* @{
75	*/
76	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
77	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
78	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
79	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
80	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
81	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
82	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
83	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
84	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
85	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
86	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
87	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
88
89	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
90	\| HWACCM_CHANGED_GUEST_CR0 \
91	\| HWACCM_CHANGED_GUEST_CR3 \
92	\| HWACCM_CHANGED_GUEST_CR4 \
93	\| HWACCM_CHANGED_GUEST_GDTR \
94	\| HWACCM_CHANGED_GUEST_IDTR \
95	\| HWACCM_CHANGED_GUEST_LDTR \
96	\| HWACCM_CHANGED_GUEST_TR \
97	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
98	\| HWACCM_CHANGED_GUEST_FPU \
99	\| HWACCM_CHANGED_GUEST_DEBUG \
100	\| HWACCM_CHANGED_HOST_CONTEXT)
101
102	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
103	\| HWACCM_CHANGED_GUEST_CR0 \
104	\| HWACCM_CHANGED_GUEST_CR3 \
105	\| HWACCM_CHANGED_GUEST_CR4 \
106	\| HWACCM_CHANGED_GUEST_GDTR \
107	\| HWACCM_CHANGED_GUEST_IDTR \
108	\| HWACCM_CHANGED_GUEST_LDTR \
109	\| HWACCM_CHANGED_GUEST_TR \
110	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
111	\| HWACCM_CHANGED_GUEST_DEBUG \
112	\| HWACCM_CHANGED_GUEST_FPU)
113
114	/** @} */
115
116	/** @name Intercepted traps
117	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
118	* Currently #NM and #PF only
119	*/
120	#ifdef VBOX_STRICT
121	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
122	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
123	#else
124	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
125	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
126	#endif
127	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
128	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
129	/** @} */
130
131
132	/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
133	#define HWACCM_MAX_TLB_SHOOTDOWN_PAGES 8
134
135	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
136	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
137	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
138	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
139	/** Total guest mapped memory needed. */
140	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
141
142	/* Enable for TPR guest patching. */
143	#define VBOX_HWACCM_WITH_GUEST_PATCHING
144
145	/** HWACCM SSM version
146	*/
147	#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
148	#define HWACCM_SSM_VERSION 5
149	#define HWACCM_SSM_VERSION_NO_PATCHING 4
150	#else
151	#define HWACCM_SSM_VERSION 4
152	#define HWACCM_SSM_VERSION_NO_PATCHING 4
153	#endif
154	#define HWACCM_SSM_VERSION_2_0_X 3
155
156	/* Per-cpu information. (host) */
157	typedef struct
158	{
159	RTCPUID idCpu;
160
161	RTR0MEMOBJ pMemObj;
162	/* Current ASID (AMD-V)/VPID (Intel) */
163	uint32_t uCurrentASID;
164	/* TLB flush count */
165	uint32_t cTLBFlushes;
166
167	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
168	bool fFlushTLB;
169
170	/** Configured for VT-x or AMD-V. */
171	bool fConfigured;
172
173	/** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
174	bool fIgnoreAMDVInUseError;
175
176	/** In use by our code. (for power suspend) */
177	volatile bool fInUse;
178	} HWACCM_CPUINFO;
179	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
180
181	typedef enum
182	{
183	HWACCMPENDINGIO_INVALID = 0,
184	HWACCMPENDINGIO_PORT_READ,
185	HWACCMPENDINGIO_PORT_WRITE,
186	HWACCMPENDINGIO_STRING_READ,
187	HWACCMPENDINGIO_STRING_WRITE,
188	/** The usual 32-bit paranoia. */
189	HWACCMPENDINGIO_32BIT_HACK = 0x7fffffff
190	} HWACCMPENDINGIO;
191
192
193	typedef enum
194	{
195	HWACCMTPRINSTR_INVALID,
196	HWACCMTPRINSTR_READ,
197	HWACCMTPRINSTR_READ_SHR4,
198	HWACCMTPRINSTR_WRITE_REG,
199	HWACCMTPRINSTR_WRITE_IMM,
200	HWACCMTPRINSTR_JUMP_REPLACEMENT,
201	/** The usual 32-bit paranoia. */
202	HWACCMTPRINSTR_32BIT_HACK = 0x7fffffff
203	} HWACCMTPRINSTR;
204
205	typedef struct
206	{
207	/** The key is the address of patched instruction. (32 bits GC ptr) */
208	AVLOU32NODECORE Core;
209	/** Original opcode. */
210	uint8_t aOpcode[16];
211	/** Instruction size. */
212	uint32_t cbOp;
213	/** Replacement opcode. */
214	uint8_t aNewOpcode[16];
215	/** Replacement instruction size. */
216	uint32_t cbNewOp;
217	/** Instruction type. */
218	HWACCMTPRINSTR enmType;
219	/** Source operand. */
220	uint32_t uSrcOperand;
221	/** Destination operand. */
222	uint32_t uDstOperand;
223	/** Number of times the instruction caused a fault. */
224	uint32_t cFaults;
225	/** Patch address of the jump replacement. */
226	RTGCPTR32 pJumpTarget;
227	} HWACCMTPRPATCH;
228	/** Pointer to HWACCMTPRPATCH. */
229	typedef HWACCMTPRPATCH *PHWACCMTPRPATCH;
230
231	/**
232	* Switcher function, HC to RC.
233	*
234	* @param pVM The VM handle.
235	* @param uOffsetVMCPU VMCPU offset from pVM
236	* @returns Return code indicating the action to take.
237	*/
238	typedef DECLCALLBACK (int) FNHWACCMSWITCHERHC(PVM pVM, uint32_t uOffsetVMCPU);
239	/** Pointer to switcher function. */
240	typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
241
242	/**
243	* HWACCM VM Instance data.
244	* Changes to this must checked against the padding of the cfgm union in VM!
245	*/
246	typedef struct HWACCM
247	{
248	/** Set when we've initialized VMX or SVM. */
249	bool fInitialized;
250
251	/** Set when hardware acceleration is allowed. */
252	bool fAllowed;
253
254	/** Set if nested paging is enabled. */
255	bool fNestedPaging;
256
257	/** Set if nested paging is allowed. */
258	bool fAllowNestedPaging;
259
260	/** Set if large pages are enabled (requires nested paging). */
261	bool fLargePages;
262
263	/** Set if we can support 64-bit guests or not. */
264	bool fAllow64BitGuests;
265
266	/** Set if an IO-APIC is configured for this VM. */
267	bool fHasIoApic;
268
269	/** Set when TPR patching is allowed. */
270	bool fTRPPatchingAllowed;
271
272	/** Set when we initialize VT-x or AMD-V once for all CPUs. */
273	bool fGlobalInit;
274
275	/** Set when TPR patching is active. */
276	bool fTPRPatchingActive;
277	bool u8Alignment[6];
278
279	/** And mask for copying register contents. */
280	uint64_t u64RegisterMask;
281
282	/** Maximum ASID allowed. */
283	RTUINT uMaxASID;
284
285	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
286	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
287	uint32_t cMaxResumeLoops;
288
289	/** Guest allocated memory for patching purposes. */
290	RTGCPTR pGuestPatchMem;
291	/** Current free pointer inside the patch block. */
292	RTGCPTR pFreeGuestPatchMem;
293	/** Size of the guest patch memory block. */
294	uint32_t cbGuestPatchMem;
295	uint32_t uPadding1;
296
297	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
298	/** 32 to 64 bits switcher entrypoint. */
299	R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
300
301	/* AMD-V 64 bits vmrun handler */
302	RTRCPTR pfnSVMGCVMRun64;
303
304	/* VT-x 64 bits vmlaunch handler */
305	RTRCPTR pfnVMXGCStartVM64;
306
307	/* RC handler to setup the 64 bits FPU state. */
308	RTRCPTR pfnSaveGuestFPU64;
309
310	/* RC handler to setup the 64 bits debug state. */
311	RTRCPTR pfnSaveGuestDebug64;
312
313	/* Test handler */
314	RTRCPTR pfnTest64;
315
316	RTRCPTR uAlignment[2];
317	/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
318	uint32_t u32Alignment[1]; */
319	#endif
320
321	struct
322	{
323	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
324	bool fSupported;
325
326	/** Set when we've enabled VMX. */
327	bool fEnabled;
328
329	/** Set if VPID is supported. */
330	bool fVPID;
331
332	/** Set if VT-x VPID is allowed. */
333	bool fAllowVPID;
334
335	/** Set if unrestricted guest execution is allowed (real and protected mode without paging). */
336	bool fUnrestrictedGuest;
337	bool uAlignment[3];
338
339	/** Virtual address of the TSS page used for real mode emulation. */
340	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
341
342	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
343	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
344
345	/** R0 memory object for the APIC physical page (serves for filtering accesses). */
346	RTR0MEMOBJ pMemObjAPIC;
347	/** Physical address of the APIC physical page (serves for filtering accesses). */
348	RTHCPHYS pAPICPhys;
349	/** Virtual address of the APIC physical page (serves for filtering accesses). */
350	R0PTRTYPE(uint8_t *) pAPIC;
351
352	/** R0 memory object for the MSR entry load page (guest MSRs). */
353	RTR0MEMOBJ pMemObjMSREntryLoad;
354	/** Physical address of the MSR entry load page (guest MSRs). */
355	RTHCPHYS pMSREntryLoadPhys;
356	/** Virtual address of the MSR entry load page (guest MSRs). */
357	R0PTRTYPE(uint8_t *) pMSREntryLoad;
358
359	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
360	RTR0MEMOBJ pMemObjScratch;
361	RTHCPHYS pScratchPhys;
362	R0PTRTYPE(uint8_t *) pScratch;
363	#endif
364	/** R0 memory object for the MSR exit store page (guest MSRs). */
365	RTR0MEMOBJ pMemObjMSRExitStore;
366	/** Physical address of the MSR exit store page (guest MSRs). */
367	RTHCPHYS pMSRExitStorePhys;
368	/** Virtual address of the MSR exit store page (guest MSRs). */
369	R0PTRTYPE(uint8_t *) pMSRExitStore;
370
371	/** R0 memory object for the MSR exit load page (host MSRs). */
372	RTR0MEMOBJ pMemObjMSRExitLoad;
373	/** Physical address of the MSR exit load page (host MSRs). */
374	RTHCPHYS pMSRExitLoadPhys;
375	/** Virtual address of the MSR exit load page (host MSRs). */
376	R0PTRTYPE(uint8_t *) pMSRExitLoad;
377
378	/** Ring 0 handlers for VT-x. */
379	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
380
381	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
382	uint32_t u32Alignment;
383	#endif
384	/** Host CR4 value (set by ring-0 VMX init) */
385	uint64_t hostCR4;
386
387	/** Host EFER value (set by ring-0 VMX init) */
388	uint64_t hostEFER;
389
390	/** VMX MSR values */
391	struct
392	{
393	uint64_t feature_ctrl;
394	uint64_t vmx_basic_info;
395	VMX_CAPABILITY vmx_pin_ctls;
396	VMX_CAPABILITY vmx_proc_ctls;
397	VMX_CAPABILITY vmx_proc_ctls2;
398	VMX_CAPABILITY vmx_exit;
399	VMX_CAPABILITY vmx_entry;
400	uint64_t vmx_misc;
401	uint64_t vmx_cr0_fixed0;
402	uint64_t vmx_cr0_fixed1;
403	uint64_t vmx_cr4_fixed0;
404	uint64_t vmx_cr4_fixed1;
405	uint64_t vmx_vmcs_enum;
406	uint64_t vmx_eptcaps;
407	} msr;
408
409	/** Flush types for invept & invvpid; they depend on capabilities. */
410	VMX_FLUSH enmFlushPage;
411	VMX_FLUSH enmFlushContext;
412	} vmx;
413
414	struct
415	{
416	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
417	bool fSupported;
418	/** Set when we've enabled SVM. */
419	bool fEnabled;
420	/** Set if erratum 170 affects the AMD cpu. */
421	bool fAlwaysFlushTLB;
422	/** Set when the hack to ignore VERR_SVM_IN_USE is active. */
423	bool fIgnoreInUseError;
424
425	/** R0 memory object for the IO bitmap (12kb). */
426	RTR0MEMOBJ pMemObjIOBitmap;
427	/** Physical address of the IO bitmap (12kb). */
428	RTHCPHYS pIOBitmapPhys;
429	/** Virtual address of the IO bitmap. */
430	R0PTRTYPE(void *) pIOBitmap;
431
432	/* HWCR msr (for diagnostics) */
433	uint64_t msrHWCR;
434
435	/** SVM revision. */
436	uint32_t u32Rev;
437
438	/** SVM feature bits from cpuid 0x8000000a */
439	uint32_t u32Features;
440	} svm;
441
442	/**
443	* AVL tree with all patches (active or disabled) sorted by guest instruction address
444	*/
445	AVLOU32TREE PatchTree;
446	uint32_t cPatches;
447	HWACCMTPRPATCH aPatches[64];
448
449	struct
450	{
451	uint32_t u32AMDFeatureECX;
452	uint32_t u32AMDFeatureEDX;
453	} cpuid;
454
455	/** Saved error from detection */
456	int32_t lLastError;
457
458	/** HWACCMR0Init was run */
459	bool fHWACCMR0Init;
460	bool u8Alignment1[7];
461
462	STAMCOUNTER StatTPRPatchSuccess;
463	STAMCOUNTER StatTPRPatchFailure;
464	STAMCOUNTER StatTPRReplaceSuccess;
465	STAMCOUNTER StatTPRReplaceFailure;
466	} HWACCM;
467	/** Pointer to HWACCM VM instance data. */
468	typedef HWACCM *PHWACCM;
469
470	/* Maximum number of cached entries. */
471	#define VMCSCACHE_MAX_ENTRY 128
472
473	/* Structure for storing read and write VMCS actions. */
474	typedef struct VMCSCACHE
475	{
476	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
477	/* Magic marker for searching in crash dumps. */
478	uint8_t aMagic[16];
479	uint64_t uMagic;
480	uint64_t u64TimeEntry;
481	uint64_t u64TimeSwitch;
482	uint64_t cResume;
483	uint64_t interPD;
484	uint64_t pSwitcher;
485	uint32_t uPos;
486	uint32_t idCpu;
487	#endif
488	/* CR2 is saved here for EPT syncing. */
489	uint64_t cr2;
490	struct
491	{
492	uint32_t cValidEntries;
493	uint32_t uAlignment;
494	uint32_t aField[VMCSCACHE_MAX_ENTRY];
495	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
496	} Write;
497	struct
498	{
499	uint32_t cValidEntries;
500	uint32_t uAlignment;
501	uint32_t aField[VMCSCACHE_MAX_ENTRY];
502	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
503	} Read;
504	#ifdef DEBUG
505	struct
506	{
507	RTHCPHYS pPageCpuPhys;
508	RTHCPHYS pVMCSPhys;
509	RTGCPTR pCache;
510	RTGCPTR pCtx;
511	} TestIn;
512	struct
513	{
514	RTHCPHYS pVMCSPhys;
515	RTGCPTR pCache;
516	RTGCPTR pCtx;
517	uint64_t eflags;
518	uint64_t cr8;
519	} TestOut;
520	struct
521	{
522	uint64_t param1;
523	uint64_t param2;
524	uint64_t param3;
525	uint64_t param4;
526	} ScratchPad;
527	#endif
528	} VMCSCACHE;
529	/** Pointer to VMCSCACHE. */
530	typedef VMCSCACHE *PVMCSCACHE;
531
532	/** VMX StartVM function. */
533	typedef DECLCALLBACK(int) FNHWACCMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
534	/** Pointer to a VMX StartVM function. */
535	typedef R0PTRTYPE(FNHWACCMVMXSTARTVM *) PFNHWACCMVMXSTARTVM;
536
537	/** SVM VMRun function. */
538	typedef DECLCALLBACK(int) FNHWACCMSVMVMRUN(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
539	/** Pointer to a SVM VMRun function. */
540	typedef R0PTRTYPE(FNHWACCMSVMVMRUN *) PFNHWACCMSVMVMRUN;
541
542	/**
543	* HWACCM VMCPU Instance data.
544	*/
545	typedef struct HWACCMCPU
546	{
547	/** Old style FPU reporting trap mask override performed (optimization) */
548	bool fFPUOldStyleOverride;
549
550	/** Set if we don't have to flush the TLB on VM entry. */
551	bool fResumeVM;
552
553	/** Set if we need to flush the TLB during the world switch. */
554	bool fForceTLBFlush;
555
556	/** Set when we're using VT-x or AMD-V at that moment. */
557	bool fActive;
558
559	/** Set when the TLB has been checked until we return from the world switch. */
560	volatile uint8_t fCheckedTLBFlush;
561	uint8_t bAlignment[3];
562
563	/** HWACCM_CHANGED_* flags. */
564	RTUINT fContextUseFlags;
565
566	/** Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
567	RTCPUID idLastCpu;
568
569	/** TLB flush count */
570	RTUINT cTLBFlushes;
571
572	/** Current ASID in use by the VM */
573	RTUINT uCurrentASID;
574
575	/** World switch exit counter. */
576	volatile uint32_t cWorldSwitchExit;
577	uint32_t u32Alignment;
578
579	struct
580	{
581	/** Physical address of the VM control structure (VMCS). */
582	RTHCPHYS pVMCSPhys;
583	/** R0 memory object for the VM control structure (VMCS). */
584	RTR0MEMOBJ pMemObjVMCS;
585	/** Virtual address of the VM control structure (VMCS). */
586	R0PTRTYPE(void *) pVMCS;
587
588	/** Ring 0 handlers for VT-x. */
589	PFNHWACCMVMXSTARTVM pfnStartVM;
590
591	#if HC_ARCH_BITS == 32
592	uint32_t u32Alignment;
593	#endif
594
595	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
596	uint64_t proc_ctls;
597
598	/** Current VMX_VMCS_CTRL_PROC_EXEC2_CONTROLS. */
599	uint64_t proc_ctls2;
600
601	/** Physical address of the virtual APIC page for TPR caching. */
602	RTHCPHYS pVAPICPhys;
603	/** R0 memory object for the virtual APIC page for TPR caching. */
604	RTR0MEMOBJ pMemObjVAPIC;
605	/** Virtual address of the virtual APIC page for TPR caching. */
606	R0PTRTYPE(uint8_t *) pVAPIC;
607
608	/** Current CR0 mask. */
609	uint64_t cr0_mask;
610	/** Current CR4 mask. */
611	uint64_t cr4_mask;
612
613	/** Current EPTP. */
614	RTHCPHYS GCPhysEPTP;
615
616	/** Physical address of the MSR bitmap (1 page). */
617	RTHCPHYS pMSRBitmapPhys;
618	/** R0 memory object for the MSR bitmap (1 page). */
619	RTR0MEMOBJ pMemObjMSRBitmap;
620	/** Virtual address of the MSR bitmap (1 page). */
621	R0PTRTYPE(uint8_t *) pMSRBitmap;
622
623	#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
624	/** Physical address of the guest MSR load area (1 page). */
625	RTHCPHYS pGuestMSRPhys;
626	/** R0 memory object for the guest MSR load area (1 page). */
627	RTR0MEMOBJ pMemObjGuestMSR;
628	/** Virtual address of the guest MSR load area (1 page). */
629	R0PTRTYPE(uint8_t *) pGuestMSR;
630
631	/** Physical address of the MSR load area (1 page). */
632	RTHCPHYS pHostMSRPhys;
633	/** R0 memory object for the MSR load area (1 page). */
634	RTR0MEMOBJ pMemObjHostMSR;
635	/** Virtual address of the MSR load area (1 page). */
636	R0PTRTYPE(uint8_t *) pHostMSR;
637	#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
638
639	/* Number of automatically loaded/restored MSRs. */
640	uint32_t cCachedMSRs;
641	uint32_t uAlignement;
642
643	/* Last use TSC offset value. (cached) */
644	uint64_t u64TSCOffset;
645
646	/** VMCS cache. */
647	VMCSCACHE VMCSCache;
648
649	/** Real-mode emulation state. */
650	struct
651	{
652	X86EFLAGS eflags;
653	uint32_t fValid;
654	} RealMode;
655
656	struct
657	{
658	uint64_t u64VMCSPhys;
659	uint32_t ulVMCSRevision;
660	uint32_t ulInstrError;
661	uint32_t ulExitReason;
662	RTCPUID idEnteredCpu;
663	RTCPUID idCurrentCpu;
664	uint32_t padding;
665	} lasterror;
666
667	/** The last seen guest paging mode (by VT-x). */
668	PGMMODE enmLastSeenGuestMode;
669	/** Current guest paging mode (as seen by HWACCMR3PagingModeChanged). */
670	PGMMODE enmCurrGuestMode;
671	/** Previous guest paging mode (as seen by HWACCMR3PagingModeChanged). */
672	PGMMODE enmPrevGuestMode;
673	} vmx;
674
675	struct
676	{
677	/** R0 memory object for the host VM control block (VMCB). */
678	RTR0MEMOBJ pMemObjVMCBHost;
679	/** Physical address of the host VM control block (VMCB). */
680	RTHCPHYS pVMCBHostPhys;
681	/** Virtual address of the host VM control block (VMCB). */
682	R0PTRTYPE(void *) pVMCBHost;
683
684	/** R0 memory object for the VM control block (VMCB). */
685	RTR0MEMOBJ pMemObjVMCB;
686	/** Physical address of the VM control block (VMCB). */
687	RTHCPHYS pVMCBPhys;
688	/** Virtual address of the VM control block (VMCB). */
689	R0PTRTYPE(void *) pVMCB;
690
691	/** Ring 0 handlers for VT-x. */
692	PFNHWACCMSVMVMRUN pfnVMRun;
693
694	/** R0 memory object for the MSR bitmap (8kb). */
695	RTR0MEMOBJ pMemObjMSRBitmap;
696	/** Physical address of the MSR bitmap (8kb). */
697	RTHCPHYS pMSRBitmapPhys;
698	/** Virtual address of the MSR bitmap. */
699	R0PTRTYPE(void *) pMSRBitmap;
700	} svm;
701
702	/** Event injection state. */
703	struct
704	{
705	uint32_t fPending;
706	uint32_t errCode;
707	uint64_t intInfo;
708	} Event;
709
710	/** IO Block emulation state. */
711	struct
712	{
713	bool fEnabled;
714	uint8_t u8Align[7];
715
716	/** RIP at the start of the io code we wish to emulate in the recompiler. */
717	RTGCPTR GCPtrFunctionEip;
718
719	uint64_t cr0;
720	} EmulateIoBlock;
721
722	struct
723	{
724	/* Pending IO operation type. */
725	HWACCMPENDINGIO enmType;
726	uint32_t uPadding;
727	RTGCPTR GCPtrRip;
728	RTGCPTR GCPtrRipNext;
729	union
730	{
731	struct
732	{
733	unsigned uPort;
734	unsigned uAndVal;
735	unsigned cbSize;
736	} Port;
737	uint64_t aRaw[2];
738	} s;
739	} PendingIO;
740
741	/** Currenty shadow paging mode. */
742	PGMMODE enmShadowMode;
743
744	/** The CPU ID of the CPU currently owning the VMCS. Set in
745	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
746	RTCPUID idEnteredCpu;
747
748	/** To keep track of pending TLB shootdown pages. (SMP guest only) */
749	struct
750	{
751	RTGCPTR aPages[HWACCM_MAX_TLB_SHOOTDOWN_PAGES];
752	unsigned cPages;
753	} TlbShootdown;
754
755	/** For saving stack space, the disassembler state is allocated here instead of
756	* on the stack.
757	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
758	union
759	{
760	/** The disassembler scratch space. */
761	DISCPUSTATE DisState;
762	/** Padding. */
763	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
764	};
765
766	RTUINT padding2[1];
767
768	STAMPROFILEADV StatEntry;
769	STAMPROFILEADV StatExit1;
770	STAMPROFILEADV StatExit2;
771	#if 1 /* temporary for tracking down darwin issues. */
772	STAMPROFILEADV StatExit2Sub1;
773	STAMPROFILEADV StatExit2Sub2;
774	STAMPROFILEADV StatExit2Sub3;
775	#endif
776	STAMPROFILEADV StatInGC;
777
778	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
779	STAMPROFILEADV StatWorldSwitch3264;
780	#endif
781	STAMPROFILEADV StatPoke;
782	STAMPROFILEADV StatSpinPoke;
783	STAMPROFILEADV StatSpinPokeFailed;
784
785	STAMCOUNTER StatIntInject;
786
787	STAMCOUNTER StatExitShadowNM;
788	STAMCOUNTER StatExitGuestNM;
789	STAMCOUNTER StatExitShadowPF;
790	STAMCOUNTER StatExitGuestPF;
791	STAMCOUNTER StatExitGuestUD;
792	STAMCOUNTER StatExitGuestSS;
793	STAMCOUNTER StatExitGuestNP;
794	STAMCOUNTER StatExitGuestGP;
795	STAMCOUNTER StatExitGuestDE;
796	STAMCOUNTER StatExitGuestDB;
797	STAMCOUNTER StatExitGuestMF;
798	STAMCOUNTER StatExitInvpg;
799	STAMCOUNTER StatExitInvd;
800	STAMCOUNTER StatExitCpuid;
801	STAMCOUNTER StatExitRdtsc;
802	STAMCOUNTER StatExitRdpmc;
803	STAMCOUNTER StatExitCli;
804	STAMCOUNTER StatExitSti;
805	STAMCOUNTER StatExitPushf;
806	STAMCOUNTER StatExitPopf;
807	STAMCOUNTER StatExitIret;
808	STAMCOUNTER StatExitInt;
809	STAMCOUNTER StatExitCRxWrite[16];
810	STAMCOUNTER StatExitCRxRead[16];
811	STAMCOUNTER StatExitDRxWrite;
812	STAMCOUNTER StatExitDRxRead;
813	STAMCOUNTER StatExitRdmsr;
814	STAMCOUNTER StatExitWrmsr;
815	STAMCOUNTER StatExitCLTS;
816	STAMCOUNTER StatExitHlt;
817	STAMCOUNTER StatExitMwait;
818	STAMCOUNTER StatExitMonitor;
819	STAMCOUNTER StatExitLMSW;
820	STAMCOUNTER StatExitIOWrite;
821	STAMCOUNTER StatExitIORead;
822	STAMCOUNTER StatExitIOStringWrite;
823	STAMCOUNTER StatExitIOStringRead;
824	STAMCOUNTER StatExitIrqWindow;
825	STAMCOUNTER StatExitMaxResume;
826	STAMCOUNTER StatExitPreemptPending;
827	STAMCOUNTER StatIntReinject;
828	STAMCOUNTER StatPendingHostIrq;
829
830	STAMCOUNTER StatFlushPage;
831	STAMCOUNTER StatFlushPageManual;
832	STAMCOUNTER StatFlushPhysPageManual;
833	STAMCOUNTER StatFlushTLB;
834	STAMCOUNTER StatFlushTLBManual;
835	STAMCOUNTER StatFlushPageInvlpg;
836	STAMCOUNTER StatFlushTLBWorldSwitch;
837	STAMCOUNTER StatNoFlushTLBWorldSwitch;
838	STAMCOUNTER StatFlushTLBCRxChange;
839	STAMCOUNTER StatFlushASID;
840	STAMCOUNTER StatFlushTLBInvlpga;
841	STAMCOUNTER StatTlbShootdown;
842	STAMCOUNTER StatTlbShootdownFlush;
843
844	STAMCOUNTER StatSwitchGuestIrq;
845	STAMCOUNTER StatSwitchToR3;
846
847	STAMCOUNTER StatTSCOffset;
848	STAMCOUNTER StatTSCIntercept;
849	STAMCOUNTER StatTSCInterceptOverFlow;
850
851	STAMCOUNTER StatExitReasonNPF;
852	STAMCOUNTER StatDRxArmed;
853	STAMCOUNTER StatDRxContextSwitch;
854	STAMCOUNTER StatDRxIOCheck;
855
856	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
857	STAMCOUNTER StatFpu64SwitchBack;
858	STAMCOUNTER StatDebug64SwitchBack;
859	#endif
860
861	#ifdef VBOX_WITH_STATISTICS
862	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
863	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
864	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
865	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
866	#endif
867	} HWACCMCPU;
868	/** Pointer to HWACCM VM instance data. */
869	typedef HWACCMCPU *PHWACCMCPU;
870
871
872	#ifdef IN_RING0
873
874	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
875	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
876
877
878	#ifdef VBOX_STRICT
879	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
880	VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
881	#else
882	# define HWACCMDumpRegs(a, b ,c) do { } while (0)
883	# define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
884	#endif
885
886	/* Dummy callback handlers. */
887	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
888	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
889	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
890	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
891	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
892	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
893	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
894	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
895	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
896	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
897
898	# ifdef VBOX_WITH_KERNEL_USING_XMM
899	DECLASM(int) hwaccmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHWACCMVMXSTARTVM pfnStartVM);
900	DECLASM(int) hwaccmR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHWACCMSVMVMRUN pfnVMRun);
901	# endif
902
903	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
904	/**
905	* Gets 64-bit GDTR and IDTR on darwin.
906	* @param pGdtr Where to store the 64-bit GDTR.
907	* @param pIdtr Where to store the 64-bit IDTR.
908	*/
909	DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
910
911	/**
912	* Gets 64-bit CR3 on darwin.
913	* @returns CR3
914	*/
915	DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
916	# endif
917
918	#endif /* IN_RING0 */
919
920	/** @} */
921
922	RT_C_DECLS_END
923
924	#endif
925

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 32217

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