HWACCMInternal.h@ 9026

Last change on this file since 9026 was 9021, checked in by vboxsync, 17 years ago
Nested paging updates. Extra paging mode added to prevent illegal changes to the shadow page table.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 13.5 KB

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1	/* $Id: HWACCMInternal.h 9021 2008-05-21 14:38:13Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <iprt/memobj.h>
33	#include <iprt/cpuset.h>
34	#include <iprt/mp.h>
35
36	__BEGIN_DECLS
37
38
39	/** @defgroup grp_hwaccm_int Internal
40	* @ingroup grp_hwaccm
41	* @internal
42	* @{
43	*/
44
45
46	/**
47	* Converts a HWACCM pointer into a VM pointer.
48	* @returns Pointer to the VM structure the EM is part of.
49	* @param pHWACCM Pointer to HWACCM instance data.
50	*/
51	#define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
52
53	/** Maximum number of exit reason statistics counters. */
54	#define MAX_EXITREASON_STAT 0x100
55	#define MASK_EXITREASON_STAT 0xff
56
57	/** @name Changed flags
58	* These flags are used to keep track of which important registers that
59	* have been changed since last they were reset.
60	* @{
61	*/
62	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
63	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
64	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
65	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
66	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
67	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
68	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
69	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
70	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
71	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
72	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
73	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
74
75	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
76	\| HWACCM_CHANGED_GUEST_CR0 \
77	\| HWACCM_CHANGED_GUEST_CR3 \
78	\| HWACCM_CHANGED_GUEST_CR4 \
79	\| HWACCM_CHANGED_GUEST_GDTR \
80	\| HWACCM_CHANGED_GUEST_IDTR \
81	\| HWACCM_CHANGED_GUEST_LDTR \
82	\| HWACCM_CHANGED_GUEST_TR \
83	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
84	\| HWACCM_CHANGED_GUEST_FPU \
85	\| HWACCM_CHANGED_GUEST_DEBUG \
86	\| HWACCM_CHANGED_HOST_CONTEXT)
87
88	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
89	\| HWACCM_CHANGED_GUEST_CR0 \
90	\| HWACCM_CHANGED_GUEST_CR3 \
91	\| HWACCM_CHANGED_GUEST_CR4 \
92	\| HWACCM_CHANGED_GUEST_GDTR \
93	\| HWACCM_CHANGED_GUEST_IDTR \
94	\| HWACCM_CHANGED_GUEST_LDTR \
95	\| HWACCM_CHANGED_GUEST_TR \
96	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
97	\| HWACCM_CHANGED_GUEST_DEBUG \
98	\| HWACCM_CHANGED_GUEST_FPU)
99
100	/** @} */
101
102	/** @name Intercepted traps
103	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
104	* Currently #NM and #PF only
105	*/
106	#ifdef VBOX_STRICT
107	#define HWACCM_VMX_TRAP_MASK RT_BIT(0) \| RT_BIT(7) \| RT_BIT(14) \| RT_BIT(6) \| RT_BIT(11) \| RT_BIT(12) \| RT_BIT(13) \| RT_BIT(16)
108	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
109	#else
110	#define HWACCM_VMX_TRAP_MASK RT_BIT(7) \| RT_BIT(14)
111	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
112	#endif
113	/** @} */
114
115
116	/** Maxium resume loops allowed in ring 0 (safety precaution) */
117	#define HWACCM_MAX_RESUME_LOOPS 1024
118
119	/** HWACCM SSM version
120	*/
121	#define HWACCM_SSM_VERSION 3
122
123	/**
124	* HWACCM VM Instance data.
125	* Changes to this must checked against the padding of the cfgm union in VM!
126	*/
127	typedef struct HWACCM
128	{
129	/** Offset to the VM structure.
130	* See HWACCM2VM(). */
131	RTUINT offVM;
132
133	/** Set when we've initialized VMX or SVM. */
134	bool fInitialized;
135	/** Set when we're using VMX/SVN at that moment. */
136	bool fActive;
137
138	/** Set when hardware acceleration is allowed. */
139	bool fAllowed;
140
141	/** Set if nested paging is enabled. */
142	bool fNestedPaging;
143
144	/** HWACCM_CHANGED_* flags. */
145	uint32_t fContextUseFlags;
146
147	/** Old style FPU reporting trap mask override performed (optimization) */
148	uint32_t fFPUOldStyleOverride;
149
150	struct
151	{
152	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
153	bool fSupported;
154
155	/** Set when we've enabled VMX. */
156	bool fEnabled;
157
158	/** Set if we can use VMXResume to execute guest code. */
159	bool fResumeVM;
160
161	/** R0 memory object for the VM control structure (VMCS). */
162	RTR0MEMOBJ pMemObjVMCS;
163	/** Physical address of the VM control structure (VMCS). */
164	RTHCPHYS pVMCSPhys;
165	/** Virtual address of the VM control structure (VMCS). */
166	R0PTRTYPE(void *) pVMCS;
167
168	/** R0 memory object for the TSS page used for real mode emulation. */
169	RTR0MEMOBJ pMemObjRealModeTSS;
170	/** Physical address of the TSS page used for real mode emulation. */
171	RTHCPHYS pRealModeTSSPhys;
172	/** Virtual address of the TSS page used for real mode emulation. */
173	R0PTRTYPE(PVBOXTSS) pRealModeTSS;
174
175	/** Host CR4 value (set by ring-0 VMX init) */
176	uint64_t hostCR4;
177
178	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
179	uint64_t proc_ctls;
180
181	/** Current CR0 mask. */
182	uint64_t cr0_mask;
183	/** Current CR4 mask. */
184	uint64_t cr4_mask;
185
186	/** VMX MSR values */
187	struct
188	{
189	uint64_t feature_ctrl;
190	uint64_t vmx_basic_info;
191	uint64_t vmx_pin_ctls;
192	uint64_t vmx_proc_ctls;
193	uint64_t vmx_exit;
194	uint64_t vmx_entry;
195	uint64_t vmx_misc;
196	uint64_t vmx_cr0_fixed0;
197	uint64_t vmx_cr0_fixed1;
198	uint64_t vmx_cr4_fixed0;
199	uint64_t vmx_cr4_fixed1;
200	uint64_t vmx_vmcs_enum;
201	} msr;
202
203	/* Last instruction error */
204	uint32_t ulLastInstrError;
205	} vmx;
206
207	struct
208	{
209	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
210	bool fSupported;
211	/** Set when we've enabled SVM. */
212	bool fEnabled;
213	/** Set if we don't have to flush the TLB on VM entry. */
214	bool fResumeVM;
215	/** Set if erratum 170 affects the AMD cpu. */
216	bool fAlwaysFlushTLB;
217	/** Set if we need to flush the TLB during the world switch. */
218	bool fForceTLBFlush;
219
220	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
221	RTCPUID idLastCpu;
222
223	/* TLB flush count */
224	uint32_t cTLBFlushes;
225
226	/** R0 memory object for the VM control block (VMCB). */
227	RTR0MEMOBJ pMemObjVMCB;
228	/** Physical address of the VM control block (VMCB). */
229	RTHCPHYS pVMCBPhys;
230	/** Virtual address of the VM control block (VMCB). */
231	R0PTRTYPE(void *) pVMCB;
232
233	/** R0 memory object for the host VM control block (VMCB). */
234	RTR0MEMOBJ pMemObjVMCBHost;
235	/** Physical address of the host VM control block (VMCB). */
236	RTHCPHYS pVMCBHostPhys;
237	/** Virtual address of the host VM control block (VMCB). */
238	R0PTRTYPE(void *) pVMCBHost;
239
240	/** R0 memory object for the IO bitmap (12kb). */
241	RTR0MEMOBJ pMemObjIOBitmap;
242	/** Physical address of the IO bitmap (12kb). */
243	RTHCPHYS pIOBitmapPhys;
244	/** Virtual address of the IO bitmap. */
245	R0PTRTYPE(void *) pIOBitmap;
246
247	/** R0 memory object for the MSR bitmap (8kb). */
248	RTR0MEMOBJ pMemObjMSRBitmap;
249	/** Physical address of the MSR bitmap (8kb). */
250	RTHCPHYS pMSRBitmapPhys;
251	/** Virtual address of the MSR bitmap. */
252	R0PTRTYPE(void *) pMSRBitmap;
253
254	/** SVM revision. */
255	uint32_t u32Rev;
256
257	/** Maximum ASID allowed. */
258	uint32_t u32MaxASID;
259
260	/** SVM feature bits from cpuid 0x8000000a */
261	uint32_t u32Features;
262	} svm;
263
264	struct
265	{
266	uint32_t u32AMDFeatureECX;
267	uint32_t u32AMDFeatureEDX;
268	} cpuid;
269
270	/* Event injection state. */
271	struct
272	{
273	uint32_t fPending;
274	uint32_t errCode;
275	uint64_t intInfo;
276	} Event;
277
278	/** Saved error from detection */
279	int32_t lLastError;
280
281	/** HWACCMR0Init was run */
282	bool fHWACCMR0Init;
283
284	/** Currenty shadow paging mode. */
285	PGMMODE enmShadowMode;
286
287	STAMPROFILEADV StatEntry;
288	STAMPROFILEADV StatExit;
289	STAMPROFILEADV StatInGC;
290
291	STAMCOUNTER StatIntInject;
292
293	STAMCOUNTER StatExitShadowNM;
294	STAMCOUNTER StatExitGuestNM;
295	STAMCOUNTER StatExitShadowPF;
296	STAMCOUNTER StatExitGuestPF;
297	STAMCOUNTER StatExitGuestUD;
298	STAMCOUNTER StatExitGuestSS;
299	STAMCOUNTER StatExitGuestNP;
300	STAMCOUNTER StatExitGuestGP;
301	STAMCOUNTER StatExitGuestDE;
302	STAMCOUNTER StatExitGuestMF;
303	STAMCOUNTER StatExitInvpg;
304	STAMCOUNTER StatExitInvd;
305	STAMCOUNTER StatExitCpuid;
306	STAMCOUNTER StatExitRdtsc;
307	STAMCOUNTER StatExitCRxWrite;
308	STAMCOUNTER StatExitCRxRead;
309	STAMCOUNTER StatExitDRxWrite;
310	STAMCOUNTER StatExitDRxRead;
311	STAMCOUNTER StatExitCLTS;
312	STAMCOUNTER StatExitLMSW;
313	STAMCOUNTER StatExitIOWrite;
314	STAMCOUNTER StatExitIORead;
315	STAMCOUNTER StatExitIOStringWrite;
316	STAMCOUNTER StatExitIOStringRead;
317	STAMCOUNTER StatExitIrqWindow;
318	STAMCOUNTER StatExitMaxResume;
319	STAMCOUNTER StatIntReinject;
320	STAMCOUNTER StatPendingHostIrq;
321
322	STAMCOUNTER StatFlushPageManual;
323	STAMCOUNTER StatFlushTLBManual;
324	STAMCOUNTER StatFlushPageInvlpg;
325	STAMCOUNTER StatFlushTLBWorldSwitch;
326	STAMCOUNTER StatNoFlushTLBWorldSwitch;
327	STAMCOUNTER StatFlushTLBCRxChange;
328	STAMCOUNTER StatFlushASID;
329
330	STAMCOUNTER StatSwitchGuestIrq;
331	STAMCOUNTER StatSwitchToR3;
332
333	R3PTRTYPE(PSTAMCOUNTER) pStatExitReason;
334	R0PTRTYPE(PSTAMCOUNTER) pStatExitReasonR0;
335	} HWACCM;
336	/** Pointer to HWACCM VM instance data. */
337	typedef HWACCM *PHWACCM;
338
339	typedef struct
340	{
341	RTCPUID idCpu;
342
343	RTR0MEMOBJ pMemObj;
344	/* Current ASID (AMD-V only) */
345	uint32_t uCurrentASID;
346	/* TLB flush count */
347	uint32_t cTLBFlushes;
348
349	bool fVMXConfigured;
350	bool fSVMConfigured;
351	} HWACCM_CPUINFO;
352	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
353
354	#ifdef IN_RING0
355
356	#ifdef VBOX_STRICT
357	HWACCMR0DECL(void) HWACCMDumpRegs(PCPUMCTX pCtx);
358	HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
359	#else
360	#define HWACCMDumpRegs(a) do { } while (0)
361	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
362	#endif
363
364	#endif
365
366	/** @} */
367
368	__END_DECLS
369
370	#endif
371

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 9026

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