VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 10318

Last change on this file since 10318 was 10290, checked in by vboxsync, 17 years ago

Enable 64 bits guest support.
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1/* $Id: HWACCMInternal.h 10290 2008-07-05 17:52:55Z vboxsync $ */
2/** @file
3 * HWACCM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___HWACCMInternal_h
23#define ___HWACCMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/em.h>
28#include <VBox/stam.h>
29#include <VBox/dis.h>
30#include <VBox/hwaccm.h>
31#include <VBox/pgm.h>
32#include <iprt/memobj.h>
33#include <iprt/cpuset.h>
34#include <iprt/mp.h>
35
36/* Uncomment to enable experimental nested paging. */
37/////#define VBOX_WITH_NESTED_PAGING
38#if HC_ARCH_BITS == 64
39/* Enable 64 bits guest support. */
40# define VBOX_ENABLE_64_BITS_GUESTS
41#endif
42
43__BEGIN_DECLS
44
45
46/** @defgroup grp_hwaccm_int Internal
47 * @ingroup grp_hwaccm
48 * @internal
49 * @{
50 */
51
52
53/**
54 * Converts a HWACCM pointer into a VM pointer.
55 * @returns Pointer to the VM structure the EM is part of.
56 * @param pHWACCM Pointer to HWACCM instance data.
57 */
58#define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
59
60/** Maximum number of exit reason statistics counters. */
61#define MAX_EXITREASON_STAT 0x100
62#define MASK_EXITREASON_STAT 0xff
63
64/** @name Changed flags
65 * These flags are used to keep track of which important registers that
66 * have been changed since last they were reset.
67 * @{
68 */
69#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
70#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
71#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
72#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
73#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
74#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
75#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
76#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
77#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
78#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
79#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
80#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
81#define HWACCM_CHANGED_GUEST_CR8 RT_BIT(12)
82
83#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
84 | HWACCM_CHANGED_GUEST_CR0 \
85 | HWACCM_CHANGED_GUEST_CR3 \
86 | HWACCM_CHANGED_GUEST_CR4 \
87 | HWACCM_CHANGED_GUEST_CR8 \
88 | HWACCM_CHANGED_GUEST_GDTR \
89 | HWACCM_CHANGED_GUEST_IDTR \
90 | HWACCM_CHANGED_GUEST_LDTR \
91 | HWACCM_CHANGED_GUEST_TR \
92 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
93 | HWACCM_CHANGED_GUEST_FPU \
94 | HWACCM_CHANGED_GUEST_DEBUG \
95 | HWACCM_CHANGED_HOST_CONTEXT)
96
97#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
98 | HWACCM_CHANGED_GUEST_CR0 \
99 | HWACCM_CHANGED_GUEST_CR3 \
100 | HWACCM_CHANGED_GUEST_CR4 \
101 | HWACCM_CHANGED_GUEST_CR8 \
102 | HWACCM_CHANGED_GUEST_GDTR \
103 | HWACCM_CHANGED_GUEST_IDTR \
104 | HWACCM_CHANGED_GUEST_LDTR \
105 | HWACCM_CHANGED_GUEST_TR \
106 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
107 | HWACCM_CHANGED_GUEST_DEBUG \
108 | HWACCM_CHANGED_GUEST_FPU)
109
110/** @} */
111
112/** @name Intercepted traps
113 * Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
114 * Currently #NM and #PF only
115 */
116#ifdef VBOX_STRICT
117#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF)
118#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
119#else
120#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
121#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
122#endif
123/** @} */
124
125
126/** Maxium resume loops allowed in ring 0 (safety precaution) */
127#define HWACCM_MAX_RESUME_LOOPS 1024
128
129/** HWACCM SSM version
130 */
131#define HWACCM_SSM_VERSION 3
132
133/* Per-cpu information. */
134typedef struct
135{
136 RTCPUID idCpu;
137
138 RTR0MEMOBJ pMemObj;
139 /* Current ASID (AMD-V only) */
140 uint32_t uCurrentASID;
141 /* TLB flush count */
142 uint32_t cTLBFlushes;
143
144 bool fConfigured;
145} HWACCM_CPUINFO;
146typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
147
148/**
149 * HWACCM VM Instance data.
150 * Changes to this must checked against the padding of the cfgm union in VM!
151 */
152typedef struct HWACCM
153{
154 /** Offset to the VM structure.
155 * See HWACCM2VM(). */
156 RTUINT offVM;
157
158 /** Set when we've initialized VMX or SVM. */
159 bool fInitialized;
160 /** Set when we're using VMX/SVN at that moment. */
161 bool fActive;
162
163 /** Set when hardware acceleration is allowed. */
164 bool fAllowed;
165
166 /** Set if nested paging is enabled. */
167 bool fNestedPaging;
168
169 /** HWACCM_CHANGED_* flags. */
170 uint32_t fContextUseFlags;
171
172 /** Old style FPU reporting trap mask override performed (optimization) */
173 uint32_t fFPUOldStyleOverride;
174
175 /** And mask for copying register contents. */
176 uint64_t u64RegisterMask;
177 struct
178 {
179 /** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
180 bool fSupported;
181
182 /** Set when we've enabled VMX. */
183 bool fEnabled;
184
185 /** Set if we can use VMXResume to execute guest code. */
186 bool fResumeVM;
187
188 /** R0 memory object for the VM control structure (VMCS). */
189 RTR0MEMOBJ pMemObjVMCS;
190 /** Physical address of the VM control structure (VMCS). */
191 RTHCPHYS pVMCSPhys;
192 /** Virtual address of the VM control structure (VMCS). */
193 R0PTRTYPE(void *) pVMCS;
194
195 /** R0 memory object for the TSS page used for real mode emulation. */
196 RTR0MEMOBJ pMemObjRealModeTSS;
197 /** Physical address of the TSS page used for real mode emulation. */
198 RTHCPHYS pRealModeTSSPhys;
199 /** Virtual address of the TSS page used for real mode emulation. */
200 R0PTRTYPE(PVBOXTSS) pRealModeTSS;
201
202 /** Ring 0 handlers for VT-x. */
203 DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx));
204
205 /** Host CR4 value (set by ring-0 VMX init) */
206 uint64_t hostCR4;
207
208 /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
209 uint64_t proc_ctls;
210
211 /** Current CR0 mask. */
212 uint64_t cr0_mask;
213 /** Current CR4 mask. */
214 uint64_t cr4_mask;
215
216 /** VMX MSR values */
217 struct
218 {
219 uint64_t feature_ctrl;
220 uint64_t vmx_basic_info;
221 uint64_t vmx_pin_ctls;
222 uint64_t vmx_proc_ctls;
223 uint64_t vmx_exit;
224 uint64_t vmx_entry;
225 uint64_t vmx_misc;
226 uint64_t vmx_cr0_fixed0;
227 uint64_t vmx_cr0_fixed1;
228 uint64_t vmx_cr4_fixed0;
229 uint64_t vmx_cr4_fixed1;
230 uint64_t vmx_vmcs_enum;
231 } msr;
232
233 /* Last instruction error */
234 uint32_t ulLastInstrError;
235 } vmx;
236
237 struct
238 {
239 /** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
240 bool fSupported;
241 /** Set when we've enabled SVM. */
242 bool fEnabled;
243 /** Set if we don't have to flush the TLB on VM entry. */
244 bool fResumeVM;
245 /** Set if erratum 170 affects the AMD cpu. */
246 bool fAlwaysFlushTLB;
247 /** Set if we need to flush the TLB during the world switch. */
248 bool fForceTLBFlush;
249
250 /* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
251 RTCPUID idLastCpu;
252
253 /* TLB flush count */
254 uint32_t cTLBFlushes;
255
256 /** R0 memory object for the VM control block (VMCB). */
257 RTR0MEMOBJ pMemObjVMCB;
258 /** Physical address of the VM control block (VMCB). */
259 RTHCPHYS pVMCBPhys;
260 /** Virtual address of the VM control block (VMCB). */
261 R0PTRTYPE(void *) pVMCB;
262
263 /** R0 memory object for the host VM control block (VMCB). */
264 RTR0MEMOBJ pMemObjVMCBHost;
265 /** Physical address of the host VM control block (VMCB). */
266 RTHCPHYS pVMCBHostPhys;
267 /** Virtual address of the host VM control block (VMCB). */
268 R0PTRTYPE(void *) pVMCBHost;
269
270 /** R0 memory object for the IO bitmap (12kb). */
271 RTR0MEMOBJ pMemObjIOBitmap;
272 /** Physical address of the IO bitmap (12kb). */
273 RTHCPHYS pIOBitmapPhys;
274 /** Virtual address of the IO bitmap. */
275 R0PTRTYPE(void *) pIOBitmap;
276
277 /** R0 memory object for the MSR bitmap (8kb). */
278 RTR0MEMOBJ pMemObjMSRBitmap;
279 /** Physical address of the MSR bitmap (8kb). */
280 RTHCPHYS pMSRBitmapPhys;
281 /** Virtual address of the MSR bitmap. */
282 R0PTRTYPE(void *) pMSRBitmap;
283
284 /** Ring 0 handlers for VT-x. */
285 DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx));
286
287 /** SVM revision. */
288 uint32_t u32Rev;
289
290 /** Maximum ASID allowed. */
291 uint32_t u32MaxASID;
292
293 /** SVM feature bits from cpuid 0x8000000a */
294 uint32_t u32Features;
295 } svm;
296
297 struct
298 {
299 uint32_t u32AMDFeatureECX;
300 uint32_t u32AMDFeatureEDX;
301 } cpuid;
302
303 /* Event injection state. */
304 struct
305 {
306 uint32_t fPending;
307 uint32_t errCode;
308 uint64_t intInfo;
309 } Event;
310
311 /** Saved error from detection */
312 int32_t lLastError;
313
314 /** HWACCMR0Init was run */
315 bool fHWACCMR0Init;
316
317 /** Currenty shadow paging mode. */
318 PGMMODE enmShadowMode;
319
320 STAMPROFILEADV StatEntry;
321 STAMPROFILEADV StatExit;
322 STAMPROFILEADV StatInGC;
323
324 STAMCOUNTER StatIntInject;
325
326 STAMCOUNTER StatExitShadowNM;
327 STAMCOUNTER StatExitGuestNM;
328 STAMCOUNTER StatExitShadowPF;
329 STAMCOUNTER StatExitGuestPF;
330 STAMCOUNTER StatExitGuestUD;
331 STAMCOUNTER StatExitGuestSS;
332 STAMCOUNTER StatExitGuestNP;
333 STAMCOUNTER StatExitGuestGP;
334 STAMCOUNTER StatExitGuestDE;
335 STAMCOUNTER StatExitGuestMF;
336 STAMCOUNTER StatExitInvpg;
337 STAMCOUNTER StatExitInvd;
338 STAMCOUNTER StatExitCpuid;
339 STAMCOUNTER StatExitRdtsc;
340 STAMCOUNTER StatExitCRxWrite;
341 STAMCOUNTER StatExitCRxRead;
342 STAMCOUNTER StatExitDRxWrite;
343 STAMCOUNTER StatExitDRxRead;
344 STAMCOUNTER StatExitCLTS;
345 STAMCOUNTER StatExitLMSW;
346 STAMCOUNTER StatExitIOWrite;
347 STAMCOUNTER StatExitIORead;
348 STAMCOUNTER StatExitIOStringWrite;
349 STAMCOUNTER StatExitIOStringRead;
350 STAMCOUNTER StatExitIrqWindow;
351 STAMCOUNTER StatExitMaxResume;
352 STAMCOUNTER StatIntReinject;
353 STAMCOUNTER StatPendingHostIrq;
354
355 STAMCOUNTER StatFlushPageManual;
356 STAMCOUNTER StatFlushPhysPageManual;
357 STAMCOUNTER StatFlushTLBManual;
358 STAMCOUNTER StatFlushPageInvlpg;
359 STAMCOUNTER StatFlushTLBWorldSwitch;
360 STAMCOUNTER StatNoFlushTLBWorldSwitch;
361 STAMCOUNTER StatFlushTLBCRxChange;
362 STAMCOUNTER StatFlushASID;
363
364 STAMCOUNTER StatSwitchGuestIrq;
365 STAMCOUNTER StatSwitchToR3;
366
367 STAMCOUNTER StatTSCOffset;
368 STAMCOUNTER StatTSCIntercept;
369
370 STAMCOUNTER StatExitReasonNPF;
371 R3PTRTYPE(PSTAMCOUNTER) pStatExitReason;
372 R0PTRTYPE(PSTAMCOUNTER) pStatExitReasonR0;
373} HWACCM;
374/** Pointer to HWACCM VM instance data. */
375typedef HWACCM *PHWACCM;
376
377#ifdef IN_RING0
378
379#ifdef VBOX_STRICT
380HWACCMR0DECL(void) HWACCMDumpRegs(PCPUMCTX pCtx);
381HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
382#else
383#define HWACCMDumpRegs(a) do { } while (0)
384#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
385#endif
386
387/* Dummy callback handlers. */
388HWACCMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu);
389HWACCMR0DECL(int) HWACCMR0DummyLeave(PVM pVM);
390HWACCMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
391HWACCMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
392HWACCMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
393HWACCMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
394HWACCMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
395HWACCMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx, PHWACCM_CPUINFO pCpu);
396HWACCMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM);
397HWACCMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx);
398
399#endif
400
401/** @} */
402
403__END_DECLS
404
405#endif
406
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