VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 10409

Last change on this file since 10409 was 10359, checked in by vboxsync, 16 years ago

Removed obsolete HWACCM_CHANGED_GUEST_CR8
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 15.4 KB
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1/* $Id: HWACCMInternal.h 10359 2008-07-08 12:20:11Z vboxsync $ */
2/** @file
3 * HWACCM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___HWACCMInternal_h
23#define ___HWACCMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/em.h>
28#include <VBox/stam.h>
29#include <VBox/dis.h>
30#include <VBox/hwaccm.h>
31#include <VBox/pgm.h>
32#include <iprt/memobj.h>
33#include <iprt/cpuset.h>
34#include <iprt/mp.h>
35
36/* Uncomment to enable experimental nested paging. */
37/////#define VBOX_WITH_NESTED_PAGING
38#if HC_ARCH_BITS == 64
39/* Enable 64 bits guest support. */
40# define VBOX_ENABLE_64_BITS_GUESTS
41#endif
42
43__BEGIN_DECLS
44
45
46/** @defgroup grp_hwaccm_int Internal
47 * @ingroup grp_hwaccm
48 * @internal
49 * @{
50 */
51
52
53/**
54 * Converts a HWACCM pointer into a VM pointer.
55 * @returns Pointer to the VM structure the EM is part of.
56 * @param pHWACCM Pointer to HWACCM instance data.
57 */
58#define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
59
60/** Maximum number of exit reason statistics counters. */
61#define MAX_EXITREASON_STAT 0x100
62#define MASK_EXITREASON_STAT 0xff
63
64/** @name Changed flags
65 * These flags are used to keep track of which important registers that
66 * have been changed since last they were reset.
67 * @{
68 */
69#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
70#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
71#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
72#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
73#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
74#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
75#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
76#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
77#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
78#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
79#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
80#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
81
82#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
83 | HWACCM_CHANGED_GUEST_CR0 \
84 | HWACCM_CHANGED_GUEST_CR3 \
85 | HWACCM_CHANGED_GUEST_CR4 \
86 | HWACCM_CHANGED_GUEST_GDTR \
87 | HWACCM_CHANGED_GUEST_IDTR \
88 | HWACCM_CHANGED_GUEST_LDTR \
89 | HWACCM_CHANGED_GUEST_TR \
90 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
91 | HWACCM_CHANGED_GUEST_FPU \
92 | HWACCM_CHANGED_GUEST_DEBUG \
93 | HWACCM_CHANGED_HOST_CONTEXT)
94
95#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
96 | HWACCM_CHANGED_GUEST_CR0 \
97 | HWACCM_CHANGED_GUEST_CR3 \
98 | HWACCM_CHANGED_GUEST_CR4 \
99 | HWACCM_CHANGED_GUEST_GDTR \
100 | HWACCM_CHANGED_GUEST_IDTR \
101 | HWACCM_CHANGED_GUEST_LDTR \
102 | HWACCM_CHANGED_GUEST_TR \
103 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
104 | HWACCM_CHANGED_GUEST_DEBUG \
105 | HWACCM_CHANGED_GUEST_FPU)
106
107/** @} */
108
109/** @name Intercepted traps
110 * Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
111 * Currently #NM and #PF only
112 */
113#ifdef VBOX_STRICT
114#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF)
115#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
116#else
117#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
118#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
119#endif
120/** @} */
121
122
123/** Maxium resume loops allowed in ring 0 (safety precaution) */
124#define HWACCM_MAX_RESUME_LOOPS 1024
125
126/** HWACCM SSM version
127 */
128#define HWACCM_SSM_VERSION 3
129
130/* Per-cpu information. */
131typedef struct
132{
133 RTCPUID idCpu;
134
135 RTR0MEMOBJ pMemObj;
136 /* Current ASID (AMD-V only) */
137 uint32_t uCurrentASID;
138 /* TLB flush count */
139 uint32_t cTLBFlushes;
140
141 bool fConfigured;
142} HWACCM_CPUINFO;
143typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
144
145/**
146 * HWACCM VM Instance data.
147 * Changes to this must checked against the padding of the cfgm union in VM!
148 */
149typedef struct HWACCM
150{
151 /** Offset to the VM structure.
152 * See HWACCM2VM(). */
153 RTUINT offVM;
154
155 /** Set when we've initialized VMX or SVM. */
156 bool fInitialized;
157 /** Set when we're using VMX/SVN at that moment. */
158 bool fActive;
159
160 /** Set when hardware acceleration is allowed. */
161 bool fAllowed;
162
163 /** Set if nested paging is enabled. */
164 bool fNestedPaging;
165
166 /** HWACCM_CHANGED_* flags. */
167 uint32_t fContextUseFlags;
168
169 /** Old style FPU reporting trap mask override performed (optimization) */
170 uint32_t fFPUOldStyleOverride;
171
172 /** And mask for copying register contents. */
173 uint64_t u64RegisterMask;
174 struct
175 {
176 /** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
177 bool fSupported;
178
179 /** Set when we've enabled VMX. */
180 bool fEnabled;
181
182 /** Set if we can use VMXResume to execute guest code. */
183 bool fResumeVM;
184
185 /** R0 memory object for the VM control structure (VMCS). */
186 RTR0MEMOBJ pMemObjVMCS;
187 /** Physical address of the VM control structure (VMCS). */
188 RTHCPHYS pVMCSPhys;
189 /** Virtual address of the VM control structure (VMCS). */
190 R0PTRTYPE(void *) pVMCS;
191
192 /** R0 memory object for the TSS page used for real mode emulation. */
193 RTR0MEMOBJ pMemObjRealModeTSS;
194 /** Physical address of the TSS page used for real mode emulation. */
195 RTHCPHYS pRealModeTSSPhys;
196 /** Virtual address of the TSS page used for real mode emulation. */
197 R0PTRTYPE(PVBOXTSS) pRealModeTSS;
198
199 /** R0 memory object for the virtual APIC mmio cache. */
200 RTR0MEMOBJ pMemObjAPIC;
201 /** Physical address of the virtual APIC mmio cache. */
202 RTHCPHYS pAPICPhys;
203 /** Virtual address of the virtual APIC mmio cache. */
204 R0PTRTYPE(uint8_t *) pAPIC;
205
206 /** Ring 0 handlers for VT-x. */
207 DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx));
208
209 /** Host CR4 value (set by ring-0 VMX init) */
210 uint64_t hostCR4;
211
212 /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
213 uint64_t proc_ctls;
214
215 /** Current CR0 mask. */
216 uint64_t cr0_mask;
217 /** Current CR4 mask. */
218 uint64_t cr4_mask;
219
220 /** VMX MSR values */
221 struct
222 {
223 uint64_t feature_ctrl;
224 uint64_t vmx_basic_info;
225 uint64_t vmx_pin_ctls;
226 uint64_t vmx_proc_ctls;
227 uint64_t vmx_exit;
228 uint64_t vmx_entry;
229 uint64_t vmx_misc;
230 uint64_t vmx_cr0_fixed0;
231 uint64_t vmx_cr0_fixed1;
232 uint64_t vmx_cr4_fixed0;
233 uint64_t vmx_cr4_fixed1;
234 uint64_t vmx_vmcs_enum;
235 } msr;
236
237 /* Last instruction error */
238 uint32_t ulLastInstrError;
239 } vmx;
240
241 struct
242 {
243 /** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
244 bool fSupported;
245 /** Set when we've enabled SVM. */
246 bool fEnabled;
247 /** Set if we don't have to flush the TLB on VM entry. */
248 bool fResumeVM;
249 /** Set if erratum 170 affects the AMD cpu. */
250 bool fAlwaysFlushTLB;
251 /** Set if we need to flush the TLB during the world switch. */
252 bool fForceTLBFlush;
253
254 /* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
255 RTCPUID idLastCpu;
256
257 /* TLB flush count */
258 uint32_t cTLBFlushes;
259
260 /** R0 memory object for the VM control block (VMCB). */
261 RTR0MEMOBJ pMemObjVMCB;
262 /** Physical address of the VM control block (VMCB). */
263 RTHCPHYS pVMCBPhys;
264 /** Virtual address of the VM control block (VMCB). */
265 R0PTRTYPE(void *) pVMCB;
266
267 /** R0 memory object for the host VM control block (VMCB). */
268 RTR0MEMOBJ pMemObjVMCBHost;
269 /** Physical address of the host VM control block (VMCB). */
270 RTHCPHYS pVMCBHostPhys;
271 /** Virtual address of the host VM control block (VMCB). */
272 R0PTRTYPE(void *) pVMCBHost;
273
274 /** R0 memory object for the IO bitmap (12kb). */
275 RTR0MEMOBJ pMemObjIOBitmap;
276 /** Physical address of the IO bitmap (12kb). */
277 RTHCPHYS pIOBitmapPhys;
278 /** Virtual address of the IO bitmap. */
279 R0PTRTYPE(void *) pIOBitmap;
280
281 /** R0 memory object for the MSR bitmap (8kb). */
282 RTR0MEMOBJ pMemObjMSRBitmap;
283 /** Physical address of the MSR bitmap (8kb). */
284 RTHCPHYS pMSRBitmapPhys;
285 /** Virtual address of the MSR bitmap. */
286 R0PTRTYPE(void *) pMSRBitmap;
287
288 /** Ring 0 handlers for VT-x. */
289 DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx));
290
291 /** SVM revision. */
292 uint32_t u32Rev;
293
294 /** Maximum ASID allowed. */
295 uint32_t u32MaxASID;
296
297 /** SVM feature bits from cpuid 0x8000000a */
298 uint32_t u32Features;
299 } svm;
300
301 struct
302 {
303 uint32_t u32AMDFeatureECX;
304 uint32_t u32AMDFeatureEDX;
305 } cpuid;
306
307 /* Event injection state. */
308 struct
309 {
310 uint32_t fPending;
311 uint32_t errCode;
312 uint64_t intInfo;
313 } Event;
314
315 /** Saved error from detection */
316 int32_t lLastError;
317
318 /** HWACCMR0Init was run */
319 bool fHWACCMR0Init;
320
321 /** Currenty shadow paging mode. */
322 PGMMODE enmShadowMode;
323
324 STAMPROFILEADV StatEntry;
325 STAMPROFILEADV StatExit;
326 STAMPROFILEADV StatInGC;
327
328 STAMCOUNTER StatIntInject;
329
330 STAMCOUNTER StatExitShadowNM;
331 STAMCOUNTER StatExitGuestNM;
332 STAMCOUNTER StatExitShadowPF;
333 STAMCOUNTER StatExitGuestPF;
334 STAMCOUNTER StatExitGuestUD;
335 STAMCOUNTER StatExitGuestSS;
336 STAMCOUNTER StatExitGuestNP;
337 STAMCOUNTER StatExitGuestGP;
338 STAMCOUNTER StatExitGuestDE;
339 STAMCOUNTER StatExitGuestMF;
340 STAMCOUNTER StatExitInvpg;
341 STAMCOUNTER StatExitInvd;
342 STAMCOUNTER StatExitCpuid;
343 STAMCOUNTER StatExitRdtsc;
344 STAMCOUNTER StatExitCRxWrite;
345 STAMCOUNTER StatExitCRxRead;
346 STAMCOUNTER StatExitDRxWrite;
347 STAMCOUNTER StatExitDRxRead;
348 STAMCOUNTER StatExitCLTS;
349 STAMCOUNTER StatExitLMSW;
350 STAMCOUNTER StatExitIOWrite;
351 STAMCOUNTER StatExitIORead;
352 STAMCOUNTER StatExitIOStringWrite;
353 STAMCOUNTER StatExitIOStringRead;
354 STAMCOUNTER StatExitIrqWindow;
355 STAMCOUNTER StatExitMaxResume;
356 STAMCOUNTER StatIntReinject;
357 STAMCOUNTER StatPendingHostIrq;
358
359 STAMCOUNTER StatFlushPageManual;
360 STAMCOUNTER StatFlushPhysPageManual;
361 STAMCOUNTER StatFlushTLBManual;
362 STAMCOUNTER StatFlushPageInvlpg;
363 STAMCOUNTER StatFlushTLBWorldSwitch;
364 STAMCOUNTER StatNoFlushTLBWorldSwitch;
365 STAMCOUNTER StatFlushTLBCRxChange;
366 STAMCOUNTER StatFlushASID;
367
368 STAMCOUNTER StatSwitchGuestIrq;
369 STAMCOUNTER StatSwitchToR3;
370
371 STAMCOUNTER StatTSCOffset;
372 STAMCOUNTER StatTSCIntercept;
373
374 STAMCOUNTER StatExitReasonNPF;
375 R3PTRTYPE(PSTAMCOUNTER) pStatExitReason;
376 R0PTRTYPE(PSTAMCOUNTER) pStatExitReasonR0;
377} HWACCM;
378/** Pointer to HWACCM VM instance data. */
379typedef HWACCM *PHWACCM;
380
381#ifdef IN_RING0
382
383#ifdef VBOX_STRICT
384HWACCMR0DECL(void) HWACCMDumpRegs(PCPUMCTX pCtx);
385HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
386#else
387#define HWACCMDumpRegs(a) do { } while (0)
388#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
389#endif
390
391/* Dummy callback handlers. */
392HWACCMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu);
393HWACCMR0DECL(int) HWACCMR0DummyLeave(PVM pVM);
394HWACCMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
395HWACCMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
396HWACCMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
397HWACCMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
398HWACCMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
399HWACCMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx, PHWACCM_CPUINFO pCpu);
400HWACCMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM);
401HWACCMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx);
402
403#endif
404
405/** @} */
406
407__END_DECLS
408
409#endif
410
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