VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 11681

Last change on this file since 11681 was 11474, checked in by vboxsync, 16 years ago

AMD-V: Corrected current asid handling. (multiple VMs could end up using each other's ASID)
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File size: 16.1 KB
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1/* $Id: HWACCMInternal.h 11474 2008-08-19 08:11:20Z vboxsync $ */
2/** @file
3 * HWACCM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___HWACCMInternal_h
23#define ___HWACCMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/em.h>
28#include <VBox/stam.h>
29#include <VBox/dis.h>
30#include <VBox/hwaccm.h>
31#include <VBox/pgm.h>
32#include <iprt/memobj.h>
33#include <iprt/cpuset.h>
34#include <iprt/mp.h>
35
36#if HC_ARCH_BITS == 64
37/* Enable 64 bits guest support. */
38# define VBOX_ENABLE_64_BITS_GUESTS
39#endif
40
41__BEGIN_DECLS
42
43
44/** @defgroup grp_hwaccm_int Internal
45 * @ingroup grp_hwaccm
46 * @internal
47 * @{
48 */
49
50
51/**
52 * Converts a HWACCM pointer into a VM pointer.
53 * @returns Pointer to the VM structure the EM is part of.
54 * @param pHWACCM Pointer to HWACCM instance data.
55 */
56#define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
57
58/** Maximum number of exit reason statistics counters. */
59#define MAX_EXITREASON_STAT 0x100
60#define MASK_EXITREASON_STAT 0xff
61
62/** @name Changed flags
63 * These flags are used to keep track of which important registers that
64 * have been changed since last they were reset.
65 * @{
66 */
67#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
68#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
69#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
70#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
71#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
72#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
73#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
74#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
75#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
76#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
77#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
78#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
79
80#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
81 | HWACCM_CHANGED_GUEST_CR0 \
82 | HWACCM_CHANGED_GUEST_CR3 \
83 | HWACCM_CHANGED_GUEST_CR4 \
84 | HWACCM_CHANGED_GUEST_GDTR \
85 | HWACCM_CHANGED_GUEST_IDTR \
86 | HWACCM_CHANGED_GUEST_LDTR \
87 | HWACCM_CHANGED_GUEST_TR \
88 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
89 | HWACCM_CHANGED_GUEST_FPU \
90 | HWACCM_CHANGED_GUEST_DEBUG \
91 | HWACCM_CHANGED_HOST_CONTEXT)
92
93#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
94 | HWACCM_CHANGED_GUEST_CR0 \
95 | HWACCM_CHANGED_GUEST_CR3 \
96 | HWACCM_CHANGED_GUEST_CR4 \
97 | HWACCM_CHANGED_GUEST_GDTR \
98 | HWACCM_CHANGED_GUEST_IDTR \
99 | HWACCM_CHANGED_GUEST_LDTR \
100 | HWACCM_CHANGED_GUEST_TR \
101 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
102 | HWACCM_CHANGED_GUEST_DEBUG \
103 | HWACCM_CHANGED_GUEST_FPU)
104
105/** @} */
106
107/** @name Intercepted traps
108 * Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
109 * Currently #NM and #PF only
110 */
111#ifdef VBOX_STRICT
112#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF)
113#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
114#else
115#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
116#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
117#endif
118/** @} */
119
120
121/** Maxium resume loops allowed in ring 0 (safety precaution) */
122#define HWACCM_MAX_RESUME_LOOPS 1024
123
124/** HWACCM SSM version
125 */
126#define HWACCM_SSM_VERSION 3
127
128/* Per-cpu information. */
129typedef struct
130{
131 RTCPUID idCpu;
132
133 RTR0MEMOBJ pMemObj;
134 /* Current ASID (AMD-V only) */
135 uint32_t uCurrentASID;
136 /* TLB flush count */
137 uint32_t cTLBFlushes;
138
139 /* Set the first time a cpu is used to make sure we start with a clean TLB. */
140 bool fFlushTLB;
141
142 bool fConfigured;
143} HWACCM_CPUINFO;
144typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
145
146/* VT-x capability qword. */
147typedef union
148{
149 struct
150 {
151 uint32_t disallowed0;
152 uint32_t allowed1;
153 } n;
154 uint64_t u;
155} VMX_CAPABILITY;
156
157/**
158 * HWACCM VM Instance data.
159 * Changes to this must checked against the padding of the cfgm union in VM!
160 */
161typedef struct HWACCM
162{
163 /** Offset to the VM structure.
164 * See HWACCM2VM(). */
165 RTUINT offVM;
166
167 /** Set when we've initialized VMX or SVM. */
168 bool fInitialized;
169 /** Set when we're using VMX/SVN at that moment. */
170 bool fActive;
171
172 /** Set when hardware acceleration is allowed. */
173 bool fAllowed;
174
175 /** Set if nested paging is enabled. */
176 bool fNestedPaging;
177
178 /** Set if nested paging is allowed. */
179 bool fAllowNestedPaging;
180
181 /** HWACCM_CHANGED_* flags. */
182 uint32_t fContextUseFlags;
183
184 /** Old style FPU reporting trap mask override performed (optimization) */
185 uint32_t fFPUOldStyleOverride;
186
187 /** And mask for copying register contents. */
188 uint64_t u64RegisterMask;
189 struct
190 {
191 /** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
192 bool fSupported;
193
194 /** Set when we've enabled VMX. */
195 bool fEnabled;
196
197 /** Set if we can use VMXResume to execute guest code. */
198 bool fResumeVM;
199
200 /** R0 memory object for the VM control structure (VMCS). */
201 RTR0MEMOBJ pMemObjVMCS;
202 /** Physical address of the VM control structure (VMCS). */
203 RTHCPHYS pVMCSPhys;
204 /** Virtual address of the VM control structure (VMCS). */
205 R0PTRTYPE(void *) pVMCS;
206
207 /** R0 memory object for the TSS page used for real mode emulation. */
208 RTR0MEMOBJ pMemObjRealModeTSS;
209 /** Physical address of the TSS page used for real mode emulation. */
210 RTHCPHYS pRealModeTSSPhys;
211 /** Virtual address of the TSS page used for real mode emulation. */
212 R0PTRTYPE(PVBOXTSS) pRealModeTSS;
213
214 /** R0 memory object for the virtual APIC mmio cache. */
215 RTR0MEMOBJ pMemObjAPIC;
216 /** Physical address of the virtual APIC mmio cache. */
217 RTHCPHYS pAPICPhys;
218 /** Virtual address of the virtual APIC mmio cache. */
219 R0PTRTYPE(uint8_t *) pAPIC;
220
221 /** Ring 0 handlers for VT-x. */
222 DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx));
223
224 /** Host CR4 value (set by ring-0 VMX init) */
225 uint64_t hostCR4;
226
227 /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
228 uint64_t proc_ctls;
229
230 /** Current CR0 mask. */
231 uint64_t cr0_mask;
232 /** Current CR4 mask. */
233 uint64_t cr4_mask;
234
235 /** VMX MSR values */
236 struct
237 {
238 uint64_t feature_ctrl;
239 uint64_t vmx_basic_info;
240 VMX_CAPABILITY vmx_pin_ctls;
241 VMX_CAPABILITY vmx_proc_ctls;
242 VMX_CAPABILITY vmx_proc_ctls2;
243 VMX_CAPABILITY vmx_exit;
244 VMX_CAPABILITY vmx_entry;
245 uint64_t vmx_misc;
246 uint64_t vmx_cr0_fixed0;
247 uint64_t vmx_cr0_fixed1;
248 uint64_t vmx_cr4_fixed0;
249 uint64_t vmx_cr4_fixed1;
250 uint64_t vmx_vmcs_enum;
251 uint64_t vmx_eptcaps;
252 } msr;
253
254 /* Last instruction error */
255 uint32_t ulLastInstrError;
256 } vmx;
257
258 struct
259 {
260 /** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
261 bool fSupported;
262 /** Set when we've enabled SVM. */
263 bool fEnabled;
264 /** Set if we don't have to flush the TLB on VM entry. */
265 bool fResumeVM;
266 /** Set if erratum 170 affects the AMD cpu. */
267 bool fAlwaysFlushTLB;
268 /** Set if we need to flush the TLB during the world switch. */
269 bool fForceTLBFlush;
270
271 /* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
272 RTCPUID idLastCpu;
273
274 /* TLB flush count */
275 uint32_t cTLBFlushes;
276
277 /* Current ASID in use by the VM */
278 uint32_t uCurrentASID;
279
280 /** R0 memory object for the VM control block (VMCB). */
281 RTR0MEMOBJ pMemObjVMCB;
282 /** Physical address of the VM control block (VMCB). */
283 RTHCPHYS pVMCBPhys;
284 /** Virtual address of the VM control block (VMCB). */
285 R0PTRTYPE(void *) pVMCB;
286
287 /** R0 memory object for the host VM control block (VMCB). */
288 RTR0MEMOBJ pMemObjVMCBHost;
289 /** Physical address of the host VM control block (VMCB). */
290 RTHCPHYS pVMCBHostPhys;
291 /** Virtual address of the host VM control block (VMCB). */
292 R0PTRTYPE(void *) pVMCBHost;
293
294 /** R0 memory object for the IO bitmap (12kb). */
295 RTR0MEMOBJ pMemObjIOBitmap;
296 /** Physical address of the IO bitmap (12kb). */
297 RTHCPHYS pIOBitmapPhys;
298 /** Virtual address of the IO bitmap. */
299 R0PTRTYPE(void *) pIOBitmap;
300
301 /** R0 memory object for the MSR bitmap (8kb). */
302 RTR0MEMOBJ pMemObjMSRBitmap;
303 /** Physical address of the MSR bitmap (8kb). */
304 RTHCPHYS pMSRBitmapPhys;
305 /** Virtual address of the MSR bitmap. */
306 R0PTRTYPE(void *) pMSRBitmap;
307
308 /** Ring 0 handlers for VT-x. */
309 DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx));
310
311 /** SVM revision. */
312 uint32_t u32Rev;
313
314 /** Maximum ASID allowed. */
315 uint32_t u32MaxASID;
316
317 /** SVM feature bits from cpuid 0x8000000a */
318 uint32_t u32Features;
319 } svm;
320
321 struct
322 {
323 uint32_t u32AMDFeatureECX;
324 uint32_t u32AMDFeatureEDX;
325 } cpuid;
326
327 /* Event injection state. */
328 struct
329 {
330 uint32_t fPending;
331 uint32_t errCode;
332 uint64_t intInfo;
333 } Event;
334
335 /** Saved error from detection */
336 int32_t lLastError;
337
338 /** HWACCMR0Init was run */
339 bool fHWACCMR0Init;
340
341 /** Currenty shadow paging mode. */
342 PGMMODE enmShadowMode;
343
344 STAMPROFILEADV StatEntry;
345 STAMPROFILEADV StatExit;
346 STAMPROFILEADV StatInGC;
347
348 STAMCOUNTER StatIntInject;
349
350 STAMCOUNTER StatExitShadowNM;
351 STAMCOUNTER StatExitGuestNM;
352 STAMCOUNTER StatExitShadowPF;
353 STAMCOUNTER StatExitGuestPF;
354 STAMCOUNTER StatExitGuestUD;
355 STAMCOUNTER StatExitGuestSS;
356 STAMCOUNTER StatExitGuestNP;
357 STAMCOUNTER StatExitGuestGP;
358 STAMCOUNTER StatExitGuestDE;
359 STAMCOUNTER StatExitGuestMF;
360 STAMCOUNTER StatExitInvpg;
361 STAMCOUNTER StatExitInvd;
362 STAMCOUNTER StatExitCpuid;
363 STAMCOUNTER StatExitRdtsc;
364 STAMCOUNTER StatExitCRxWrite;
365 STAMCOUNTER StatExitCRxRead;
366 STAMCOUNTER StatExitDRxWrite;
367 STAMCOUNTER StatExitDRxRead;
368 STAMCOUNTER StatExitCLTS;
369 STAMCOUNTER StatExitLMSW;
370 STAMCOUNTER StatExitIOWrite;
371 STAMCOUNTER StatExitIORead;
372 STAMCOUNTER StatExitIOStringWrite;
373 STAMCOUNTER StatExitIOStringRead;
374 STAMCOUNTER StatExitIrqWindow;
375 STAMCOUNTER StatExitMaxResume;
376 STAMCOUNTER StatIntReinject;
377 STAMCOUNTER StatPendingHostIrq;
378
379 STAMCOUNTER StatFlushPageManual;
380 STAMCOUNTER StatFlushPhysPageManual;
381 STAMCOUNTER StatFlushTLBManual;
382 STAMCOUNTER StatFlushPageInvlpg;
383 STAMCOUNTER StatFlushTLBWorldSwitch;
384 STAMCOUNTER StatNoFlushTLBWorldSwitch;
385 STAMCOUNTER StatFlushTLBCRxChange;
386 STAMCOUNTER StatFlushASID;
387
388 STAMCOUNTER StatSwitchGuestIrq;
389 STAMCOUNTER StatSwitchToR3;
390
391 STAMCOUNTER StatTSCOffset;
392 STAMCOUNTER StatTSCIntercept;
393
394 STAMCOUNTER StatExitReasonNPF;
395 R3PTRTYPE(PSTAMCOUNTER) pStatExitReason;
396 R0PTRTYPE(PSTAMCOUNTER) pStatExitReasonR0;
397} HWACCM;
398/** Pointer to HWACCM VM instance data. */
399typedef HWACCM *PHWACCM;
400
401#ifdef IN_RING0
402
403/**
404 * Returns the cpu structure for the current cpu.
405 * Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
406 *
407 * @returns cpu structure pointer
408 * @param pVM The VM to operate on.
409 */
410HWACCMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
411
412#ifdef VBOX_STRICT
413HWACCMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx);
414HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
415#else
416#define HWACCMDumpRegs(a, b) do { } while (0)
417#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
418#endif
419
420/* Dummy callback handlers. */
421HWACCMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu);
422HWACCMR0DECL(int) HWACCMR0DummyLeave(PVM pVM);
423HWACCMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
424HWACCMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
425HWACCMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
426HWACCMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
427HWACCMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
428HWACCMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx);
429HWACCMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM);
430HWACCMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx);
431
432#endif
433
434/** @} */
435
436__END_DECLS
437
438#endif
439
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